diff options
author | Xiubo Li <lixiubo@cmss.chinamobile.com> | 2015-08-12 02:38:18 -0400 |
---|---|---|
committer | Mark Brown <broonie@kernel.org> | 2015-08-12 08:36:58 -0400 |
commit | dcfcf2c2cd71906073beef32aadb1989e8996951 (patch) | |
tree | 62645c5ac4fb8b7c9afb067b976e0ee3837d6400 | |
parent | 0d69e0dddf5fe86675c56bc0f0520ffb0cbf1fcd (diff) |
ASoC: fsl: fix typos for sound/soc/fsl/*
There are too much noise about the typos for fsl's drivers. So I fix
all the typos here in this patch in almost every file I touched.
Signed-off-by: Xiubo Li <lixiubo@cmss.chinamobile.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r-- | sound/soc/fsl/eukrea-tlv320.c | 2 | ||||
-rw-r--r-- | sound/soc/fsl/fsl_sai.h | 12 | ||||
-rw-r--r-- | sound/soc/fsl/fsl_spdif.c | 6 | ||||
-rw-r--r-- | sound/soc/fsl/fsl_ssi.c | 4 |
4 files changed, 12 insertions, 12 deletions
diff --git a/sound/soc/fsl/eukrea-tlv320.c b/sound/soc/fsl/eukrea-tlv320.c index e1aa3834b101..883087f2b092 100644 --- a/sound/soc/fsl/eukrea-tlv320.c +++ b/sound/soc/fsl/eukrea-tlv320.c | |||
@@ -182,7 +182,7 @@ static int eukrea_tlv320_probe(struct platform_device *pdev) | |||
182 | ); | 182 | ); |
183 | } else { | 183 | } else { |
184 | if (np) { | 184 | if (np) { |
185 | /* The eukrea,asoc-tlv320 driver was explicitely | 185 | /* The eukrea,asoc-tlv320 driver was explicitly |
186 | * requested (through the device tree). | 186 | * requested (through the device tree). |
187 | */ | 187 | */ |
188 | dev_err(&pdev->dev, | 188 | dev_err(&pdev->dev, |
diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h index 066280953c85..b4666fd79f6e 100644 --- a/sound/soc/fsl/fsl_sai.h +++ b/sound/soc/fsl/fsl_sai.h | |||
@@ -45,7 +45,7 @@ | |||
45 | #define FSL_SAI_xFR(tx) (tx ? FSL_SAI_TFR : FSL_SAI_RFR) | 45 | #define FSL_SAI_xFR(tx) (tx ? FSL_SAI_TFR : FSL_SAI_RFR) |
46 | #define FSL_SAI_xMR(tx) (tx ? FSL_SAI_TMR : FSL_SAI_RMR) | 46 | #define FSL_SAI_xMR(tx) (tx ? FSL_SAI_TMR : FSL_SAI_RMR) |
47 | 47 | ||
48 | /* SAI Transmit/Recieve Control Register */ | 48 | /* SAI Transmit/Receive Control Register */ |
49 | #define FSL_SAI_CSR_TERE BIT(31) | 49 | #define FSL_SAI_CSR_TERE BIT(31) |
50 | #define FSL_SAI_CSR_FR BIT(25) | 50 | #define FSL_SAI_CSR_FR BIT(25) |
51 | #define FSL_SAI_CSR_SR BIT(24) | 51 | #define FSL_SAI_CSR_SR BIT(24) |
@@ -67,10 +67,10 @@ | |||
67 | #define FSL_SAI_CSR_FRIE BIT(8) | 67 | #define FSL_SAI_CSR_FRIE BIT(8) |
68 | #define FSL_SAI_CSR_FRDE BIT(0) | 68 | #define FSL_SAI_CSR_FRDE BIT(0) |
69 | 69 | ||
70 | /* SAI Transmit and Recieve Configuration 1 Register */ | 70 | /* SAI Transmit and Receive Configuration 1 Register */ |
71 | #define FSL_SAI_CR1_RFW_MASK 0x1f | 71 | #define FSL_SAI_CR1_RFW_MASK 0x1f |
72 | 72 | ||
73 | /* SAI Transmit and Recieve Configuration 2 Register */ | 73 | /* SAI Transmit and Receive Configuration 2 Register */ |
74 | #define FSL_SAI_CR2_SYNC BIT(30) | 74 | #define FSL_SAI_CR2_SYNC BIT(30) |
75 | #define FSL_SAI_CR2_MSEL_MASK (0x3 << 26) | 75 | #define FSL_SAI_CR2_MSEL_MASK (0x3 << 26) |
76 | #define FSL_SAI_CR2_MSEL_BUS 0 | 76 | #define FSL_SAI_CR2_MSEL_BUS 0 |
@@ -82,12 +82,12 @@ | |||
82 | #define FSL_SAI_CR2_BCD_MSTR BIT(24) | 82 | #define FSL_SAI_CR2_BCD_MSTR BIT(24) |
83 | #define FSL_SAI_CR2_DIV_MASK 0xff | 83 | #define FSL_SAI_CR2_DIV_MASK 0xff |
84 | 84 | ||
85 | /* SAI Transmit and Recieve Configuration 3 Register */ | 85 | /* SAI Transmit and Receive Configuration 3 Register */ |
86 | #define FSL_SAI_CR3_TRCE BIT(16) | 86 | #define FSL_SAI_CR3_TRCE BIT(16) |
87 | #define FSL_SAI_CR3_WDFL(x) (x) | 87 | #define FSL_SAI_CR3_WDFL(x) (x) |
88 | #define FSL_SAI_CR3_WDFL_MASK 0x1f | 88 | #define FSL_SAI_CR3_WDFL_MASK 0x1f |
89 | 89 | ||
90 | /* SAI Transmit and Recieve Configuration 4 Register */ | 90 | /* SAI Transmit and Receive Configuration 4 Register */ |
91 | #define FSL_SAI_CR4_FRSZ(x) (((x) - 1) << 16) | 91 | #define FSL_SAI_CR4_FRSZ(x) (((x) - 1) << 16) |
92 | #define FSL_SAI_CR4_FRSZ_MASK (0x1f << 16) | 92 | #define FSL_SAI_CR4_FRSZ_MASK (0x1f << 16) |
93 | #define FSL_SAI_CR4_SYWD(x) (((x) - 1) << 8) | 93 | #define FSL_SAI_CR4_SYWD(x) (((x) - 1) << 8) |
@@ -97,7 +97,7 @@ | |||
97 | #define FSL_SAI_CR4_FSP BIT(1) | 97 | #define FSL_SAI_CR4_FSP BIT(1) |
98 | #define FSL_SAI_CR4_FSD_MSTR BIT(0) | 98 | #define FSL_SAI_CR4_FSD_MSTR BIT(0) |
99 | 99 | ||
100 | /* SAI Transmit and Recieve Configuration 5 Register */ | 100 | /* SAI Transmit and Receive Configuration 5 Register */ |
101 | #define FSL_SAI_CR5_WNW(x) (((x) - 1) << 24) | 101 | #define FSL_SAI_CR5_WNW(x) (((x) - 1) << 24) |
102 | #define FSL_SAI_CR5_WNW_MASK (0x1f << 24) | 102 | #define FSL_SAI_CR5_WNW_MASK (0x1f << 24) |
103 | #define FSL_SAI_CR5_W0W(x) (((x) - 1) << 16) | 103 | #define FSL_SAI_CR5_W0W(x) (((x) - 1) << 16) |
diff --git a/sound/soc/fsl/fsl_spdif.c b/sound/soc/fsl/fsl_spdif.c index d1e9be771f84..92efbc55e32e 100644 --- a/sound/soc/fsl/fsl_spdif.c +++ b/sound/soc/fsl/fsl_spdif.c | |||
@@ -707,7 +707,7 @@ static int fsl_spdif_subcode_get(struct snd_kcontrol *kcontrol, | |||
707 | return ret; | 707 | return ret; |
708 | } | 708 | } |
709 | 709 | ||
710 | /* Q-subcode infomation. The byte size is SPDIF_UBITS_SIZE/8 */ | 710 | /* Q-subcode information. The byte size is SPDIF_UBITS_SIZE/8 */ |
711 | static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol, | 711 | static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol, |
712 | struct snd_ctl_elem_info *uinfo) | 712 | struct snd_ctl_elem_info *uinfo) |
713 | { | 713 | { |
@@ -739,7 +739,7 @@ static int fsl_spdif_qget(struct snd_kcontrol *kcontrol, | |||
739 | return ret; | 739 | return ret; |
740 | } | 740 | } |
741 | 741 | ||
742 | /* Valid bit infomation */ | 742 | /* Valid bit information */ |
743 | static int fsl_spdif_vbit_info(struct snd_kcontrol *kcontrol, | 743 | static int fsl_spdif_vbit_info(struct snd_kcontrol *kcontrol, |
744 | struct snd_ctl_elem_info *uinfo) | 744 | struct snd_ctl_elem_info *uinfo) |
745 | { | 745 | { |
@@ -767,7 +767,7 @@ static int fsl_spdif_vbit_get(struct snd_kcontrol *kcontrol, | |||
767 | return 0; | 767 | return 0; |
768 | } | 768 | } |
769 | 769 | ||
770 | /* DPLL lock infomation */ | 770 | /* DPLL lock information */ |
771 | static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol, | 771 | static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol, |
772 | struct snd_ctl_elem_info *uinfo) | 772 | struct snd_ctl_elem_info *uinfo) |
773 | { | 773 | { |
diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c index e122dab944f4..6a338b88239c 100644 --- a/sound/soc/fsl/fsl_ssi.c +++ b/sound/soc/fsl/fsl_ssi.c | |||
@@ -156,7 +156,7 @@ struct fsl_ssi_soc_data { | |||
156 | * | 156 | * |
157 | * @dbg_stats: Debugging statistics | 157 | * @dbg_stats: Debugging statistics |
158 | * | 158 | * |
159 | * @soc: SoC specifc data | 159 | * @soc: SoC specific data |
160 | */ | 160 | */ |
161 | struct fsl_ssi_private { | 161 | struct fsl_ssi_private { |
162 | struct regmap *regs; | 162 | struct regmap *regs; |
@@ -1210,7 +1210,7 @@ static int fsl_ssi_imx_probe(struct platform_device *pdev, | |||
1210 | } | 1210 | } |
1211 | } | 1211 | } |
1212 | 1212 | ||
1213 | /* For those SLAVE implementations, we ingore non-baudclk cases | 1213 | /* For those SLAVE implementations, we ignore non-baudclk cases |
1214 | * and, instead, abandon MASTER mode that needs baud clock. | 1214 | * and, instead, abandon MASTER mode that needs baud clock. |
1215 | */ | 1215 | */ |
1216 | ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud"); | 1216 | ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud"); |