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authorDave Airlie <airlied@redhat.com>2015-06-10 23:04:07 -0400
committerDave Airlie <airlied@redhat.com>2015-06-10 23:04:07 -0400
commitdc9be8e2175e5e6e53456d8d52eac9b1dd7ec2a7 (patch)
tree8e893d3a7039430a81a50b31637d306ecabf1cbe
parentae45577324d1f749c907840247d443696ac3bc7a (diff)
parent6d8db6ce239587c3d300d79fce3f5bb376232475 (diff)
Merge branch 'drm-next-4.2-amdgpu' of git://people.freedesktop.org/~agd5f/linux into drm-next
More fixes for amdgpu for 4.2. We've integrated Jerome's comments about the interface among other things. I'll be on vacation next week so Christian will be handling any updates next week. * 'drm-next-4.2-amdgpu' of git://people.freedesktop.org/~agd5f/linux: (23 commits) drm/amdgpu: fix a amdgpu_dpm=0 bug drm/amdgpu: don't enable/disable display twice on suspend/resume drm/amdgpu: fix UVD/VCE VM emulation drm/amdgpu: enable vce powergating drm/amdgpu/iceland: don't call smu_init on resume drm/amdgpu/tonga: don't call smu_init on resume drm/amdgpu/cz: don't call smu_init on resume drm/amdgpu: update to latest gfx8 golden register settings drm/amdgpu: whitespace cleanup in gmc8 golden regs drm/admgpu: move XDMA golden registers to dce code drm/amdgpu: fix the build on big endian drm/amdgpu: cleanup UAPI comments drm/amdgpu: remove AMDGPU_CTX_OP_STATE_RUNNING drm/amdgpu: remove the VI hardware semaphore in ring sync drm/amdgpu: set the gfx config properly for all CZ variants (v2) drm/amdgpu: also print the pci revision when printing the pci ids drm/amdgpu: cleanup VA IOCTL drm/amdgpu: fix saddr handling in amdgpu_vm_bo_unmap drm/amdgpu: fix amdgpu_vm_bo_map drm/amdgpu: remove unused AMDGPU_IB_FLAG_GDS ...
Diffstat
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h9
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c18
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_device.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c8
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c65
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_object.c1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c26
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik_sdma.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cz_dpm.c153
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v10_0.c27
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v11_0.c27
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v8_0.c18
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c18
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c68
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/iceland_dpm.c25
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c5
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c5
-rw-r--r--drivers/gpu/drm/amd/amdgpu/tonga_dpm.c25
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vi.c6
-rw-r--r--include/uapi/drm/amdgpu_drm.h146
28 files changed, 445 insertions, 244 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index c33c1af36fa2..22866d1c3d69 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -317,7 +317,7 @@ struct amdgpu_ring_funcs {
317 void (*emit_ib)(struct amdgpu_ring *ring, 317 void (*emit_ib)(struct amdgpu_ring *ring,
318 struct amdgpu_ib *ib); 318 struct amdgpu_ib *ib);
319 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, 319 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
320 uint64_t seq, bool write64bit); 320 uint64_t seq, unsigned flags);
321 bool (*emit_semaphore)(struct amdgpu_ring *ring, 321 bool (*emit_semaphore)(struct amdgpu_ring *ring,
322 struct amdgpu_semaphore *semaphore, 322 struct amdgpu_semaphore *semaphore,
323 bool emit_wait); 323 bool emit_wait);
@@ -392,6 +392,9 @@ struct amdgpu_fence_driver {
392#define AMDGPU_FENCE_OWNER_VM ((void*)1ul) 392#define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
393#define AMDGPU_FENCE_OWNER_MOVE ((void*)2ul) 393#define AMDGPU_FENCE_OWNER_MOVE ((void*)2ul)
394 394
395#define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
396#define AMDGPU_FENCE_FLAG_INT (1 << 1)
397
395struct amdgpu_fence { 398struct amdgpu_fence {
396 struct fence base; 399 struct fence base;
397 400
@@ -1506,6 +1509,7 @@ struct amdgpu_dpm_funcs {
1506 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level); 1509 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1507 bool (*vblank_too_short)(struct amdgpu_device *adev); 1510 bool (*vblank_too_short)(struct amdgpu_device *adev);
1508 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate); 1511 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
1512 void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
1509 void (*enable_bapm)(struct amdgpu_device *adev, bool enable); 1513 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1510 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode); 1514 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1511 u32 (*get_fan_control_mode)(struct amdgpu_device *adev); 1515 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
@@ -2142,7 +2146,7 @@ static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2142#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 2146#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2143#define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib)) 2147#define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
2144#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 2148#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
2145#define amdgpu_ring_emit_fence(r, addr, seq, write64bit) (r)->funcs->emit_fence((r), (addr), (seq), (write64bit)) 2149#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
2146#define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait)) 2150#define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait))
2147#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 2151#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
2148#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 2152#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
@@ -2179,6 +2183,7 @@ static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2179#define amdgpu_dpm_force_performance_level(adev, l) (adev)->pm.funcs->force_performance_level((adev), (l)) 2183#define amdgpu_dpm_force_performance_level(adev, l) (adev)->pm.funcs->force_performance_level((adev), (l))
2180#define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev)) 2184#define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
2181#define amdgpu_dpm_powergate_uvd(adev, g) (adev)->pm.funcs->powergate_uvd((adev), (g)) 2185#define amdgpu_dpm_powergate_uvd(adev, g) (adev)->pm.funcs->powergate_uvd((adev), (g))
2186#define amdgpu_dpm_powergate_vce(adev, g) (adev)->pm.funcs->powergate_vce((adev), (g))
2182#define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e)) 2187#define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
2183#define amdgpu_dpm_set_fan_control_mode(adev, m) (adev)->pm.funcs->set_fan_control_mode((adev), (m)) 2188#define amdgpu_dpm_set_fan_control_mode(adev, m) (adev)->pm.funcs->set_fan_control_mode((adev), (m))
2184#define amdgpu_dpm_get_fan_control_mode(adev) (adev)->pm.funcs->get_fan_control_mode((adev)) 2189#define amdgpu_dpm_get_fan_control_mode(adev) (adev)->pm.funcs->get_fan_control_mode((adev))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index f6b224a69b3a..f09b2cba40ca 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -564,21 +564,33 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
564 return r; 564 return r;
565 565
566 if (ring->funcs->parse_cs) { 566 if (ring->funcs->parse_cs) {
567 struct amdgpu_bo_va_mapping *m;
567 struct amdgpu_bo *aobj = NULL; 568 struct amdgpu_bo *aobj = NULL;
568 void *kptr; 569 uint64_t offset;
570 uint8_t *kptr;
569 571
570 amdgpu_cs_find_mapping(parser, chunk_ib->va_start, &aobj); 572 m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start,
573 &aobj);
571 if (!aobj) { 574 if (!aobj) {
572 DRM_ERROR("IB va_start is invalid\n"); 575 DRM_ERROR("IB va_start is invalid\n");
573 return -EINVAL; 576 return -EINVAL;
574 } 577 }
575 578
579 if ((chunk_ib->va_start + chunk_ib->ib_bytes) >
580 (m->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) {
581 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
582 return -EINVAL;
583 }
584
576 /* the IB should be reserved at this point */ 585 /* the IB should be reserved at this point */
577 r = amdgpu_bo_kmap(aobj, &kptr); 586 r = amdgpu_bo_kmap(aobj, (void **)&kptr);
578 if (r) { 587 if (r) {
579 return r; 588 return r;
580 } 589 }
581 590
591 offset = ((uint64_t)m->it.start) * AMDGPU_GPU_PAGE_SIZE;
592 kptr += chunk_ib->va_start - offset;
593
582 r = amdgpu_ib_get(ring, NULL, chunk_ib->ib_bytes, ib); 594 r = amdgpu_ib_get(ring, NULL, chunk_ib->ib_bytes, ib);
583 if (r) { 595 if (r) {
584 DRM_ERROR("Failed to get ib !\n"); 596 DRM_ERROR("Failed to get ib !\n");
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 36be03ce76c2..fec487d1c870 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1388,9 +1388,9 @@ int amdgpu_device_init(struct amdgpu_device *adev,
1388 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; 1388 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
1389 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; 1389 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
1390 1390
1391 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n", 1391 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1392 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device, 1392 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
1393 pdev->subsystem_vendor, pdev->subsystem_device); 1393 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
1394 1394
1395 /* mutex initialization are all done here so we 1395 /* mutex initialization are all done here so we
1396 * can recall function without having locking issues */ 1396 * can recall function without having locking issues */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index 9ce6023a4261..5c9918d01bf9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -128,7 +128,9 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
128 fence_init(&(*fence)->base, &amdgpu_fence_ops, 128 fence_init(&(*fence)->base, &amdgpu_fence_ops,
129 &adev->fence_queue.lock, adev->fence_context + ring->idx, 129 &adev->fence_queue.lock, adev->fence_context + ring->idx,
130 (*fence)->seq); 130 (*fence)->seq);
131 amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr, (*fence)->seq, false); 131 amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
132 (*fence)->seq,
133 AMDGPU_FENCE_FLAG_INT);
132 trace_amdgpu_fence_emit(ring->adev->ddev, ring->idx, (*fence)->seq); 134 trace_amdgpu_fence_emit(ring->adev->ddev, ring->idx, (*fence)->seq);
133 return 0; 135 return 0;
134} 136}
@@ -522,6 +524,10 @@ long amdgpu_fence_wait_seq_timeout(struct amdgpu_device *adev, u64 *target_seq,
522 bool signaled; 524 bool signaled;
523 int i, r; 525 int i, r;
524 526
527 if (timeout == 0) {
528 return amdgpu_fence_any_seq_signaled(adev, target_seq);
529 }
530
525 while (!amdgpu_fence_any_seq_signaled(adev, target_seq)) { 531 while (!amdgpu_fence_any_seq_signaled(adev, target_seq)) {
526 532
527 /* Save current sequence values, used to check for GPU lockups */ 533 /* Save current sequence values, used to check for GPU lockups */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index ad5b9c676fd8..0ec222295fee 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -37,6 +37,7 @@ void amdgpu_gem_object_free(struct drm_gem_object *gobj)
37 if (robj) { 37 if (robj) {
38 if (robj->gem_base.import_attach) 38 if (robj->gem_base.import_attach)
39 drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg); 39 drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg);
40 amdgpu_mn_unregister(robj);
40 amdgpu_bo_unref(&robj); 41 amdgpu_bo_unref(&robj);
41 } 42 }
42} 43}
@@ -504,7 +505,7 @@ error_free:
504int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 505int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
505 struct drm_file *filp) 506 struct drm_file *filp)
506{ 507{
507 union drm_amdgpu_gem_va *args = data; 508 struct drm_amdgpu_gem_va *args = data;
508 struct drm_gem_object *gobj; 509 struct drm_gem_object *gobj;
509 struct amdgpu_device *adev = dev->dev_private; 510 struct amdgpu_device *adev = dev->dev_private;
510 struct amdgpu_fpriv *fpriv = filp->driver_priv; 511 struct amdgpu_fpriv *fpriv = filp->driver_priv;
@@ -513,95 +514,73 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
513 uint32_t invalid_flags, va_flags = 0; 514 uint32_t invalid_flags, va_flags = 0;
514 int r = 0; 515 int r = 0;
515 516
516 if (!adev->vm_manager.enabled) { 517 if (!adev->vm_manager.enabled)
517 memset(args, 0, sizeof(*args));
518 args->out.result = AMDGPU_VA_RESULT_ERROR;
519 return -ENOTTY; 518 return -ENOTTY;
520 }
521 519
522 if (args->in.va_address < AMDGPU_VA_RESERVED_SIZE) { 520 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
523 dev_err(&dev->pdev->dev, 521 dev_err(&dev->pdev->dev,
524 "va_address 0x%lX is in reserved area 0x%X\n", 522 "va_address 0x%lX is in reserved area 0x%X\n",
525 (unsigned long)args->in.va_address, 523 (unsigned long)args->va_address,
526 AMDGPU_VA_RESERVED_SIZE); 524 AMDGPU_VA_RESERVED_SIZE);
527 memset(args, 0, sizeof(*args));
528 args->out.result = AMDGPU_VA_RESULT_ERROR;
529 return -EINVAL; 525 return -EINVAL;
530 } 526 }
531 527
532 invalid_flags = ~(AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | 528 invalid_flags = ~(AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
533 AMDGPU_VM_PAGE_EXECUTABLE); 529 AMDGPU_VM_PAGE_EXECUTABLE);
534 if ((args->in.flags & invalid_flags)) { 530 if ((args->flags & invalid_flags)) {
535 dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs 0x%08X\n", 531 dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs 0x%08X\n",
536 args->in.flags, invalid_flags); 532 args->flags, invalid_flags);
537 memset(args, 0, sizeof(*args));
538 args->out.result = AMDGPU_VA_RESULT_ERROR;
539 return -EINVAL; 533 return -EINVAL;
540 } 534 }
541 535
542 switch (args->in.operation) { 536 switch (args->operation) {
543 case AMDGPU_VA_OP_MAP: 537 case AMDGPU_VA_OP_MAP:
544 case AMDGPU_VA_OP_UNMAP: 538 case AMDGPU_VA_OP_UNMAP:
545 break; 539 break;
546 default: 540 default:
547 dev_err(&dev->pdev->dev, "unsupported operation %d\n", 541 dev_err(&dev->pdev->dev, "unsupported operation %d\n",
548 args->in.operation); 542 args->operation);
549 memset(args, 0, sizeof(*args));
550 args->out.result = AMDGPU_VA_RESULT_ERROR;
551 return -EINVAL; 543 return -EINVAL;
552 } 544 }
553 545
554 gobj = drm_gem_object_lookup(dev, filp, args->in.handle); 546 gobj = drm_gem_object_lookup(dev, filp, args->handle);
555 if (gobj == NULL) { 547 if (gobj == NULL)
556 memset(args, 0, sizeof(*args));
557 args->out.result = AMDGPU_VA_RESULT_ERROR;
558 return -ENOENT; 548 return -ENOENT;
559 } 549
560 rbo = gem_to_amdgpu_bo(gobj); 550 rbo = gem_to_amdgpu_bo(gobj);
561 r = amdgpu_bo_reserve(rbo, false); 551 r = amdgpu_bo_reserve(rbo, false);
562 if (r) { 552 if (r) {
563 if (r != -ERESTARTSYS) {
564 memset(args, 0, sizeof(*args));
565 args->out.result = AMDGPU_VA_RESULT_ERROR;
566 }
567 drm_gem_object_unreference_unlocked(gobj); 553 drm_gem_object_unreference_unlocked(gobj);
568 return r; 554 return r;
569 } 555 }
556
570 bo_va = amdgpu_vm_bo_find(&fpriv->vm, rbo); 557 bo_va = amdgpu_vm_bo_find(&fpriv->vm, rbo);
571 if (!bo_va) { 558 if (!bo_va) {
572 memset(args, 0, sizeof(*args)); 559 amdgpu_bo_unreserve(rbo);
573 args->out.result = AMDGPU_VA_RESULT_ERROR;
574 drm_gem_object_unreference_unlocked(gobj);
575 return -ENOENT; 560 return -ENOENT;
576 } 561 }
577 562
578 switch (args->in.operation) { 563 switch (args->operation) {
579 case AMDGPU_VA_OP_MAP: 564 case AMDGPU_VA_OP_MAP:
580 if (args->in.flags & AMDGPU_VM_PAGE_READABLE) 565 if (args->flags & AMDGPU_VM_PAGE_READABLE)
581 va_flags |= AMDGPU_PTE_READABLE; 566 va_flags |= AMDGPU_PTE_READABLE;
582 if (args->in.flags & AMDGPU_VM_PAGE_WRITEABLE) 567 if (args->flags & AMDGPU_VM_PAGE_WRITEABLE)
583 va_flags |= AMDGPU_PTE_WRITEABLE; 568 va_flags |= AMDGPU_PTE_WRITEABLE;
584 if (args->in.flags & AMDGPU_VM_PAGE_EXECUTABLE) 569 if (args->flags & AMDGPU_VM_PAGE_EXECUTABLE)
585 va_flags |= AMDGPU_PTE_EXECUTABLE; 570 va_flags |= AMDGPU_PTE_EXECUTABLE;
586 r = amdgpu_vm_bo_map(adev, bo_va, args->in.va_address, 571 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
587 args->in.offset_in_bo, args->in.map_size, 572 args->offset_in_bo, args->map_size,
588 va_flags); 573 va_flags);
589 break; 574 break;
590 case AMDGPU_VA_OP_UNMAP: 575 case AMDGPU_VA_OP_UNMAP:
591 r = amdgpu_vm_bo_unmap(adev, bo_va, args->in.va_address); 576 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address);
592 break; 577 break;
593 default: 578 default:
594 break; 579 break;
595 } 580 }
596 581
597 if (!r) { 582 if (!r)
598 amdgpu_gem_va_update_vm(adev, bo_va); 583 amdgpu_gem_va_update_vm(adev, bo_va);
599 memset(args, 0, sizeof(*args));
600 args->out.result = AMDGPU_VA_RESULT_OK;
601 } else {
602 memset(args, 0, sizeof(*args));
603 args->out.result = AMDGPU_VA_RESULT_ERROR;
604 }
605 584
606 drm_gem_object_unreference_unlocked(gobj); 585 drm_gem_object_unreference_unlocked(gobj);
607 return r; 586 return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 560c5fd347be..52dff75aac6f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -216,7 +216,8 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
216 if (ib->user) { 216 if (ib->user) {
217 uint64_t addr = amdgpu_bo_gpu_offset(ib->user->bo); 217 uint64_t addr = amdgpu_bo_gpu_offset(ib->user->bo);
218 addr += ib->user->offset; 218 addr += ib->user->offset;
219 amdgpu_ring_emit_fence(ring, addr, ib->fence->seq, true); 219 amdgpu_ring_emit_fence(ring, addr, ib->fence->seq,
220 AMDGPU_FENCE_FLAG_64BIT);
220 } 221 }
221 222
222 if (ib->vm) 223 if (ib->vm)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 7d801e016e31..8da64245b31b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -95,7 +95,6 @@ static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
95 bo = container_of(tbo, struct amdgpu_bo, tbo); 95 bo = container_of(tbo, struct amdgpu_bo, tbo);
96 96
97 amdgpu_update_memory_usage(bo->adev, &bo->tbo.mem, NULL); 97 amdgpu_update_memory_usage(bo->adev, &bo->tbo.mem, NULL);
98 amdgpu_mn_unregister(bo);
99 98
100 mutex_lock(&bo->adev->gem.mutex); 99 mutex_lock(&bo->adev->gem.mutex);
101 list_del_init(&bo->list); 100 list_del_init(&bo->list);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 605a9e42f943..ed13baa7c976 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -656,19 +656,27 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
656 656
657void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable) 657void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
658{ 658{
659 if (enable) { 659 if (adev->pm.funcs->powergate_vce) {
660 mutex_lock(&adev->pm.mutex); 660 mutex_lock(&adev->pm.mutex);
661 adev->pm.dpm.vce_active = true; 661 /* enable/disable VCE */
662 /* XXX select vce level based on ring/task */ 662 amdgpu_dpm_powergate_vce(adev, !enable);
663 adev->pm.dpm.vce_level = AMDGPU_VCE_LEVEL_AC_ALL; 663
664 mutex_unlock(&adev->pm.mutex); 664 mutex_unlock(&adev->pm.mutex);
665 } else { 665 } else {
666 mutex_lock(&adev->pm.mutex); 666 if (enable) {
667 adev->pm.dpm.vce_active = false; 667 mutex_lock(&adev->pm.mutex);
668 mutex_unlock(&adev->pm.mutex); 668 adev->pm.dpm.vce_active = true;
669 } 669 /* XXX select vce level based on ring/task */
670 adev->pm.dpm.vce_level = AMDGPU_VCE_LEVEL_AC_ALL;
671 mutex_unlock(&adev->pm.mutex);
672 } else {
673 mutex_lock(&adev->pm.mutex);
674 adev->pm.dpm.vce_active = false;
675 mutex_unlock(&adev->pm.mutex);
676 }
670 677
671 amdgpu_pm_compute_clocks(adev); 678 amdgpu_pm_compute_clocks(adev);
679 }
672} 680}
673 681
674void amdgpu_pm_print_power_states(struct amdgpu_device *adev) 682void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 62018b37273e..1127a504f118 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -637,9 +637,9 @@ void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
637 * 637 *
638 */ 638 */
639void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 639void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
640 bool write64bits) 640 unsigned flags)
641{ 641{
642 WARN_ON(write64bits); 642 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
643 643
644 amdgpu_ring_write(ring, VCE_CMD_FENCE); 644 amdgpu_ring_write(ring, VCE_CMD_FENCE);
645 amdgpu_ring_write(ring, addr); 645 amdgpu_ring_write(ring, addr);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
index 4294854912e7..b6a9d0956c60 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
@@ -40,7 +40,7 @@ bool amdgpu_vce_ring_emit_semaphore(struct amdgpu_ring *ring,
40 bool emit_wait); 40 bool emit_wait);
41void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 41void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
42void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 42void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
43 bool write64bit); 43 unsigned flags);
44int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring); 44int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring);
45int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring); 45int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring);
46 46
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index fd28e890693e..407882b233c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1002,6 +1002,8 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
1002 list_add(&mapping->list, &bo_va->mappings); 1002 list_add(&mapping->list, &bo_va->mappings);
1003 interval_tree_insert(&mapping->it, &vm->va); 1003 interval_tree_insert(&mapping->it, &vm->va);
1004 1004
1005 bo_va->addr = 0;
1006
1005 /* Make sure the page tables are allocated */ 1007 /* Make sure the page tables are allocated */
1006 saddr >>= amdgpu_vm_block_size; 1008 saddr >>= amdgpu_vm_block_size;
1007 eaddr >>= amdgpu_vm_block_size; 1009 eaddr >>= amdgpu_vm_block_size;
@@ -1082,6 +1084,8 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
1082 struct amdgpu_bo_va_mapping *mapping; 1084 struct amdgpu_bo_va_mapping *mapping;
1083 struct amdgpu_vm *vm = bo_va->vm; 1085 struct amdgpu_vm *vm = bo_va->vm;
1084 1086
1087 saddr /= AMDGPU_GPU_PAGE_SIZE;
1088
1085 list_for_each_entry(mapping, &bo_va->mappings, list) { 1089 list_for_each_entry(mapping, &bo_va->mappings, list) {
1086 if (mapping->it.start == saddr) 1090 if (mapping->it.start == saddr)
1087 break; 1091 break;
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index ef5e9f9b5ab2..ab83cc1ca4cc 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -259,8 +259,9 @@ static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
259 * an interrupt if needed (CIK). 259 * an interrupt if needed (CIK).
260 */ 260 */
261static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 261static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
262 bool write64bit) 262 unsigned flags)
263{ 263{
264 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
264 /* write the fence */ 265 /* write the fence */
265 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); 266 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
266 amdgpu_ring_write(ring, lower_32_bits(addr)); 267 amdgpu_ring_write(ring, lower_32_bits(addr));
@@ -410,7 +411,8 @@ static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
410 rb_bufsz = order_base_2(ring->ring_size / 4); 411 rb_bufsz = order_base_2(ring->ring_size / 4);
411 rb_cntl = rb_bufsz << 1; 412 rb_cntl = rb_bufsz << 1;
412#ifdef __BIG_ENDIAN 413#ifdef __BIG_ENDIAN
413 rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE; 414 rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK |
415 SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK;
414#endif 416#endif
415 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 417 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
416 418
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
index f275b5d2d060..e4936a452bc6 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
@@ -43,6 +43,7 @@
43#include "gfx_v8_0.h" 43#include "gfx_v8_0.h"
44 44
45static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate); 45static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate);
46static void cz_dpm_powergate_vce(struct amdgpu_device *adev, bool gate);
46 47
47static struct cz_ps *cz_get_ps(struct amdgpu_ps *rps) 48static struct cz_ps *cz_get_ps(struct amdgpu_ps *rps)
48{ 49{
@@ -556,8 +557,11 @@ static int cz_dpm_late_init(void *handle)
556{ 557{
557 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 558 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
558 559
559 /* powerdown unused blocks for now */ 560 if (amdgpu_dpm) {
560 cz_dpm_powergate_uvd(adev, true); 561 /* powerdown unused blocks for now */
562 cz_dpm_powergate_uvd(adev, true);
563 cz_dpm_powergate_vce(adev, true);
564 }
561 565
562 return 0; 566 return 0;
563} 567}
@@ -826,16 +830,16 @@ static void cz_init_vce_limit(struct amdgpu_device *adev)
826 return; 830 return;
827 } 831 }
828 832
829 pi->vce_dpm.soft_min_clk = 0; 833 pi->vce_dpm.soft_min_clk = table->entries[0].ecclk;
830 pi->vce_dpm.hard_min_clk = 0; 834 pi->vce_dpm.hard_min_clk = table->entries[0].ecclk;
831 cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxEclkLevel); 835 cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxEclkLevel);
832 level = cz_get_argument(adev); 836 level = cz_get_argument(adev);
833 if (level < table->count) 837 if (level < table->count)
834 clock = table->entries[level].evclk; 838 clock = table->entries[level].ecclk;
835 else { 839 else {
836 /* future BIOS would fix this error */ 840 /* future BIOS would fix this error */
837 DRM_ERROR("Invalid VCE Voltage Dependency table entry.\n"); 841 DRM_ERROR("Invalid VCE Voltage Dependency table entry.\n");
838 clock = table->entries[table->count - 1].evclk; 842 clock = table->entries[table->count - 1].ecclk;
839 } 843 }
840 844
841 pi->vce_dpm.soft_max_clk = clock; 845 pi->vce_dpm.soft_max_clk = clock;
@@ -1004,6 +1008,36 @@ static uint32_t cz_get_sclk_level(struct amdgpu_device *adev,
1004 return i; 1008 return i;
1005} 1009}
1006 1010
1011static uint32_t cz_get_eclk_level(struct amdgpu_device *adev,
1012 uint32_t clock, uint16_t msg)
1013{
1014 int i = 0;
1015 struct amdgpu_vce_clock_voltage_dependency_table *table =
1016 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1017
1018 if (table->count == 0)
1019 return 0;
1020
1021 switch (msg) {
1022 case PPSMC_MSG_SetEclkSoftMin:
1023 case PPSMC_MSG_SetEclkHardMin:
1024 for (i = 0; i < table->count-1; i++)
1025 if (clock <= table->entries[i].ecclk)
1026 break;
1027 break;
1028 case PPSMC_MSG_SetEclkSoftMax:
1029 case PPSMC_MSG_SetEclkHardMax:
1030 for (i = table->count - 1; i > 0; i--)
1031 if (clock >= table->entries[i].ecclk)
1032 break;
1033 break;
1034 default:
1035 break;
1036 }
1037
1038 return i;
1039}
1040
1007static int cz_program_bootup_state(struct amdgpu_device *adev) 1041static int cz_program_bootup_state(struct amdgpu_device *adev)
1008{ 1042{
1009 struct cz_power_info *pi = cz_get_pi(adev); 1043 struct cz_power_info *pi = cz_get_pi(adev);
@@ -1230,7 +1264,10 @@ static int cz_dpm_hw_init(void *handle)
1230 1264
1231 mutex_lock(&adev->pm.mutex); 1265 mutex_lock(&adev->pm.mutex);
1232 1266
1233 /* init smc in dpm hw init */ 1267 /* smu init only needs to be called at startup, not resume.
1268 * It should be in sw_init, but requires the fw info gathered
1269 * in sw_init from other IP modules.
1270 */
1234 ret = cz_smu_init(adev); 1271 ret = cz_smu_init(adev);
1235 if (ret) { 1272 if (ret) {
1236 DRM_ERROR("amdgpu: smc initialization failed\n"); 1273 DRM_ERROR("amdgpu: smc initialization failed\n");
@@ -1282,6 +1319,7 @@ static int cz_dpm_disable(struct amdgpu_device *adev)
1282 1319
1283 /* powerup blocks */ 1320 /* powerup blocks */
1284 cz_dpm_powergate_uvd(adev, false); 1321 cz_dpm_powergate_uvd(adev, false);
1322 cz_dpm_powergate_vce(adev, false);
1285 1323
1286 cz_clear_voting_clients(adev); 1324 cz_clear_voting_clients(adev);
1287 cz_stop_dpm(adev); 1325 cz_stop_dpm(adev);
@@ -1297,6 +1335,10 @@ static int cz_dpm_hw_fini(void *handle)
1297 1335
1298 mutex_lock(&adev->pm.mutex); 1336 mutex_lock(&adev->pm.mutex);
1299 1337
1338 /* smu fini only needs to be called at teardown, not suspend.
1339 * It should be in sw_fini, but we put it here for symmetry
1340 * with smu init.
1341 */
1300 cz_smu_fini(adev); 1342 cz_smu_fini(adev);
1301 1343
1302 if (adev->pm.dpm_enabled) { 1344 if (adev->pm.dpm_enabled) {
@@ -1340,12 +1382,6 @@ static int cz_dpm_resume(void *handle)
1340 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1382 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1341 1383
1342 mutex_lock(&adev->pm.mutex); 1384 mutex_lock(&adev->pm.mutex);
1343 ret = cz_smu_init(adev);
1344 if (ret) {
1345 DRM_ERROR("amdgpu: smc resume failed\n");
1346 mutex_unlock(&adev->pm.mutex);
1347 return ret;
1348 }
1349 1385
1350 /* do the actual fw loading */ 1386 /* do the actual fw loading */
1351 ret = cz_smu_start(adev); 1387 ret = cz_smu_start(adev);
@@ -1774,6 +1810,96 @@ static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
1774 } 1810 }
1775} 1811}
1776 1812
1813static int cz_enable_vce_dpm(struct amdgpu_device *adev, bool enable)
1814{
1815 struct cz_power_info *pi = cz_get_pi(adev);
1816 int ret = 0;
1817
1818 if (enable && pi->caps_vce_dpm) {
1819 pi->dpm_flags |= DPMFlags_VCE_Enabled;
1820 DRM_DEBUG("VCE DPM Enabled.\n");
1821
1822 ret = cz_send_msg_to_smc_with_parameter(adev,
1823 PPSMC_MSG_EnableAllSmuFeatures, VCE_DPM_MASK);
1824
1825 } else {
1826 pi->dpm_flags &= ~DPMFlags_VCE_Enabled;
1827 DRM_DEBUG("VCE DPM Stopped\n");
1828
1829 ret = cz_send_msg_to_smc_with_parameter(adev,
1830 PPSMC_MSG_DisableAllSmuFeatures, VCE_DPM_MASK);
1831 }
1832
1833 return ret;
1834}
1835
1836static int cz_update_vce_dpm(struct amdgpu_device *adev)
1837{
1838 struct cz_power_info *pi = cz_get_pi(adev);
1839 struct amdgpu_vce_clock_voltage_dependency_table *table =
1840 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1841
1842 /* Stable Pstate is enabled and we need to set the VCE DPM to highest level */
1843 if (pi->caps_stable_power_state) {
1844 pi->vce_dpm.hard_min_clk = table->entries[table->count-1].ecclk;
1845
1846 } else { /* non-stable p-state cases. without vce.Arbiter.EcclkHardMin */
1847 pi->vce_dpm.hard_min_clk = table->entries[0].ecclk;
1848 }
1849
1850 cz_send_msg_to_smc_with_parameter(adev,
1851 PPSMC_MSG_SetEclkHardMin,
1852 cz_get_eclk_level(adev,
1853 pi->vce_dpm.hard_min_clk,
1854 PPSMC_MSG_SetEclkHardMin));
1855 return 0;
1856}
1857
1858static void cz_dpm_powergate_vce(struct amdgpu_device *adev, bool gate)
1859{
1860 struct cz_power_info *pi = cz_get_pi(adev);
1861
1862 if (pi->caps_vce_pg) {
1863 if (pi->vce_power_gated != gate) {
1864 if (gate) {
1865 /* disable clockgating so we can properly shut down the block */
1866 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1867 AMD_CG_STATE_UNGATE);
1868 /* shutdown the VCE block */
1869 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1870 AMD_PG_STATE_GATE);
1871
1872 cz_enable_vce_dpm(adev, false);
1873 /* TODO: to figure out why vce can't be poweroff. */
1874 /* cz_send_msg_to_smc(adev, PPSMC_MSG_VCEPowerOFF); */
1875 pi->vce_power_gated = true;
1876 } else {
1877 cz_send_msg_to_smc(adev, PPSMC_MSG_VCEPowerON);
1878 pi->vce_power_gated = false;
1879
1880 /* re-init the VCE block */
1881 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1882 AMD_PG_STATE_UNGATE);
1883 /* enable clockgating. hw will dynamically gate/ungate clocks on the fly */
1884 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1885 AMD_CG_STATE_GATE);
1886
1887 cz_update_vce_dpm(adev);
1888 cz_enable_vce_dpm(adev, true);
1889 }
1890 } else {
1891 if (! pi->vce_power_gated) {
1892 cz_update_vce_dpm(adev);
1893 }
1894 }
1895 } else { /*pi->caps_vce_pg*/
1896 cz_update_vce_dpm(adev);
1897 cz_enable_vce_dpm(adev, true);
1898 }
1899
1900 return;
1901}
1902
1777const struct amd_ip_funcs cz_dpm_ip_funcs = { 1903const struct amd_ip_funcs cz_dpm_ip_funcs = {
1778 .early_init = cz_dpm_early_init, 1904 .early_init = cz_dpm_early_init,
1779 .late_init = cz_dpm_late_init, 1905 .late_init = cz_dpm_late_init,
@@ -1805,6 +1931,7 @@ static const struct amdgpu_dpm_funcs cz_dpm_funcs = {
1805 .force_performance_level = cz_dpm_force_dpm_level, 1931 .force_performance_level = cz_dpm_force_dpm_level,
1806 .vblank_too_short = NULL, 1932 .vblank_too_short = NULL,
1807 .powergate_uvd = cz_dpm_powergate_uvd, 1933 .powergate_uvd = cz_dpm_powergate_uvd,
1934 .powergate_vce = cz_dpm_powergate_vce,
1808}; 1935};
1809 1936
1810static void cz_dpm_set_funcs(struct amdgpu_device *adev) 1937static void cz_dpm_set_funcs(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 926c8e0789b0..5cde635978f9 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -120,11 +120,20 @@ static const u32 golden_settings_tonga_a11[] =
120 mmHDMI_CONTROL, 0x31000111, 0x00000011, 120 mmHDMI_CONTROL, 0x31000111, 0x00000011,
121}; 121};
122 122
123static const u32 tonga_mgcg_cgcg_init[] =
124{
125 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
126 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
127};
128
123static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev) 129static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev)
124{ 130{
125 switch (adev->asic_type) { 131 switch (adev->asic_type) {
126 case CHIP_TONGA: 132 case CHIP_TONGA:
127 amdgpu_program_register_sequence(adev, 133 amdgpu_program_register_sequence(adev,
134 tonga_mgcg_cgcg_init,
135 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
136 amdgpu_program_register_sequence(adev,
128 golden_settings_tonga_a11, 137 golden_settings_tonga_a11,
129 (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); 138 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
130 break; 139 break;
@@ -3008,16 +3017,8 @@ static int dce_v10_0_hw_fini(void *handle)
3008 3017
3009static int dce_v10_0_suspend(void *handle) 3018static int dce_v10_0_suspend(void *handle)
3010{ 3019{
3011 struct drm_connector *connector;
3012 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3020 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3013 3021
3014 drm_kms_helper_poll_disable(adev->ddev);
3015
3016 /* turn off display hw */
3017 list_for_each_entry(connector, &adev->ddev->mode_config.connector_list, head) {
3018 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
3019 }
3020
3021 amdgpu_atombios_scratch_regs_save(adev); 3022 amdgpu_atombios_scratch_regs_save(adev);
3022 3023
3023 dce_v10_0_hpd_fini(adev); 3024 dce_v10_0_hpd_fini(adev);
@@ -3027,7 +3028,6 @@ static int dce_v10_0_suspend(void *handle)
3027 3028
3028static int dce_v10_0_resume(void *handle) 3029static int dce_v10_0_resume(void *handle)
3029{ 3030{
3030 struct drm_connector *connector;
3031 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3031 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3032 3032
3033 dce_v10_0_init_golden_registers(adev); 3033 dce_v10_0_init_golden_registers(adev);
@@ -3048,15 +3048,6 @@ static int dce_v10_0_resume(void *handle)
3048 /* initialize hpd */ 3048 /* initialize hpd */
3049 dce_v10_0_hpd_init(adev); 3049 dce_v10_0_hpd_init(adev);
3050 3050
3051 /* blat the mode back in */
3052 drm_helper_resume_force_mode(adev->ddev);
3053 /* turn on display hw */
3054 list_for_each_entry(connector, &adev->ddev->mode_config.connector_list, head) {
3055 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
3056 }
3057
3058 drm_kms_helper_poll_enable(adev->ddev);
3059
3060 return 0; 3051 return 0;
3061} 3052}
3062 3053
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index bc60fd1844f3..95efd98b202d 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -120,11 +120,20 @@ static const u32 cz_golden_settings_a11[] =
120 mmFBC_MISC, 0x1f311fff, 0x14300000, 120 mmFBC_MISC, 0x1f311fff, 0x14300000,
121}; 121};
122 122
123static const u32 cz_mgcg_cgcg_init[] =
124{
125 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
126 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
127};
128
123static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) 129static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
124{ 130{
125 switch (adev->asic_type) { 131 switch (adev->asic_type) {
126 case CHIP_CARRIZO: 132 case CHIP_CARRIZO:
127 amdgpu_program_register_sequence(adev, 133 amdgpu_program_register_sequence(adev,
134 cz_mgcg_cgcg_init,
135 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
136 amdgpu_program_register_sequence(adev,
128 cz_golden_settings_a11, 137 cz_golden_settings_a11,
129 (const u32)ARRAY_SIZE(cz_golden_settings_a11)); 138 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
130 break; 139 break;
@@ -3006,16 +3015,8 @@ static int dce_v11_0_hw_fini(void *handle)
3006 3015
3007static int dce_v11_0_suspend(void *handle) 3016static int dce_v11_0_suspend(void *handle)
3008{ 3017{
3009 struct drm_connector *connector;
3010 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3018 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3011 3019
3012 drm_kms_helper_poll_disable(adev->ddev);
3013
3014 /* turn off display hw */
3015 list_for_each_entry(connector, &adev->ddev->mode_config.connector_list, head) {
3016 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
3017 }
3018
3019 amdgpu_atombios_scratch_regs_save(adev); 3020 amdgpu_atombios_scratch_regs_save(adev);
3020 3021
3021 dce_v11_0_hpd_fini(adev); 3022 dce_v11_0_hpd_fini(adev);
@@ -3025,7 +3026,6 @@ static int dce_v11_0_suspend(void *handle)
3025 3026
3026static int dce_v11_0_resume(void *handle) 3027static int dce_v11_0_resume(void *handle)
3027{ 3028{
3028 struct drm_connector *connector;
3029 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3029 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3030 3030
3031 dce_v11_0_init_golden_registers(adev); 3031 dce_v11_0_init_golden_registers(adev);
@@ -3047,15 +3047,6 @@ static int dce_v11_0_resume(void *handle)
3047 /* initialize hpd */ 3047 /* initialize hpd */
3048 dce_v11_0_hpd_init(adev); 3048 dce_v11_0_hpd_init(adev);
3049 3049
3050 /* blat the mode back in */
3051 drm_helper_resume_force_mode(adev->ddev);
3052 /* turn on display hw */
3053 list_for_each_entry(connector, &adev->ddev->mode_config.connector_list, head) {
3054 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
3055 }
3056
3057 drm_kms_helper_poll_enable(adev->ddev);
3058
3059 return 0; 3050 return 0;
3060} 3051}
3061 3052
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index 9e8b9f1fad18..72c27ac915f2 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -2948,16 +2948,8 @@ static int dce_v8_0_hw_fini(void *handle)
2948 2948
2949static int dce_v8_0_suspend(void *handle) 2949static int dce_v8_0_suspend(void *handle)
2950{ 2950{
2951 struct drm_connector *connector;
2952 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2951 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2953 2952
2954 drm_kms_helper_poll_disable(adev->ddev);
2955
2956 /* turn off display hw */
2957 list_for_each_entry(connector, &adev->ddev->mode_config.connector_list, head) {
2958 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
2959 }
2960
2961 amdgpu_atombios_scratch_regs_save(adev); 2953 amdgpu_atombios_scratch_regs_save(adev);
2962 2954
2963 dce_v8_0_hpd_fini(adev); 2955 dce_v8_0_hpd_fini(adev);
@@ -2967,7 +2959,6 @@ static int dce_v8_0_suspend(void *handle)
2967 2959
2968static int dce_v8_0_resume(void *handle) 2960static int dce_v8_0_resume(void *handle)
2969{ 2961{
2970 struct drm_connector *connector;
2971 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2962 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2972 2963
2973 amdgpu_atombios_scratch_regs_restore(adev); 2964 amdgpu_atombios_scratch_regs_restore(adev);
@@ -2986,15 +2977,6 @@ static int dce_v8_0_resume(void *handle)
2986 /* initialize hpd */ 2977 /* initialize hpd */
2987 dce_v8_0_hpd_init(adev); 2978 dce_v8_0_hpd_init(adev);
2988 2979
2989 /* blat the mode back in */
2990 drm_helper_resume_force_mode(adev->ddev);
2991 /* turn on display hw */
2992 list_for_each_entry(connector, &adev->ddev->mode_config.connector_list, head) {
2993 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
2994 }
2995
2996 drm_kms_helper_poll_enable(adev->ddev);
2997
2998 return 0; 2980 return 0;
2999} 2981}
3000 2982
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 5fefe402e085..cb7907447b81 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -2414,8 +2414,10 @@ static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
2414 * GPU caches. 2414 * GPU caches.
2415 */ 2415 */
2416static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, 2416static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
2417 u64 seq, bool write64bit) 2417 u64 seq, unsigned flags)
2418{ 2418{
2419 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2420 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2419 /* Workaround for cache flush problems. First send a dummy EOP 2421 /* Workaround for cache flush problems. First send a dummy EOP
2420 * event down the pipe with seq one below. 2422 * event down the pipe with seq one below.
2421 */ 2423 */
@@ -2438,7 +2440,7 @@ static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
2438 EVENT_INDEX(5))); 2440 EVENT_INDEX(5)));
2439 amdgpu_ring_write(ring, addr & 0xfffffffc); 2441 amdgpu_ring_write(ring, addr & 0xfffffffc);
2440 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 2442 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
2441 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(2)); 2443 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2442 amdgpu_ring_write(ring, lower_32_bits(seq)); 2444 amdgpu_ring_write(ring, lower_32_bits(seq));
2443 amdgpu_ring_write(ring, upper_32_bits(seq)); 2445 amdgpu_ring_write(ring, upper_32_bits(seq));
2444} 2446}
@@ -2454,15 +2456,18 @@ static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
2454 */ 2456 */
2455static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring, 2457static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
2456 u64 addr, u64 seq, 2458 u64 addr, u64 seq,
2457 bool write64bits) 2459 unsigned flags)
2458{ 2460{
2461 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2462 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2463
2459 /* RELEASE_MEM - flush caches, send int */ 2464 /* RELEASE_MEM - flush caches, send int */
2460 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); 2465 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
2461 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 2466 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2462 EOP_TC_ACTION_EN | 2467 EOP_TC_ACTION_EN |
2463 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2468 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2464 EVENT_INDEX(5))); 2469 EVENT_INDEX(5)));
2465 amdgpu_ring_write(ring, DATA_SEL(write64bits ? 2 : 1) | INT_SEL(2)); 2470 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2466 amdgpu_ring_write(ring, addr & 0xfffffffc); 2471 amdgpu_ring_write(ring, addr & 0xfffffffc);
2467 amdgpu_ring_write(ring, upper_32_bits(addr)); 2472 amdgpu_ring_write(ring, upper_32_bits(addr));
2468 amdgpu_ring_write(ring, lower_32_bits(seq)); 2473 amdgpu_ring_write(ring, lower_32_bits(seq));
@@ -2876,7 +2881,7 @@ static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)
2876 rb_bufsz = order_base_2(ring->ring_size / 8); 2881 rb_bufsz = order_base_2(ring->ring_size / 8);
2877 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2882 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2878#ifdef __BIG_ENDIAN 2883#ifdef __BIG_ENDIAN
2879 tmp |= BUF_SWAP_32BIT; 2884 tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT;
2880#endif 2885#endif
2881 WREG32(mmCP_RB0_CNTL, tmp); 2886 WREG32(mmCP_RB0_CNTL, tmp);
2882 2887
@@ -3395,7 +3400,8 @@ static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev)
3395 mqd->queue_state.cp_hqd_pq_control |= 3400 mqd->queue_state.cp_hqd_pq_control |=
3396 (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8); 3401 (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8);
3397#ifdef __BIG_ENDIAN 3402#ifdef __BIG_ENDIAN
3398 mqd->queue_state.cp_hqd_pq_control |= BUF_SWAP_32BIT; 3403 mqd->queue_state.cp_hqd_pq_control |=
3404 2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT;
3399#endif 3405#endif
3400 mqd->queue_state.cp_hqd_pq_control &= 3406 mqd->queue_state.cp_hqd_pq_control &=
3401 ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK | 3407 ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK |
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 04b91523008c..14242bd33363 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -116,11 +116,14 @@ static const u32 golden_settings_tonga_a11[] =
116 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, 116 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
117 mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc, 117 mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
118 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 118 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
119 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
119 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, 120 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
120 mmTCC_CTRL, 0x00100000, 0xf31fff7f, 121 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
122 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
121 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb, 123 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
122 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b, 124 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
123 mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876, 125 mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
126 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
124}; 127};
125 128
126static const u32 tonga_golden_common_all[] = 129static const u32 tonga_golden_common_all[] =
@@ -224,8 +227,10 @@ static const u32 golden_settings_iceland_a11[] =
224 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 227 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
225 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002, 228 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
226 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000, 229 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
230 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
227 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, 231 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
228 mmTCC_CTRL, 0x00100000, 0xf31fff7f, 232 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
233 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
229 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1, 234 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
230 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, 235 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
231 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010, 236 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
@@ -318,7 +323,9 @@ static const u32 cz_golden_settings_a11[] =
318 mmGB_GPU_ID, 0x0000000f, 0x00000000, 323 mmGB_GPU_ID, 0x0000000f, 0x00000000,
319 mmPA_SC_ENHANCE, 0xffffffff, 0x00000001, 324 mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
320 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 325 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
326 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
321 mmTA_CNTL_AUX, 0x000f000f, 0x00010000, 327 mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
328 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
322 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3, 329 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
323 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302 330 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302
324}; 331};
@@ -1933,9 +1940,43 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
1933 case CHIP_CARRIZO: 1940 case CHIP_CARRIZO:
1934 adev->gfx.config.max_shader_engines = 1; 1941 adev->gfx.config.max_shader_engines = 1;
1935 adev->gfx.config.max_tile_pipes = 2; 1942 adev->gfx.config.max_tile_pipes = 2;
1936 adev->gfx.config.max_cu_per_sh = 8;
1937 adev->gfx.config.max_sh_per_se = 1; 1943 adev->gfx.config.max_sh_per_se = 1;
1938 adev->gfx.config.max_backends_per_se = 2; 1944
1945 switch (adev->pdev->revision) {
1946 case 0xc4:
1947 case 0x84:
1948 case 0xc8:
1949 case 0xcc:
1950 /* B10 */
1951 adev->gfx.config.max_cu_per_sh = 8;
1952 adev->gfx.config.max_backends_per_se = 2;
1953 break;
1954 case 0xc5:
1955 case 0x81:
1956 case 0x85:
1957 case 0xc9:
1958 case 0xcd:
1959 /* B8 */
1960 adev->gfx.config.max_cu_per_sh = 6;
1961 adev->gfx.config.max_backends_per_se = 2;
1962 break;
1963 case 0xc6:
1964 case 0xca:
1965 case 0xce:
1966 /* B6 */
1967 adev->gfx.config.max_cu_per_sh = 6;
1968 adev->gfx.config.max_backends_per_se = 2;
1969 break;
1970 case 0xc7:
1971 case 0x87:
1972 case 0xcb:
1973 default:
1974 /* B4 */
1975 adev->gfx.config.max_cu_per_sh = 4;
1976 adev->gfx.config.max_backends_per_se = 1;
1977 break;
1978 }
1979
1939 adev->gfx.config.max_texture_channel_caches = 2; 1980 adev->gfx.config.max_texture_channel_caches = 2;
1940 adev->gfx.config.max_gprs = 256; 1981 adev->gfx.config.max_gprs = 256;
1941 adev->gfx.config.max_gs_threads = 32; 1982 adev->gfx.config.max_gs_threads = 32;
@@ -3713,8 +3754,11 @@ static void gfx_v8_0_ring_emit_ib(struct amdgpu_ring *ring,
3713} 3754}
3714 3755
3715static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, 3756static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
3716 u64 seq, bool write64bit) 3757 u64 seq, unsigned flags)
3717{ 3758{
3759 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
3760 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
3761
3718 /* EVENT_WRITE_EOP - flush caches, send int */ 3762 /* EVENT_WRITE_EOP - flush caches, send int */
3719 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 3763 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
3720 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 3764 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
@@ -3723,7 +3767,7 @@ static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
3723 EVENT_INDEX(5))); 3767 EVENT_INDEX(5)));
3724 amdgpu_ring_write(ring, addr & 0xfffffffc); 3768 amdgpu_ring_write(ring, addr & 0xfffffffc);
3725 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 3769 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
3726 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(2)); 3770 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
3727 amdgpu_ring_write(ring, lower_32_bits(seq)); 3771 amdgpu_ring_write(ring, lower_32_bits(seq));
3728 amdgpu_ring_write(ring, upper_32_bits(seq)); 3772 amdgpu_ring_write(ring, upper_32_bits(seq));
3729} 3773}
@@ -3746,11 +3790,10 @@ static bool gfx_v8_0_ring_emit_semaphore(struct amdgpu_ring *ring,
3746 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL; 3790 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
3747 3791
3748 if (ring->adev->asic_type == CHIP_TOPAZ || 3792 if (ring->adev->asic_type == CHIP_TOPAZ ||
3749 ring->adev->asic_type == CHIP_TONGA) { 3793 ring->adev->asic_type == CHIP_TONGA)
3750 amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); 3794 /* we got a hw semaphore bug in VI TONGA, return false to switch back to sw fence wait */
3751 amdgpu_ring_write(ring, lower_32_bits(addr)); 3795 return false;
3752 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel); 3796 else {
3753 } else {
3754 amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 2)); 3797 amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 2));
3755 amdgpu_ring_write(ring, lower_32_bits(addr)); 3798 amdgpu_ring_write(ring, lower_32_bits(addr));
3756 amdgpu_ring_write(ring, upper_32_bits(addr)); 3799 amdgpu_ring_write(ring, upper_32_bits(addr));
@@ -3880,15 +3923,18 @@ static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
3880 3923
3881static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring, 3924static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
3882 u64 addr, u64 seq, 3925 u64 addr, u64 seq,
3883 bool write64bits) 3926 unsigned flags)
3884{ 3927{
3928 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
3929 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
3930
3885 /* RELEASE_MEM - flush caches, send int */ 3931 /* RELEASE_MEM - flush caches, send int */
3886 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); 3932 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
3887 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 3933 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
3888 EOP_TC_ACTION_EN | 3934 EOP_TC_ACTION_EN |
3889 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 3935 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3890 EVENT_INDEX(5))); 3936 EVENT_INDEX(5)));
3891 amdgpu_ring_write(ring, DATA_SEL(write64bits ? 2 : 1) | INT_SEL(2)); 3937 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
3892 amdgpu_ring_write(ring, addr & 0xfffffffc); 3938 amdgpu_ring_write(ring, addr & 0xfffffffc);
3893 amdgpu_ring_write(ring, upper_32_bits(addr)); 3939 amdgpu_ring_write(ring, upper_32_bits(addr));
3894 amdgpu_ring_write(ring, lower_32_bits(seq)); 3940 amdgpu_ring_write(ring, lower_32_bits(seq));
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 6206fcd39df9..8135963a66be 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -71,7 +71,7 @@ static const u32 golden_settings_iceland_a11[] =
71 71
72static const u32 iceland_mgcg_cgcg_init[] = 72static const u32 iceland_mgcg_cgcg_init[] =
73{ 73{
74 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 74 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
75}; 75};
76 76
77static const u32 cz_mgcg_cgcg_init[] = 77static const u32 cz_mgcg_cgcg_init[] =
diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c b/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c
index 4b773f29167a..208d55f41c7f 100644
--- a/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c
@@ -82,6 +82,10 @@ static int iceland_dpm_hw_init(void *handle)
82 82
83 mutex_lock(&adev->pm.mutex); 83 mutex_lock(&adev->pm.mutex);
84 84
85 /* smu init only needs to be called at startup, not resume.
86 * It should be in sw_init, but requires the fw info gathered
87 * in sw_init from other IP modules.
88 */
85 ret = iceland_smu_init(adev); 89 ret = iceland_smu_init(adev);
86 if (ret) { 90 if (ret) {
87 DRM_ERROR("SMU initialization failed\n"); 91 DRM_ERROR("SMU initialization failed\n");
@@ -108,6 +112,10 @@ static int iceland_dpm_hw_fini(void *handle)
108 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 112 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
109 113
110 mutex_lock(&adev->pm.mutex); 114 mutex_lock(&adev->pm.mutex);
115 /* smu fini only needs to be called at teardown, not suspend.
116 * It should be in sw_fini, but we put it here for symmetry
117 * with smu init.
118 */
111 iceland_smu_fini(adev); 119 iceland_smu_fini(adev);
112 mutex_unlock(&adev->pm.mutex); 120 mutex_unlock(&adev->pm.mutex);
113 return 0; 121 return 0;
@@ -115,20 +123,25 @@ static int iceland_dpm_hw_fini(void *handle)
115 123
116static int iceland_dpm_suspend(void *handle) 124static int iceland_dpm_suspend(void *handle)
117{ 125{
118 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
119
120 iceland_dpm_hw_fini(adev);
121
122 return 0; 126 return 0;
123} 127}
124 128
125static int iceland_dpm_resume(void *handle) 129static int iceland_dpm_resume(void *handle)
126{ 130{
131 int ret;
127 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 132 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
128 133
129 iceland_dpm_hw_init(adev); 134 mutex_lock(&adev->pm.mutex);
130 135
131 return 0; 136 ret = iceland_smu_start(adev);
137 if (ret) {
138 DRM_ERROR("SMU start failed\n");
139 goto fail;
140 }
141
142fail:
143 mutex_unlock(&adev->pm.mutex);
144 return ret;
132} 145}
133 146
134static int iceland_dpm_set_clockgating_state(void *handle, 147static int iceland_dpm_set_clockgating_state(void *handle,
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index d09aa7eeb40e..d7895885fe0c 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -292,8 +292,9 @@ static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring)
292 * an interrupt if needed (VI). 292 * an interrupt if needed (VI).
293 */ 293 */
294static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 294static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
295 bool write64bits) 295 unsigned flags)
296{ 296{
297 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
297 /* write the fence */ 298 /* write the fence */
298 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 299 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
299 amdgpu_ring_write(ring, lower_32_bits(addr)); 300 amdgpu_ring_write(ring, lower_32_bits(addr));
@@ -301,7 +302,7 @@ static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 se
301 amdgpu_ring_write(ring, lower_32_bits(seq)); 302 amdgpu_ring_write(ring, lower_32_bits(seq));
302 303
303 /* optionally write high bits as well */ 304 /* optionally write high bits as well */
304 if (write64bits) { 305 if (write64bit) {
305 addr += 4; 306 addr += 4;
306 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 307 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
307 amdgpu_ring_write(ring, lower_32_bits(addr)); 308 amdgpu_ring_write(ring, lower_32_bits(addr));
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 555c0e1e4c97..e3c1fde75363 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -347,8 +347,9 @@ static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
347 * an interrupt if needed (VI). 347 * an interrupt if needed (VI).
348 */ 348 */
349static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 349static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
350 bool write64bits) 350 unsigned flags)
351{ 351{
352 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
352 /* write the fence */ 353 /* write the fence */
353 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 354 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
354 amdgpu_ring_write(ring, lower_32_bits(addr)); 355 amdgpu_ring_write(ring, lower_32_bits(addr));
@@ -356,7 +357,7 @@ static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 se
356 amdgpu_ring_write(ring, lower_32_bits(seq)); 357 amdgpu_ring_write(ring, lower_32_bits(seq));
357 358
358 /* optionally write high bits as well */ 359 /* optionally write high bits as well */
359 if (write64bits) { 360 if (write64bit) {
360 addr += 4; 361 addr += 4;
361 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 362 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
362 amdgpu_ring_write(ring, lower_32_bits(addr)); 363 amdgpu_ring_write(ring, lower_32_bits(addr));
diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c b/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c
index 2d5b1bd52afa..204903897b4f 100644
--- a/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c
@@ -81,6 +81,10 @@ static int tonga_dpm_hw_init(void *handle)
81 81
82 mutex_lock(&adev->pm.mutex); 82 mutex_lock(&adev->pm.mutex);
83 83
84 /* smu init only needs to be called at startup, not resume.
85 * It should be in sw_init, but requires the fw info gathered
86 * in sw_init from other IP modules.
87 */
84 ret = tonga_smu_init(adev); 88 ret = tonga_smu_init(adev);
85 if (ret) { 89 if (ret) {
86 DRM_ERROR("SMU initialization failed\n"); 90 DRM_ERROR("SMU initialization failed\n");
@@ -107,6 +111,10 @@ static int tonga_dpm_hw_fini(void *handle)
107 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 111 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
108 112
109 mutex_lock(&adev->pm.mutex); 113 mutex_lock(&adev->pm.mutex);
114 /* smu fini only needs to be called at teardown, not suspend.
115 * It should be in sw_fini, but we put it here for symmetry
116 * with smu init.
117 */
110 tonga_smu_fini(adev); 118 tonga_smu_fini(adev);
111 mutex_unlock(&adev->pm.mutex); 119 mutex_unlock(&adev->pm.mutex);
112 return 0; 120 return 0;
@@ -114,20 +122,25 @@ static int tonga_dpm_hw_fini(void *handle)
114 122
115static int tonga_dpm_suspend(void *handle) 123static int tonga_dpm_suspend(void *handle)
116{ 124{
117 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
118
119 tonga_dpm_hw_fini(adev);
120
121 return 0; 125 return 0;
122} 126}
123 127
124static int tonga_dpm_resume(void *handle) 128static int tonga_dpm_resume(void *handle)
125{ 129{
130 int ret;
126 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 131 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
127 132
128 tonga_dpm_hw_init(adev); 133 mutex_lock(&adev->pm.mutex);
129 134
130 return 0; 135 ret = tonga_smu_start(adev);
136 if (ret) {
137 DRM_ERROR("SMU start failed\n");
138 goto fail;
139 }
140
141fail:
142 mutex_unlock(&adev->pm.mutex);
143 return ret;
131} 144}
132 145
133static int tonga_dpm_set_clockgating_state(void *handle, 146static int tonga_dpm_set_clockgating_state(void *handle,
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index 292932a73c81..4efd671d7a9b 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -417,9 +417,9 @@ static void uvd_v4_2_stop(struct amdgpu_device *adev)
417 * Write a fence and a trap command to the ring. 417 * Write a fence and a trap command to the ring.
418 */ 418 */
419static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 419static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
420 bool write64bit) 420 unsigned flags)
421{ 421{
422 WARN_ON(write64bit); 422 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
423 423
424 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 424 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
425 amdgpu_ring_write(ring, seq); 425 amdgpu_ring_write(ring, seq);
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index 004c56496fc4..b756bd99c0fd 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -461,9 +461,9 @@ static void uvd_v5_0_stop(struct amdgpu_device *adev)
461 * Write a fence and a trap command to the ring. 461 * Write a fence and a trap command to the ring.
462 */ 462 */
463static void uvd_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 463static void uvd_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
464 bool write64bit) 464 unsigned flags)
465{ 465{
466 WARN_ON(write64bit); 466 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
467 467
468 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 468 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
469 amdgpu_ring_write(ring, seq); 469 amdgpu_ring_write(ring, seq);
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 8c790fb31e2f..49aa931b2cb4 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -457,9 +457,9 @@ static void uvd_v6_0_stop(struct amdgpu_device *adev)
457 * Write a fence and a trap command to the ring. 457 * Write a fence and a trap command to the ring.
458 */ 458 */
459static void uvd_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 459static void uvd_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
460 bool write64bit) 460 unsigned flags)
461{ 461{
462 WARN_ON(write64bit); 462 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
463 463
464 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 464 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
465 amdgpu_ring_write(ring, seq); 465 amdgpu_ring_write(ring, seq);
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index be7c17610696..90fc93c2c1d0 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -173,8 +173,6 @@ static const u32 tonga_mgcg_cgcg_init[] =
173 mmPCIE_DATA, 0x000f0000, 0x00000000, 173 mmPCIE_DATA, 0x000f0000, 0x00000000,
174 mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C, 174 mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
175 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100, 175 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
176 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
177 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
178 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, 176 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
179 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 177 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
180}; 178};
@@ -193,8 +191,6 @@ static const u32 cz_mgcg_cgcg_init[] =
193 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100, 191 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
194 mmPCIE_INDEX, 0xffffffff, 0x0140001c, 192 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
195 mmPCIE_DATA, 0x000f0000, 0x00000000, 193 mmPCIE_DATA, 0x000f0000, 0x00000000,
196 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
197 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
198 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, 194 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
199 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 195 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
200}; 196};
@@ -1267,7 +1263,7 @@ static int vi_common_early_init(void *handle)
1267 case CHIP_CARRIZO: 1263 case CHIP_CARRIZO:
1268 adev->has_uvd = true; 1264 adev->has_uvd = true;
1269 adev->cg_flags = 0; 1265 adev->cg_flags = 0;
1270 adev->pg_flags = AMDGPU_PG_SUPPORT_UVD; 1266 adev->pg_flags = AMDGPU_PG_SUPPORT_UVD | AMDGPU_PG_SUPPORT_VCE;
1271 adev->external_rev_id = adev->rev_id + 0x1; 1267 adev->external_rev_id = adev->rev_id + 0x1;
1272 if (amdgpu_smc_load_fw && smc_enabled) 1268 if (amdgpu_smc_load_fw && smc_enabled)
1273 adev->firmware.smu_load = true; 1269 adev->firmware.smu_load = true;
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 780a5815fb12..d3f4832db289 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -55,7 +55,7 @@
55#define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 55#define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
56#define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 56#define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
57#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 57#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
58#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, union drm_amdgpu_gem_va) 58#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va)
59#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 59#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
60#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 60#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
61#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 61#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
@@ -139,16 +139,19 @@ union drm_amdgpu_bo_list {
139#define AMDGPU_CTX_OP_FREE_CTX 2 139#define AMDGPU_CTX_OP_FREE_CTX 2
140#define AMDGPU_CTX_OP_QUERY_STATE 3 140#define AMDGPU_CTX_OP_QUERY_STATE 3
141 141
142#define AMDGPU_CTX_OP_STATE_RUNNING 1
143
144/* GPU reset status */ 142/* GPU reset status */
145#define AMDGPU_CTX_NO_RESET 0 143#define AMDGPU_CTX_NO_RESET 0
146#define AMDGPU_CTX_GUILTY_RESET 1 /* this the context caused it */ 144/* this the context caused it */
147#define AMDGPU_CTX_INNOCENT_RESET 2 /* some other context caused it */ 145#define AMDGPU_CTX_GUILTY_RESET 1
148#define AMDGPU_CTX_UNKNOWN_RESET 3 /* unknown cause */ 146/* some other context caused it */
147#define AMDGPU_CTX_INNOCENT_RESET 2
148/* unknown cause */
149#define AMDGPU_CTX_UNKNOWN_RESET 3
149 150
150struct drm_amdgpu_ctx_in { 151struct drm_amdgpu_ctx_in {
152 /** AMDGPU_CTX_OP_* */
151 uint32_t op; 153 uint32_t op;
154 /** For future use, no flags defined so far */
152 uint32_t flags; 155 uint32_t flags;
153 uint32_t ctx_id; 156 uint32_t ctx_id;
154 uint32_t _pad; 157 uint32_t _pad;
@@ -161,6 +164,7 @@ union drm_amdgpu_ctx_out {
161 } alloc; 164 } alloc;
162 165
163 struct { 166 struct {
167 /** For future use, no flags defined so far */
164 uint64_t flags; 168 uint64_t flags;
165 /** Number of resets caused by this context so far. */ 169 /** Number of resets caused by this context so far. */
166 uint32_t hangs; 170 uint32_t hangs;
@@ -187,7 +191,9 @@ union drm_amdgpu_ctx {
187struct drm_amdgpu_gem_userptr { 191struct drm_amdgpu_gem_userptr {
188 uint64_t addr; 192 uint64_t addr;
189 uint64_t size; 193 uint64_t size;
194 /* AMDGPU_GEM_USERPTR_* */
190 uint32_t flags; 195 uint32_t flags;
196 /* Resulting GEM handle */
191 uint32_t handle; 197 uint32_t handle;
192}; 198};
193 199
@@ -219,23 +225,29 @@ struct drm_amdgpu_gem_userptr {
219 225
220/** The same structure is shared for input/output */ 226/** The same structure is shared for input/output */
221struct drm_amdgpu_gem_metadata { 227struct drm_amdgpu_gem_metadata {
222 uint32_t handle; /* GEM Object handle */ 228 /** GEM Object handle */
223 uint32_t op; /** Do we want get or set metadata */ 229 uint32_t handle;
230 /** Do we want get or set metadata */
231 uint32_t op;
224 struct { 232 struct {
233 /** For future use, no flags defined so far */
225 uint64_t flags; 234 uint64_t flags;
226 uint64_t tiling_info; /* family specific tiling info */ 235 /** family specific tiling info */
236 uint64_t tiling_info;
227 uint32_t data_size_bytes; 237 uint32_t data_size_bytes;
228 uint32_t data[64]; 238 uint32_t data[64];
229 } data; 239 } data;
230}; 240};
231 241
232struct drm_amdgpu_gem_mmap_in { 242struct drm_amdgpu_gem_mmap_in {
233 uint32_t handle; /** the GEM object handle */ 243 /** the GEM object handle */
244 uint32_t handle;
234 uint32_t _pad; 245 uint32_t _pad;
235}; 246};
236 247
237struct drm_amdgpu_gem_mmap_out { 248struct drm_amdgpu_gem_mmap_out {
238 uint64_t addr_ptr; /** mmap offset from the vma offset manager */ 249 /** mmap offset from the vma offset manager */
250 uint64_t addr_ptr;
239}; 251};
240 252
241union drm_amdgpu_gem_mmap { 253union drm_amdgpu_gem_mmap {
@@ -244,14 +256,19 @@ union drm_amdgpu_gem_mmap {
244}; 256};
245 257
246struct drm_amdgpu_gem_wait_idle_in { 258struct drm_amdgpu_gem_wait_idle_in {
247 uint32_t handle; /* GEM object handle */ 259 /** GEM object handle */
260 uint32_t handle;
261 /** For future use, no flags defined so far */
248 uint32_t flags; 262 uint32_t flags;
249 uint64_t timeout; /* Timeout to wait. If 0 then returned immediately with the status */ 263 /** Absolute timeout to wait */
264 uint64_t timeout;
250}; 265};
251 266
252struct drm_amdgpu_gem_wait_idle_out { 267struct drm_amdgpu_gem_wait_idle_out {
253 uint32_t status; /* BO status: 0 - BO is idle, 1 - BO is busy */ 268 /** BO status: 0 - BO is idle, 1 - BO is busy */
254 uint32_t domain; /* Returned current memory domain */ 269 uint32_t status;
270 /** Returned current memory domain */
271 uint32_t domain;
255}; 272};
256 273
257union drm_amdgpu_gem_wait_idle { 274union drm_amdgpu_gem_wait_idle {
@@ -260,7 +277,9 @@ union drm_amdgpu_gem_wait_idle {
260}; 277};
261 278
262struct drm_amdgpu_wait_cs_in { 279struct drm_amdgpu_wait_cs_in {
280 /** Command submission handle */
263 uint64_t handle; 281 uint64_t handle;
282 /** Absolute timeout to wait */
264 uint64_t timeout; 283 uint64_t timeout;
265 uint32_t ip_type; 284 uint32_t ip_type;
266 uint32_t ip_instance; 285 uint32_t ip_instance;
@@ -269,6 +288,7 @@ struct drm_amdgpu_wait_cs_in {
269}; 288};
270 289
271struct drm_amdgpu_wait_cs_out { 290struct drm_amdgpu_wait_cs_out {
291 /** CS status: 0 - CS completed, 1 - CS still busy */
272 uint64_t status; 292 uint64_t status;
273}; 293};
274 294
@@ -277,23 +297,22 @@ union drm_amdgpu_wait_cs {
277 struct drm_amdgpu_wait_cs_out out; 297 struct drm_amdgpu_wait_cs_out out;
278}; 298};
279 299
300#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0
301#define AMDGPU_GEM_OP_SET_PLACEMENT 1
302
280/* Sets or returns a value associated with a buffer. */ 303/* Sets or returns a value associated with a buffer. */
281struct drm_amdgpu_gem_op { 304struct drm_amdgpu_gem_op {
282 uint32_t handle; /* buffer */ 305 /** GEM object handle */
283 uint32_t op; /* AMDGPU_GEM_OP_* */ 306 uint32_t handle;
284 uint64_t value; /* input or return value */ 307 /** AMDGPU_GEM_OP_* */
308 uint32_t op;
309 /** Input or return value */
310 uint64_t value;
285}; 311};
286 312
287#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0
288#define AMDGPU_GEM_OP_SET_PLACEMENT 1
289
290#define AMDGPU_VA_OP_MAP 1 313#define AMDGPU_VA_OP_MAP 1
291#define AMDGPU_VA_OP_UNMAP 2 314#define AMDGPU_VA_OP_UNMAP 2
292 315
293#define AMDGPU_VA_RESULT_OK 0
294#define AMDGPU_VA_RESULT_ERROR 1
295#define AMDGPU_VA_RESULT_VA_INVALID_ALIGNMENT 2
296
297/* Mapping flags */ 316/* Mapping flags */
298/* readable mapping */ 317/* readable mapping */
299#define AMDGPU_VM_PAGE_READABLE (1 << 1) 318#define AMDGPU_VM_PAGE_READABLE (1 << 1)
@@ -302,33 +321,22 @@ struct drm_amdgpu_gem_op {
302/* executable mapping, new for VI */ 321/* executable mapping, new for VI */
303#define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 322#define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3)
304 323
305struct drm_amdgpu_gem_va_in { 324struct drm_amdgpu_gem_va {
306 /* GEM object handle */ 325 /** GEM object handle */
307 uint32_t handle; 326 uint32_t handle;
308 uint32_t _pad; 327 uint32_t _pad;
309 /* map or unmap*/ 328 /** AMDGPU_VA_OP_* */
310 uint32_t operation; 329 uint32_t operation;
311 /* specify mapping flags */ 330 /** AMDGPU_VM_PAGE_* */
312 uint32_t flags; 331 uint32_t flags;
313 /* va address to assign . Must be correctly aligned.*/ 332 /** va address to assign . Must be correctly aligned.*/
314 uint64_t va_address; 333 uint64_t va_address;
315 /* Specify offset inside of BO to assign. Must be correctly aligned.*/ 334 /** Specify offset inside of BO to assign. Must be correctly aligned.*/
316 uint64_t offset_in_bo; 335 uint64_t offset_in_bo;
317 /* Specify mapping size. If 0 and offset is 0 then map the whole BO.*/ 336 /** Specify mapping size. Must be correctly aligned. */
318 /* Must be correctly aligned. */
319 uint64_t map_size; 337 uint64_t map_size;
320}; 338};
321 339
322struct drm_amdgpu_gem_va_out {
323 uint32_t result;
324 uint32_t _pad;
325};
326
327union drm_amdgpu_gem_va {
328 struct drm_amdgpu_gem_va_in in;
329 struct drm_amdgpu_gem_va_out out;
330};
331
332#define AMDGPU_HW_IP_GFX 0 340#define AMDGPU_HW_IP_GFX 0
333#define AMDGPU_HW_IP_COMPUTE 1 341#define AMDGPU_HW_IP_COMPUTE 1
334#define AMDGPU_HW_IP_DMA 2 342#define AMDGPU_HW_IP_DMA 2
@@ -340,6 +348,7 @@ union drm_amdgpu_gem_va {
340 348
341#define AMDGPU_CHUNK_ID_IB 0x01 349#define AMDGPU_CHUNK_ID_IB 0x01
342#define AMDGPU_CHUNK_ID_FENCE 0x02 350#define AMDGPU_CHUNK_ID_FENCE 0x02
351
343struct drm_amdgpu_cs_chunk { 352struct drm_amdgpu_cs_chunk {
344 uint32_t chunk_id; 353 uint32_t chunk_id;
345 uint32_t length_dw; 354 uint32_t length_dw;
@@ -353,7 +362,7 @@ struct drm_amdgpu_cs_in {
353 uint32_t bo_list_handle; 362 uint32_t bo_list_handle;
354 uint32_t num_chunks; 363 uint32_t num_chunks;
355 uint32_t _pad; 364 uint32_t _pad;
356 /* this points to uint64_t * which point to cs chunks */ 365 /** this points to uint64_t * which point to cs chunks */
357 uint64_t chunks; 366 uint64_t chunks;
358}; 367};
359 368
@@ -362,8 +371,8 @@ struct drm_amdgpu_cs_out {
362}; 371};
363 372
364union drm_amdgpu_cs { 373union drm_amdgpu_cs {
365 struct drm_amdgpu_cs_in in; 374 struct drm_amdgpu_cs_in in;
366 struct drm_amdgpu_cs_out out; 375 struct drm_amdgpu_cs_out out;
367}; 376};
368 377
369/* Specify flags to be used for IB */ 378/* Specify flags to be used for IB */
@@ -371,20 +380,23 @@ union drm_amdgpu_cs {
371/* This IB should be submitted to CE */ 380/* This IB should be submitted to CE */
372#define AMDGPU_IB_FLAG_CE (1<<0) 381#define AMDGPU_IB_FLAG_CE (1<<0)
373 382
374/* GDS is used by this IB */
375#define AMDGPU_IB_FLAG_GDS (1<<1)
376
377/* CE Preamble */ 383/* CE Preamble */
378#define AMDGPU_IB_FLAG_PREAMBLE (1<<2) 384#define AMDGPU_IB_FLAG_PREAMBLE (1<<1)
379 385
380struct drm_amdgpu_cs_chunk_ib { 386struct drm_amdgpu_cs_chunk_ib {
381 uint32_t _pad; 387 uint32_t _pad;
382 uint32_t flags; /* IB Flags */ 388 /** AMDGPU_IB_FLAG_* */
383 uint64_t va_start; /* Virtual address to begin IB execution */ 389 uint32_t flags;
384 uint32_t ib_bytes; /* Size of submission */ 390 /** Virtual address to begin IB execution */
385 uint32_t ip_type; /* HW IP to submit to */ 391 uint64_t va_start;
386 uint32_t ip_instance; /* HW IP index of the same type to submit to */ 392 /** Size of submission */
387 uint32_t ring; /* Ring index to submit to */ 393 uint32_t ib_bytes;
394 /** HW IP to submit to */
395 uint32_t ip_type;
396 /** HW IP index of the same type to submit to */
397 uint32_t ip_instance;
398 /** Ring index to submit to */
399 uint32_t ring;
388}; 400};
389 401
390struct drm_amdgpu_cs_chunk_fence { 402struct drm_amdgpu_cs_chunk_fence {
@@ -479,23 +491,28 @@ struct drm_amdgpu_info {
479 /** AMDGPU_HW_IP_* */ 491 /** AMDGPU_HW_IP_* */
480 uint32_t type; 492 uint32_t type;
481 /** 493 /**
482 * Index of the IP if there are more IPs of the same type. 494 * Index of the IP if there are more IPs of the same
483 * Ignored by AMDGPU_INFO_HW_IP_COUNT. 495 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT.
484 */ 496 */
485 uint32_t ip_instance; 497 uint32_t ip_instance;
486 } query_hw_ip; 498 } query_hw_ip;
487 499
488 struct { 500 struct {
489 uint32_t dword_offset; 501 uint32_t dword_offset;
490 uint32_t count; /* number of registers to read */ 502 /** number of registers to read */
503 uint32_t count;
491 uint32_t instance; 504 uint32_t instance;
505 /** For future use, no flags defined so far */
492 uint32_t flags; 506 uint32_t flags;
493 } read_mmr_reg; 507 } read_mmr_reg;
494 508
495 struct { 509 struct {
496 /** AMDGPU_INFO_FW_* */ 510 /** AMDGPU_INFO_FW_* */
497 uint32_t fw_type; 511 uint32_t fw_type;
498 /** Index of the IP if there are more IPs of the same type. */ 512 /**
513 * Index of the IP if there are more IPs of
514 * the same type.
515 */
499 uint32_t ip_instance; 516 uint32_t ip_instance;
500 /** 517 /**
501 * Index of the engine. Whether this is used depends 518 * Index of the engine. Whether this is used depends
@@ -556,9 +573,10 @@ struct drm_amdgpu_info_device {
556 uint32_t family; 573 uint32_t family;
557 uint32_t num_shader_engines; 574 uint32_t num_shader_engines;
558 uint32_t num_shader_arrays_per_engine; 575 uint32_t num_shader_arrays_per_engine;
559 uint32_t gpu_counter_freq; /* in KHz */ 576 /* in KHz */
560 uint64_t max_engine_clock; /* in KHz */ 577 uint32_t gpu_counter_freq;
561 uint64_t max_memory_clock; /* in KHz */ 578 uint64_t max_engine_clock;
579 uint64_t max_memory_clock;
562 /* cu information */ 580 /* cu information */
563 uint32_t cu_active_number; 581 uint32_t cu_active_number;
564 uint32_t cu_ao_mask; 582 uint32_t cu_ao_mask;
@@ -580,7 +598,7 @@ struct drm_amdgpu_info_device {
580 uint32_t gart_page_size; 598 uint32_t gart_page_size;
581 /** constant engine ram size*/ 599 /** constant engine ram size*/
582 uint32_t ce_ram_size; 600 uint32_t ce_ram_size;
583 /** video memory type infro*/ 601 /** video memory type info*/
584 uint32_t vram_type; 602 uint32_t vram_type;
585 /** video memory bit width*/ 603 /** video memory bit width*/
586 uint32_t vram_bit_width; 604 uint32_t vram_bit_width;
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-24 08:09:15 -0400