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authorDave Airlie <airlied@redhat.com>2016-11-06 18:19:23 -0500
committerDave Airlie <airlied@redhat.com>2016-11-06 18:19:23 -0500
commitdc345c46774bc150ab852d2c74ee6542de438d46 (patch)
treecaf3e15fd648b4c3ead39641a67e911d9be959c1
parentfb422950c6cd726fd36eb72a7cf84583440a18a2 (diff)
parentd7b56e6f4e34b6d182b3c4e03c1bd88a3acfb210 (diff)
Merge tag 'omapdrm-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linux into drm-next
omapdrm changes for v4.10 The main change here is the big refactoring to remove omapdrm's own 'omap_video_timings', and use the standard display timings. Besides that, a few minor fixes and cleanups.
Diffstat
-rw-r--r--Documentation/devicetree/bindings/display/panel/display-timing.txt8
-rw-r--r--drivers/gpu/drm/omapdrm/displays/connector-analog-tv.c47
-rw-r--r--drivers/gpu/drm/omapdrm/displays/connector-dvi.c50
-rw-r--r--drivers/gpu/drm/omapdrm/displays/connector-hdmi.c49
-rw-r--r--drivers/gpu/drm/omapdrm/displays/encoder-opa362.c20
-rw-r--r--drivers/gpu/drm/omapdrm/displays/encoder-tfp410.c31
-rw-r--r--drivers/gpu/drm/omapdrm/displays/encoder-tpd12s015.c20
-rw-r--r--drivers/gpu/drm/omapdrm/displays/panel-dpi.c30
-rw-r--r--drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c25
-rw-r--r--drivers/gpu/drm/omapdrm/displays/panel-lgphilips-lb035q02.c59
-rw-r--r--drivers/gpu/drm/omapdrm/displays/panel-nec-nl8048hl11.c52
-rw-r--r--drivers/gpu/drm/omapdrm/displays/panel-sharp-ls037v7dw01.c58
-rw-r--r--drivers/gpu/drm/omapdrm/displays/panel-sony-acx565akm.c53
-rw-r--r--drivers/gpu/drm/omapdrm/displays/panel-tpo-td028ttec1.c57
-rw-r--r--drivers/gpu/drm/omapdrm/displays/panel-tpo-td043mtea1.c54
-rw-r--r--drivers/gpu/drm/omapdrm/dss/dispc.c228
-rw-r--r--drivers/gpu/drm/omapdrm/dss/display.c78
-rw-r--r--drivers/gpu/drm/omapdrm/dss/dpi.c40
-rw-r--r--drivers/gpu/drm/omapdrm/dss/dsi.c160
-rw-r--r--drivers/gpu/drm/omapdrm/dss/dss.h5
-rw-r--r--drivers/gpu/drm/omapdrm/dss/hdmi.h8
-rw-r--r--drivers/gpu/drm/omapdrm/dss/hdmi4.c31
-rw-r--r--drivers/gpu/drm/omapdrm/dss/hdmi4_core.c8
-rw-r--r--drivers/gpu/drm/omapdrm/dss/hdmi5.c31
-rw-r--r--drivers/gpu/drm/omapdrm/dss/hdmi5_core.c85
-rw-r--r--drivers/gpu/drm/omapdrm/dss/hdmi_wp.c73
-rw-r--r--drivers/gpu/drm/omapdrm/dss/omapdss.h98
-rw-r--r--drivers/gpu/drm/omapdrm/dss/output.c5
-rw-r--r--drivers/gpu/drm/omapdrm/dss/rfbi.c49
-rw-r--r--drivers/gpu/drm/omapdrm/dss/sdi.c33
-rw-r--r--drivers/gpu/drm/omapdrm/dss/venc.c97
-rw-r--r--drivers/gpu/drm/omapdrm/omap_connector.c87
-rw-r--r--drivers/gpu/drm/omapdrm/omap_crtc.c30
-rw-r--r--drivers/gpu/drm/omapdrm/omap_drv.h7
-rw-r--r--drivers/gpu/drm/omapdrm/omap_encoder.c10
-rw-r--r--drivers/gpu/drm/omapdrm/omap_gem.c6
-rw-r--r--drivers/gpu/drm/omapdrm/omap_plane.c28
-rw-r--r--drivers/video/of_display_timing.c9
-rw-r--r--include/video/display_timing.h4
39 files changed, 807 insertions, 1016 deletions
diff --git a/Documentation/devicetree/bindings/display/panel/display-timing.txt b/Documentation/devicetree/bindings/display/panel/display-timing.txt
index e1d4a0b59612..81a75893d1b8 100644
--- a/Documentation/devicetree/bindings/display/panel/display-timing.txt
+++ b/Documentation/devicetree/bindings/display/panel/display-timing.txt
@@ -32,6 +32,14 @@ optional properties:
32 - active low = drive pixel data on falling edge/ 32 - active low = drive pixel data on falling edge/
33 sample data on rising edge 33 sample data on rising edge
34 - ignored = ignored 34 - ignored = ignored
35 - syncclk-active: with
36 - active high = drive sync on rising edge/
37 sample sync on falling edge of pixel
38 clock
39 - active low = drive sync on falling edge/
40 sample sync on rising edge of pixel
41 clock
42 - omitted = same configuration as pixelclk-active
35 - interlaced (bool): boolean to enable interlaced mode 43 - interlaced (bool): boolean to enable interlaced mode
36 - doublescan (bool): boolean to enable doublescan mode 44 - doublescan (bool): boolean to enable doublescan mode
37 - doubleclk (bool): boolean to enable doubleclock mode 45 - doubleclk (bool): boolean to enable doubleclock mode
diff --git a/drivers/gpu/drm/omapdrm/displays/connector-analog-tv.c b/drivers/gpu/drm/omapdrm/displays/connector-analog-tv.c
index 3485d1ecd655..aaa8a58390f1 100644
--- a/drivers/gpu/drm/omapdrm/displays/connector-analog-tv.c
+++ b/drivers/gpu/drm/omapdrm/displays/connector-analog-tv.c
@@ -24,23 +24,24 @@ struct panel_drv_data {
24 24
25 struct device *dev; 25 struct device *dev;
26 26
27 struct omap_video_timings timings; 27 struct videomode vm;
28 28
29 bool invert_polarity; 29 bool invert_polarity;
30}; 30};
31 31
32static const struct omap_video_timings tvc_pal_timings = { 32static const struct videomode tvc_pal_vm = {
33 .x_res = 720, 33 .hactive = 720,
34 .y_res = 574, 34 .vactive = 574,
35 .pixelclock = 13500000, 35 .pixelclock = 13500000,
36 .hsw = 64, 36 .hsync_len = 64,
37 .hfp = 12, 37 .hfront_porch = 12,
38 .hbp = 68, 38 .hback_porch = 68,
39 .vsw = 5, 39 .vsync_len = 5,
40 .vfp = 5, 40 .vfront_porch = 5,
41 .vbp = 41, 41 .vback_porch = 41,
42 42
43 .interlace = true, 43 .flags = DISPLAY_FLAGS_INTERLACED | DISPLAY_FLAGS_HSYNC_LOW |
44 DISPLAY_FLAGS_VSYNC_LOW,
44}; 45};
45 46
46static const struct of_device_id tvc_of_match[]; 47static const struct of_device_id tvc_of_match[];
@@ -92,7 +93,7 @@ static int tvc_enable(struct omap_dss_device *dssdev)
92 if (omapdss_device_is_enabled(dssdev)) 93 if (omapdss_device_is_enabled(dssdev))
93 return 0; 94 return 0;
94 95
95 in->ops.atv->set_timings(in, &ddata->timings); 96 in->ops.atv->set_timings(in, &ddata->vm);
96 97
97 if (!ddata->dev->of_node) { 98 if (!ddata->dev->of_node) {
98 in->ops.atv->set_type(in, OMAP_DSS_VENC_TYPE_COMPOSITE); 99 in->ops.atv->set_type(in, OMAP_DSS_VENC_TYPE_COMPOSITE);
@@ -126,32 +127,32 @@ static void tvc_disable(struct omap_dss_device *dssdev)
126} 127}
127 128
128static void tvc_set_timings(struct omap_dss_device *dssdev, 129static void tvc_set_timings(struct omap_dss_device *dssdev,
129 struct omap_video_timings *timings) 130 struct videomode *vm)
130{ 131{
131 struct panel_drv_data *ddata = to_panel_data(dssdev); 132 struct panel_drv_data *ddata = to_panel_data(dssdev);
132 struct omap_dss_device *in = ddata->in; 133 struct omap_dss_device *in = ddata->in;
133 134
134 ddata->timings = *timings; 135 ddata->vm = *vm;
135 dssdev->panel.timings = *timings; 136 dssdev->panel.vm = *vm;
136 137
137 in->ops.atv->set_timings(in, timings); 138 in->ops.atv->set_timings(in, vm);
138} 139}
139 140
140static void tvc_get_timings(struct omap_dss_device *dssdev, 141static void tvc_get_timings(struct omap_dss_device *dssdev,
141 struct omap_video_timings *timings) 142 struct videomode *vm)
142{ 143{
143 struct panel_drv_data *ddata = to_panel_data(dssdev); 144 struct panel_drv_data *ddata = to_panel_data(dssdev);
144 145
145 *timings = ddata->timings; 146 *vm = ddata->vm;
146} 147}
147 148
148static int tvc_check_timings(struct omap_dss_device *dssdev, 149static int tvc_check_timings(struct omap_dss_device *dssdev,
149 struct omap_video_timings *timings) 150 struct videomode *vm)
150{ 151{
151 struct panel_drv_data *ddata = to_panel_data(dssdev); 152 struct panel_drv_data *ddata = to_panel_data(dssdev);
152 struct omap_dss_device *in = ddata->in; 153 struct omap_dss_device *in = ddata->in;
153 154
154 return in->ops.atv->check_timings(in, timings); 155 return in->ops.atv->check_timings(in, vm);
155} 156}
156 157
157static u32 tvc_get_wss(struct omap_dss_device *dssdev) 158static u32 tvc_get_wss(struct omap_dss_device *dssdev)
@@ -253,14 +254,14 @@ static int tvc_probe(struct platform_device *pdev)
253 return -ENODEV; 254 return -ENODEV;
254 } 255 }
255 256
256 ddata->timings = tvc_pal_timings; 257 ddata->vm = tvc_pal_vm;
257 258
258 dssdev = &ddata->dssdev; 259 dssdev = &ddata->dssdev;
259 dssdev->driver = &tvc_driver; 260 dssdev->driver = &tvc_driver;
260 dssdev->dev = &pdev->dev; 261 dssdev->dev = &pdev->dev;
261 dssdev->type = OMAP_DISPLAY_TYPE_VENC; 262 dssdev->type = OMAP_DISPLAY_TYPE_VENC;
262 dssdev->owner = THIS_MODULE; 263 dssdev->owner = THIS_MODULE;
263 dssdev->panel.timings = tvc_pal_timings; 264 dssdev->panel.vm = tvc_pal_vm;
264 265
265 r = omapdss_register_display(dssdev); 266 r = omapdss_register_display(dssdev);
266 if (r) { 267 if (r) {
diff --git a/drivers/gpu/drm/omapdrm/displays/connector-dvi.c b/drivers/gpu/drm/omapdrm/displays/connector-dvi.c
index 684b7aeda411..d6875d9fcefa 100644
--- a/drivers/gpu/drm/omapdrm/displays/connector-dvi.c
+++ b/drivers/gpu/drm/omapdrm/displays/connector-dvi.c
@@ -19,32 +19,30 @@
19 19
20#include "../dss/omapdss.h" 20#include "../dss/omapdss.h"
21 21
22static const struct omap_video_timings dvic_default_timings = { 22static const struct videomode dvic_default_vm = {
23 .x_res = 640, 23 .hactive = 640,
24 .y_res = 480, 24 .vactive = 480,
25 25
26 .pixelclock = 23500000, 26 .pixelclock = 23500000,
27 27
28 .hfp = 48, 28 .hfront_porch = 48,
29 .hsw = 32, 29 .hsync_len = 32,
30 .hbp = 80, 30 .hback_porch = 80,
31 31
32 .vfp = 3, 32 .vfront_porch = 3,
33 .vsw = 4, 33 .vsync_len = 4,
34 .vbp = 7, 34 .vback_porch = 7,
35 35
36 .vsync_level = OMAPDSS_SIG_ACTIVE_HIGH, 36 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
37 .hsync_level = OMAPDSS_SIG_ACTIVE_HIGH, 37 DISPLAY_FLAGS_SYNC_NEGEDGE | DISPLAY_FLAGS_DE_HIGH |
38 .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE, 38 DISPLAY_FLAGS_PIXDATA_POSEDGE,
39 .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
40 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
41}; 39};
42 40
43struct panel_drv_data { 41struct panel_drv_data {
44 struct omap_dss_device dssdev; 42 struct omap_dss_device dssdev;
45 struct omap_dss_device *in; 43 struct omap_dss_device *in;
46 44
47 struct omap_video_timings timings; 45 struct videomode vm;
48 46
49 struct i2c_adapter *i2c_adapter; 47 struct i2c_adapter *i2c_adapter;
50}; 48};
@@ -90,7 +88,7 @@ static int dvic_enable(struct omap_dss_device *dssdev)
90 if (omapdss_device_is_enabled(dssdev)) 88 if (omapdss_device_is_enabled(dssdev))
91 return 0; 89 return 0;
92 90
93 in->ops.dvi->set_timings(in, &ddata->timings); 91 in->ops.dvi->set_timings(in, &ddata->vm);
94 92
95 r = in->ops.dvi->enable(in); 93 r = in->ops.dvi->enable(in);
96 if (r) 94 if (r)
@@ -115,32 +113,32 @@ static void dvic_disable(struct omap_dss_device *dssdev)
115} 113}
116 114
117static void dvic_set_timings(struct omap_dss_device *dssdev, 115static void dvic_set_timings(struct omap_dss_device *dssdev,
118 struct omap_video_timings *timings) 116 struct videomode *vm)
119{ 117{
120 struct panel_drv_data *ddata = to_panel_data(dssdev); 118 struct panel_drv_data *ddata = to_panel_data(dssdev);
121 struct omap_dss_device *in = ddata->in; 119 struct omap_dss_device *in = ddata->in;
122 120
123 ddata->timings = *timings; 121 ddata->vm = *vm;
124 dssdev->panel.timings = *timings; 122 dssdev->panel.vm = *vm;
125 123
126 in->ops.dvi->set_timings(in, timings); 124 in->ops.dvi->set_timings(in, vm);
127} 125}
128 126
129static void dvic_get_timings(struct omap_dss_device *dssdev, 127static void dvic_get_timings(struct omap_dss_device *dssdev,
130 struct omap_video_timings *timings) 128 struct videomode *vm)
131{ 129{
132 struct panel_drv_data *ddata = to_panel_data(dssdev); 130 struct panel_drv_data *ddata = to_panel_data(dssdev);
133 131
134 *timings = ddata->timings; 132 *vm = ddata->vm;
135} 133}
136 134
137static int dvic_check_timings(struct omap_dss_device *dssdev, 135static int dvic_check_timings(struct omap_dss_device *dssdev,
138 struct omap_video_timings *timings) 136 struct videomode *vm)
139{ 137{
140 struct panel_drv_data *ddata = to_panel_data(dssdev); 138 struct panel_drv_data *ddata = to_panel_data(dssdev);
141 struct omap_dss_device *in = ddata->in; 139 struct omap_dss_device *in = ddata->in;
142 140
143 return in->ops.dvi->check_timings(in, timings); 141 return in->ops.dvi->check_timings(in, vm);
144} 142}
145 143
146static int dvic_ddc_read(struct i2c_adapter *adapter, 144static int dvic_ddc_read(struct i2c_adapter *adapter,
@@ -287,14 +285,14 @@ static int dvic_probe(struct platform_device *pdev)
287 if (r) 285 if (r)
288 return r; 286 return r;
289 287
290 ddata->timings = dvic_default_timings; 288 ddata->vm = dvic_default_vm;
291 289
292 dssdev = &ddata->dssdev; 290 dssdev = &ddata->dssdev;
293 dssdev->driver = &dvic_driver; 291 dssdev->driver = &dvic_driver;
294 dssdev->dev = &pdev->dev; 292 dssdev->dev = &pdev->dev;
295 dssdev->type = OMAP_DISPLAY_TYPE_DVI; 293 dssdev->type = OMAP_DISPLAY_TYPE_DVI;
296 dssdev->owner = THIS_MODULE; 294 dssdev->owner = THIS_MODULE;
297 dssdev->panel.timings = dvic_default_timings; 295 dssdev->panel.vm = dvic_default_vm;
298 296
299 r = omapdss_register_display(dssdev); 297 r = omapdss_register_display(dssdev);
300 if (r) { 298 if (r) {
diff --git a/drivers/gpu/drm/omapdrm/displays/connector-hdmi.c b/drivers/gpu/drm/omapdrm/displays/connector-hdmi.c
index 7bdf83af9797..1ef130641bae 100644
--- a/drivers/gpu/drm/omapdrm/displays/connector-hdmi.c
+++ b/drivers/gpu/drm/omapdrm/displays/connector-hdmi.c
@@ -21,21 +21,18 @@
21 21
22#include "../dss/omapdss.h" 22#include "../dss/omapdss.h"
23 23
24static const struct omap_video_timings hdmic_default_timings = { 24static const struct videomode hdmic_default_vm = {
25 .x_res = 640, 25 .hactive = 640,
26 .y_res = 480, 26 .vactive = 480,
27 .pixelclock = 25175000, 27 .pixelclock = 25175000,
28 .hsw = 96, 28 .hsync_len = 96,
29 .hfp = 16, 29 .hfront_porch = 16,
30 .hbp = 48, 30 .hback_porch = 48,
31 .vsw = 2, 31 .vsync_len = 2,
32 .vfp = 11, 32 .vfront_porch = 11,
33 .vbp = 31, 33 .vback_porch = 31,
34 34
35 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW, 35 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
36 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
37
38 .interlace = false,
39}; 36};
40 37
41struct panel_drv_data { 38struct panel_drv_data {
@@ -44,7 +41,7 @@ struct panel_drv_data {
44 41
45 struct device *dev; 42 struct device *dev;
46 43
47 struct omap_video_timings timings; 44 struct videomode vm;
48 45
49 int hpd_gpio; 46 int hpd_gpio;
50}; 47};
@@ -96,7 +93,7 @@ static int hdmic_enable(struct omap_dss_device *dssdev)
96 if (omapdss_device_is_enabled(dssdev)) 93 if (omapdss_device_is_enabled(dssdev))
97 return 0; 94 return 0;
98 95
99 in->ops.hdmi->set_timings(in, &ddata->timings); 96 in->ops.hdmi->set_timings(in, &ddata->vm);
100 97
101 r = in->ops.hdmi->enable(in); 98 r = in->ops.hdmi->enable(in);
102 if (r) 99 if (r)
@@ -123,32 +120,32 @@ static void hdmic_disable(struct omap_dss_device *dssdev)
123} 120}
124 121
125static void hdmic_set_timings(struct omap_dss_device *dssdev, 122static void hdmic_set_timings(struct omap_dss_device *dssdev,
126 struct omap_video_timings *timings) 123 struct videomode *vm)
127{ 124{
128 struct panel_drv_data *ddata = to_panel_data(dssdev); 125 struct panel_drv_data *ddata = to_panel_data(dssdev);
129 struct omap_dss_device *in = ddata->in; 126 struct omap_dss_device *in = ddata->in;
130 127
131 ddata->timings = *timings; 128 ddata->vm = *vm;
132 dssdev->panel.timings = *timings; 129 dssdev->panel.vm = *vm;
133 130
134 in->ops.hdmi->set_timings(in, timings); 131 in->ops.hdmi->set_timings(in, vm);
135} 132}
136 133
137static void hdmic_get_timings(struct omap_dss_device *dssdev, 134static void hdmic_get_timings(struct omap_dss_device *dssdev,
138 struct omap_video_timings *timings) 135 struct videomode *vm)
139{ 136{
140 struct panel_drv_data *ddata = to_panel_data(dssdev); 137 struct panel_drv_data *ddata = to_panel_data(dssdev);
141 138
142 *timings = ddata->timings; 139 *vm = ddata->vm;
143} 140}
144 141
145static int hdmic_check_timings(struct omap_dss_device *dssdev, 142static int hdmic_check_timings(struct omap_dss_device *dssdev,
146 struct omap_video_timings *timings) 143 struct videomode *vm)
147{ 144{
148 struct panel_drv_data *ddata = to_panel_data(dssdev); 145 struct panel_drv_data *ddata = to_panel_data(dssdev);
149 struct omap_dss_device *in = ddata->in; 146 struct omap_dss_device *in = ddata->in;
150 147
151 return in->ops.hdmi->check_timings(in, timings); 148 return in->ops.hdmi->check_timings(in, vm);
152} 149}
153 150
154static int hdmic_read_edid(struct omap_dss_device *dssdev, 151static int hdmic_read_edid(struct omap_dss_device *dssdev,
@@ -259,14 +256,14 @@ static int hdmic_probe(struct platform_device *pdev)
259 goto err_reg; 256 goto err_reg;
260 } 257 }
261 258
262 ddata->timings = hdmic_default_timings; 259 ddata->vm = hdmic_default_vm;
263 260
264 dssdev = &ddata->dssdev; 261 dssdev = &ddata->dssdev;
265 dssdev->driver = &hdmic_driver; 262 dssdev->driver = &hdmic_driver;
266 dssdev->dev = &pdev->dev; 263 dssdev->dev = &pdev->dev;
267 dssdev->type = OMAP_DISPLAY_TYPE_HDMI; 264 dssdev->type = OMAP_DISPLAY_TYPE_HDMI;
268 dssdev->owner = THIS_MODULE; 265 dssdev->owner = THIS_MODULE;
269 dssdev->panel.timings = hdmic_default_timings; 266 dssdev->panel.vm = hdmic_default_vm;
270 267
271 r = omapdss_register_display(dssdev); 268 r = omapdss_register_display(dssdev);
272 if (r) { 269 if (r) {
diff --git a/drivers/gpu/drm/omapdrm/displays/encoder-opa362.c b/drivers/gpu/drm/omapdrm/displays/encoder-opa362.c
index fe4e7ec3bab0..f7a5731492d0 100644
--- a/drivers/gpu/drm/omapdrm/displays/encoder-opa362.c
+++ b/drivers/gpu/drm/omapdrm/displays/encoder-opa362.c
@@ -27,7 +27,7 @@ struct panel_drv_data {
27 27
28 struct gpio_desc *enable_gpio; 28 struct gpio_desc *enable_gpio;
29 29
30 struct omap_video_timings timings; 30 struct videomode vm;
31}; 31};
32 32
33#define to_panel_data(x) container_of(x, struct panel_drv_data, dssdev) 33#define to_panel_data(x) container_of(x, struct panel_drv_data, dssdev)
@@ -90,7 +90,7 @@ static int opa362_enable(struct omap_dss_device *dssdev)
90 if (omapdss_device_is_enabled(dssdev)) 90 if (omapdss_device_is_enabled(dssdev))
91 return 0; 91 return 0;
92 92
93 in->ops.atv->set_timings(in, &ddata->timings); 93 in->ops.atv->set_timings(in, &ddata->vm);
94 94
95 r = in->ops.atv->enable(in); 95 r = in->ops.atv->enable(in);
96 if (r) 96 if (r)
@@ -123,38 +123,38 @@ static void opa362_disable(struct omap_dss_device *dssdev)
123} 123}
124 124
125static void opa362_set_timings(struct omap_dss_device *dssdev, 125static void opa362_set_timings(struct omap_dss_device *dssdev,
126 struct omap_video_timings *timings) 126 struct videomode *vm)
127{ 127{
128 struct panel_drv_data *ddata = to_panel_data(dssdev); 128 struct panel_drv_data *ddata = to_panel_data(dssdev);
129 struct omap_dss_device *in = ddata->in; 129 struct omap_dss_device *in = ddata->in;
130 130
131 dev_dbg(dssdev->dev, "set_timings\n"); 131 dev_dbg(dssdev->dev, "set_timings\n");
132 132
133 ddata->timings = *timings; 133 ddata->vm = *vm;
134 dssdev->panel.timings = *timings; 134 dssdev->panel.vm = *vm;
135 135
136 in->ops.atv->set_timings(in, timings); 136 in->ops.atv->set_timings(in, vm);
137} 137}
138 138
139static void opa362_get_timings(struct omap_dss_device *dssdev, 139static void opa362_get_timings(struct omap_dss_device *dssdev,
140 struct omap_video_timings *timings) 140 struct videomode *vm)
141{ 141{
142 struct panel_drv_data *ddata = to_panel_data(dssdev); 142 struct panel_drv_data *ddata = to_panel_data(dssdev);
143 143
144 dev_dbg(dssdev->dev, "get_timings\n"); 144 dev_dbg(dssdev->dev, "get_timings\n");
145 145
146 *timings = ddata->timings; 146 *vm = ddata->vm;
147} 147}
148 148
149static int opa362_check_timings(struct omap_dss_device *dssdev, 149static int opa362_check_timings(struct omap_dss_device *dssdev,
150 struct omap_video_timings *timings) 150 struct videomode *vm)
151{ 151{
152 struct panel_drv_data *ddata = to_panel_data(dssdev); 152 struct panel_drv_data *ddata = to_panel_data(dssdev);
153 struct omap_dss_device *in = ddata->in; 153 struct omap_dss_device *in = ddata->in;
154 154
155 dev_dbg(dssdev->dev, "check_timings\n"); 155 dev_dbg(dssdev->dev, "check_timings\n");
156 156
157 return in->ops.atv->check_timings(in, timings); 157 return in->ops.atv->check_timings(in, vm);
158} 158}
159 159
160static void opa362_set_type(struct omap_dss_device *dssdev, 160static void opa362_set_type(struct omap_dss_device *dssdev,
diff --git a/drivers/gpu/drm/omapdrm/displays/encoder-tfp410.c b/drivers/gpu/drm/omapdrm/displays/encoder-tfp410.c
index d768217cefe0..13e32d02c884 100644
--- a/drivers/gpu/drm/omapdrm/displays/encoder-tfp410.c
+++ b/drivers/gpu/drm/omapdrm/displays/encoder-tfp410.c
@@ -24,7 +24,7 @@ struct panel_drv_data {
24 int pd_gpio; 24 int pd_gpio;
25 int data_lines; 25 int data_lines;
26 26
27 struct omap_video_timings timings; 27 struct videomode vm;
28}; 28};
29 29
30#define to_panel_data(x) container_of(x, struct panel_drv_data, dssdev) 30#define to_panel_data(x) container_of(x, struct panel_drv_data, dssdev)
@@ -81,7 +81,7 @@ static int tfp410_enable(struct omap_dss_device *dssdev)
81 if (omapdss_device_is_enabled(dssdev)) 81 if (omapdss_device_is_enabled(dssdev))
82 return 0; 82 return 0;
83 83
84 in->ops.dpi->set_timings(in, &ddata->timings); 84 in->ops.dpi->set_timings(in, &ddata->vm);
85 if (ddata->data_lines) 85 if (ddata->data_lines)
86 in->ops.dpi->set_data_lines(in, ddata->data_lines); 86 in->ops.dpi->set_data_lines(in, ddata->data_lines);
87 87
@@ -113,44 +113,43 @@ static void tfp410_disable(struct omap_dss_device *dssdev)
113 dssdev->state = OMAP_DSS_DISPLAY_DISABLED; 113 dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
114} 114}
115 115
116static void tfp410_fix_timings(struct omap_video_timings *timings) 116static void tfp410_fix_timings(struct videomode *vm)
117{ 117{
118 timings->data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE; 118 vm->flags |= DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
119 timings->sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE; 119 DISPLAY_FLAGS_SYNC_POSEDGE;
120 timings->de_level = OMAPDSS_SIG_ACTIVE_HIGH;
121} 120}
122 121
123static void tfp410_set_timings(struct omap_dss_device *dssdev, 122static void tfp410_set_timings(struct omap_dss_device *dssdev,
124 struct omap_video_timings *timings) 123 struct videomode *vm)
125{ 124{
126 struct panel_drv_data *ddata = to_panel_data(dssdev); 125 struct panel_drv_data *ddata = to_panel_data(dssdev);
127 struct omap_dss_device *in = ddata->in; 126 struct omap_dss_device *in = ddata->in;
128 127
129 tfp410_fix_timings(timings); 128 tfp410_fix_timings(vm);
130 129
131 ddata->timings = *timings; 130 ddata->vm = *vm;
132 dssdev->panel.timings = *timings; 131 dssdev->panel.vm = *vm;
133 132
134 in->ops.dpi->set_timings(in, timings); 133 in->ops.dpi->set_timings(in, vm);
135} 134}
136 135
137static void tfp410_get_timings(struct omap_dss_device *dssdev, 136static void tfp410_get_timings(struct omap_dss_device *dssdev,
138 struct omap_video_timings *timings) 137 struct videomode *vm)
139{ 138{
140 struct panel_drv_data *ddata = to_panel_data(dssdev); 139 struct panel_drv_data *ddata = to_panel_data(dssdev);
141 140
142 *timings = ddata->timings; 141 *vm = ddata->vm;
143} 142}
144 143
145static int tfp410_check_timings(struct omap_dss_device *dssdev, 144static int tfp410_check_timings(struct omap_dss_device *dssdev,
146 struct omap_video_timings *timings) 145 struct videomode *vm)
147{ 146{
148 struct panel_drv_data *ddata = to_panel_data(dssdev); 147 struct panel_drv_data *ddata = to_panel_data(dssdev);
149 struct omap_dss_device *in = ddata->in; 148 struct omap_dss_device *in = ddata->in;
150 149
151 tfp410_fix_timings(timings); 150 tfp410_fix_timings(vm);
152 151
153 return in->ops.dpi->check_timings(in, timings); 152 return in->ops.dpi->check_timings(in, vm);
154} 153}
155 154
156static const struct omapdss_dvi_ops tfp410_dvi_ops = { 155static const struct omapdss_dvi_ops tfp410_dvi_ops = {
diff --git a/drivers/gpu/drm/omapdrm/displays/encoder-tpd12s015.c b/drivers/gpu/drm/omapdrm/displays/encoder-tpd12s015.c
index 46855c8f5cbf..6d8f79b29af6 100644
--- a/drivers/gpu/drm/omapdrm/displays/encoder-tpd12s015.c
+++ b/drivers/gpu/drm/omapdrm/displays/encoder-tpd12s015.c
@@ -26,7 +26,7 @@ struct panel_drv_data {
26 struct gpio_desc *ls_oe_gpio; 26 struct gpio_desc *ls_oe_gpio;
27 struct gpio_desc *hpd_gpio; 27 struct gpio_desc *hpd_gpio;
28 28
29 struct omap_video_timings timings; 29 struct videomode vm;
30}; 30};
31 31
32#define to_panel_data(x) container_of(x, struct panel_drv_data, dssdev) 32#define to_panel_data(x) container_of(x, struct panel_drv_data, dssdev)
@@ -80,7 +80,7 @@ static int tpd_enable(struct omap_dss_device *dssdev)
80 if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) 80 if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE)
81 return 0; 81 return 0;
82 82
83 in->ops.hdmi->set_timings(in, &ddata->timings); 83 in->ops.hdmi->set_timings(in, &ddata->vm);
84 84
85 r = in->ops.hdmi->enable(in); 85 r = in->ops.hdmi->enable(in);
86 if (r) 86 if (r)
@@ -105,33 +105,33 @@ static void tpd_disable(struct omap_dss_device *dssdev)
105} 105}
106 106
107static void tpd_set_timings(struct omap_dss_device *dssdev, 107static void tpd_set_timings(struct omap_dss_device *dssdev,
108 struct omap_video_timings *timings) 108 struct videomode *vm)
109{ 109{
110 struct panel_drv_data *ddata = to_panel_data(dssdev); 110 struct panel_drv_data *ddata = to_panel_data(dssdev);
111 struct omap_dss_device *in = ddata->in; 111 struct omap_dss_device *in = ddata->in;
112 112
113 ddata->timings = *timings; 113 ddata->vm = *vm;
114 dssdev->panel.timings = *timings; 114 dssdev->panel.vm = *vm;
115 115
116 in->ops.hdmi->set_timings(in, timings); 116 in->ops.hdmi->set_timings(in, vm);
117} 117}
118 118
119static void tpd_get_timings(struct omap_dss_device *dssdev, 119static void tpd_get_timings(struct omap_dss_device *dssdev,
120 struct omap_video_timings *timings) 120 struct videomode *vm)
121{ 121{
122 struct panel_drv_data *ddata = to_panel_data(dssdev); 122 struct panel_drv_data *ddata = to_panel_data(dssdev);
123 123
124 *timings = ddata->timings; 124 *vm = ddata->vm;
125} 125}
126 126
127static int tpd_check_timings(struct omap_dss_device *dssdev, 127static int tpd_check_timings(struct omap_dss_device *dssdev,
128 struct omap_video_timings *timings) 128 struct videomode *vm)
129{ 129{
130 struct panel_drv_data *ddata = to_panel_data(dssdev); 130 struct panel_drv_data *ddata = to_panel_data(dssdev);
131 struct omap_dss_device *in = ddata->in; 131 struct omap_dss_device *in = ddata->in;
132 int r; 132 int r;
133 133
134 r = in->ops.hdmi->check_timings(in, timings); 134 r = in->ops.hdmi->check_timings(in, vm);
135 135
136 return r; 136 return r;
137} 137}
diff --git a/drivers/gpu/drm/omapdrm/displays/panel-dpi.c b/drivers/gpu/drm/omapdrm/displays/panel-dpi.c
index 7f16f985ab22..38003208d9ca 100644
--- a/drivers/gpu/drm/omapdrm/displays/panel-dpi.c
+++ b/drivers/gpu/drm/omapdrm/displays/panel-dpi.c
@@ -28,7 +28,7 @@ struct panel_drv_data {
28 28
29 int data_lines; 29 int data_lines;
30 30
31 struct omap_video_timings videomode; 31 struct videomode vm;
32 32
33 /* used for non-DT boot, to be removed */ 33 /* used for non-DT boot, to be removed */
34 int backlight_gpio; 34 int backlight_gpio;
@@ -80,7 +80,7 @@ static int panel_dpi_enable(struct omap_dss_device *dssdev)
80 80
81 if (ddata->data_lines) 81 if (ddata->data_lines)
82 in->ops.dpi->set_data_lines(in, ddata->data_lines); 82 in->ops.dpi->set_data_lines(in, ddata->data_lines);
83 in->ops.dpi->set_timings(in, &ddata->videomode); 83 in->ops.dpi->set_timings(in, &ddata->vm);
84 84
85 r = in->ops.dpi->enable(in); 85 r = in->ops.dpi->enable(in);
86 if (r) 86 if (r)
@@ -122,32 +122,32 @@ static void panel_dpi_disable(struct omap_dss_device *dssdev)
122} 122}
123 123
124static void panel_dpi_set_timings(struct omap_dss_device *dssdev, 124static void panel_dpi_set_timings(struct omap_dss_device *dssdev,
125 struct omap_video_timings *timings) 125 struct videomode *vm)
126{ 126{
127 struct panel_drv_data *ddata = to_panel_data(dssdev); 127 struct panel_drv_data *ddata = to_panel_data(dssdev);
128 struct omap_dss_device *in = ddata->in; 128 struct omap_dss_device *in = ddata->in;
129 129
130 ddata->videomode = *timings; 130 ddata->vm = *vm;
131 dssdev->panel.timings = *timings; 131 dssdev->panel.vm = *vm;
132 132
133 in->ops.dpi->set_timings(in, timings); 133 in->ops.dpi->set_timings(in, vm);
134} 134}
135 135
136static void panel_dpi_get_timings(struct omap_dss_device *dssdev, 136static void panel_dpi_get_timings(struct omap_dss_device *dssdev,
137 struct omap_video_timings *timings) 137 struct videomode *vm)
138{ 138{
139 struct panel_drv_data *ddata = to_panel_data(dssdev); 139 struct panel_drv_data *ddata = to_panel_data(dssdev);
140 140
141 *timings = ddata->videomode; 141 *vm = ddata->vm;
142} 142}
143 143
144static int panel_dpi_check_timings(struct omap_dss_device *dssdev, 144static int panel_dpi_check_timings(struct omap_dss_device *dssdev,
145 struct omap_video_timings *timings) 145 struct videomode *vm)
146{ 146{
147 struct panel_drv_data *ddata = to_panel_data(dssdev); 147 struct panel_drv_data *ddata = to_panel_data(dssdev);
148 struct omap_dss_device *in = ddata->in; 148 struct omap_dss_device *in = ddata->in;
149 149
150 return in->ops.dpi->check_timings(in, timings); 150 return in->ops.dpi->check_timings(in, vm);
151} 151}
152 152
153static struct omap_dss_driver panel_dpi_ops = { 153static struct omap_dss_driver panel_dpi_ops = {
@@ -169,7 +169,6 @@ static int panel_dpi_probe_pdata(struct platform_device *pdev)
169 const struct panel_dpi_platform_data *pdata; 169 const struct panel_dpi_platform_data *pdata;
170 struct panel_drv_data *ddata = platform_get_drvdata(pdev); 170 struct panel_drv_data *ddata = platform_get_drvdata(pdev);
171 struct omap_dss_device *dssdev, *in; 171 struct omap_dss_device *dssdev, *in;
172 struct videomode vm;
173 int r; 172 int r;
174 173
175 pdata = dev_get_platdata(&pdev->dev); 174 pdata = dev_get_platdata(&pdev->dev);
@@ -185,8 +184,7 @@ static int panel_dpi_probe_pdata(struct platform_device *pdev)
185 184
186 ddata->data_lines = pdata->data_lines; 185 ddata->data_lines = pdata->data_lines;
187 186
188 videomode_from_timing(pdata->display_timing, &vm); 187 videomode_from_timing(pdata->display_timing, &ddata->vm);
189 videomode_to_omap_video_timings(&vm, &ddata->videomode);
190 188
191 dssdev = &ddata->dssdev; 189 dssdev = &ddata->dssdev;
192 dssdev->name = pdata->name; 190 dssdev->name = pdata->name;
@@ -214,7 +212,6 @@ static int panel_dpi_probe_of(struct platform_device *pdev)
214 struct omap_dss_device *in; 212 struct omap_dss_device *in;
215 int r; 213 int r;
216 struct display_timing timing; 214 struct display_timing timing;
217 struct videomode vm;
218 struct gpio_desc *gpio; 215 struct gpio_desc *gpio;
219 216
220 gpio = devm_gpiod_get_optional(&pdev->dev, "enable", GPIOD_OUT_LOW); 217 gpio = devm_gpiod_get_optional(&pdev->dev, "enable", GPIOD_OUT_LOW);
@@ -245,8 +242,7 @@ static int panel_dpi_probe_of(struct platform_device *pdev)
245 return r; 242 return r;
246 } 243 }
247 244
248 videomode_from_timing(&timing, &vm); 245 videomode_from_timing(&timing, &ddata->vm);
249 videomode_to_omap_video_timings(&vm, &ddata->videomode);
250 246
251 in = omapdss_of_find_source_for_first_ep(node); 247 in = omapdss_of_find_source_for_first_ep(node);
252 if (IS_ERR(in)) { 248 if (IS_ERR(in)) {
@@ -295,7 +291,7 @@ static int panel_dpi_probe(struct platform_device *pdev)
295 dssdev->driver = &panel_dpi_ops; 291 dssdev->driver = &panel_dpi_ops;
296 dssdev->type = OMAP_DISPLAY_TYPE_DPI; 292 dssdev->type = OMAP_DISPLAY_TYPE_DPI;
297 dssdev->owner = THIS_MODULE; 293 dssdev->owner = THIS_MODULE;
298 dssdev->panel.timings = ddata->videomode; 294 dssdev->panel.vm = ddata->vm;
299 dssdev->phy.dpi.data_lines = ddata->data_lines; 295 dssdev->phy.dpi.data_lines = ddata->data_lines;
300 296
301 r = omapdss_register_display(dssdev); 297 r = omapdss_register_display(dssdev);
diff --git a/drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c b/drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c
index b1f3b818edf4..dc026a843712 100644
--- a/drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c
+++ b/drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c
@@ -42,7 +42,7 @@ struct panel_drv_data {
42 struct omap_dss_device dssdev; 42 struct omap_dss_device dssdev;
43 struct omap_dss_device *in; 43 struct omap_dss_device *in;
44 44
45 struct omap_video_timings timings; 45 struct videomode vm;
46 46
47 struct platform_device *pdev; 47 struct platform_device *pdev;
48 48
@@ -382,8 +382,8 @@ static const struct backlight_ops dsicm_bl_ops = {
382static void dsicm_get_resolution(struct omap_dss_device *dssdev, 382static void dsicm_get_resolution(struct omap_dss_device *dssdev,
383 u16 *xres, u16 *yres) 383 u16 *xres, u16 *yres)
384{ 384{
385 *xres = dssdev->panel.timings.x_res; 385 *xres = dssdev->panel.vm.hactive;
386 *yres = dssdev->panel.timings.y_res; 386 *yres = dssdev->panel.vm.vactive;
387} 387}
388 388
389static ssize_t dsicm_num_errors_show(struct device *dev, 389static ssize_t dsicm_num_errors_show(struct device *dev,
@@ -589,7 +589,7 @@ static int dsicm_power_on(struct panel_drv_data *ddata)
589 struct omap_dss_dsi_config dsi_config = { 589 struct omap_dss_dsi_config dsi_config = {
590 .mode = OMAP_DSS_DSI_CMD_MODE, 590 .mode = OMAP_DSS_DSI_CMD_MODE,
591 .pixel_format = OMAP_DSS_DSI_FMT_RGB888, 591 .pixel_format = OMAP_DSS_DSI_FMT_RGB888,
592 .timings = &ddata->timings, 592 .vm = &ddata->vm,
593 .hs_clk_min = 150000000, 593 .hs_clk_min = 150000000,
594 .hs_clk_max = 300000000, 594 .hs_clk_max = 300000000,
595 .lp_clk_min = 7000000, 595 .lp_clk_min = 7000000,
@@ -892,8 +892,8 @@ static int dsicm_update(struct omap_dss_device *dssdev,
892 892
893 /* XXX no need to send this every frame, but dsi break if not done */ 893 /* XXX no need to send this every frame, but dsi break if not done */
894 r = dsicm_set_update_window(ddata, 0, 0, 894 r = dsicm_set_update_window(ddata, 0, 0,
895 dssdev->panel.timings.x_res, 895 dssdev->panel.vm.hactive,
896 dssdev->panel.timings.y_res); 896 dssdev->panel.vm.vactive);
897 if (r) 897 if (r)
898 goto err; 898 goto err;
899 899
@@ -1023,9 +1023,8 @@ static int dsicm_memory_read(struct omap_dss_device *dssdev,
1023 goto err1; 1023 goto err1;
1024 } 1024 }
1025 1025
1026 size = min(w * h * 3, 1026 size = min((u32)w * h * 3,
1027 dssdev->panel.timings.x_res * 1027 dssdev->panel.vm.hactive * dssdev->panel.vm.vactive * 3);
1028 dssdev->panel.timings.y_res * 3);
1029 1028
1030 in->ops.dsi->bus_lock(in); 1029 in->ops.dsi->bus_lock(in);
1031 1030
@@ -1186,14 +1185,14 @@ static int dsicm_probe(struct platform_device *pdev)
1186 if (r) 1185 if (r)
1187 return r; 1186 return r;
1188 1187
1189 ddata->timings.x_res = 864; 1188 ddata->vm.hactive = 864;
1190 ddata->timings.y_res = 480; 1189 ddata->vm.vactive = 480;
1191 ddata->timings.pixelclock = 864 * 480 * 60; 1190 ddata->vm.pixelclock = 864 * 480 * 60;
1192 1191
1193 dssdev = &ddata->dssdev; 1192 dssdev = &ddata->dssdev;
1194 dssdev->dev = dev; 1193 dssdev->dev = dev;
1195 dssdev->driver = &dsicm_ops; 1194 dssdev->driver = &dsicm_ops;
1196 dssdev->panel.timings = ddata->timings; 1195 dssdev->panel.vm = ddata->vm;
1197 dssdev->type = OMAP_DISPLAY_TYPE_DSI; 1196 dssdev->type = OMAP_DISPLAY_TYPE_DSI;
1198 dssdev->owner = THIS_MODULE; 1197 dssdev->owner = THIS_MODULE;
1199 1198
diff --git a/drivers/gpu/drm/omapdrm/displays/panel-lgphilips-lb035q02.c b/drivers/gpu/drm/omapdrm/displays/panel-lgphilips-lb035q02.c
index 6dfb96cea293..43d21edb51f5 100644
--- a/drivers/gpu/drm/omapdrm/displays/panel-lgphilips-lb035q02.c
+++ b/drivers/gpu/drm/omapdrm/displays/panel-lgphilips-lb035q02.c
@@ -19,25 +19,28 @@
19 19
20#include "../dss/omapdss.h" 20#include "../dss/omapdss.h"
21 21
22static struct omap_video_timings lb035q02_timings = { 22static struct videomode lb035q02_vm = {
23 .x_res = 320, 23 .hactive = 320,
24 .y_res = 240, 24 .vactive = 240,
25 25
26 .pixelclock = 6500000, 26 .pixelclock = 6500000,
27 27
28 .hsw = 2, 28 .hsync_len = 2,
29 .hfp = 20, 29 .hfront_porch = 20,
30 .hbp = 68, 30 .hback_porch = 68,
31 31
32 .vsw = 2, 32 .vsync_len = 2,
33 .vfp = 4, 33 .vfront_porch = 4,
34 .vbp = 18, 34 .vback_porch = 18,
35 35
36 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW, 36 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
37 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW, 37 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_SYNC_NEGEDGE |
38 .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE, 38 DISPLAY_FLAGS_PIXDATA_POSEDGE,
39 .de_level = OMAPDSS_SIG_ACTIVE_HIGH, 39 /*
40 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE, 40 * Note: According to the panel documentation:
41 * DE is active LOW
42 * DATA needs to be driven on the FALLING edge
43 */
41}; 44};
42 45
43struct panel_drv_data { 46struct panel_drv_data {
@@ -48,7 +51,7 @@ struct panel_drv_data {
48 51
49 int data_lines; 52 int data_lines;
50 53
51 struct omap_video_timings videomode; 54 struct videomode vm;
52 55
53 struct gpio_desc *enable_gpio; 56 struct gpio_desc *enable_gpio;
54}; 57};
@@ -158,7 +161,7 @@ static int lb035q02_enable(struct omap_dss_device *dssdev)
158 161
159 if (ddata->data_lines) 162 if (ddata->data_lines)
160 in->ops.dpi->set_data_lines(in, ddata->data_lines); 163 in->ops.dpi->set_data_lines(in, ddata->data_lines);
161 in->ops.dpi->set_timings(in, &ddata->videomode); 164 in->ops.dpi->set_timings(in, &ddata->vm);
162 165
163 r = in->ops.dpi->enable(in); 166 r = in->ops.dpi->enable(in);
164 if (r) 167 if (r)
@@ -189,32 +192,32 @@ static void lb035q02_disable(struct omap_dss_device *dssdev)
189} 192}
190 193
191static void lb035q02_set_timings(struct omap_dss_device *dssdev, 194static void lb035q02_set_timings(struct omap_dss_device *dssdev,
192 struct omap_video_timings *timings) 195 struct videomode *vm)
193{ 196{
194 struct panel_drv_data *ddata = to_panel_data(dssdev); 197 struct panel_drv_data *ddata = to_panel_data(dssdev);
195 struct omap_dss_device *in = ddata->in; 198 struct omap_dss_device *in = ddata->in;
196 199
197 ddata->videomode = *timings; 200 ddata->vm = *vm;
198 dssdev->panel.timings = *timings; 201 dssdev->panel.vm = *vm;
199 202
200 in->ops.dpi->set_timings(in, timings); 203 in->ops.dpi->set_timings(in, vm);
201} 204}
202 205
203static void lb035q02_get_timings(struct omap_dss_device *dssdev, 206static void lb035q02_get_timings(struct omap_dss_device *dssdev,
204 struct omap_video_timings *timings) 207 struct videomode *vm)
205{ 208{
206 struct panel_drv_data *ddata = to_panel_data(dssdev); 209 struct panel_drv_data *ddata = to_panel_data(dssdev);
207 210
208 *timings = ddata->videomode; 211 *vm = ddata->vm;
209} 212}
210 213
211static int lb035q02_check_timings(struct omap_dss_device *dssdev, 214static int lb035q02_check_timings(struct omap_dss_device *dssdev,
212 struct omap_video_timings *timings) 215 struct videomode *vm)
213{ 216{
214 struct panel_drv_data *ddata = to_panel_data(dssdev); 217 struct panel_drv_data *ddata = to_panel_data(dssdev);
215 struct omap_dss_device *in = ddata->in; 218 struct omap_dss_device *in = ddata->in;
216 219
217 return in->ops.dpi->check_timings(in, timings); 220 return in->ops.dpi->check_timings(in, vm);
218} 221}
219 222
220static struct omap_dss_driver lb035q02_ops = { 223static struct omap_dss_driver lb035q02_ops = {
@@ -278,14 +281,14 @@ static int lb035q02_panel_spi_probe(struct spi_device *spi)
278 if (r) 281 if (r)
279 return r; 282 return r;
280 283
281 ddata->videomode = lb035q02_timings; 284 ddata->vm = lb035q02_vm;
282 285
283 dssdev = &ddata->dssdev; 286 dssdev = &ddata->dssdev;
284 dssdev->dev = &spi->dev; 287 dssdev->dev = &spi->dev;
285 dssdev->driver = &lb035q02_ops; 288 dssdev->driver = &lb035q02_ops;
286 dssdev->type = OMAP_DISPLAY_TYPE_DPI; 289 dssdev->type = OMAP_DISPLAY_TYPE_DPI;
287 dssdev->owner = THIS_MODULE; 290 dssdev->owner = THIS_MODULE;
288 dssdev->panel.timings = ddata->videomode; 291 dssdev->panel.vm = ddata->vm;
289 dssdev->phy.dpi.data_lines = ddata->data_lines; 292 dssdev->phy.dpi.data_lines = ddata->data_lines;
290 293
291 r = omapdss_register_display(dssdev); 294 r = omapdss_register_display(dssdev);
diff --git a/drivers/gpu/drm/omapdrm/displays/panel-nec-nl8048hl11.c b/drivers/gpu/drm/omapdrm/displays/panel-nec-nl8048hl11.c
index 9f3d6f48f3e1..2de27ba01552 100644
--- a/drivers/gpu/drm/omapdrm/displays/panel-nec-nl8048hl11.c
+++ b/drivers/gpu/drm/omapdrm/displays/panel-nec-nl8048hl11.c
@@ -23,7 +23,7 @@ struct panel_drv_data {
23 struct omap_dss_device dssdev; 23 struct omap_dss_device dssdev;
24 struct omap_dss_device *in; 24 struct omap_dss_device *in;
25 25
26 struct omap_video_timings videomode; 26 struct videomode vm;
27 27
28 int data_lines; 28 int data_lines;
29 29
@@ -65,22 +65,20 @@ static const struct {
65 { 156, 0x00 }, { 157, 0x00 }, { 2, 0x00 }, 65 { 156, 0x00 }, { 157, 0x00 }, { 2, 0x00 },
66}; 66};
67 67
68static const struct omap_video_timings nec_8048_panel_timings = { 68static const struct videomode nec_8048_panel_vm = {
69 .x_res = LCD_XRES, 69 .hactive = LCD_XRES,
70 .y_res = LCD_YRES, 70 .vactive = LCD_YRES,
71 .pixelclock = LCD_PIXEL_CLOCK, 71 .pixelclock = LCD_PIXEL_CLOCK,
72 .hfp = 6, 72 .hfront_porch = 6,
73 .hsw = 1, 73 .hsync_len = 1,
74 .hbp = 4, 74 .hback_porch = 4,
75 .vfp = 3, 75 .vfront_porch = 3,
76 .vsw = 1, 76 .vsync_len = 1,
77 .vbp = 4, 77 .vback_porch = 4,
78 78
79 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW, 79 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
80 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW, 80 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_SYNC_POSEDGE |
81 .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE, 81 DISPLAY_FLAGS_PIXDATA_POSEDGE,
82 .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
83 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
84}; 82};
85 83
86#define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev) 84#define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev)
@@ -157,7 +155,7 @@ static int nec_8048_enable(struct omap_dss_device *dssdev)
157 155
158 if (ddata->data_lines) 156 if (ddata->data_lines)
159 in->ops.dpi->set_data_lines(in, ddata->data_lines); 157 in->ops.dpi->set_data_lines(in, ddata->data_lines);
160 in->ops.dpi->set_timings(in, &ddata->videomode); 158 in->ops.dpi->set_timings(in, &ddata->vm);
161 159
162 r = in->ops.dpi->enable(in); 160 r = in->ops.dpi->enable(in);
163 if (r) 161 if (r)
@@ -188,32 +186,32 @@ static void nec_8048_disable(struct omap_dss_device *dssdev)
188} 186}
189 187
190static void nec_8048_set_timings(struct omap_dss_device *dssdev, 188static void nec_8048_set_timings(struct omap_dss_device *dssdev,
191 struct omap_video_timings *timings) 189 struct videomode *vm)
192{ 190{
193 struct panel_drv_data *ddata = to_panel_data(dssdev); 191 struct panel_drv_data *ddata = to_panel_data(dssdev);
194 struct omap_dss_device *in = ddata->in; 192 struct omap_dss_device *in = ddata->in;
195 193
196 ddata->videomode = *timings; 194 ddata->vm = *vm;
197 dssdev->panel.timings = *timings; 195 dssdev->panel.vm = *vm;
198 196
199 in->ops.dpi->set_timings(in, timings); 197 in->ops.dpi->set_timings(in, vm);
200} 198}
201 199
202static void nec_8048_get_timings(struct omap_dss_device *dssdev, 200static void nec_8048_get_timings(struct omap_dss_device *dssdev,
203 struct omap_video_timings *timings) 201 struct videomode *vm)
204{ 202{
205 struct panel_drv_data *ddata = to_panel_data(dssdev); 203 struct panel_drv_data *ddata = to_panel_data(dssdev);
206 204
207 *timings = ddata->videomode; 205 *vm = ddata->vm;
208} 206}
209 207
210static int nec_8048_check_timings(struct omap_dss_device *dssdev, 208static int nec_8048_check_timings(struct omap_dss_device *dssdev,
211 struct omap_video_timings *timings) 209 struct videomode *vm)
212{ 210{
213 struct panel_drv_data *ddata = to_panel_data(dssdev); 211 struct panel_drv_data *ddata = to_panel_data(dssdev);
214 struct omap_dss_device *in = ddata->in; 212 struct omap_dss_device *in = ddata->in;
215 213
216 return in->ops.dpi->check_timings(in, timings); 214 return in->ops.dpi->check_timings(in, vm);
217} 215}
218 216
219static struct omap_dss_driver nec_8048_ops = { 217static struct omap_dss_driver nec_8048_ops = {
@@ -306,14 +304,14 @@ static int nec_8048_probe(struct spi_device *spi)
306 goto err_gpio; 304 goto err_gpio;
307 } 305 }
308 306
309 ddata->videomode = nec_8048_panel_timings; 307 ddata->vm = nec_8048_panel_vm;
310 308
311 dssdev = &ddata->dssdev; 309 dssdev = &ddata->dssdev;
312 dssdev->dev = &spi->dev; 310 dssdev->dev = &spi->dev;
313 dssdev->driver = &nec_8048_ops; 311 dssdev->driver = &nec_8048_ops;
314 dssdev->type = OMAP_DISPLAY_TYPE_DPI; 312 dssdev->type = OMAP_DISPLAY_TYPE_DPI;
315 dssdev->owner = THIS_MODULE; 313 dssdev->owner = THIS_MODULE;
316 dssdev->panel.timings = ddata->videomode; 314 dssdev->panel.vm = ddata->vm;
317 315
318 r = omapdss_register_display(dssdev); 316 r = omapdss_register_display(dssdev);
319 if (r) { 317 if (r) {
diff --git a/drivers/gpu/drm/omapdrm/displays/panel-sharp-ls037v7dw01.c b/drivers/gpu/drm/omapdrm/displays/panel-sharp-ls037v7dw01.c
index 3d3efc561ea9..04fe235b7cac 100644
--- a/drivers/gpu/drm/omapdrm/displays/panel-sharp-ls037v7dw01.c
+++ b/drivers/gpu/drm/omapdrm/displays/panel-sharp-ls037v7dw01.c
@@ -26,7 +26,7 @@ struct panel_drv_data {
26 26
27 int data_lines; 27 int data_lines;
28 28
29 struct omap_video_timings videomode; 29 struct videomode vm;
30 30
31 struct gpio_desc *resb_gpio; /* low = reset active min 20 us */ 31 struct gpio_desc *resb_gpio; /* low = reset active min 20 us */
32 struct gpio_desc *ini_gpio; /* high = power on */ 32 struct gpio_desc *ini_gpio; /* high = power on */
@@ -35,25 +35,27 @@ struct panel_drv_data {
35 struct gpio_desc *ud_gpio; /* high = conventional vertical scanning */ 35 struct gpio_desc *ud_gpio; /* high = conventional vertical scanning */
36}; 36};
37 37
38static const struct omap_video_timings sharp_ls_timings = { 38static const struct videomode sharp_ls_vm = {
39 .x_res = 480, 39 .hactive = 480,
40 .y_res = 640, 40 .vactive = 640,
41 41
42 .pixelclock = 19200000, 42 .pixelclock = 19200000,
43 43
44 .hsw = 2, 44 .hsync_len = 2,
45 .hfp = 1, 45 .hfront_porch = 1,
46 .hbp = 28, 46 .hback_porch = 28,
47 47
48 .vsw = 1, 48 .vsync_len = 1,
49 .vfp = 1, 49 .vfront_porch = 1,
50 .vbp = 1, 50 .vback_porch = 1,
51 51
52 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW, 52 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
53 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW, 53 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_SYNC_NEGEDGE |
54 .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE, 54 DISPLAY_FLAGS_PIXDATA_POSEDGE,
55 .de_level = OMAPDSS_SIG_ACTIVE_HIGH, 55 /*
56 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE, 56 * Note: According to the panel documentation:
57 * DATA needs to be driven on the FALLING edge
58 */
57}; 59};
58 60
59#define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev) 61#define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev)
@@ -99,7 +101,7 @@ static int sharp_ls_enable(struct omap_dss_device *dssdev)
99 101
100 if (ddata->data_lines) 102 if (ddata->data_lines)
101 in->ops.dpi->set_data_lines(in, ddata->data_lines); 103 in->ops.dpi->set_data_lines(in, ddata->data_lines);
102 in->ops.dpi->set_timings(in, &ddata->videomode); 104 in->ops.dpi->set_timings(in, &ddata->vm);
103 105
104 if (ddata->vcc) { 106 if (ddata->vcc) {
105 r = regulator_enable(ddata->vcc); 107 r = regulator_enable(ddata->vcc);
@@ -154,32 +156,32 @@ static void sharp_ls_disable(struct omap_dss_device *dssdev)
154} 156}
155 157
156static void sharp_ls_set_timings(struct omap_dss_device *dssdev, 158static void sharp_ls_set_timings(struct omap_dss_device *dssdev,
157 struct omap_video_timings *timings) 159 struct videomode *vm)
158{ 160{
159 struct panel_drv_data *ddata = to_panel_data(dssdev); 161 struct panel_drv_data *ddata = to_panel_data(dssdev);
160 struct omap_dss_device *in = ddata->in; 162 struct omap_dss_device *in = ddata->in;
161 163
162 ddata->videomode = *timings; 164 ddata->vm = *vm;
163 dssdev->panel.timings = *timings; 165 dssdev->panel.vm = *vm;
164 166
165 in->ops.dpi->set_timings(in, timings); 167 in->ops.dpi->set_timings(in, vm);
166} 168}
167 169
168static void sharp_ls_get_timings(struct omap_dss_device *dssdev, 170static void sharp_ls_get_timings(struct omap_dss_device *dssdev,
169 struct omap_video_timings *timings) 171 struct videomode *vm)
170{ 172{
171 struct panel_drv_data *ddata = to_panel_data(dssdev); 173 struct panel_drv_data *ddata = to_panel_data(dssdev);
172 174
173 *timings = ddata->videomode; 175 *vm = ddata->vm;
174} 176}
175 177
176static int sharp_ls_check_timings(struct omap_dss_device *dssdev, 178static int sharp_ls_check_timings(struct omap_dss_device *dssdev,
177 struct omap_video_timings *timings) 179 struct videomode *vm)
178{ 180{
179 struct panel_drv_data *ddata = to_panel_data(dssdev); 181 struct panel_drv_data *ddata = to_panel_data(dssdev);
180 struct omap_dss_device *in = ddata->in; 182 struct omap_dss_device *in = ddata->in;
181 183
182 return in->ops.dpi->check_timings(in, timings); 184 return in->ops.dpi->check_timings(in, vm);
183} 185}
184 186
185static struct omap_dss_driver sharp_ls_ops = { 187static struct omap_dss_driver sharp_ls_ops = {
@@ -279,14 +281,14 @@ static int sharp_ls_probe(struct platform_device *pdev)
279 if (r) 281 if (r)
280 return r; 282 return r;
281 283
282 ddata->videomode = sharp_ls_timings; 284 ddata->vm = sharp_ls_vm;
283 285
284 dssdev = &ddata->dssdev; 286 dssdev = &ddata->dssdev;
285 dssdev->dev = &pdev->dev; 287 dssdev->dev = &pdev->dev;
286 dssdev->driver = &sharp_ls_ops; 288 dssdev->driver = &sharp_ls_ops;
287 dssdev->type = OMAP_DISPLAY_TYPE_DPI; 289 dssdev->type = OMAP_DISPLAY_TYPE_DPI;
288 dssdev->owner = THIS_MODULE; 290 dssdev->owner = THIS_MODULE;
289 dssdev->panel.timings = ddata->videomode; 291 dssdev->panel.vm = ddata->vm;
290 dssdev->phy.dpi.data_lines = ddata->data_lines; 292 dssdev->phy.dpi.data_lines = ddata->data_lines;
291 293
292 r = omapdss_register_display(dssdev); 294 r = omapdss_register_display(dssdev);
diff --git a/drivers/gpu/drm/omapdrm/displays/panel-sony-acx565akm.c b/drivers/gpu/drm/omapdrm/displays/panel-sony-acx565akm.c
index 3557a4c7dd7b..746cb8d9cba1 100644
--- a/drivers/gpu/drm/omapdrm/displays/panel-sony-acx565akm.c
+++ b/drivers/gpu/drm/omapdrm/displays/panel-sony-acx565akm.c
@@ -71,7 +71,7 @@ struct panel_drv_data {
71 int reset_gpio; 71 int reset_gpio;
72 int datapairs; 72 int datapairs;
73 73
74 struct omap_video_timings videomode; 74 struct videomode vm;
75 75
76 char *name; 76 char *name;
77 int enabled; 77 int enabled;
@@ -92,23 +92,20 @@ struct panel_drv_data {
92 struct backlight_device *bl_dev; 92 struct backlight_device *bl_dev;
93}; 93};
94 94
95static const struct omap_video_timings acx565akm_panel_timings = { 95static const struct videomode acx565akm_panel_vm = {
96 .x_res = 800, 96 .hactive = 800,
97 .y_res = 480, 97 .vactive = 480,
98 .pixelclock = 24000000, 98 .pixelclock = 24000000,
99 .hfp = 28, 99 .hfront_porch = 28,
100 .hsw = 4, 100 .hsync_len = 4,
101 .hbp = 24, 101 .hback_porch = 24,
102 .vfp = 3, 102 .vfront_porch = 3,
103 .vsw = 3, 103 .vsync_len = 3,
104 .vbp = 4, 104 .vback_porch = 4,
105 105
106 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW, 106 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
107 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW, 107 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_SYNC_NEGEDGE |
108 108 DISPLAY_FLAGS_PIXDATA_POSEDGE,
109 .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
110 .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
111 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
112}; 109};
113 110
114#define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev) 111#define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev)
@@ -548,7 +545,7 @@ static int acx565akm_panel_power_on(struct omap_dss_device *dssdev)
548 545
549 dev_dbg(&ddata->spi->dev, "%s\n", __func__); 546 dev_dbg(&ddata->spi->dev, "%s\n", __func__);
550 547
551 in->ops.sdi->set_timings(in, &ddata->videomode); 548 in->ops.sdi->set_timings(in, &ddata->vm);
552 549
553 if (ddata->datapairs > 0) 550 if (ddata->datapairs > 0)
554 in->ops.sdi->set_datapairs(in, ddata->datapairs); 551 in->ops.sdi->set_datapairs(in, ddata->datapairs);
@@ -662,32 +659,32 @@ static void acx565akm_disable(struct omap_dss_device *dssdev)
662} 659}
663 660
664static void acx565akm_set_timings(struct omap_dss_device *dssdev, 661static void acx565akm_set_timings(struct omap_dss_device *dssdev,
665 struct omap_video_timings *timings) 662 struct videomode *vm)
666{ 663{
667 struct panel_drv_data *ddata = to_panel_data(dssdev); 664 struct panel_drv_data *ddata = to_panel_data(dssdev);
668 struct omap_dss_device *in = ddata->in; 665 struct omap_dss_device *in = ddata->in;
669 666
670 ddata->videomode = *timings; 667 ddata->vm = *vm;
671 dssdev->panel.timings = *timings; 668 dssdev->panel.vm = *vm;
672 669
673 in->ops.sdi->set_timings(in, timings); 670 in->ops.sdi->set_timings(in, vm);
674} 671}
675 672
676static void acx565akm_get_timings(struct omap_dss_device *dssdev, 673static void acx565akm_get_timings(struct omap_dss_device *dssdev,
677 struct omap_video_timings *timings) 674 struct videomode *vm)
678{ 675{
679 struct panel_drv_data *ddata = to_panel_data(dssdev); 676 struct panel_drv_data *ddata = to_panel_data(dssdev);
680 677
681 *timings = ddata->videomode; 678 *vm = ddata->vm;
682} 679}
683 680
684static int acx565akm_check_timings(struct omap_dss_device *dssdev, 681static int acx565akm_check_timings(struct omap_dss_device *dssdev,
685 struct omap_video_timings *timings) 682 struct videomode *vm)
686{ 683{
687 struct panel_drv_data *ddata = to_panel_data(dssdev); 684 struct panel_drv_data *ddata = to_panel_data(dssdev);
688 struct omap_dss_device *in = ddata->in; 685 struct omap_dss_device *in = ddata->in;
689 686
690 return in->ops.sdi->check_timings(in, timings); 687 return in->ops.sdi->check_timings(in, vm);
691} 688}
692 689
693static struct omap_dss_driver acx565akm_ops = { 690static struct omap_dss_driver acx565akm_ops = {
@@ -845,14 +842,14 @@ static int acx565akm_probe(struct spi_device *spi)
845 acx565akm_bl_update_status(bldev); 842 acx565akm_bl_update_status(bldev);
846 843
847 844
848 ddata->videomode = acx565akm_panel_timings; 845 ddata->vm = acx565akm_panel_vm;
849 846
850 dssdev = &ddata->dssdev; 847 dssdev = &ddata->dssdev;
851 dssdev->dev = &spi->dev; 848 dssdev->dev = &spi->dev;
852 dssdev->driver = &acx565akm_ops; 849 dssdev->driver = &acx565akm_ops;
853 dssdev->type = OMAP_DISPLAY_TYPE_SDI; 850 dssdev->type = OMAP_DISPLAY_TYPE_SDI;
854 dssdev->owner = THIS_MODULE; 851 dssdev->owner = THIS_MODULE;
855 dssdev->panel.timings = ddata->videomode; 852 dssdev->panel.vm = ddata->vm;
856 853
857 r = omapdss_register_display(dssdev); 854 r = omapdss_register_display(dssdev);
858 if (r) { 855 if (r) {
diff --git a/drivers/gpu/drm/omapdrm/displays/panel-tpo-td028ttec1.c b/drivers/gpu/drm/omapdrm/displays/panel-tpo-td028ttec1.c
index e859b3f893f7..f313dbfcbacb 100644
--- a/drivers/gpu/drm/omapdrm/displays/panel-tpo-td028ttec1.c
+++ b/drivers/gpu/drm/omapdrm/displays/panel-tpo-td028ttec1.c
@@ -37,28 +37,29 @@ struct panel_drv_data {
37 37
38 int data_lines; 38 int data_lines;
39 39
40 struct omap_video_timings videomode; 40 struct videomode vm;
41 41
42 struct spi_device *spi_dev; 42 struct spi_device *spi_dev;
43}; 43};
44 44
45static struct omap_video_timings td028ttec1_panel_timings = { 45static struct videomode td028ttec1_panel_vm = {
46 .x_res = 480, 46 .hactive = 480,
47 .y_res = 640, 47 .vactive = 640,
48 .pixelclock = 22153000, 48 .pixelclock = 22153000,
49 .hfp = 24, 49 .hfront_porch = 24,
50 .hsw = 8, 50 .hsync_len = 8,
51 .hbp = 8, 51 .hback_porch = 8,
52 .vfp = 4, 52 .vfront_porch = 4,
53 .vsw = 2, 53 .vsync_len = 2,
54 .vbp = 2, 54 .vback_porch = 2,
55 55
56 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW, 56 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
57 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW, 57 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_SYNC_POSEDGE |
58 58 DISPLAY_FLAGS_PIXDATA_NEGEDGE,
59 .data_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE, 59 /*
60 .de_level = OMAPDSS_SIG_ACTIVE_HIGH, 60 * Note: According to the panel documentation:
61 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE, 61 * SYNC needs to be driven on the FALLING edge
62 */
62}; 63};
63 64
64#define JBT_COMMAND 0x000 65#define JBT_COMMAND 0x000
@@ -208,7 +209,7 @@ static int td028ttec1_panel_enable(struct omap_dss_device *dssdev)
208 209
209 if (ddata->data_lines) 210 if (ddata->data_lines)
210 in->ops.dpi->set_data_lines(in, ddata->data_lines); 211 in->ops.dpi->set_data_lines(in, ddata->data_lines);
211 in->ops.dpi->set_timings(in, &ddata->videomode); 212 in->ops.dpi->set_timings(in, &ddata->vm);
212 213
213 r = in->ops.dpi->enable(in); 214 r = in->ops.dpi->enable(in);
214 if (r) 215 if (r)
@@ -325,32 +326,32 @@ static void td028ttec1_panel_disable(struct omap_dss_device *dssdev)
325} 326}
326 327
327static void td028ttec1_panel_set_timings(struct omap_dss_device *dssdev, 328static void td028ttec1_panel_set_timings(struct omap_dss_device *dssdev,
328 struct omap_video_timings *timings) 329 struct videomode *vm)
329{ 330{
330 struct panel_drv_data *ddata = to_panel_data(dssdev); 331 struct panel_drv_data *ddata = to_panel_data(dssdev);
331 struct omap_dss_device *in = ddata->in; 332 struct omap_dss_device *in = ddata->in;
332 333
333 ddata->videomode = *timings; 334 ddata->vm = *vm;
334 dssdev->panel.timings = *timings; 335 dssdev->panel.vm = *vm;
335 336
336 in->ops.dpi->set_timings(in, timings); 337 in->ops.dpi->set_timings(in, vm);
337} 338}
338 339
339static void td028ttec1_panel_get_timings(struct omap_dss_device *dssdev, 340static void td028ttec1_panel_get_timings(struct omap_dss_device *dssdev,
340 struct omap_video_timings *timings) 341 struct videomode *vm)
341{ 342{
342 struct panel_drv_data *ddata = to_panel_data(dssdev); 343 struct panel_drv_data *ddata = to_panel_data(dssdev);
343 344
344 *timings = ddata->videomode; 345 *vm = ddata->vm;
345} 346}
346 347
347static int td028ttec1_panel_check_timings(struct omap_dss_device *dssdev, 348static int td028ttec1_panel_check_timings(struct omap_dss_device *dssdev,
348 struct omap_video_timings *timings) 349 struct videomode *vm)
349{ 350{
350 struct panel_drv_data *ddata = to_panel_data(dssdev); 351 struct panel_drv_data *ddata = to_panel_data(dssdev);
351 struct omap_dss_device *in = ddata->in; 352 struct omap_dss_device *in = ddata->in;
352 353
353 return in->ops.dpi->check_timings(in, timings); 354 return in->ops.dpi->check_timings(in, vm);
354} 355}
355 356
356static struct omap_dss_driver td028ttec1_ops = { 357static struct omap_dss_driver td028ttec1_ops = {
@@ -414,14 +415,14 @@ static int td028ttec1_panel_probe(struct spi_device *spi)
414 if (r) 415 if (r)
415 return r; 416 return r;
416 417
417 ddata->videomode = td028ttec1_panel_timings; 418 ddata->vm = td028ttec1_panel_vm;
418 419
419 dssdev = &ddata->dssdev; 420 dssdev = &ddata->dssdev;
420 dssdev->dev = &spi->dev; 421 dssdev->dev = &spi->dev;
421 dssdev->driver = &td028ttec1_ops; 422 dssdev->driver = &td028ttec1_ops;
422 dssdev->type = OMAP_DISPLAY_TYPE_DPI; 423 dssdev->type = OMAP_DISPLAY_TYPE_DPI;
423 dssdev->owner = THIS_MODULE; 424 dssdev->owner = THIS_MODULE;
424 dssdev->panel.timings = ddata->videomode; 425 dssdev->panel.vm = ddata->vm;
425 dssdev->phy.dpi.data_lines = ddata->data_lines; 426 dssdev->phy.dpi.data_lines = ddata->data_lines;
426 427
427 r = omapdss_register_display(dssdev); 428 r = omapdss_register_display(dssdev);
diff --git a/drivers/gpu/drm/omapdrm/displays/panel-tpo-td043mtea1.c b/drivers/gpu/drm/omapdrm/displays/panel-tpo-td043mtea1.c
index 66c6bbe6472b..0787dba44faa 100644
--- a/drivers/gpu/drm/omapdrm/displays/panel-tpo-td043mtea1.c
+++ b/drivers/gpu/drm/omapdrm/displays/panel-tpo-td043mtea1.c
@@ -56,7 +56,7 @@ struct panel_drv_data {
56 struct omap_dss_device dssdev; 56 struct omap_dss_device dssdev;
57 struct omap_dss_device *in; 57 struct omap_dss_device *in;
58 58
59 struct omap_video_timings videomode; 59 struct videomode vm;
60 60
61 int data_lines; 61 int data_lines;
62 62
@@ -72,25 +72,27 @@ struct panel_drv_data {
72 u32 power_on_resume:1; 72 u32 power_on_resume:1;
73}; 73};
74 74
75static const struct omap_video_timings tpo_td043_timings = { 75static const struct videomode tpo_td043_vm = {
76 .x_res = 800, 76 .hactive = 800,
77 .y_res = 480, 77 .vactive = 480,
78 78
79 .pixelclock = 36000000, 79 .pixelclock = 36000000,
80 80
81 .hsw = 1, 81 .hsync_len = 1,
82 .hfp = 68, 82 .hfront_porch = 68,
83 .hbp = 214, 83 .hback_porch = 214,
84 84
85 .vsw = 1, 85 .vsync_len = 1,
86 .vfp = 39, 86 .vfront_porch = 39,
87 .vbp = 34, 87 .vback_porch = 34,
88 88
89 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW, 89 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
90 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW, 90 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_SYNC_POSEDGE |
91 .data_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE, 91 DISPLAY_FLAGS_PIXDATA_NEGEDGE,
92 .de_level = OMAPDSS_SIG_ACTIVE_HIGH, 92 /*
93 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE, 93 * Note: According to the panel documentation:
94 * SYNC needs to be driven on the FALLING edge
95 */
94}; 96};
95 97
96#define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev) 98#define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev)
@@ -378,7 +380,7 @@ static int tpo_td043_enable(struct omap_dss_device *dssdev)
378 380
379 if (ddata->data_lines) 381 if (ddata->data_lines)
380 in->ops.dpi->set_data_lines(in, ddata->data_lines); 382 in->ops.dpi->set_data_lines(in, ddata->data_lines);
381 in->ops.dpi->set_timings(in, &ddata->videomode); 383 in->ops.dpi->set_timings(in, &ddata->vm);
382 384
383 r = in->ops.dpi->enable(in); 385 r = in->ops.dpi->enable(in);
384 if (r) 386 if (r)
@@ -418,32 +420,32 @@ static void tpo_td043_disable(struct omap_dss_device *dssdev)
418} 420}
419 421
420static void tpo_td043_set_timings(struct omap_dss_device *dssdev, 422static void tpo_td043_set_timings(struct omap_dss_device *dssdev,
421 struct omap_video_timings *timings) 423 struct videomode *vm)
422{ 424{
423 struct panel_drv_data *ddata = to_panel_data(dssdev); 425 struct panel_drv_data *ddata = to_panel_data(dssdev);
424 struct omap_dss_device *in = ddata->in; 426 struct omap_dss_device *in = ddata->in;
425 427
426 ddata->videomode = *timings; 428 ddata->vm = *vm;
427 dssdev->panel.timings = *timings; 429 dssdev->panel.vm = *vm;
428 430
429 in->ops.dpi->set_timings(in, timings); 431 in->ops.dpi->set_timings(in, vm);
430} 432}
431 433
432static void tpo_td043_get_timings(struct omap_dss_device *dssdev, 434static void tpo_td043_get_timings(struct omap_dss_device *dssdev,
433 struct omap_video_timings *timings) 435 struct videomode *vm)
434{ 436{
435 struct panel_drv_data *ddata = to_panel_data(dssdev); 437 struct panel_drv_data *ddata = to_panel_data(dssdev);
436 438
437 *timings = ddata->videomode; 439 *vm = ddata->vm;
438} 440}
439 441
440static int tpo_td043_check_timings(struct omap_dss_device *dssdev, 442static int tpo_td043_check_timings(struct omap_dss_device *dssdev,
441 struct omap_video_timings *timings) 443 struct videomode *vm)
442{ 444{
443 struct panel_drv_data *ddata = to_panel_data(dssdev); 445 struct panel_drv_data *ddata = to_panel_data(dssdev);
444 struct omap_dss_device *in = ddata->in; 446 struct omap_dss_device *in = ddata->in;
445 447
446 return in->ops.dpi->check_timings(in, timings); 448 return in->ops.dpi->check_timings(in, vm);
447} 449}
448 450
449static struct omap_dss_driver tpo_td043_ops = { 451static struct omap_dss_driver tpo_td043_ops = {
@@ -546,14 +548,14 @@ static int tpo_td043_probe(struct spi_device *spi)
546 goto err_sysfs; 548 goto err_sysfs;
547 } 549 }
548 550
549 ddata->videomode = tpo_td043_timings; 551 ddata->vm = tpo_td043_vm;
550 552
551 dssdev = &ddata->dssdev; 553 dssdev = &ddata->dssdev;
552 dssdev->dev = &spi->dev; 554 dssdev->dev = &spi->dev;
553 dssdev->driver = &tpo_td043_ops; 555 dssdev->driver = &tpo_td043_ops;
554 dssdev->type = OMAP_DISPLAY_TYPE_DPI; 556 dssdev->type = OMAP_DISPLAY_TYPE_DPI;
555 dssdev->owner = THIS_MODULE; 557 dssdev->owner = THIS_MODULE;
556 dssdev->panel.timings = ddata->videomode; 558 dssdev->panel.vm = ddata->vm;
557 559
558 r = omapdss_register_display(dssdev); 560 r = omapdss_register_display(dssdev);
559 if (r) { 561 if (r) {
diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c
index 535240fba671..c839f6456db2 100644
--- a/drivers/gpu/drm/omapdrm/dss/dispc.c
+++ b/drivers/gpu/drm/omapdrm/dss/dispc.c
@@ -75,7 +75,7 @@ struct dispc_features {
75 unsigned long max_lcd_pclk; 75 unsigned long max_lcd_pclk;
76 unsigned long max_tv_pclk; 76 unsigned long max_tv_pclk;
77 int (*calc_scaling) (unsigned long pclk, unsigned long lclk, 77 int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
78 const struct omap_video_timings *mgr_timings, 78 const struct videomode *vm,
79 u16 width, u16 height, u16 out_width, u16 out_height, 79 u16 width, u16 height, u16 out_width, u16 out_height,
80 enum omap_color_mode color_mode, bool *five_taps, 80 enum omap_color_mode color_mode, bool *five_taps,
81 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, 81 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
@@ -1679,7 +1679,7 @@ static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1679{ 1679{
1680 int scale_x = out_width != orig_width; 1680 int scale_x = out_width != orig_width;
1681 int scale_y = out_height != orig_height; 1681 int scale_y = out_height != orig_height;
1682 bool chroma_upscale = plane != OMAP_DSS_WB ? true : false; 1682 bool chroma_upscale = plane != OMAP_DSS_WB;
1683 1683
1684 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) 1684 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1685 return; 1685 return;
@@ -2179,7 +2179,7 @@ static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
2179 * undocumented horizontal position and timing related limitations. 2179 * undocumented horizontal position and timing related limitations.
2180 */ 2180 */
2181static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk, 2181static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
2182 const struct omap_video_timings *t, u16 pos_x, 2182 const struct videomode *vm, u16 pos_x,
2183 u16 width, u16 height, u16 out_width, u16 out_height, 2183 u16 width, u16 height, u16 out_width, u16 out_height,
2184 bool five_taps) 2184 bool five_taps)
2185{ 2185{
@@ -2189,14 +2189,16 @@ static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
2189 u64 val, blank; 2189 u64 val, blank;
2190 int i; 2190 int i;
2191 2191
2192 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width; 2192 nonactive = vm->hactive + vm->hfront_porch + vm->hsync_len +
2193 vm->hback_porch - out_width;
2193 2194
2194 i = 0; 2195 i = 0;
2195 if (out_height < height) 2196 if (out_height < height)
2196 i++; 2197 i++;
2197 if (out_width < width) 2198 if (out_width < width)
2198 i++; 2199 i++;
2199 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk); 2200 blank = div_u64((u64)(vm->hback_porch + vm->hsync_len + vm->hfront_porch) *
2201 lclk, pclk);
2200 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]); 2202 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2201 if (blank <= limits[i]) 2203 if (blank <= limits[i])
2202 return -EINVAL; 2204 return -EINVAL;
@@ -2231,7 +2233,7 @@ static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
2231} 2233}
2232 2234
2233static unsigned long calc_core_clk_five_taps(unsigned long pclk, 2235static unsigned long calc_core_clk_five_taps(unsigned long pclk,
2234 const struct omap_video_timings *mgr_timings, u16 width, 2236 const struct videomode *vm, u16 width,
2235 u16 height, u16 out_width, u16 out_height, 2237 u16 height, u16 out_width, u16 out_height,
2236 enum omap_color_mode color_mode) 2238 enum omap_color_mode color_mode)
2237{ 2239{
@@ -2242,7 +2244,7 @@ static unsigned long calc_core_clk_five_taps(unsigned long pclk,
2242 return (unsigned long) pclk; 2244 return (unsigned long) pclk;
2243 2245
2244 if (height > out_height) { 2246 if (height > out_height) {
2245 unsigned int ppl = mgr_timings->x_res; 2247 unsigned int ppl = vm->hactive;
2246 2248
2247 tmp = (u64)pclk * height * out_width; 2249 tmp = (u64)pclk * height * out_width;
2248 do_div(tmp, 2 * out_height * ppl); 2250 do_div(tmp, 2 * out_height * ppl);
@@ -2324,7 +2326,7 @@ static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
2324} 2326}
2325 2327
2326static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk, 2328static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
2327 const struct omap_video_timings *mgr_timings, 2329 const struct videomode *vm,
2328 u16 width, u16 height, u16 out_width, u16 out_height, 2330 u16 width, u16 height, u16 out_width, u16 out_height,
2329 enum omap_color_mode color_mode, bool *five_taps, 2331 enum omap_color_mode color_mode, bool *five_taps,
2330 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, 2332 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
@@ -2370,7 +2372,7 @@ static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
2370} 2372}
2371 2373
2372static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk, 2374static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
2373 const struct omap_video_timings *mgr_timings, 2375 const struct videomode *vm,
2374 u16 width, u16 height, u16 out_width, u16 out_height, 2376 u16 width, u16 height, u16 out_width, u16 out_height,
2375 enum omap_color_mode color_mode, bool *five_taps, 2377 enum omap_color_mode color_mode, bool *five_taps,
2376 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, 2378 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
@@ -2392,7 +2394,7 @@ static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
2392 *five_taps = false; 2394 *five_taps = false;
2393again: 2395again:
2394 if (*five_taps) 2396 if (*five_taps)
2395 *core_clk = calc_core_clk_five_taps(pclk, mgr_timings, 2397 *core_clk = calc_core_clk_five_taps(pclk, vm,
2396 in_width, in_height, out_width, 2398 in_width, in_height, out_width,
2397 out_height, color_mode); 2399 out_height, color_mode);
2398 else 2400 else
@@ -2400,7 +2402,7 @@ again:
2400 in_height, out_width, out_height, 2402 in_height, out_width, out_height,
2401 mem_to_mem); 2403 mem_to_mem);
2402 2404
2403 error = check_horiz_timing_omap3(pclk, lclk, mgr_timings, 2405 error = check_horiz_timing_omap3(pclk, lclk, vm,
2404 pos_x, in_width, in_height, out_width, 2406 pos_x, in_width, in_height, out_width,
2405 out_height, *five_taps); 2407 out_height, *five_taps);
2406 if (error && *five_taps) { 2408 if (error && *five_taps) {
@@ -2435,7 +2437,7 @@ again:
2435 return -EINVAL; 2437 return -EINVAL;
2436 } 2438 }
2437 2439
2438 if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, in_width, 2440 if (check_horiz_timing_omap3(pclk, lclk, vm, pos_x, in_width,
2439 in_height, out_width, out_height, *five_taps)) { 2441 in_height, out_width, out_height, *five_taps)) {
2440 DSSERR("horizontal timing too tight\n"); 2442 DSSERR("horizontal timing too tight\n");
2441 return -EINVAL; 2443 return -EINVAL;
@@ -2455,7 +2457,7 @@ again:
2455} 2457}
2456 2458
2457static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk, 2459static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
2458 const struct omap_video_timings *mgr_timings, 2460 const struct videomode *vm,
2459 u16 width, u16 height, u16 out_width, u16 out_height, 2461 u16 width, u16 height, u16 out_width, u16 out_height,
2460 enum omap_color_mode color_mode, bool *five_taps, 2462 enum omap_color_mode color_mode, bool *five_taps,
2461 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, 2463 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
@@ -2501,7 +2503,7 @@ static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
2501 2503
2502static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk, 2504static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
2503 enum omap_overlay_caps caps, 2505 enum omap_overlay_caps caps,
2504 const struct omap_video_timings *mgr_timings, 2506 const struct videomode *vm,
2505 u16 width, u16 height, u16 out_width, u16 out_height, 2507 u16 width, u16 height, u16 out_width, u16 out_height,
2506 enum omap_color_mode color_mode, bool *five_taps, 2508 enum omap_color_mode color_mode, bool *five_taps,
2507 int *x_predecim, int *y_predecim, u16 pos_x, 2509 int *x_predecim, int *y_predecim, u16 pos_x,
@@ -2515,7 +2517,7 @@ static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
2515 if (width == out_width && height == out_height) 2517 if (width == out_width && height == out_height)
2516 return 0; 2518 return 0;
2517 2519
2518 if (!mem_to_mem && (pclk == 0 || mgr_timings->pixelclock == 0)) { 2520 if (!mem_to_mem && (pclk == 0 || vm->pixelclock == 0)) {
2519 DSSERR("cannot calculate scaling settings: pclk is zero\n"); 2521 DSSERR("cannot calculate scaling settings: pclk is zero\n");
2520 return -EINVAL; 2522 return -EINVAL;
2521 } 2523 }
@@ -2551,7 +2553,7 @@ static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
2551 if (decim_y > *y_predecim || out_height > height * 8) 2553 if (decim_y > *y_predecim || out_height > height * 8)
2552 return -EINVAL; 2554 return -EINVAL;
2553 2555
2554 ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height, 2556 ret = dispc.feat->calc_scaling(pclk, lclk, vm, width, height,
2555 out_width, out_height, color_mode, five_taps, 2557 out_width, out_height, color_mode, five_taps,
2556 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk, 2558 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2557 mem_to_mem); 2559 mem_to_mem);
@@ -2591,7 +2593,7 @@ static int dispc_ovl_setup_common(enum omap_plane plane,
2591 u16 out_width, u16 out_height, enum omap_color_mode color_mode, 2593 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2592 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha, 2594 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2593 u8 global_alpha, enum omap_dss_rotation_type rotation_type, 2595 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
2594 bool replication, const struct omap_video_timings *mgr_timings, 2596 bool replication, const struct videomode *vm,
2595 bool mem_to_mem) 2597 bool mem_to_mem)
2596{ 2598{
2597 bool five_taps = true; 2599 bool five_taps = true;
@@ -2605,7 +2607,7 @@ static int dispc_ovl_setup_common(enum omap_plane plane,
2605 u16 in_height = height; 2607 u16 in_height = height;
2606 u16 in_width = width; 2608 u16 in_width = width;
2607 int x_predecim = 1, y_predecim = 1; 2609 int x_predecim = 1, y_predecim = 1;
2608 bool ilace = mgr_timings->interlace; 2610 bool ilace = !!(vm->flags & DISPLAY_FLAGS_INTERLACED);
2609 unsigned long pclk = dispc_plane_pclk_rate(plane); 2611 unsigned long pclk = dispc_plane_pclk_rate(plane);
2610 unsigned long lclk = dispc_plane_lclk_rate(plane); 2612 unsigned long lclk = dispc_plane_lclk_rate(plane);
2611 2613
@@ -2647,7 +2649,7 @@ static int dispc_ovl_setup_common(enum omap_plane plane,
2647 if (!dss_feat_color_mode_supported(plane, color_mode)) 2649 if (!dss_feat_color_mode_supported(plane, color_mode))
2648 return -EINVAL; 2650 return -EINVAL;
2649 2651
2650 r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width, 2652 r = dispc_ovl_calc_scaling(pclk, lclk, caps, vm, in_width,
2651 in_height, out_width, out_height, color_mode, 2653 in_height, out_width, out_height, color_mode,
2652 &five_taps, &x_predecim, &y_predecim, pos_x, 2654 &five_taps, &x_predecim, &y_predecim, pos_x,
2653 rotation_type, mem_to_mem); 2655 rotation_type, mem_to_mem);
@@ -2784,7 +2786,7 @@ static int dispc_ovl_setup_common(enum omap_plane plane,
2784} 2786}
2785 2787
2786int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi, 2788int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
2787 bool replication, const struct omap_video_timings *mgr_timings, 2789 bool replication, const struct videomode *vm,
2788 bool mem_to_mem) 2790 bool mem_to_mem)
2789{ 2791{
2790 int r; 2792 int r;
@@ -2803,14 +2805,14 @@ int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
2803 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height, 2805 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2804 oi->out_width, oi->out_height, oi->color_mode, oi->rotation, 2806 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2805 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha, 2807 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
2806 oi->rotation_type, replication, mgr_timings, mem_to_mem); 2808 oi->rotation_type, replication, vm, mem_to_mem);
2807 2809
2808 return r; 2810 return r;
2809} 2811}
2810EXPORT_SYMBOL(dispc_ovl_setup); 2812EXPORT_SYMBOL(dispc_ovl_setup);
2811 2813
2812int dispc_wb_setup(const struct omap_dss_writeback_info *wi, 2814int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
2813 bool mem_to_mem, const struct omap_video_timings *mgr_timings) 2815 bool mem_to_mem, const struct videomode *vm)
2814{ 2816{
2815 int r; 2817 int r;
2816 u32 l; 2818 u32 l;
@@ -2819,8 +2821,8 @@ int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
2819 const u8 zorder = 0, global_alpha = 0; 2821 const u8 zorder = 0, global_alpha = 0;
2820 const bool replication = false; 2822 const bool replication = false;
2821 bool truncation; 2823 bool truncation;
2822 int in_width = mgr_timings->x_res; 2824 int in_width = vm->hactive;
2823 int in_height = mgr_timings->y_res; 2825 int in_height = vm->vactive;
2824 enum omap_overlay_caps caps = 2826 enum omap_overlay_caps caps =
2825 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA; 2827 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2826 2828
@@ -2833,7 +2835,7 @@ int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
2833 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width, 2835 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2834 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder, 2836 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2835 wi->pre_mult_alpha, global_alpha, wi->rotation_type, 2837 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
2836 replication, mgr_timings, mem_to_mem); 2838 replication, vm, mem_to_mem);
2837 2839
2838 switch (wi->color_mode) { 2840 switch (wi->color_mode) {
2839 case OMAP_DSS_COLOR_RGB16: 2841 case OMAP_DSS_COLOR_RGB16:
@@ -2867,8 +2869,8 @@ int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
2867 } else { 2869 } else {
2868 int wbdelay; 2870 int wbdelay;
2869 2871
2870 wbdelay = min(mgr_timings->vfp + mgr_timings->vsw + 2872 wbdelay = min(vm->vfront_porch +
2871 mgr_timings->vbp, 255); 2873 vm->vsync_len + vm->vback_porch, (u32)255);
2872 2874
2873 /* WBDELAYCOUNT */ 2875 /* WBDELAYCOUNT */
2874 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0); 2876 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0);
@@ -3093,10 +3095,10 @@ static bool _dispc_mgr_size_ok(u16 width, u16 height)
3093 height <= dispc.feat->mgr_height_max; 3095 height <= dispc.feat->mgr_height_max;
3094} 3096}
3095 3097
3096static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp, 3098static bool _dispc_lcd_timings_ok(int hsync_len, int hfp, int hbp,
3097 int vsw, int vfp, int vbp) 3099 int vsw, int vfp, int vbp)
3098{ 3100{
3099 if (hsw < 1 || hsw > dispc.feat->sw_max || 3101 if (hsync_len < 1 || hsync_len > dispc.feat->sw_max ||
3100 hfp < 1 || hfp > dispc.feat->hp_max || 3102 hfp < 1 || hfp > dispc.feat->hp_max ||
3101 hbp < 1 || hbp > dispc.feat->hp_max || 3103 hbp < 1 || hbp > dispc.feat->hp_max ||
3102 vsw < 1 || vsw > dispc.feat->sw_max || 3104 vsw < 1 || vsw > dispc.feat->sw_max ||
@@ -3110,113 +3112,77 @@ static bool _dispc_mgr_pclk_ok(enum omap_channel channel,
3110 unsigned long pclk) 3112 unsigned long pclk)
3111{ 3113{
3112 if (dss_mgr_is_lcd(channel)) 3114 if (dss_mgr_is_lcd(channel))
3113 return pclk <= dispc.feat->max_lcd_pclk ? true : false; 3115 return pclk <= dispc.feat->max_lcd_pclk;
3114 else 3116 else
3115 return pclk <= dispc.feat->max_tv_pclk ? true : false; 3117 return pclk <= dispc.feat->max_tv_pclk;
3116} 3118}
3117 3119
3118bool dispc_mgr_timings_ok(enum omap_channel channel, 3120bool dispc_mgr_timings_ok(enum omap_channel channel, const struct videomode *vm)
3119 const struct omap_video_timings *timings)
3120{ 3121{
3121 if (!_dispc_mgr_size_ok(timings->x_res, timings->y_res)) 3122 if (!_dispc_mgr_size_ok(vm->hactive, vm->vactive))
3122 return false; 3123 return false;
3123 3124
3124 if (!_dispc_mgr_pclk_ok(channel, timings->pixelclock)) 3125 if (!_dispc_mgr_pclk_ok(channel, vm->pixelclock))
3125 return false; 3126 return false;
3126 3127
3127 if (dss_mgr_is_lcd(channel)) { 3128 if (dss_mgr_is_lcd(channel)) {
3128 /* TODO: OMAP4+ supports interlace for LCD outputs */ 3129 /* TODO: OMAP4+ supports interlace for LCD outputs */
3129 if (timings->interlace) 3130 if (vm->flags & DISPLAY_FLAGS_INTERLACED)
3130 return false; 3131 return false;
3131 3132
3132 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp, 3133 if (!_dispc_lcd_timings_ok(vm->hsync_len,
3133 timings->hbp, timings->vsw, timings->vfp, 3134 vm->hfront_porch, vm->hback_porch,
3134 timings->vbp)) 3135 vm->vsync_len, vm->vfront_porch,
3136 vm->vback_porch))
3135 return false; 3137 return false;
3136 } 3138 }
3137 3139
3138 return true; 3140 return true;
3139} 3141}
3140 3142
3141static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw, 3143static void _dispc_mgr_set_lcd_timings(enum omap_channel channel,
3142 int hfp, int hbp, int vsw, int vfp, int vbp, 3144 const struct videomode *vm)
3143 enum omap_dss_signal_level vsync_level,
3144 enum omap_dss_signal_level hsync_level,
3145 enum omap_dss_signal_edge data_pclk_edge,
3146 enum omap_dss_signal_level de_level,
3147 enum omap_dss_signal_edge sync_pclk_edge)
3148
3149{ 3145{
3150 u32 timing_h, timing_v, l; 3146 u32 timing_h, timing_v, l;
3151 bool onoff, rf, ipc, vs, hs, de; 3147 bool onoff, rf, ipc, vs, hs, de;
3152 3148
3153 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) | 3149 timing_h = FLD_VAL(vm->hsync_len - 1, dispc.feat->sw_start, 0) |
3154 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) | 3150 FLD_VAL(vm->hfront_porch - 1, dispc.feat->fp_start, 8) |
3155 FLD_VAL(hbp-1, dispc.feat->bp_start, 20); 3151 FLD_VAL(vm->hback_porch - 1, dispc.feat->bp_start, 20);
3156 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) | 3152 timing_v = FLD_VAL(vm->vsync_len - 1, dispc.feat->sw_start, 0) |
3157 FLD_VAL(vfp, dispc.feat->fp_start, 8) | 3153 FLD_VAL(vm->vfront_porch, dispc.feat->fp_start, 8) |
3158 FLD_VAL(vbp, dispc.feat->bp_start, 20); 3154 FLD_VAL(vm->vback_porch, dispc.feat->bp_start, 20);
3159 3155
3160 dispc_write_reg(DISPC_TIMING_H(channel), timing_h); 3156 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
3161 dispc_write_reg(DISPC_TIMING_V(channel), timing_v); 3157 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
3162 3158
3163 switch (vsync_level) { 3159 if (vm->flags & DISPLAY_FLAGS_VSYNC_HIGH)
3164 case OMAPDSS_SIG_ACTIVE_LOW:
3165 vs = true;
3166 break;
3167 case OMAPDSS_SIG_ACTIVE_HIGH:
3168 vs = false; 3160 vs = false;
3169 break; 3161 else
3170 default: 3162 vs = true;
3171 BUG();
3172 }
3173 3163
3174 switch (hsync_level) { 3164 if (vm->flags & DISPLAY_FLAGS_HSYNC_HIGH)
3175 case OMAPDSS_SIG_ACTIVE_LOW:
3176 hs = true;
3177 break;
3178 case OMAPDSS_SIG_ACTIVE_HIGH:
3179 hs = false; 3165 hs = false;
3180 break; 3166 else
3181 default: 3167 hs = true;
3182 BUG();
3183 }
3184 3168
3185 switch (de_level) { 3169 if (vm->flags & DISPLAY_FLAGS_DE_HIGH)
3186 case OMAPDSS_SIG_ACTIVE_LOW:
3187 de = true;
3188 break;
3189 case OMAPDSS_SIG_ACTIVE_HIGH:
3190 de = false; 3170 de = false;
3191 break; 3171 else
3192 default: 3172 de = true;
3193 BUG();
3194 }
3195 3173
3196 switch (data_pclk_edge) { 3174 if (vm->flags & DISPLAY_FLAGS_PIXDATA_POSEDGE)
3197 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3198 ipc = false; 3175 ipc = false;
3199 break; 3176 else
3200 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3201 ipc = true; 3177 ipc = true;
3202 break;
3203 default:
3204 BUG();
3205 }
3206 3178
3207 /* always use the 'rf' setting */ 3179 /* always use the 'rf' setting */
3208 onoff = true; 3180 onoff = true;
3209 3181
3210 switch (sync_pclk_edge) { 3182 if (vm->flags & DISPLAY_FLAGS_SYNC_POSEDGE)
3211 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3212 rf = false;
3213 break;
3214 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3215 rf = true; 3183 rf = true;
3216 break; 3184 else
3217 default: 3185 rf = false;
3218 BUG();
3219 }
3220 3186
3221 l = FLD_VAL(onoff, 17, 17) | 3187 l = FLD_VAL(onoff, 17, 17) |
3222 FLD_VAL(rf, 16, 16) | 3188 FLD_VAL(rf, 16, 16) |
@@ -3253,13 +3219,13 @@ static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
3253 3219
3254/* change name to mode? */ 3220/* change name to mode? */
3255void dispc_mgr_set_timings(enum omap_channel channel, 3221void dispc_mgr_set_timings(enum omap_channel channel,
3256 const struct omap_video_timings *timings) 3222 const struct videomode *vm)
3257{ 3223{
3258 unsigned xtot, ytot; 3224 unsigned xtot, ytot;
3259 unsigned long ht, vt; 3225 unsigned long ht, vt;
3260 struct omap_video_timings t = *timings; 3226 struct videomode t = *vm;
3261 3227
3262 DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res); 3228 DSSDBG("channel %d xres %u yres %u\n", channel, t.hactive, t.vactive);
3263 3229
3264 if (!dispc_mgr_timings_ok(channel, &t)) { 3230 if (!dispc_mgr_timings_ok(channel, &t)) {
3265 BUG(); 3231 BUG();
@@ -3267,34 +3233,37 @@ void dispc_mgr_set_timings(enum omap_channel channel,
3267 } 3233 }
3268 3234
3269 if (dss_mgr_is_lcd(channel)) { 3235 if (dss_mgr_is_lcd(channel)) {
3270 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw, 3236 _dispc_mgr_set_lcd_timings(channel, &t);
3271 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
3272 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
3273 3237
3274 xtot = t.x_res + t.hfp + t.hsw + t.hbp; 3238 xtot = t.hactive + t.hfront_porch + t.hsync_len + t.hback_porch;
3275 ytot = t.y_res + t.vfp + t.vsw + t.vbp; 3239 ytot = t.vactive + t.vfront_porch + t.vsync_len + t.vback_porch;
3276 3240
3277 ht = timings->pixelclock / xtot; 3241 ht = vm->pixelclock / xtot;
3278 vt = timings->pixelclock / xtot / ytot; 3242 vt = vm->pixelclock / xtot / ytot;
3279 3243
3280 DSSDBG("pck %u\n", timings->pixelclock); 3244 DSSDBG("pck %lu\n", vm->pixelclock);
3281 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n", 3245 DSSDBG("hsync_len %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
3282 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp); 3246 t.hsync_len, t.hfront_porch, t.hback_porch,
3247 t.vsync_len, t.vfront_porch, t.vback_porch);
3283 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n", 3248 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
3284 t.vsync_level, t.hsync_level, t.data_pclk_edge, 3249 !!(t.flags & DISPLAY_FLAGS_VSYNC_HIGH),
3285 t.de_level, t.sync_pclk_edge); 3250 !!(t.flags & DISPLAY_FLAGS_HSYNC_HIGH),
3251 !!(t.flags & DISPLAY_FLAGS_PIXDATA_POSEDGE),
3252 !!(t.flags & DISPLAY_FLAGS_DE_HIGH),
3253 !!(t.flags & DISPLAY_FLAGS_SYNC_POSEDGE));
3286 3254
3287 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt); 3255 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
3288 } else { 3256 } else {
3289 if (t.interlace) 3257 if (t.flags & DISPLAY_FLAGS_INTERLACED)
3290 t.y_res /= 2; 3258 t.vactive /= 2;
3291 3259
3292 if (dispc.feat->supports_double_pixel) 3260 if (dispc.feat->supports_double_pixel)
3293 REG_FLD_MOD(DISPC_CONTROL, t.double_pixel ? 1 : 0, 3261 REG_FLD_MOD(DISPC_CONTROL,
3294 19, 17); 3262 !!(t.flags & DISPLAY_FLAGS_DOUBLECLK),
3263 19, 17);
3295 } 3264 }
3296 3265
3297 dispc_mgr_set_size(channel, t.x_res, t.y_res); 3266 dispc_mgr_set_size(channel, t.hactive, t.vactive);
3298} 3267}
3299EXPORT_SYMBOL(dispc_mgr_set_timings); 3268EXPORT_SYMBOL(dispc_mgr_set_timings);
3300 3269
@@ -4214,23 +4183,20 @@ EXPORT_SYMBOL(dispc_free_irq);
4214 */ 4183 */
4215 4184
4216static const struct dispc_errata_i734_data { 4185static const struct dispc_errata_i734_data {
4217 struct omap_video_timings timings; 4186 struct videomode vm;
4218 struct omap_overlay_info ovli; 4187 struct omap_overlay_info ovli;
4219 struct omap_overlay_manager_info mgri; 4188 struct omap_overlay_manager_info mgri;
4220 struct dss_lcd_mgr_config lcd_conf; 4189 struct dss_lcd_mgr_config lcd_conf;
4221} i734 = { 4190} i734 = {
4222 .timings = { 4191 .vm = {
4223 .x_res = 8, .y_res = 1, 4192 .hactive = 8, .vactive = 1,
4224 .pixelclock = 16000000, 4193 .pixelclock = 16000000,
4225 .hsw = 8, .hfp = 4, .hbp = 4, 4194 .hsync_len = 8, .hfront_porch = 4, .hback_porch = 4,
4226 .vsw = 1, .vfp = 1, .vbp = 1, 4195 .vsync_len = 1, .vfront_porch = 1, .vback_porch = 1,
4227 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW, 4196
4228 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW, 4197 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
4229 .interlace = false, 4198 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_SYNC_POSEDGE |
4230 .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE, 4199 DISPLAY_FLAGS_PIXDATA_POSEDGE,
4231 .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
4232 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
4233 .double_pixel = false,
4234 }, 4200 },
4235 .ovli = { 4201 .ovli = {
4236 .screen_width = 1, 4202 .screen_width = 1,
@@ -4320,7 +4286,7 @@ static void dispc_errata_i734_wa(void)
4320 4286
4321 /* Setup and enable GFX plane */ 4287 /* Setup and enable GFX plane */
4322 dispc_ovl_set_channel_out(OMAP_DSS_GFX, OMAP_DSS_CHANNEL_LCD); 4288 dispc_ovl_set_channel_out(OMAP_DSS_GFX, OMAP_DSS_CHANNEL_LCD);
4323 dispc_ovl_setup(OMAP_DSS_GFX, &ovli, false, &i734.timings, false); 4289 dispc_ovl_setup(OMAP_DSS_GFX, &ovli, false, &i734.vm, false);
4324 dispc_ovl_enable(OMAP_DSS_GFX, true); 4290 dispc_ovl_enable(OMAP_DSS_GFX, true);
4325 4291
4326 /* Set up and enable display manager for LCD1 */ 4292 /* Set up and enable display manager for LCD1 */
@@ -4328,7 +4294,7 @@ static void dispc_errata_i734_wa(void)
4328 dispc_calc_clock_rates(dss_get_dispc_clk_rate(), 4294 dispc_calc_clock_rates(dss_get_dispc_clk_rate(),
4329 &lcd_conf.clock_info); 4295 &lcd_conf.clock_info);
4330 dispc_mgr_set_lcd_config(OMAP_DSS_CHANNEL_LCD, &lcd_conf); 4296 dispc_mgr_set_lcd_config(OMAP_DSS_CHANNEL_LCD, &lcd_conf);
4331 dispc_mgr_set_timings(OMAP_DSS_CHANNEL_LCD, &i734.timings); 4297 dispc_mgr_set_timings(OMAP_DSS_CHANNEL_LCD, &i734.vm);
4332 4298
4333 dispc_clear_irqstatus(framedone_irq); 4299 dispc_clear_irqstatus(framedone_irq);
4334 4300
diff --git a/drivers/gpu/drm/omapdrm/dss/display.c b/drivers/gpu/drm/omapdrm/dss/display.c
index 8dcdd7cf9937..425a5a8dff8b 100644
--- a/drivers/gpu/drm/omapdrm/dss/display.c
+++ b/drivers/gpu/drm/omapdrm/dss/display.c
@@ -35,8 +35,8 @@
35void omapdss_default_get_resolution(struct omap_dss_device *dssdev, 35void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
36 u16 *xres, u16 *yres) 36 u16 *xres, u16 *yres)
37{ 37{
38 *xres = dssdev->panel.timings.x_res; 38 *xres = dssdev->panel.vm.hactive;
39 *yres = dssdev->panel.timings.y_res; 39 *yres = dssdev->panel.vm.vactive;
40} 40}
41EXPORT_SYMBOL(omapdss_default_get_resolution); 41EXPORT_SYMBOL(omapdss_default_get_resolution);
42 42
@@ -72,9 +72,9 @@ int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev)
72EXPORT_SYMBOL(omapdss_default_get_recommended_bpp); 72EXPORT_SYMBOL(omapdss_default_get_recommended_bpp);
73 73
74void omapdss_default_get_timings(struct omap_dss_device *dssdev, 74void omapdss_default_get_timings(struct omap_dss_device *dssdev,
75 struct omap_video_timings *timings) 75 struct videomode *vm)
76{ 76{
77 *timings = dssdev->panel.timings; 77 *vm = dssdev->panel.vm;
78} 78}
79EXPORT_SYMBOL(omapdss_default_get_timings); 79EXPORT_SYMBOL(omapdss_default_get_timings);
80 80
@@ -217,73 +217,3 @@ struct omap_dss_device *omap_dss_find_device(void *data,
217 return NULL; 217 return NULL;
218} 218}
219EXPORT_SYMBOL(omap_dss_find_device); 219EXPORT_SYMBOL(omap_dss_find_device);
220
221void videomode_to_omap_video_timings(const struct videomode *vm,
222 struct omap_video_timings *ovt)
223{
224 memset(ovt, 0, sizeof(*ovt));
225
226 ovt->pixelclock = vm->pixelclock;
227 ovt->x_res = vm->hactive;
228 ovt->hbp = vm->hback_porch;
229 ovt->hfp = vm->hfront_porch;
230 ovt->hsw = vm->hsync_len;
231 ovt->y_res = vm->vactive;
232 ovt->vbp = vm->vback_porch;
233 ovt->vfp = vm->vfront_porch;
234 ovt->vsw = vm->vsync_len;
235
236 ovt->vsync_level = vm->flags & DISPLAY_FLAGS_VSYNC_HIGH ?
237 OMAPDSS_SIG_ACTIVE_HIGH :
238 OMAPDSS_SIG_ACTIVE_LOW;
239 ovt->hsync_level = vm->flags & DISPLAY_FLAGS_HSYNC_HIGH ?
240 OMAPDSS_SIG_ACTIVE_HIGH :
241 OMAPDSS_SIG_ACTIVE_LOW;
242 ovt->de_level = vm->flags & DISPLAY_FLAGS_DE_HIGH ?
243 OMAPDSS_SIG_ACTIVE_HIGH :
244 OMAPDSS_SIG_ACTIVE_LOW;
245 ovt->data_pclk_edge = vm->flags & DISPLAY_FLAGS_PIXDATA_POSEDGE ?
246 OMAPDSS_DRIVE_SIG_RISING_EDGE :
247 OMAPDSS_DRIVE_SIG_FALLING_EDGE;
248
249 ovt->sync_pclk_edge = ovt->data_pclk_edge;
250}
251EXPORT_SYMBOL(videomode_to_omap_video_timings);
252
253void omap_video_timings_to_videomode(const struct omap_video_timings *ovt,
254 struct videomode *vm)
255{
256 memset(vm, 0, sizeof(*vm));
257
258 vm->pixelclock = ovt->pixelclock;
259
260 vm->hactive = ovt->x_res;
261 vm->hback_porch = ovt->hbp;
262 vm->hfront_porch = ovt->hfp;
263 vm->hsync_len = ovt->hsw;
264 vm->vactive = ovt->y_res;
265 vm->vback_porch = ovt->vbp;
266 vm->vfront_porch = ovt->vfp;
267 vm->vsync_len = ovt->vsw;
268
269 if (ovt->hsync_level == OMAPDSS_SIG_ACTIVE_HIGH)
270 vm->flags |= DISPLAY_FLAGS_HSYNC_HIGH;
271 else
272 vm->flags |= DISPLAY_FLAGS_HSYNC_LOW;
273
274 if (ovt->vsync_level == OMAPDSS_SIG_ACTIVE_HIGH)
275 vm->flags |= DISPLAY_FLAGS_VSYNC_HIGH;
276 else
277 vm->flags |= DISPLAY_FLAGS_VSYNC_LOW;
278
279 if (ovt->de_level == OMAPDSS_SIG_ACTIVE_HIGH)
280 vm->flags |= DISPLAY_FLAGS_DE_HIGH;
281 else
282 vm->flags |= DISPLAY_FLAGS_DE_LOW;
283
284 if (ovt->data_pclk_edge == OMAPDSS_DRIVE_SIG_RISING_EDGE)
285 vm->flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE;
286 else
287 vm->flags |= DISPLAY_FLAGS_PIXDATA_NEGEDGE;
288}
289EXPORT_SYMBOL(omap_video_timings_to_videomode);
diff --git a/drivers/gpu/drm/omapdrm/dss/dpi.c b/drivers/gpu/drm/omapdrm/dss/dpi.c
index b268295b76cf..e75162d26ac0 100644
--- a/drivers/gpu/drm/omapdrm/dss/dpi.c
+++ b/drivers/gpu/drm/omapdrm/dss/dpi.c
@@ -47,7 +47,7 @@ struct dpi_data {
47 47
48 struct mutex lock; 48 struct mutex lock;
49 49
50 struct omap_video_timings timings; 50 struct videomode vm;
51 struct dss_lcd_mgr_config mgr_config; 51 struct dss_lcd_mgr_config mgr_config;
52 int data_lines; 52 int data_lines;
53 53
@@ -333,31 +333,31 @@ static int dpi_set_mode(struct dpi_data *dpi)
333{ 333{
334 struct omap_dss_device *out = &dpi->output; 334 struct omap_dss_device *out = &dpi->output;
335 enum omap_channel channel = out->dispc_channel; 335 enum omap_channel channel = out->dispc_channel;
336 struct omap_video_timings *t = &dpi->timings; 336 struct videomode *vm = &dpi->vm;
337 int lck_div = 0, pck_div = 0; 337 int lck_div = 0, pck_div = 0;
338 unsigned long fck = 0; 338 unsigned long fck = 0;
339 unsigned long pck; 339 unsigned long pck;
340 int r = 0; 340 int r = 0;
341 341
342 if (dpi->pll) 342 if (dpi->pll)
343 r = dpi_set_pll_clk(dpi, channel, t->pixelclock, &fck, 343 r = dpi_set_pll_clk(dpi, channel, vm->pixelclock, &fck,
344 &lck_div, &pck_div); 344 &lck_div, &pck_div);
345 else 345 else
346 r = dpi_set_dispc_clk(dpi, t->pixelclock, &fck, 346 r = dpi_set_dispc_clk(dpi, vm->pixelclock, &fck,
347 &lck_div, &pck_div); 347 &lck_div, &pck_div);
348 if (r) 348 if (r)
349 return r; 349 return r;
350 350
351 pck = fck / lck_div / pck_div; 351 pck = fck / lck_div / pck_div;
352 352
353 if (pck != t->pixelclock) { 353 if (pck != vm->pixelclock) {
354 DSSWARN("Could not find exact pixel clock. Requested %d Hz, got %lu Hz\n", 354 DSSWARN("Could not find exact pixel clock. Requested %lu Hz, got %lu Hz\n",
355 t->pixelclock, pck); 355 vm->pixelclock, pck);
356 356
357 t->pixelclock = pck; 357 vm->pixelclock = pck;
358 } 358 }
359 359
360 dss_mgr_set_timings(channel, t); 360 dss_mgr_set_timings(channel, vm);
361 361
362 return 0; 362 return 0;
363} 363}
@@ -476,7 +476,7 @@ static void dpi_display_disable(struct omap_dss_device *dssdev)
476} 476}
477 477
478static void dpi_set_timings(struct omap_dss_device *dssdev, 478static void dpi_set_timings(struct omap_dss_device *dssdev,
479 struct omap_video_timings *timings) 479 struct videomode *vm)
480{ 480{
481 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev); 481 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev);
482 482
@@ -484,25 +484,25 @@ static void dpi_set_timings(struct omap_dss_device *dssdev,
484 484
485 mutex_lock(&dpi->lock); 485 mutex_lock(&dpi->lock);
486 486
487 dpi->timings = *timings; 487 dpi->vm = *vm;
488 488
489 mutex_unlock(&dpi->lock); 489 mutex_unlock(&dpi->lock);
490} 490}
491 491
492static void dpi_get_timings(struct omap_dss_device *dssdev, 492static void dpi_get_timings(struct omap_dss_device *dssdev,
493 struct omap_video_timings *timings) 493 struct videomode *vm)
494{ 494{
495 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev); 495 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev);
496 496
497 mutex_lock(&dpi->lock); 497 mutex_lock(&dpi->lock);
498 498
499 *timings = dpi->timings; 499 *vm = dpi->vm;
500 500
501 mutex_unlock(&dpi->lock); 501 mutex_unlock(&dpi->lock);
502} 502}
503 503
504static int dpi_check_timings(struct omap_dss_device *dssdev, 504static int dpi_check_timings(struct omap_dss_device *dssdev,
505 struct omap_video_timings *timings) 505 struct videomode *vm)
506{ 506{
507 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev); 507 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev);
508 enum omap_channel channel = dpi->output.dispc_channel; 508 enum omap_channel channel = dpi->output.dispc_channel;
@@ -512,23 +512,23 @@ static int dpi_check_timings(struct omap_dss_device *dssdev,
512 struct dpi_clk_calc_ctx ctx; 512 struct dpi_clk_calc_ctx ctx;
513 bool ok; 513 bool ok;
514 514
515 if (timings->x_res % 8 != 0) 515 if (vm->hactive % 8 != 0)
516 return -EINVAL; 516 return -EINVAL;
517 517
518 if (!dispc_mgr_timings_ok(channel, timings)) 518 if (!dispc_mgr_timings_ok(channel, vm))
519 return -EINVAL; 519 return -EINVAL;
520 520
521 if (timings->pixelclock == 0) 521 if (vm->pixelclock == 0)
522 return -EINVAL; 522 return -EINVAL;
523 523
524 if (dpi->pll) { 524 if (dpi->pll) {
525 ok = dpi_pll_clk_calc(dpi, timings->pixelclock, &ctx); 525 ok = dpi_pll_clk_calc(dpi, vm->pixelclock, &ctx);
526 if (!ok) 526 if (!ok)
527 return -EINVAL; 527 return -EINVAL;
528 528
529 fck = ctx.pll_cinfo.clkout[ctx.clkout_idx]; 529 fck = ctx.pll_cinfo.clkout[ctx.clkout_idx];
530 } else { 530 } else {
531 ok = dpi_dss_clk_calc(timings->pixelclock, &ctx); 531 ok = dpi_dss_clk_calc(vm->pixelclock, &ctx);
532 if (!ok) 532 if (!ok)
533 return -EINVAL; 533 return -EINVAL;
534 534
@@ -540,7 +540,7 @@ static int dpi_check_timings(struct omap_dss_device *dssdev,
540 540
541 pck = fck / lck_div / pck_div; 541 pck = fck / lck_div / pck_div;
542 542
543 timings->pixelclock = pck; 543 vm->pixelclock = pck;
544 544
545 return 0; 545 return 0;
546} 546}
diff --git a/drivers/gpu/drm/omapdrm/dss/dsi.c b/drivers/gpu/drm/omapdrm/dss/dsi.c
index e1be5e795cd8..f060bda31235 100644
--- a/drivers/gpu/drm/omapdrm/dss/dsi.c
+++ b/drivers/gpu/drm/omapdrm/dss/dsi.c
@@ -289,7 +289,7 @@ struct dsi_clk_calc_ctx {
289 struct dss_pll_clock_info dsi_cinfo; 289 struct dss_pll_clock_info dsi_cinfo;
290 struct dispc_clock_info dispc_cinfo; 290 struct dispc_clock_info dispc_cinfo;
291 291
292 struct omap_video_timings dispc_vm; 292 struct videomode vm;
293 struct omap_dss_dsi_videomode_timings dsi_vm; 293 struct omap_dss_dsi_videomode_timings dsi_vm;
294}; 294};
295 295
@@ -383,7 +383,7 @@ struct dsi_data {
383 unsigned scp_clk_refcount; 383 unsigned scp_clk_refcount;
384 384
385 struct dss_lcd_mgr_config mgr_config; 385 struct dss_lcd_mgr_config mgr_config;
386 struct omap_video_timings timings; 386 struct videomode vm;
387 enum omap_dss_dsi_pixel_format pix_fmt; 387 enum omap_dss_dsi_pixel_format pix_fmt;
388 enum omap_dss_dsi_mode mode; 388 enum omap_dss_dsi_mode mode;
389 struct omap_dss_dsi_videomode_timings vm_timings; 389 struct omap_dss_dsi_videomode_timings vm_timings;
@@ -3321,12 +3321,12 @@ static void dsi_config_vp_num_line_buffers(struct platform_device *dsidev)
3321 3321
3322 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3322 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3323 int bpp = dsi_get_pixel_size(dsi->pix_fmt); 3323 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3324 struct omap_video_timings *timings = &dsi->timings; 3324 struct videomode *vm = &dsi->vm;
3325 /* 3325 /*
3326 * Don't use line buffers if width is greater than the video 3326 * Don't use line buffers if width is greater than the video
3327 * port's line buffer size 3327 * port's line buffer size
3328 */ 3328 */
3329 if (dsi->line_buffer_size <= timings->x_res * bpp / 8) 3329 if (dsi->line_buffer_size <= vm->hactive * bpp / 8)
3330 num_line_buffers = 0; 3330 num_line_buffers = 0;
3331 else 3331 else
3332 num_line_buffers = 2; 3332 num_line_buffers = 2;
@@ -3453,7 +3453,7 @@ static void dsi_config_cmd_mode_interleaving(struct platform_device *dsidev)
3453 int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat; 3453 int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat;
3454 int tclk_trail, ths_exit, exiths_clk; 3454 int tclk_trail, ths_exit, exiths_clk;
3455 bool ddr_alwon; 3455 bool ddr_alwon;
3456 struct omap_video_timings *timings = &dsi->timings; 3456 struct videomode *vm = &dsi->vm;
3457 int bpp = dsi_get_pixel_size(dsi->pix_fmt); 3457 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3458 int ndl = dsi->num_lanes_used - 1; 3458 int ndl = dsi->num_lanes_used - 1;
3459 int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.mX[HSDIV_DSI] + 1; 3459 int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.mX[HSDIV_DSI] + 1;
@@ -3494,7 +3494,7 @@ static void dsi_config_cmd_mode_interleaving(struct platform_device *dsidev)
3494 3494
3495 exiths_clk = ths_exit + tclk_trail; 3495 exiths_clk = ths_exit + tclk_trail;
3496 3496
3497 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8); 3497 width_bytes = DIV_ROUND_UP(vm->hactive * bpp, 8);
3498 bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl); 3498 bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl);
3499 3499
3500 if (!hsa_blanking_mode) { 3500 if (!hsa_blanking_mode) {
@@ -3705,7 +3705,7 @@ static void dsi_proto_timings(struct platform_device *dsidev)
3705 int vbp = dsi->vm_timings.vbp; 3705 int vbp = dsi->vm_timings.vbp;
3706 int window_sync = dsi->vm_timings.window_sync; 3706 int window_sync = dsi->vm_timings.window_sync;
3707 bool hsync_end; 3707 bool hsync_end;
3708 struct omap_video_timings *timings = &dsi->timings; 3708 struct videomode *vm = &dsi->vm;
3709 int bpp = dsi_get_pixel_size(dsi->pix_fmt); 3709 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3710 int tl, t_he, width_bytes; 3710 int tl, t_he, width_bytes;
3711 3711
@@ -3713,7 +3713,7 @@ static void dsi_proto_timings(struct platform_device *dsidev)
3713 t_he = hsync_end ? 3713 t_he = hsync_end ?
3714 ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0; 3714 ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;
3715 3715
3716 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8); 3716 width_bytes = DIV_ROUND_UP(vm->hactive * bpp, 8);
3717 3717
3718 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */ 3718 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
3719 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp + 3719 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
@@ -3722,7 +3722,7 @@ static void dsi_proto_timings(struct platform_device *dsidev)
3722 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp, 3722 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp,
3723 hfp, hsync_end ? hsa : 0, tl); 3723 hfp, hsync_end ? hsa : 0, tl);
3724 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp, 3724 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
3725 vsa, timings->y_res); 3725 vsa, vm->vactive);
3726 3726
3727 r = dsi_read_reg(dsidev, DSI_VM_TIMING1); 3727 r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3728 r = FLD_MOD(r, hbp, 11, 0); /* HBP */ 3728 r = FLD_MOD(r, hbp, 11, 0); /* HBP */
@@ -3738,7 +3738,7 @@ static void dsi_proto_timings(struct platform_device *dsidev)
3738 dsi_write_reg(dsidev, DSI_VM_TIMING2, r); 3738 dsi_write_reg(dsidev, DSI_VM_TIMING2, r);
3739 3739
3740 r = dsi_read_reg(dsidev, DSI_VM_TIMING3); 3740 r = dsi_read_reg(dsidev, DSI_VM_TIMING3);
3741 r = FLD_MOD(r, timings->y_res, 14, 0); /* VACT */ 3741 r = FLD_MOD(r, vm->vactive, 14, 0); /* VACT */
3742 r = FLD_MOD(r, tl, 31, 16); /* TL */ 3742 r = FLD_MOD(r, tl, 31, 16); /* TL */
3743 dsi_write_reg(dsidev, DSI_VM_TIMING3, r); 3743 dsi_write_reg(dsidev, DSI_VM_TIMING3, r);
3744 } 3744 }
@@ -3856,7 +3856,7 @@ static int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel)
3856 /* MODE, 1 = video mode */ 3856 /* MODE, 1 = video mode */
3857 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4); 3857 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4);
3858 3858
3859 word_count = DIV_ROUND_UP(dsi->timings.x_res * bpp, 8); 3859 word_count = DIV_ROUND_UP(dsi->vm.hactive * bpp, 8);
3860 3860
3861 dsi_vc_write_long_header(dsidev, channel, data_type, 3861 dsi_vc_write_long_header(dsidev, channel, data_type,
3862 word_count, 0); 3862 word_count, 0);
@@ -3918,8 +3918,8 @@ static void dsi_update_screen_dispc(struct platform_device *dsidev)
3918 int r; 3918 int r;
3919 const unsigned channel = dsi->update_channel; 3919 const unsigned channel = dsi->update_channel;
3920 const unsigned line_buf_size = dsi->line_buffer_size; 3920 const unsigned line_buf_size = dsi->line_buffer_size;
3921 u16 w = dsi->timings.x_res; 3921 u16 w = dsi->vm.hactive;
3922 u16 h = dsi->timings.y_res; 3922 u16 h = dsi->vm.vactive;
3923 3923
3924 DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h); 3924 DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h);
3925 3925
@@ -3969,7 +3969,7 @@ static void dsi_update_screen_dispc(struct platform_device *dsidev)
3969 msecs_to_jiffies(250)); 3969 msecs_to_jiffies(250));
3970 BUG_ON(r == 0); 3970 BUG_ON(r == 0);
3971 3971
3972 dss_mgr_set_timings(dispc_channel, &dsi->timings); 3972 dss_mgr_set_timings(dispc_channel, &dsi->vm);
3973 3973
3974 dss_mgr_start_update(dispc_channel); 3974 dss_mgr_start_update(dispc_channel);
3975 3975
@@ -4056,8 +4056,8 @@ static int dsi_update(struct omap_dss_device *dssdev, int channel,
4056 dsi->framedone_callback = callback; 4056 dsi->framedone_callback = callback;
4057 dsi->framedone_data = data; 4057 dsi->framedone_data = data;
4058 4058
4059 dw = dsi->timings.x_res; 4059 dw = dsi->vm.hactive;
4060 dh = dsi->timings.y_res; 4060 dh = dsi->vm.vactive;
4061 4061
4062#ifdef DSI_PERF_MEASURE 4062#ifdef DSI_PERF_MEASURE
4063 dsi->update_bytes = dw * dh * 4063 dsi->update_bytes = dw * dh *
@@ -4120,16 +4120,21 @@ static int dsi_display_init_dispc(struct platform_device *dsidev,
4120 4120
4121 /* 4121 /*
4122 * override interlace, logic level and edge related parameters in 4122 * override interlace, logic level and edge related parameters in
4123 * omap_video_timings with default values 4123 * videomode with default values
4124 */ 4124 */
4125 dsi->timings.interlace = false; 4125 dsi->vm.flags &= ~DISPLAY_FLAGS_INTERLACED;
4126 dsi->timings.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH; 4126 dsi->vm.flags &= ~DISPLAY_FLAGS_HSYNC_LOW;
4127 dsi->timings.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH; 4127 dsi->vm.flags |= DISPLAY_FLAGS_HSYNC_HIGH;
4128 dsi->timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE; 4128 dsi->vm.flags &= ~DISPLAY_FLAGS_VSYNC_LOW;
4129 dsi->timings.de_level = OMAPDSS_SIG_ACTIVE_HIGH; 4129 dsi->vm.flags |= DISPLAY_FLAGS_VSYNC_HIGH;
4130 dsi->timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE; 4130 dsi->vm.flags &= ~DISPLAY_FLAGS_PIXDATA_NEGEDGE;
4131 4131 dsi->vm.flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE;
4132 dss_mgr_set_timings(channel, &dsi->timings); 4132 dsi->vm.flags &= ~DISPLAY_FLAGS_DE_LOW;
4133 dsi->vm.flags |= DISPLAY_FLAGS_DE_HIGH;
4134 dsi->vm.flags &= ~DISPLAY_FLAGS_SYNC_POSEDGE;
4135 dsi->vm.flags |= DISPLAY_FLAGS_SYNC_NEGEDGE;
4136
4137 dss_mgr_set_timings(channel, &dsi->vm);
4133 4138
4134 r = dsi_configure_dispc_clocks(dsidev); 4139 r = dsi_configure_dispc_clocks(dsidev);
4135 if (r) 4140 if (r)
@@ -4331,7 +4336,7 @@ static void print_dsi_vm(const char *str,
4331 4336
4332 wc = DIV_ROUND_UP(t->hact * t->bitspp, 8); 4337 wc = DIV_ROUND_UP(t->hact * t->bitspp, 8);
4333 pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */ 4338 pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */
4334 bl = t->hss + t->hsa + t->hse + t->hbp + t->hfp; 4339 bl = t->hss + t->hsa + t->hse + t->hbp + t->hfront_porch;
4335 tot = bl + pps; 4340 tot = bl + pps;
4336 4341
4337#define TO_DSI_T(x) ((u32)div64_u64((u64)x * 1000000000llu, byteclk)) 4342#define TO_DSI_T(x) ((u32)div64_u64((u64)x * 1000000000llu, byteclk))
@@ -4340,14 +4345,14 @@ static void print_dsi_vm(const char *str,
4340 "%u/%u/%u/%u/%u/%u = %u + %u = %u\n", 4345 "%u/%u/%u/%u/%u/%u = %u + %u = %u\n",
4341 str, 4346 str,
4342 byteclk, 4347 byteclk,
4343 t->hss, t->hsa, t->hse, t->hbp, pps, t->hfp, 4348 t->hss, t->hsa, t->hse, t->hbp, pps, t->hfront_porch,
4344 bl, pps, tot, 4349 bl, pps, tot,
4345 TO_DSI_T(t->hss), 4350 TO_DSI_T(t->hss),
4346 TO_DSI_T(t->hsa), 4351 TO_DSI_T(t->hsa),
4347 TO_DSI_T(t->hse), 4352 TO_DSI_T(t->hse),
4348 TO_DSI_T(t->hbp), 4353 TO_DSI_T(t->hbp),
4349 TO_DSI_T(pps), 4354 TO_DSI_T(pps),
4350 TO_DSI_T(t->hfp), 4355 TO_DSI_T(t->hfront_porch),
4351 4356
4352 TO_DSI_T(bl), 4357 TO_DSI_T(bl),
4353 TO_DSI_T(pps), 4358 TO_DSI_T(pps),
@@ -4356,13 +4361,13 @@ static void print_dsi_vm(const char *str,
4356#undef TO_DSI_T 4361#undef TO_DSI_T
4357} 4362}
4358 4363
4359static void print_dispc_vm(const char *str, const struct omap_video_timings *t) 4364static void print_dispc_vm(const char *str, const struct videomode *vm)
4360{ 4365{
4361 unsigned long pck = t->pixelclock; 4366 unsigned long pck = vm->pixelclock;
4362 int hact, bl, tot; 4367 int hact, bl, tot;
4363 4368
4364 hact = t->x_res; 4369 hact = vm->hactive;
4365 bl = t->hsw + t->hbp + t->hfp; 4370 bl = vm->hsync_len + vm->hbp + vm->hfront_porch;
4366 tot = hact + bl; 4371 tot = hact + bl;
4367 4372
4368#define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck)) 4373#define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck))
@@ -4371,12 +4376,12 @@ static void print_dispc_vm(const char *str, const struct omap_video_timings *t)
4371 "%u/%u/%u/%u = %u + %u = %u\n", 4376 "%u/%u/%u/%u = %u + %u = %u\n",
4372 str, 4377 str,
4373 pck, 4378 pck,
4374 t->hsw, t->hbp, hact, t->hfp, 4379 vm->hsync_len, vm->hbp, hact, vm->hfront_porch,
4375 bl, hact, tot, 4380 bl, hact, tot,
4376 TO_DISPC_T(t->hsw), 4381 TO_DISPC_T(vm->hsync_len),
4377 TO_DISPC_T(t->hbp), 4382 TO_DISPC_T(vm->hbp),
4378 TO_DISPC_T(hact), 4383 TO_DISPC_T(hact),
4379 TO_DISPC_T(t->hfp), 4384 TO_DISPC_T(vm->hfront_porch),
4380 TO_DISPC_T(bl), 4385 TO_DISPC_T(bl),
4381 TO_DISPC_T(hact), 4386 TO_DISPC_T(hact),
4382 TO_DISPC_T(tot)); 4387 TO_DISPC_T(tot));
@@ -4387,7 +4392,7 @@ static void print_dispc_vm(const char *str, const struct omap_video_timings *t)
4387static void print_dsi_dispc_vm(const char *str, 4392static void print_dsi_dispc_vm(const char *str,
4388 const struct omap_dss_dsi_videomode_timings *t) 4393 const struct omap_dss_dsi_videomode_timings *t)
4389{ 4394{
4390 struct omap_video_timings vm = { 0 }; 4395 struct videomode vm = { 0 };
4391 unsigned long byteclk = t->hsclk / 4; 4396 unsigned long byteclk = t->hsclk / 4;
4392 unsigned long pck; 4397 unsigned long pck;
4393 u64 dsi_tput; 4398 u64 dsi_tput;
@@ -4396,13 +4401,13 @@ static void print_dsi_dispc_vm(const char *str,
4396 dsi_tput = (u64)byteclk * t->ndl * 8; 4401 dsi_tput = (u64)byteclk * t->ndl * 8;
4397 pck = (u32)div64_u64(dsi_tput, t->bitspp); 4402 pck = (u32)div64_u64(dsi_tput, t->bitspp);
4398 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(t->hact * t->bitspp, 8) + 6, t->ndl); 4403 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(t->hact * t->bitspp, 8) + 6, t->ndl);
4399 dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfp; 4404 dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfront_porch;
4400 4405
4401 vm.pixelclock = pck; 4406 vm.pixelclock = pck;
4402 vm.hsw = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk); 4407 vm.hsync_len = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk);
4403 vm.hbp = div64_u64((u64)t->hbp * pck, byteclk); 4408 vm.hbp = div64_u64((u64)t->hbp * pck, byteclk);
4404 vm.hfp = div64_u64((u64)t->hfp * pck, byteclk); 4409 vm.hfront_porch = div64_u64((u64)t->hfront_porch * pck, byteclk);
4405 vm.x_res = t->hact; 4410 vm.hactive = t->hact;
4406 4411
4407 print_dispc_vm(str, &vm); 4412 print_dispc_vm(str, &vm);
4408} 4413}
@@ -4412,19 +4417,19 @@ static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
4412 unsigned long pck, void *data) 4417 unsigned long pck, void *data)
4413{ 4418{
4414 struct dsi_clk_calc_ctx *ctx = data; 4419 struct dsi_clk_calc_ctx *ctx = data;
4415 struct omap_video_timings *t = &ctx->dispc_vm; 4420 struct videomode *vm = &ctx->vm;
4416 4421
4417 ctx->dispc_cinfo.lck_div = lckd; 4422 ctx->dispc_cinfo.lck_div = lckd;
4418 ctx->dispc_cinfo.pck_div = pckd; 4423 ctx->dispc_cinfo.pck_div = pckd;
4419 ctx->dispc_cinfo.lck = lck; 4424 ctx->dispc_cinfo.lck = lck;
4420 ctx->dispc_cinfo.pck = pck; 4425 ctx->dispc_cinfo.pck = pck;
4421 4426
4422 *t = *ctx->config->timings; 4427 *vm = *ctx->config->vm;
4423 t->pixelclock = pck; 4428 vm->pixelclock = pck;
4424 t->x_res = ctx->config->timings->x_res; 4429 vm->hactive = ctx->config->vm->hactive;
4425 t->y_res = ctx->config->timings->y_res; 4430 vm->vactive = ctx->config->vm->vactive;
4426 t->hsw = t->hfp = t->hbp = t->vsw = 1; 4431 vm->hsync_len = vm->hfront_porch = vm->hback_porch = vm->vsync_len = 1;
4427 t->vfp = t->vbp = 0; 4432 vm->vfront_porch = vm->vback_porch = 0;
4428 4433
4429 return true; 4434 return true;
4430} 4435}
@@ -4475,7 +4480,7 @@ static bool dsi_cm_calc(struct dsi_data *dsi,
4475 * especially as we go to LP between each pixel packet due to HW 4480 * especially as we go to LP between each pixel packet due to HW
4476 * "feature". So let's just estimate very roughly and multiply by 1.5. 4481 * "feature". So let's just estimate very roughly and multiply by 1.5.
4477 */ 4482 */
4478 pck = cfg->timings->pixelclock; 4483 pck = cfg->vm->pixelclock;
4479 pck = pck * 3 / 2; 4484 pck = pck * 3 / 2;
4480 txbyteclk = pck * bitspp / 8 / ndl; 4485 txbyteclk = pck * bitspp / 8 / ndl;
4481 4486
@@ -4510,14 +4515,14 @@ static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
4510 int dispc_htot, dispc_hbl; /* pixels */ 4515 int dispc_htot, dispc_hbl; /* pixels */
4511 int dsi_htot, dsi_hact, dsi_hbl, hss, hse; /* byteclks */ 4516 int dsi_htot, dsi_hact, dsi_hbl, hss, hse; /* byteclks */
4512 int hfp, hsa, hbp; 4517 int hfp, hsa, hbp;
4513 const struct omap_video_timings *req_vm; 4518 const struct videomode *req_vm;
4514 struct omap_video_timings *dispc_vm; 4519 struct videomode *dispc_vm;
4515 struct omap_dss_dsi_videomode_timings *dsi_vm; 4520 struct omap_dss_dsi_videomode_timings *dsi_vm;
4516 u64 dsi_tput, dispc_tput; 4521 u64 dsi_tput, dispc_tput;
4517 4522
4518 dsi_tput = (u64)byteclk * ndl * 8; 4523 dsi_tput = (u64)byteclk * ndl * 8;
4519 4524
4520 req_vm = cfg->timings; 4525 req_vm = cfg->vm;
4521 req_pck_min = ctx->req_pck_min; 4526 req_pck_min = ctx->req_pck_min;
4522 req_pck_max = ctx->req_pck_max; 4527 req_pck_max = ctx->req_pck_max;
4523 req_pck_nom = ctx->req_pck_nom; 4528 req_pck_nom = ctx->req_pck_nom;
@@ -4525,9 +4530,10 @@ static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
4525 dispc_pck = ctx->dispc_cinfo.pck; 4530 dispc_pck = ctx->dispc_cinfo.pck;
4526 dispc_tput = (u64)dispc_pck * bitspp; 4531 dispc_tput = (u64)dispc_pck * bitspp;
4527 4532
4528 xres = req_vm->x_res; 4533 xres = req_vm->hactive;
4529 4534
4530 panel_hbl = req_vm->hfp + req_vm->hbp + req_vm->hsw; 4535 panel_hbl = req_vm->hfront_porch + req_vm->hback_porch +
4536 req_vm->hsync_len;
4531 panel_htot = xres + panel_hbl; 4537 panel_htot = xres + panel_hbl;
4532 4538
4533 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl); 4539 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl);
@@ -4557,7 +4563,7 @@ static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
4557 hss = DIV_ROUND_UP(4, ndl); 4563 hss = DIV_ROUND_UP(4, ndl);
4558 4564
4559 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) { 4565 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
4560 if (ndl == 3 && req_vm->hsw == 0) 4566 if (ndl == 3 && req_vm->hsync_len == 0)
4561 hse = 1; 4567 hse = 1;
4562 else 4568 else
4563 hse = DIV_ROUND_UP(4, ndl); 4569 hse = DIV_ROUND_UP(4, ndl);
@@ -4596,14 +4602,14 @@ static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
4596 4602
4597 if (cfg->trans_mode != OMAP_DSS_DSI_PULSE_MODE) { 4603 if (cfg->trans_mode != OMAP_DSS_DSI_PULSE_MODE) {
4598 hsa = 0; 4604 hsa = 0;
4599 } else if (ndl == 3 && req_vm->hsw == 0) { 4605 } else if (ndl == 3 && req_vm->hsync_len == 0) {
4600 hsa = 0; 4606 hsa = 0;
4601 } else { 4607 } else {
4602 hsa = div64_u64((u64)req_vm->hsw * byteclk, req_pck_nom); 4608 hsa = div64_u64((u64)req_vm->hsync_len * byteclk, req_pck_nom);
4603 hsa = max(hsa - hse, 1); 4609 hsa = max(hsa - hse, 1);
4604 } 4610 }
4605 4611
4606 hbp = div64_u64((u64)req_vm->hbp * byteclk, req_pck_nom); 4612 hbp = div64_u64((u64)req_vm->hback_porch * byteclk, req_pck_nom);
4607 hbp = max(hbp, 1); 4613 hbp = max(hbp, 1);
4608 4614
4609 hfp = dsi_hbl - (hss + hsa + hse + hbp); 4615 hfp = dsi_hbl - (hss + hsa + hse + hbp);
@@ -4633,10 +4639,10 @@ static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
4633 dsi_vm->hact = xres; 4639 dsi_vm->hact = xres;
4634 dsi_vm->hfp = hfp; 4640 dsi_vm->hfp = hfp;
4635 4641
4636 dsi_vm->vsa = req_vm->vsw; 4642 dsi_vm->vsa = req_vm->vsync_len;
4637 dsi_vm->vbp = req_vm->vbp; 4643 dsi_vm->vbp = req_vm->vback_porch;
4638 dsi_vm->vact = req_vm->y_res; 4644 dsi_vm->vact = req_vm->vactive;
4639 dsi_vm->vfp = req_vm->vfp; 4645 dsi_vm->vfp = req_vm->vfront_porch;
4640 4646
4641 dsi_vm->trans_mode = cfg->trans_mode; 4647 dsi_vm->trans_mode = cfg->trans_mode;
4642 4648
@@ -4650,19 +4656,19 @@ static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
4650 4656
4651 /* setup DISPC videomode */ 4657 /* setup DISPC videomode */
4652 4658
4653 dispc_vm = &ctx->dispc_vm; 4659 dispc_vm = &ctx->vm;
4654 *dispc_vm = *req_vm; 4660 *dispc_vm = *req_vm;
4655 dispc_vm->pixelclock = dispc_pck; 4661 dispc_vm->pixelclock = dispc_pck;
4656 4662
4657 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) { 4663 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
4658 hsa = div64_u64((u64)req_vm->hsw * dispc_pck, 4664 hsa = div64_u64((u64)req_vm->hsync_len * dispc_pck,
4659 req_pck_nom); 4665 req_pck_nom);
4660 hsa = max(hsa, 1); 4666 hsa = max(hsa, 1);
4661 } else { 4667 } else {
4662 hsa = 1; 4668 hsa = 1;
4663 } 4669 }
4664 4670
4665 hbp = div64_u64((u64)req_vm->hbp * dispc_pck, req_pck_nom); 4671 hbp = div64_u64((u64)req_vm->hback_porch * dispc_pck, req_pck_nom);
4666 hbp = max(hbp, 1); 4672 hbp = max(hbp, 1);
4667 4673
4668 hfp = dispc_hbl - hsa - hbp; 4674 hfp = dispc_hbl - hsa - hbp;
@@ -4685,9 +4691,9 @@ static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
4685 if (hfp < 1) 4691 if (hfp < 1)
4686 return false; 4692 return false;
4687 4693
4688 dispc_vm->hfp = hfp; 4694 dispc_vm->hfront_porch = hfp;
4689 dispc_vm->hsw = hsa; 4695 dispc_vm->hsync_len = hsa;
4690 dispc_vm->hbp = hbp; 4696 dispc_vm->hback_porch = hbp;
4691 4697
4692 return true; 4698 return true;
4693} 4699}
@@ -4707,9 +4713,9 @@ static bool dsi_vm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
4707 return false; 4713 return false;
4708 4714
4709#ifdef PRINT_VERBOSE_VM_TIMINGS 4715#ifdef PRINT_VERBOSE_VM_TIMINGS
4710 print_dispc_vm("dispc", &ctx->dispc_vm); 4716 print_dispc_vm("dispc", &ctx->vm);
4711 print_dsi_vm("dsi ", &ctx->dsi_vm); 4717 print_dsi_vm("dsi ", &ctx->dsi_vm);
4712 print_dispc_vm("req ", ctx->config->timings); 4718 print_dispc_vm("req ", ctx->config->vm);
4713 print_dsi_dispc_vm("act ", &ctx->dsi_vm); 4719 print_dsi_dispc_vm("act ", &ctx->dsi_vm);
4714#endif 4720#endif
4715 4721
@@ -4758,7 +4764,7 @@ static bool dsi_vm_calc(struct dsi_data *dsi,
4758 const struct omap_dss_dsi_config *cfg, 4764 const struct omap_dss_dsi_config *cfg,
4759 struct dsi_clk_calc_ctx *ctx) 4765 struct dsi_clk_calc_ctx *ctx)
4760{ 4766{
4761 const struct omap_video_timings *t = cfg->timings; 4767 const struct videomode *vm = cfg->vm;
4762 unsigned long clkin; 4768 unsigned long clkin;
4763 unsigned long pll_min; 4769 unsigned long pll_min;
4764 unsigned long pll_max; 4770 unsigned long pll_max;
@@ -4774,9 +4780,9 @@ static bool dsi_vm_calc(struct dsi_data *dsi,
4774 ctx->config = cfg; 4780 ctx->config = cfg;
4775 4781
4776 /* these limits should come from the panel driver */ 4782 /* these limits should come from the panel driver */
4777 ctx->req_pck_min = t->pixelclock - 1000; 4783 ctx->req_pck_min = vm->pixelclock - 1000;
4778 ctx->req_pck_nom = t->pixelclock; 4784 ctx->req_pck_nom = vm->pixelclock;
4779 ctx->req_pck_max = t->pixelclock + 1000; 4785 ctx->req_pck_max = vm->pixelclock + 1000;
4780 4786
4781 byteclk_min = div64_u64((u64)ctx->req_pck_min * bitspp, ndl * 8); 4787 byteclk_min = div64_u64((u64)ctx->req_pck_min * bitspp, ndl * 8);
4782 pll_min = max(cfg->hs_clk_min * 4, byteclk_min * 4 * 4); 4788 pll_min = max(cfg->hs_clk_min * 4, byteclk_min * 4 * 4);
@@ -4833,7 +4839,7 @@ static int dsi_set_config(struct omap_dss_device *dssdev,
4833 dsi->user_dsi_cinfo = ctx.dsi_cinfo; 4839 dsi->user_dsi_cinfo = ctx.dsi_cinfo;
4834 dsi->user_dispc_cinfo = ctx.dispc_cinfo; 4840 dsi->user_dispc_cinfo = ctx.dispc_cinfo;
4835 4841
4836 dsi->timings = ctx.dispc_vm; 4842 dsi->vm = ctx.vm;
4837 dsi->vm_timings = ctx.dsi_vm; 4843 dsi->vm_timings = ctx.dsi_vm;
4838 4844
4839 mutex_unlock(&dsi->lock); 4845 mutex_unlock(&dsi->lock);
@@ -5342,7 +5348,7 @@ static int dsi_bind(struct device *dev, struct device *master, void *data)
5342 5348
5343 dsi->phy_base = devm_ioremap(&dsidev->dev, res->start, 5349 dsi->phy_base = devm_ioremap(&dsidev->dev, res->start,
5344 resource_size(res)); 5350 resource_size(res));
5345 if (!dsi->proto_base) { 5351 if (!dsi->phy_base) {
5346 DSSERR("can't ioremap DSI PHY\n"); 5352 DSSERR("can't ioremap DSI PHY\n");
5347 return -ENOMEM; 5353 return -ENOMEM;
5348 } 5354 }
@@ -5362,7 +5368,7 @@ static int dsi_bind(struct device *dev, struct device *master, void *data)
5362 5368
5363 dsi->pll_base = devm_ioremap(&dsidev->dev, res->start, 5369 dsi->pll_base = devm_ioremap(&dsidev->dev, res->start,
5364 resource_size(res)); 5370 resource_size(res));
5365 if (!dsi->proto_base) { 5371 if (!dsi->pll_base) {
5366 DSSERR("can't ioremap DSI PLL\n"); 5372 DSSERR("can't ioremap DSI PLL\n");
5367 return -ENOMEM; 5373 return -ENOMEM;
5368 } 5374 }
diff --git a/drivers/gpu/drm/omapdrm/dss/dss.h b/drivers/gpu/drm/omapdrm/dss/dss.h
index 4fd06dc41cb3..56493b290731 100644
--- a/drivers/gpu/drm/omapdrm/dss/dss.h
+++ b/drivers/gpu/drm/omapdrm/dss/dss.h
@@ -366,8 +366,7 @@ bool dispc_div_calc(unsigned long dispc,
366 unsigned long pck_min, unsigned long pck_max, 366 unsigned long pck_min, unsigned long pck_max,
367 dispc_div_calc_func func, void *data); 367 dispc_div_calc_func func, void *data);
368 368
369bool dispc_mgr_timings_ok(enum omap_channel channel, 369bool dispc_mgr_timings_ok(enum omap_channel channel, const struct videomode *vm);
370 const struct omap_video_timings *timings);
371int dispc_calc_clock_rates(unsigned long dispc_fclk_rate, 370int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
372 struct dispc_clock_info *cinfo); 371 struct dispc_clock_info *cinfo);
373 372
@@ -390,7 +389,7 @@ void dispc_wb_enable(bool enable);
390bool dispc_wb_is_enabled(void); 389bool dispc_wb_is_enabled(void);
391void dispc_wb_set_channel_in(enum dss_writeback_channel channel); 390void dispc_wb_set_channel_in(enum dss_writeback_channel channel);
392int dispc_wb_setup(const struct omap_dss_writeback_info *wi, 391int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
393 bool mem_to_mem, const struct omap_video_timings *timings); 392 bool mem_to_mem, const struct videomode *vm);
394 393
395/* VENC */ 394/* VENC */
396int venc_init_platform_driver(void) __init; 395int venc_init_platform_driver(void) __init;
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi.h b/drivers/gpu/drm/omapdrm/dss/hdmi.h
index 63e711545865..fb6cccd02374 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi.h
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi.h
@@ -181,7 +181,7 @@ struct hdmi_video_format {
181}; 181};
182 182
183struct hdmi_config { 183struct hdmi_config {
184 struct omap_video_timings timings; 184 struct videomode vm;
185 struct hdmi_avi_infoframe infoframe; 185 struct hdmi_avi_infoframe infoframe;
186 enum hdmi_core_hdmi_dvi hdmi_dvi_mode; 186 enum hdmi_core_hdmi_dvi hdmi_dvi_mode;
187}; 187};
@@ -298,11 +298,11 @@ int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val);
298void hdmi_wp_video_config_format(struct hdmi_wp_data *wp, 298void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,
299 struct hdmi_video_format *video_fmt); 299 struct hdmi_video_format *video_fmt);
300void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp, 300void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,
301 struct omap_video_timings *timings); 301 struct videomode *vm);
302void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp, 302void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,
303 struct omap_video_timings *timings); 303 struct videomode *vm);
304void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt, 304void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
305 struct omap_video_timings *timings, struct hdmi_config *param); 305 struct videomode *vm, struct hdmi_config *param);
306int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp); 306int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp);
307phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp); 307phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp);
308 308
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi4.c b/drivers/gpu/drm/omapdrm/dss/hdmi4.c
index cbd28dfdb86a..e7162c16de2e 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi4.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi4.c
@@ -155,7 +155,7 @@ static void hdmi_power_off_core(struct omap_dss_device *dssdev)
155static int hdmi_power_on_full(struct omap_dss_device *dssdev) 155static int hdmi_power_on_full(struct omap_dss_device *dssdev)
156{ 156{
157 int r; 157 int r;
158 struct omap_video_timings *p; 158 struct videomode *vm;
159 enum omap_channel channel = dssdev->dispc_channel; 159 enum omap_channel channel = dssdev->dispc_channel;
160 struct hdmi_wp_data *wp = &hdmi.wp; 160 struct hdmi_wp_data *wp = &hdmi.wp;
161 struct dss_pll_clock_info hdmi_cinfo = { 0 }; 161 struct dss_pll_clock_info hdmi_cinfo = { 0 };
@@ -169,12 +169,13 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev)
169 hdmi_wp_clear_irqenable(wp, 0xffffffff); 169 hdmi_wp_clear_irqenable(wp, 0xffffffff);
170 hdmi_wp_set_irqstatus(wp, 0xffffffff); 170 hdmi_wp_set_irqstatus(wp, 0xffffffff);
171 171
172 p = &hdmi.cfg.timings; 172 vm = &hdmi.cfg.vm;
173 173
174 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res); 174 DSSDBG("hdmi_power_on hactive= %d vactive = %d\n", vm->hactive,
175 vm->vactive);
175 176
176 pc = p->pixelclock; 177 pc = vm->pixelclock;
177 if (p->double_pixel) 178 if (vm->flags & DISPLAY_FLAGS_DOUBLECLK)
178 pc *= 2; 179 pc *= 2;
179 180
180 /* DSS_HDMI_TCLK is bitclk / 10 */ 181 /* DSS_HDMI_TCLK is bitclk / 10 */
@@ -209,7 +210,7 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev)
209 hdmi4_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg); 210 hdmi4_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg);
210 211
211 /* tv size */ 212 /* tv size */
212 dss_mgr_set_timings(channel, p); 213 dss_mgr_set_timings(channel, vm);
213 214
214 r = dss_mgr_enable(channel); 215 r = dss_mgr_enable(channel);
215 if (r) 216 if (r)
@@ -255,30 +256,30 @@ static void hdmi_power_off_full(struct omap_dss_device *dssdev)
255} 256}
256 257
257static int hdmi_display_check_timing(struct omap_dss_device *dssdev, 258static int hdmi_display_check_timing(struct omap_dss_device *dssdev,
258 struct omap_video_timings *timings) 259 struct videomode *vm)
259{ 260{
260 if (!dispc_mgr_timings_ok(dssdev->dispc_channel, timings)) 261 if (!dispc_mgr_timings_ok(dssdev->dispc_channel, vm))
261 return -EINVAL; 262 return -EINVAL;
262 263
263 return 0; 264 return 0;
264} 265}
265 266
266static void hdmi_display_set_timing(struct omap_dss_device *dssdev, 267static void hdmi_display_set_timing(struct omap_dss_device *dssdev,
267 struct omap_video_timings *timings) 268 struct videomode *vm)
268{ 269{
269 mutex_lock(&hdmi.lock); 270 mutex_lock(&hdmi.lock);
270 271
271 hdmi.cfg.timings = *timings; 272 hdmi.cfg.vm = *vm;
272 273
273 dispc_set_tv_pclk(timings->pixelclock); 274 dispc_set_tv_pclk(vm->pixelclock);
274 275
275 mutex_unlock(&hdmi.lock); 276 mutex_unlock(&hdmi.lock);
276} 277}
277 278
278static void hdmi_display_get_timings(struct omap_dss_device *dssdev, 279static void hdmi_display_get_timings(struct omap_dss_device *dssdev,
279 struct omap_video_timings *timings) 280 struct videomode *vm)
280{ 281{
281 *timings = hdmi.cfg.timings; 282 *vm = hdmi.cfg.vm;
282} 283}
283 284
284static void hdmi_dump_regs(struct seq_file *s) 285static void hdmi_dump_regs(struct seq_file *s)
@@ -352,7 +353,7 @@ static int hdmi_display_enable(struct omap_dss_device *dssdev)
352 353
353 if (hdmi.audio_configured) { 354 if (hdmi.audio_configured) {
354 r = hdmi4_audio_config(&hdmi.core, &hdmi.wp, &hdmi.audio_config, 355 r = hdmi4_audio_config(&hdmi.core, &hdmi.wp, &hdmi.audio_config,
355 hdmi.cfg.timings.pixelclock); 356 hdmi.cfg.vm.pixelclock);
356 if (r) { 357 if (r) {
357 DSSERR("Error restoring audio configuration: %d", r); 358 DSSERR("Error restoring audio configuration: %d", r);
358 hdmi.audio_abort_cb(&hdmi.pdev->dev); 359 hdmi.audio_abort_cb(&hdmi.pdev->dev);
@@ -643,7 +644,7 @@ static int hdmi_audio_config(struct device *dev,
643 } 644 }
644 645
645 ret = hdmi4_audio_config(&hd->core, &hd->wp, dss_audio, 646 ret = hdmi4_audio_config(&hd->core, &hd->wp, dss_audio,
646 hd->cfg.timings.pixelclock); 647 hd->cfg.vm.pixelclock);
647 if (!ret) { 648 if (!ret) {
648 hd->audio_configured = true; 649 hd->audio_configured = true;
649 hd->audio_config = *dss_audio; 650 hd->audio_config = *dss_audio;
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi4_core.c b/drivers/gpu/drm/omapdrm/dss/hdmi4_core.c
index ef3afe99e487..e05b7ac4f7dd 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi4_core.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi4_core.c
@@ -310,7 +310,7 @@ void hdmi4_configure(struct hdmi_core_data *core,
310 struct hdmi_wp_data *wp, struct hdmi_config *cfg) 310 struct hdmi_wp_data *wp, struct hdmi_config *cfg)
311{ 311{
312 /* HDMI */ 312 /* HDMI */
313 struct omap_video_timings video_timing; 313 struct videomode vm;
314 struct hdmi_video_format video_format; 314 struct hdmi_video_format video_format;
315 /* HDMI core */ 315 /* HDMI core */
316 struct hdmi_core_video_config v_core_cfg; 316 struct hdmi_core_video_config v_core_cfg;
@@ -318,16 +318,16 @@ void hdmi4_configure(struct hdmi_core_data *core,
318 318
319 hdmi_core_init(&v_core_cfg); 319 hdmi_core_init(&v_core_cfg);
320 320
321 hdmi_wp_init_vid_fmt_timings(&video_format, &video_timing, cfg); 321 hdmi_wp_init_vid_fmt_timings(&video_format, &vm, cfg);
322 322
323 hdmi_wp_video_config_timing(wp, &video_timing); 323 hdmi_wp_video_config_timing(wp, &vm);
324 324
325 /* video config */ 325 /* video config */
326 video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422; 326 video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422;
327 327
328 hdmi_wp_video_config_format(wp, &video_format); 328 hdmi_wp_video_config_format(wp, &video_format);
329 329
330 hdmi_wp_video_config_interface(wp, &video_timing); 330 hdmi_wp_video_config_interface(wp, &vm);
331 331
332 /* 332 /*
333 * configure core video part 333 * configure core video part
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi5.c b/drivers/gpu/drm/omapdrm/dss/hdmi5.c
index 0c0a5139a301..678dfb02764a 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi5.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi5.c
@@ -172,7 +172,7 @@ static void hdmi_power_off_core(struct omap_dss_device *dssdev)
172static int hdmi_power_on_full(struct omap_dss_device *dssdev) 172static int hdmi_power_on_full(struct omap_dss_device *dssdev)
173{ 173{
174 int r; 174 int r;
175 struct omap_video_timings *p; 175 struct videomode *vm;
176 enum omap_channel channel = dssdev->dispc_channel; 176 enum omap_channel channel = dssdev->dispc_channel;
177 struct dss_pll_clock_info hdmi_cinfo = { 0 }; 177 struct dss_pll_clock_info hdmi_cinfo = { 0 };
178 unsigned pc; 178 unsigned pc;
@@ -181,12 +181,13 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev)
181 if (r) 181 if (r)
182 return r; 182 return r;
183 183
184 p = &hdmi.cfg.timings; 184 vm = &hdmi.cfg.vm;
185 185
186 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res); 186 DSSDBG("hdmi_power_on hactive= %d vactive = %d\n", vm->hactive,
187 vm->vactive);
187 188
188 pc = p->pixelclock; 189 pc = vm->pixelclock;
189 if (p->double_pixel) 190 if (vm->flags & DISPLAY_FLAGS_DOUBLECLK)
190 pc *= 2; 191 pc *= 2;
191 192
192 /* DSS_HDMI_TCLK is bitclk / 10 */ 193 /* DSS_HDMI_TCLK is bitclk / 10 */
@@ -226,7 +227,7 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev)
226 hdmi5_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg); 227 hdmi5_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg);
227 228
228 /* tv size */ 229 /* tv size */
229 dss_mgr_set_timings(channel, p); 230 dss_mgr_set_timings(channel, vm);
230 231
231 r = dss_mgr_enable(channel); 232 r = dss_mgr_enable(channel);
232 if (r) 233 if (r)
@@ -272,30 +273,30 @@ static void hdmi_power_off_full(struct omap_dss_device *dssdev)
272} 273}
273 274
274static int hdmi_display_check_timing(struct omap_dss_device *dssdev, 275static int hdmi_display_check_timing(struct omap_dss_device *dssdev,
275 struct omap_video_timings *timings) 276 struct videomode *vm)
276{ 277{
277 if (!dispc_mgr_timings_ok(dssdev->dispc_channel, timings)) 278 if (!dispc_mgr_timings_ok(dssdev->dispc_channel, vm))
278 return -EINVAL; 279 return -EINVAL;
279 280
280 return 0; 281 return 0;
281} 282}
282 283
283static void hdmi_display_set_timing(struct omap_dss_device *dssdev, 284static void hdmi_display_set_timing(struct omap_dss_device *dssdev,
284 struct omap_video_timings *timings) 285 struct videomode *vm)
285{ 286{
286 mutex_lock(&hdmi.lock); 287 mutex_lock(&hdmi.lock);
287 288
288 hdmi.cfg.timings = *timings; 289 hdmi.cfg.vm = *vm;
289 290
290 dispc_set_tv_pclk(timings->pixelclock); 291 dispc_set_tv_pclk(vm->pixelclock);
291 292
292 mutex_unlock(&hdmi.lock); 293 mutex_unlock(&hdmi.lock);
293} 294}
294 295
295static void hdmi_display_get_timings(struct omap_dss_device *dssdev, 296static void hdmi_display_get_timings(struct omap_dss_device *dssdev,
296 struct omap_video_timings *timings) 297 struct videomode *vm)
297{ 298{
298 *timings = hdmi.cfg.timings; 299 *vm = hdmi.cfg.vm;
299} 300}
300 301
301static void hdmi_dump_regs(struct seq_file *s) 302static void hdmi_dump_regs(struct seq_file *s)
@@ -378,7 +379,7 @@ static int hdmi_display_enable(struct omap_dss_device *dssdev)
378 379
379 if (hdmi.audio_configured) { 380 if (hdmi.audio_configured) {
380 r = hdmi5_audio_config(&hdmi.core, &hdmi.wp, &hdmi.audio_config, 381 r = hdmi5_audio_config(&hdmi.core, &hdmi.wp, &hdmi.audio_config,
381 hdmi.cfg.timings.pixelclock); 382 hdmi.cfg.vm.pixelclock);
382 if (r) { 383 if (r) {
383 DSSERR("Error restoring audio configuration: %d", r); 384 DSSERR("Error restoring audio configuration: %d", r);
384 hdmi.audio_abort_cb(&hdmi.pdev->dev); 385 hdmi.audio_abort_cb(&hdmi.pdev->dev);
@@ -669,7 +670,7 @@ static int hdmi_audio_config(struct device *dev,
669 } 670 }
670 671
671 ret = hdmi5_audio_config(&hd->core, &hd->wp, dss_audio, 672 ret = hdmi5_audio_config(&hd->core, &hd->wp, dss_audio,
672 hd->cfg.timings.pixelclock); 673 hd->cfg.vm.pixelclock);
673 674
674 if (!ret) { 675 if (!ret) {
675 hd->audio_configured = true; 676 hd->audio_configured = true;
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c b/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
index 8ab2093daa12..8de1d7b2ae55 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
@@ -292,35 +292,35 @@ static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg,
292{ 292{
293 DSSDBG("hdmi_core_init\n"); 293 DSSDBG("hdmi_core_init\n");
294 294
295 video_cfg->v_fc_config.timings = cfg->timings; 295 video_cfg->v_fc_config.vm = cfg->vm;
296 296
297 /* video core */ 297 /* video core */
298 video_cfg->data_enable_pol = 1; /* It is always 1*/ 298 video_cfg->data_enable_pol = 1; /* It is always 1*/
299 video_cfg->hblank = cfg->timings.hfp + 299 video_cfg->hblank = cfg->vm.hfront_porch +
300 cfg->timings.hbp + cfg->timings.hsw; 300 cfg->vm.hback_porch + cfg->vm.hsync_len;
301 video_cfg->vblank_osc = 0; 301 video_cfg->vblank_osc = 0;
302 video_cfg->vblank = cfg->timings.vsw + 302 video_cfg->vblank = cfg->vm.vsync_len + cfg->vm.vfront_porch +
303 cfg->timings.vfp + cfg->timings.vbp; 303 cfg->vm.vback_porch;
304 video_cfg->v_fc_config.hdmi_dvi_mode = cfg->hdmi_dvi_mode; 304 video_cfg->v_fc_config.hdmi_dvi_mode = cfg->hdmi_dvi_mode;
305 305
306 if (cfg->timings.interlace) { 306 if (cfg->vm.flags & DISPLAY_FLAGS_INTERLACED) {
307 /* set vblank_osc if vblank is fractional */ 307 /* set vblank_osc if vblank is fractional */
308 if (video_cfg->vblank % 2 != 0) 308 if (video_cfg->vblank % 2 != 0)
309 video_cfg->vblank_osc = 1; 309 video_cfg->vblank_osc = 1;
310 310
311 video_cfg->v_fc_config.timings.y_res /= 2; 311 video_cfg->v_fc_config.vm.vactive /= 2;
312 video_cfg->vblank /= 2; 312 video_cfg->vblank /= 2;
313 video_cfg->v_fc_config.timings.vfp /= 2; 313 video_cfg->v_fc_config.vm.vfront_porch /= 2;
314 video_cfg->v_fc_config.timings.vsw /= 2; 314 video_cfg->v_fc_config.vm.vsync_len /= 2;
315 video_cfg->v_fc_config.timings.vbp /= 2; 315 video_cfg->v_fc_config.vm.vback_porch /= 2;
316 } 316 }
317 317
318 if (cfg->timings.double_pixel) { 318 if (cfg->vm.flags & DISPLAY_FLAGS_DOUBLECLK) {
319 video_cfg->v_fc_config.timings.x_res *= 2; 319 video_cfg->v_fc_config.vm.hactive *= 2;
320 video_cfg->hblank *= 2; 320 video_cfg->hblank *= 2;
321 video_cfg->v_fc_config.timings.hfp *= 2; 321 video_cfg->v_fc_config.vm.hfront_porch *= 2;
322 video_cfg->v_fc_config.timings.hsw *= 2; 322 video_cfg->v_fc_config.vm.hsync_len *= 2;
323 video_cfg->v_fc_config.timings.hbp *= 2; 323 video_cfg->v_fc_config.vm.hback_porch *= 2;
324 } 324 }
325} 325}
326 326
@@ -329,13 +329,12 @@ static void hdmi_core_video_config(struct hdmi_core_data *core,
329 struct hdmi_core_vid_config *cfg) 329 struct hdmi_core_vid_config *cfg)
330{ 330{
331 void __iomem *base = core->base; 331 void __iomem *base = core->base;
332 struct videomode *vm = &cfg->v_fc_config.vm;
332 unsigned char r = 0; 333 unsigned char r = 0;
333 bool vsync_pol, hsync_pol; 334 bool vsync_pol, hsync_pol;
334 335
335 vsync_pol = 336 vsync_pol = !!(vm->flags & DISPLAY_FLAGS_VSYNC_HIGH);
336 cfg->v_fc_config.timings.vsync_level == OMAPDSS_SIG_ACTIVE_HIGH; 337 hsync_pol = !!(vm->flags & DISPLAY_FLAGS_HSYNC_HIGH);
337 hsync_pol =
338 cfg->v_fc_config.timings.hsync_level == OMAPDSS_SIG_ACTIVE_HIGH;
339 338
340 /* Set hsync, vsync and data-enable polarity */ 339 /* Set hsync, vsync and data-enable polarity */
341 r = hdmi_read_reg(base, HDMI_CORE_FC_INVIDCONF); 340 r = hdmi_read_reg(base, HDMI_CORE_FC_INVIDCONF);
@@ -343,20 +342,16 @@ static void hdmi_core_video_config(struct hdmi_core_data *core,
343 r = FLD_MOD(r, hsync_pol, 5, 5); 342 r = FLD_MOD(r, hsync_pol, 5, 5);
344 r = FLD_MOD(r, cfg->data_enable_pol, 4, 4); 343 r = FLD_MOD(r, cfg->data_enable_pol, 4, 4);
345 r = FLD_MOD(r, cfg->vblank_osc, 1, 1); 344 r = FLD_MOD(r, cfg->vblank_osc, 1, 1);
346 r = FLD_MOD(r, cfg->v_fc_config.timings.interlace, 0, 0); 345 r = FLD_MOD(r, !!(vm->flags & DISPLAY_FLAGS_INTERLACED), 0, 0);
347 hdmi_write_reg(base, HDMI_CORE_FC_INVIDCONF, r); 346 hdmi_write_reg(base, HDMI_CORE_FC_INVIDCONF, r);
348 347
349 /* set x resolution */ 348 /* set x resolution */
350 REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV1, 349 REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV1, vm->hactive >> 8, 4, 0);
351 cfg->v_fc_config.timings.x_res >> 8, 4, 0); 350 REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV0, vm->hactive & 0xFF, 7, 0);
352 REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV0,
353 cfg->v_fc_config.timings.x_res & 0xFF, 7, 0);
354 351
355 /* set y resolution */ 352 /* set y resolution */
356 REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV1, 353 REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV1, vm->vactive >> 8, 4, 0);
357 cfg->v_fc_config.timings.y_res >> 8, 4, 0); 354 REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV0, vm->vactive & 0xFF, 7, 0);
358 REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV0,
359 cfg->v_fc_config.timings.y_res & 0xFF, 7, 0);
360 355
361 /* set horizontal blanking pixels */ 356 /* set horizontal blanking pixels */
362 REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK1, cfg->hblank >> 8, 4, 0); 357 REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK1, cfg->hblank >> 8, 4, 0);
@@ -366,30 +361,28 @@ static void hdmi_core_video_config(struct hdmi_core_data *core,
366 REG_FLD_MOD(base, HDMI_CORE_FC_INVBLANK, cfg->vblank, 7, 0); 361 REG_FLD_MOD(base, HDMI_CORE_FC_INVBLANK, cfg->vblank, 7, 0);
367 362
368 /* set horizontal sync offset */ 363 /* set horizontal sync offset */
369 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY1, 364 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY1, vm->hfront_porch >> 8,
370 cfg->v_fc_config.timings.hfp >> 8, 4, 0); 365 4, 0);
371 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY0, 366 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY0, vm->hfront_porch & 0xFF,
372 cfg->v_fc_config.timings.hfp & 0xFF, 7, 0); 367 7, 0);
373 368
374 /* set vertical sync offset */ 369 /* set vertical sync offset */
375 REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINDELAY, 370 REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINDELAY, vm->vfront_porch, 7, 0);
376 cfg->v_fc_config.timings.vfp, 7, 0);
377 371
378 /* set horizontal sync pulse width */ 372 /* set horizontal sync pulse width */
379 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH1, 373 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH1, (vm->hsync_len >> 8),
380 (cfg->v_fc_config.timings.hsw >> 8), 1, 0); 374 1, 0);
381 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH0, 375 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH0, vm->hsync_len & 0xFF,
382 cfg->v_fc_config.timings.hsw & 0xFF, 7, 0); 376 7, 0);
383 377
384 /* set vertical sync pulse width */ 378 /* set vertical sync pulse width */
385 REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINWIDTH, 379 REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINWIDTH, vm->vsync_len, 5, 0);
386 cfg->v_fc_config.timings.vsw, 5, 0);
387 380
388 /* select DVI mode */ 381 /* select DVI mode */
389 REG_FLD_MOD(base, HDMI_CORE_FC_INVIDCONF, 382 REG_FLD_MOD(base, HDMI_CORE_FC_INVIDCONF,
390 cfg->v_fc_config.hdmi_dvi_mode, 3, 3); 383 cfg->v_fc_config.hdmi_dvi_mode, 3, 3);
391 384
392 if (cfg->v_fc_config.timings.double_pixel) 385 if (vm->flags & DISPLAY_FLAGS_DOUBLECLK)
393 REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, 2, 7, 4); 386 REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, 2, 7, 4);
394 else 387 else
395 REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, 1, 7, 4); 388 REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, 1, 7, 4);
@@ -616,7 +609,7 @@ int hdmi5_core_handle_irqs(struct hdmi_core_data *core)
616void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp, 609void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
617 struct hdmi_config *cfg) 610 struct hdmi_config *cfg)
618{ 611{
619 struct omap_video_timings video_timing; 612 struct videomode vm;
620 struct hdmi_video_format video_format; 613 struct hdmi_video_format video_format;
621 struct hdmi_core_vid_config v_core_cfg; 614 struct hdmi_core_vid_config v_core_cfg;
622 615
@@ -624,16 +617,16 @@ void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
624 617
625 hdmi_core_init(&v_core_cfg, cfg); 618 hdmi_core_init(&v_core_cfg, cfg);
626 619
627 hdmi_wp_init_vid_fmt_timings(&video_format, &video_timing, cfg); 620 hdmi_wp_init_vid_fmt_timings(&video_format, &vm, cfg);
628 621
629 hdmi_wp_video_config_timing(wp, &video_timing); 622 hdmi_wp_video_config_timing(wp, &vm);
630 623
631 /* video config */ 624 /* video config */
632 video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422; 625 video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422;
633 626
634 hdmi_wp_video_config_format(wp, &video_format); 627 hdmi_wp_video_config_format(wp, &video_format);
635 628
636 hdmi_wp_video_config_interface(wp, &video_timing); 629 hdmi_wp_video_config_interface(wp, &vm);
637 630
638 /* support limited range with 24 bit color depth for now */ 631 /* support limited range with 24 bit color depth for now */
639 hdmi_core_configure_range(core); 632 hdmi_core_configure_range(core);
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c b/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c
index 203694a52d18..b783d5a0750e 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c
@@ -144,87 +144,84 @@ void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,
144} 144}
145 145
146void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp, 146void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,
147 struct omap_video_timings *timings) 147 struct videomode *vm)
148{ 148{
149 u32 r; 149 u32 r;
150 bool vsync_pol, hsync_pol; 150 bool vsync_pol, hsync_pol;
151 DSSDBG("Enter hdmi_wp_video_config_interface\n"); 151 DSSDBG("Enter hdmi_wp_video_config_interface\n");
152 152
153 vsync_pol = timings->vsync_level == OMAPDSS_SIG_ACTIVE_HIGH; 153 vsync_pol = !!(vm->flags & DISPLAY_FLAGS_VSYNC_HIGH);
154 hsync_pol = timings->hsync_level == OMAPDSS_SIG_ACTIVE_HIGH; 154 hsync_pol = !!(vm->flags & DISPLAY_FLAGS_HSYNC_HIGH);
155 155
156 r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG); 156 r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG);
157 r = FLD_MOD(r, vsync_pol, 7, 7); 157 r = FLD_MOD(r, vsync_pol, 7, 7);
158 r = FLD_MOD(r, hsync_pol, 6, 6); 158 r = FLD_MOD(r, hsync_pol, 6, 6);
159 r = FLD_MOD(r, timings->interlace, 3, 3); 159 r = FLD_MOD(r, !!(vm->flags & DISPLAY_FLAGS_INTERLACED), 3, 3);
160 r = FLD_MOD(r, 1, 1, 0); /* HDMI_TIMING_MASTER_24BIT */ 160 r = FLD_MOD(r, 1, 1, 0); /* HDMI_TIMING_MASTER_24BIT */
161 hdmi_write_reg(wp->base, HDMI_WP_VIDEO_CFG, r); 161 hdmi_write_reg(wp->base, HDMI_WP_VIDEO_CFG, r);
162} 162}
163 163
164void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp, 164void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,
165 struct omap_video_timings *timings) 165 struct videomode *vm)
166{ 166{
167 u32 timing_h = 0; 167 u32 timing_h = 0;
168 u32 timing_v = 0; 168 u32 timing_v = 0;
169 unsigned hsw_offset = 1; 169 unsigned hsync_len_offset = 1;
170 170
171 DSSDBG("Enter hdmi_wp_video_config_timing\n"); 171 DSSDBG("Enter hdmi_wp_video_config_timing\n");
172 172
173 /* 173 /*
174 * On OMAP4 and OMAP5 ES1 the HSW field is programmed as is. On OMAP5 174 * On OMAP4 and OMAP5 ES1 the HSW field is programmed as is. On OMAP5
175 * ES2+ (including DRA7/AM5 SoCs) HSW field is programmed to hsw-1. 175 * ES2+ (including DRA7/AM5 SoCs) HSW field is programmed to hsync_len-1.
176 * However, we don't support OMAP5 ES1 at all, so we can just check for 176 * However, we don't support OMAP5 ES1 at all, so we can just check for
177 * OMAP4 here. 177 * OMAP4 here.
178 */ 178 */
179 if (omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES1 || 179 if (omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES1 ||
180 omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES2 || 180 omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES2 ||
181 omapdss_get_version() == OMAPDSS_VER_OMAP4) 181 omapdss_get_version() == OMAPDSS_VER_OMAP4)
182 hsw_offset = 0; 182 hsync_len_offset = 0;
183 183
184 timing_h |= FLD_VAL(timings->hbp, 31, 20); 184 timing_h |= FLD_VAL(vm->hback_porch, 31, 20);
185 timing_h |= FLD_VAL(timings->hfp, 19, 8); 185 timing_h |= FLD_VAL(vm->hfront_porch, 19, 8);
186 timing_h |= FLD_VAL(timings->hsw - hsw_offset, 7, 0); 186 timing_h |= FLD_VAL(vm->hsync_len - hsync_len_offset, 7, 0);
187 hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h); 187 hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h);
188 188
189 timing_v |= FLD_VAL(timings->vbp, 31, 20); 189 timing_v |= FLD_VAL(vm->vback_porch, 31, 20);
190 timing_v |= FLD_VAL(timings->vfp, 19, 8); 190 timing_v |= FLD_VAL(vm->vfront_porch, 19, 8);
191 timing_v |= FLD_VAL(timings->vsw, 7, 0); 191 timing_v |= FLD_VAL(vm->vsync_len, 7, 0);
192 hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_V, timing_v); 192 hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_V, timing_v);
193} 193}
194 194
195void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt, 195void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
196 struct omap_video_timings *timings, struct hdmi_config *param) 196 struct videomode *vm, struct hdmi_config *param)
197{ 197{
198 DSSDBG("Enter hdmi_wp_video_init_format\n"); 198 DSSDBG("Enter hdmi_wp_video_init_format\n");
199 199
200 video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444; 200 video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444;
201 video_fmt->y_res = param->timings.y_res; 201 video_fmt->y_res = param->vm.vactive;
202 video_fmt->x_res = param->timings.x_res; 202 video_fmt->x_res = param->vm.hactive;
203 203
204 timings->hbp = param->timings.hbp; 204 vm->hback_porch = param->vm.hback_porch;
205 timings->hfp = param->timings.hfp; 205 vm->hfront_porch = param->vm.hfront_porch;
206 timings->hsw = param->timings.hsw; 206 vm->hsync_len = param->vm.hsync_len;
207 timings->vbp = param->timings.vbp; 207 vm->vback_porch = param->vm.vback_porch;
208 timings->vfp = param->timings.vfp; 208 vm->vfront_porch = param->vm.vfront_porch;
209 timings->vsw = param->timings.vsw; 209 vm->vsync_len = param->vm.vsync_len;
210 210
211 timings->vsync_level = param->timings.vsync_level; 211 vm->flags = param->vm.flags;
212 timings->hsync_level = param->timings.hsync_level; 212
213 timings->interlace = param->timings.interlace; 213 if (param->vm.flags & DISPLAY_FLAGS_INTERLACED) {
214 timings->double_pixel = param->timings.double_pixel;
215
216 if (param->timings.interlace) {
217 video_fmt->y_res /= 2; 214 video_fmt->y_res /= 2;
218 timings->vbp /= 2; 215 vm->vback_porch /= 2;
219 timings->vfp /= 2; 216 vm->vfront_porch /= 2;
220 timings->vsw /= 2; 217 vm->vsync_len /= 2;
221 } 218 }
222 219
223 if (param->timings.double_pixel) { 220 if (param->vm.flags & DISPLAY_FLAGS_DOUBLECLK) {
224 video_fmt->x_res *= 2; 221 video_fmt->x_res *= 2;
225 timings->hfp *= 2; 222 vm->hfront_porch *= 2;
226 timings->hsw *= 2; 223 vm->hsync_len *= 2;
227 timings->hbp *= 2; 224 vm->hback_porch *= 2;
228 } 225 }
229} 226}
230 227
diff --git a/drivers/gpu/drm/omapdrm/dss/omapdss.h b/drivers/gpu/drm/omapdrm/dss/omapdss.h
index 6eaf1adbd606..b420dde8c0fb 100644
--- a/drivers/gpu/drm/omapdrm/dss/omapdss.h
+++ b/drivers/gpu/drm/omapdrm/dss/omapdss.h
@@ -290,7 +290,7 @@ struct omap_dss_dsi_videomode_timings {
290struct omap_dss_dsi_config { 290struct omap_dss_dsi_config {
291 enum omap_dss_dsi_mode mode; 291 enum omap_dss_dsi_mode mode;
292 enum omap_dss_dsi_pixel_format pixel_format; 292 enum omap_dss_dsi_pixel_format pixel_format;
293 const struct omap_video_timings *timings; 293 const struct videomode *vm;
294 294
295 unsigned long hs_clk_min, hs_clk_max; 295 unsigned long hs_clk_min, hs_clk_max;
296 unsigned long lp_clk_min, lp_clk_max; 296 unsigned long lp_clk_min, lp_clk_max;
@@ -299,48 +299,12 @@ struct omap_dss_dsi_config {
299 enum omap_dss_dsi_trans_mode trans_mode; 299 enum omap_dss_dsi_trans_mode trans_mode;
300}; 300};
301 301
302struct omap_video_timings { 302/* Hardcoded videomodes for tv. Venc only uses these to
303 /* Unit: pixels */
304 u16 x_res;
305 /* Unit: pixels */
306 u16 y_res;
307 /* Unit: Hz */
308 u32 pixelclock;
309 /* Unit: pixel clocks */
310 u16 hsw; /* Horizontal synchronization pulse width */
311 /* Unit: pixel clocks */
312 u16 hfp; /* Horizontal front porch */
313 /* Unit: pixel clocks */
314 u16 hbp; /* Horizontal back porch */
315 /* Unit: line clocks */
316 u16 vsw; /* Vertical synchronization pulse width */
317 /* Unit: line clocks */
318 u16 vfp; /* Vertical front porch */
319 /* Unit: line clocks */
320 u16 vbp; /* Vertical back porch */
321
322 /* Vsync logic level */
323 enum omap_dss_signal_level vsync_level;
324 /* Hsync logic level */
325 enum omap_dss_signal_level hsync_level;
326 /* Interlaced or Progressive timings */
327 bool interlace;
328 /* Pixel clock edge to drive LCD data */
329 enum omap_dss_signal_edge data_pclk_edge;
330 /* Data enable logic level */
331 enum omap_dss_signal_level de_level;
332 /* Pixel clock edges to drive HSYNC and VSYNC signals */
333 enum omap_dss_signal_edge sync_pclk_edge;
334
335 bool double_pixel;
336};
337
338/* Hardcoded timings for tv modes. Venc only uses these to
339 * identify the mode, and does not actually use the configs 303 * identify the mode, and does not actually use the configs
340 * itself. However, the configs should be something that 304 * itself. However, the configs should be something that
341 * a normal monitor can also show */ 305 * a normal monitor can also show */
342extern const struct omap_video_timings omap_dss_pal_timings; 306extern const struct videomode omap_dss_pal_vm;
343extern const struct omap_video_timings omap_dss_ntsc_timings; 307extern const struct videomode omap_dss_ntsc_vm;
344 308
345struct omap_dss_cpr_coefs { 309struct omap_dss_cpr_coefs {
346 s16 rr, rg, rb; 310 s16 rr, rg, rb;
@@ -502,11 +466,11 @@ struct omapdss_dpi_ops {
502 void (*disable)(struct omap_dss_device *dssdev); 466 void (*disable)(struct omap_dss_device *dssdev);
503 467
504 int (*check_timings)(struct omap_dss_device *dssdev, 468 int (*check_timings)(struct omap_dss_device *dssdev,
505 struct omap_video_timings *timings); 469 struct videomode *vm);
506 void (*set_timings)(struct omap_dss_device *dssdev, 470 void (*set_timings)(struct omap_dss_device *dssdev,
507 struct omap_video_timings *timings); 471 struct videomode *vm);
508 void (*get_timings)(struct omap_dss_device *dssdev, 472 void (*get_timings)(struct omap_dss_device *dssdev,
509 struct omap_video_timings *timings); 473 struct videomode *vm);
510 474
511 void (*set_data_lines)(struct omap_dss_device *dssdev, int data_lines); 475 void (*set_data_lines)(struct omap_dss_device *dssdev, int data_lines);
512}; 476};
@@ -521,11 +485,11 @@ struct omapdss_sdi_ops {
521 void (*disable)(struct omap_dss_device *dssdev); 485 void (*disable)(struct omap_dss_device *dssdev);
522 486
523 int (*check_timings)(struct omap_dss_device *dssdev, 487 int (*check_timings)(struct omap_dss_device *dssdev,
524 struct omap_video_timings *timings); 488 struct videomode *vm);
525 void (*set_timings)(struct omap_dss_device *dssdev, 489 void (*set_timings)(struct omap_dss_device *dssdev,
526 struct omap_video_timings *timings); 490 struct videomode *vm);
527 void (*get_timings)(struct omap_dss_device *dssdev, 491 void (*get_timings)(struct omap_dss_device *dssdev,
528 struct omap_video_timings *timings); 492 struct videomode *vm);
529 493
530 void (*set_datapairs)(struct omap_dss_device *dssdev, int datapairs); 494 void (*set_datapairs)(struct omap_dss_device *dssdev, int datapairs);
531}; 495};
@@ -540,11 +504,11 @@ struct omapdss_dvi_ops {
540 void (*disable)(struct omap_dss_device *dssdev); 504 void (*disable)(struct omap_dss_device *dssdev);
541 505
542 int (*check_timings)(struct omap_dss_device *dssdev, 506 int (*check_timings)(struct omap_dss_device *dssdev,
543 struct omap_video_timings *timings); 507 struct videomode *vm);
544 void (*set_timings)(struct omap_dss_device *dssdev, 508 void (*set_timings)(struct omap_dss_device *dssdev,
545 struct omap_video_timings *timings); 509 struct videomode *vm);
546 void (*get_timings)(struct omap_dss_device *dssdev, 510 void (*get_timings)(struct omap_dss_device *dssdev,
547 struct omap_video_timings *timings); 511 struct videomode *vm);
548}; 512};
549 513
550struct omapdss_atv_ops { 514struct omapdss_atv_ops {
@@ -557,11 +521,11 @@ struct omapdss_atv_ops {
557 void (*disable)(struct omap_dss_device *dssdev); 521 void (*disable)(struct omap_dss_device *dssdev);
558 522
559 int (*check_timings)(struct omap_dss_device *dssdev, 523 int (*check_timings)(struct omap_dss_device *dssdev,
560 struct omap_video_timings *timings); 524 struct videomode *vm);
561 void (*set_timings)(struct omap_dss_device *dssdev, 525 void (*set_timings)(struct omap_dss_device *dssdev,
562 struct omap_video_timings *timings); 526 struct videomode *vm);
563 void (*get_timings)(struct omap_dss_device *dssdev, 527 void (*get_timings)(struct omap_dss_device *dssdev,
564 struct omap_video_timings *timings); 528 struct videomode *vm);
565 529
566 void (*set_type)(struct omap_dss_device *dssdev, 530 void (*set_type)(struct omap_dss_device *dssdev,
567 enum omap_dss_venc_type type); 531 enum omap_dss_venc_type type);
@@ -582,11 +546,11 @@ struct omapdss_hdmi_ops {
582 void (*disable)(struct omap_dss_device *dssdev); 546 void (*disable)(struct omap_dss_device *dssdev);
583 547
584 int (*check_timings)(struct omap_dss_device *dssdev, 548 int (*check_timings)(struct omap_dss_device *dssdev,
585 struct omap_video_timings *timings); 549 struct videomode *vm);
586 void (*set_timings)(struct omap_dss_device *dssdev, 550 void (*set_timings)(struct omap_dss_device *dssdev,
587 struct omap_video_timings *timings); 551 struct videomode *vm);
588 void (*get_timings)(struct omap_dss_device *dssdev, 552 void (*get_timings)(struct omap_dss_device *dssdev,
589 struct omap_video_timings *timings); 553 struct videomode *vm);
590 554
591 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len); 555 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
592 bool (*detect)(struct omap_dss_device *dssdev); 556 bool (*detect)(struct omap_dss_device *dssdev);
@@ -692,7 +656,7 @@ struct omap_dss_device {
692 } phy; 656 } phy;
693 657
694 struct { 658 struct {
695 struct omap_video_timings timings; 659 struct videomode vm;
696 660
697 enum omap_dss_dsi_pixel_format dsi_pix_fmt; 661 enum omap_dss_dsi_pixel_format dsi_pix_fmt;
698 enum omap_dss_dsi_mode dsi_mode; 662 enum omap_dss_dsi_mode dsi_mode;
@@ -785,11 +749,11 @@ struct omap_dss_driver {
785 int (*get_recommended_bpp)(struct omap_dss_device *dssdev); 749 int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
786 750
787 int (*check_timings)(struct omap_dss_device *dssdev, 751 int (*check_timings)(struct omap_dss_device *dssdev,
788 struct omap_video_timings *timings); 752 struct videomode *vm);
789 void (*set_timings)(struct omap_dss_device *dssdev, 753 void (*set_timings)(struct omap_dss_device *dssdev,
790 struct omap_video_timings *timings); 754 struct videomode *vm);
791 void (*get_timings)(struct omap_dss_device *dssdev, 755 void (*get_timings)(struct omap_dss_device *dssdev,
792 struct omap_video_timings *timings); 756 struct videomode *vm);
793 757
794 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss); 758 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
795 u32 (*get_wss)(struct omap_dss_device *dssdev); 759 u32 (*get_wss)(struct omap_dss_device *dssdev);
@@ -819,11 +783,6 @@ struct omap_dss_device *omap_dss_find_device(void *data,
819 int (*match)(struct omap_dss_device *dssdev, void *data)); 783 int (*match)(struct omap_dss_device *dssdev, void *data));
820const char *omapdss_get_default_display_name(void); 784const char *omapdss_get_default_display_name(void);
821 785
822void videomode_to_omap_video_timings(const struct videomode *vm,
823 struct omap_video_timings *ovt);
824void omap_video_timings_to_videomode(const struct omap_video_timings *ovt,
825 struct videomode *vm);
826
827int dss_feat_get_num_mgrs(void); 786int dss_feat_get_num_mgrs(void);
828int dss_feat_get_num_ovls(void); 787int dss_feat_get_num_ovls(void);
829enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane); 788enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane);
@@ -852,7 +811,7 @@ void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
852 u16 *xres, u16 *yres); 811 u16 *xres, u16 *yres);
853int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev); 812int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
854void omapdss_default_get_timings(struct omap_dss_device *dssdev, 813void omapdss_default_get_timings(struct omap_dss_device *dssdev,
855 struct omap_video_timings *timings); 814 struct videomode *vm);
856 815
857typedef void (*omap_dispc_isr_t) (void *arg, u32 mask); 816typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
858int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask); 817int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
@@ -906,7 +865,7 @@ void dispc_mgr_go(enum omap_channel channel);
906void dispc_mgr_set_lcd_config(enum omap_channel channel, 865void dispc_mgr_set_lcd_config(enum omap_channel channel,
907 const struct dss_lcd_mgr_config *config); 866 const struct dss_lcd_mgr_config *config);
908void dispc_mgr_set_timings(enum omap_channel channel, 867void dispc_mgr_set_timings(enum omap_channel channel,
909 const struct omap_video_timings *timings); 868 const struct videomode *vm);
910void dispc_mgr_setup(enum omap_channel channel, 869void dispc_mgr_setup(enum omap_channel channel,
911 const struct omap_overlay_manager_info *info); 870 const struct omap_overlay_manager_info *info);
912u32 dispc_mgr_gamma_size(enum omap_channel channel); 871u32 dispc_mgr_gamma_size(enum omap_channel channel);
@@ -919,8 +878,7 @@ bool dispc_ovl_enabled(enum omap_plane plane);
919void dispc_ovl_set_channel_out(enum omap_plane plane, 878void dispc_ovl_set_channel_out(enum omap_plane plane,
920 enum omap_channel channel); 879 enum omap_channel channel);
921int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi, 880int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
922 bool replication, const struct omap_video_timings *mgr_timings, 881 bool replication, const struct videomode *vm, bool mem_to_mem);
923 bool mem_to_mem);
924 882
925enum omap_dss_output_id dispc_mgr_get_supported_outputs(enum omap_channel channel); 883enum omap_dss_output_id dispc_mgr_get_supported_outputs(enum omap_channel channel);
926 884
@@ -934,7 +892,7 @@ struct dss_mgr_ops {
934 int (*enable)(enum omap_channel channel); 892 int (*enable)(enum omap_channel channel);
935 void (*disable)(enum omap_channel channel); 893 void (*disable)(enum omap_channel channel);
936 void (*set_timings)(enum omap_channel channel, 894 void (*set_timings)(enum omap_channel channel,
937 const struct omap_video_timings *timings); 895 const struct videomode *vm);
938 void (*set_lcd_config)(enum omap_channel channel, 896 void (*set_lcd_config)(enum omap_channel channel,
939 const struct dss_lcd_mgr_config *config); 897 const struct dss_lcd_mgr_config *config);
940 int (*register_framedone_handler)(enum omap_channel channel, 898 int (*register_framedone_handler)(enum omap_channel channel,
@@ -951,7 +909,7 @@ int dss_mgr_connect(enum omap_channel channel,
951void dss_mgr_disconnect(enum omap_channel channel, 909void dss_mgr_disconnect(enum omap_channel channel,
952 struct omap_dss_device *dst); 910 struct omap_dss_device *dst);
953void dss_mgr_set_timings(enum omap_channel channel, 911void dss_mgr_set_timings(enum omap_channel channel,
954 const struct omap_video_timings *timings); 912 const struct videomode *vm);
955void dss_mgr_set_lcd_config(enum omap_channel channel, 913void dss_mgr_set_lcd_config(enum omap_channel channel,
956 const struct dss_lcd_mgr_config *config); 914 const struct dss_lcd_mgr_config *config);
957int dss_mgr_enable(enum omap_channel channel); 915int dss_mgr_enable(enum omap_channel channel);
diff --git a/drivers/gpu/drm/omapdrm/dss/output.c b/drivers/gpu/drm/omapdrm/dss/output.c
index 24f859488201..a901af5a9bc3 100644
--- a/drivers/gpu/drm/omapdrm/dss/output.c
+++ b/drivers/gpu/drm/omapdrm/dss/output.c
@@ -201,10 +201,9 @@ void dss_mgr_disconnect(enum omap_channel channel,
201} 201}
202EXPORT_SYMBOL(dss_mgr_disconnect); 202EXPORT_SYMBOL(dss_mgr_disconnect);
203 203
204void dss_mgr_set_timings(enum omap_channel channel, 204void dss_mgr_set_timings(enum omap_channel channel, const struct videomode *vm)
205 const struct omap_video_timings *timings)
206{ 205{
207 dss_mgr_ops->set_timings(channel, timings); 206 dss_mgr_ops->set_timings(channel, vm);
208} 207}
209EXPORT_SYMBOL(dss_mgr_set_timings); 208EXPORT_SYMBOL(dss_mgr_set_timings);
210 209
diff --git a/drivers/gpu/drm/omapdrm/dss/rfbi.c b/drivers/gpu/drm/omapdrm/dss/rfbi.c
index cd53566d75eb..09724757366a 100644
--- a/drivers/gpu/drm/omapdrm/dss/rfbi.c
+++ b/drivers/gpu/drm/omapdrm/dss/rfbi.c
@@ -113,7 +113,7 @@ static struct {
113 113
114 struct semaphore bus_lock; 114 struct semaphore bus_lock;
115 115
116 struct omap_video_timings timings; 116 struct videomode vm;
117 int pixel_size; 117 int pixel_size;
118 int data_lines; 118 int data_lines;
119 struct rfbi_timings intf_timings; 119 struct rfbi_timings intf_timings;
@@ -308,15 +308,15 @@ static int rfbi_transfer_area(struct omap_dss_device *dssdev,
308 u32 l; 308 u32 l;
309 int r; 309 int r;
310 struct omap_overlay_manager *mgr = rfbi.output.manager; 310 struct omap_overlay_manager *mgr = rfbi.output.manager;
311 u16 width = rfbi.timings.x_res; 311 u16 width = rfbi.vm.hactive;
312 u16 height = rfbi.timings.y_res; 312 u16 height = rfbi.vm.vactive;
313 313
314 /*BUG_ON(callback == 0);*/ 314 /*BUG_ON(callback == 0);*/
315 BUG_ON(rfbi.framedone_callback != NULL); 315 BUG_ON(rfbi.framedone_callback != NULL);
316 316
317 DSSDBG("rfbi_transfer_area %dx%d\n", width, height); 317 DSSDBG("rfbi_transfer_area %dx%d\n", width, height);
318 318
319 dss_mgr_set_timings(mgr, &rfbi.timings); 319 dss_mgr_set_timings(mgr, &rfbi.vm);
320 320
321 r = dss_mgr_enable(mgr); 321 r = dss_mgr_enable(mgr);
322 if (r) 322 if (r)
@@ -777,8 +777,8 @@ static int rfbi_update(struct omap_dss_device *dssdev, void (*callback)(void *),
777 777
778static void rfbi_set_size(struct omap_dss_device *dssdev, u16 w, u16 h) 778static void rfbi_set_size(struct omap_dss_device *dssdev, u16 w, u16 h)
779{ 779{
780 rfbi.timings.x_res = w; 780 rfbi.vm.hactive = w;
781 rfbi.timings.y_res = h; 781 rfbi.vm.vactive = h;
782} 782}
783 783
784static void rfbi_set_pixel_size(struct omap_dss_device *dssdev, int pixel_size) 784static void rfbi_set_pixel_size(struct omap_dss_device *dssdev, int pixel_size)
@@ -854,25 +854,30 @@ static void rfbi_config_lcd_manager(struct omap_dss_device *dssdev)
854 dss_mgr_set_lcd_config(mgr, &mgr_config); 854 dss_mgr_set_lcd_config(mgr, &mgr_config);
855 855
856 /* 856 /*
857 * Set rfbi.timings with default values, the x_res and y_res fields 857 * Set rfbi.timings with default values, the hactive and vactive fields
858 * are expected to be already configured by the panel driver via 858 * are expected to be already configured by the panel driver via
859 * omapdss_rfbi_set_size() 859 * omapdss_rfbi_set_size()
860 */ 860 */
861 rfbi.timings.hsw = 1; 861 rfbi.vm.hsync_len = 1;
862 rfbi.timings.hfp = 1; 862 rfbi.vm.hfront_porch = 1;
863 rfbi.timings.hbp = 1; 863 rfbi.vm.hback_porch = 1;
864 rfbi.timings.vsw = 1; 864 rfbi.vm.vsync_len = 1;
865 rfbi.timings.vfp = 0; 865 rfbi.vm.vfront_porch = 0;
866 rfbi.timings.vbp = 0; 866 rfbi.vm.vback_porch = 0;
867 867
868 rfbi.timings.interlace = false; 868 rfbi.vm.flags &= ~DISPLAY_FLAGS_INTERLACED;
869 rfbi.timings.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH; 869 rfbi.vm.flags &= ~DISPLAY_FLAGS_HSYNC_LOW;
870 rfbi.timings.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH; 870 rfbi.vm.flags |= DISPLAY_FLAGS_HSYNC_HIGH;
871 rfbi.timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE; 871 rfbi.vm.flags &= ~DISPLAY_FLAGS_VSYNC_LOW;
872 rfbi.timings.de_level = OMAPDSS_SIG_ACTIVE_HIGH; 872 rfbi.vm.flags |= DISPLAY_FLAGS_VSYNC_HIGH;
873 rfbi.timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE; 873 rfbi.vm.flags &= ~DISPLAY_FLAGS_PIXDATA_NEGEDGE;
874 874 rfbi.vm.flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE;
875 dss_mgr_set_timings(mgr, &rfbi.timings); 875 rfbi.vm.flags &= ~DISPLAY_FLAGS_DE_LOW;
876 rfbi.vm.flags |= DISPLAY_FLAGS_DE_HIGH;
877 rfbi.vm.flags &= ~DISPLAY_FLAGS_SYNC_POSEDGE;
878 rfbi.vm.flags |= DISPLAY_FLAGS_SYNC_NEGEDGE;
879
880 dss_mgr_set_timings(mgr, &rfbi.vm);
876} 881}
877 882
878static int rfbi_display_enable(struct omap_dss_device *dssdev) 883static int rfbi_display_enable(struct omap_dss_device *dssdev)
diff --git a/drivers/gpu/drm/omapdrm/dss/sdi.c b/drivers/gpu/drm/omapdrm/dss/sdi.c
index 0a96c321ce62..b3bda2d3c08d 100644
--- a/drivers/gpu/drm/omapdrm/dss/sdi.c
+++ b/drivers/gpu/drm/omapdrm/dss/sdi.c
@@ -39,7 +39,7 @@ static struct {
39 struct regulator *vdds_sdi_reg; 39 struct regulator *vdds_sdi_reg;
40 40
41 struct dss_lcd_mgr_config mgr_config; 41 struct dss_lcd_mgr_config mgr_config;
42 struct omap_video_timings timings; 42 struct videomode vm;
43 int datapairs; 43 int datapairs;
44 44
45 struct omap_dss_device output; 45 struct omap_dss_device output;
@@ -131,7 +131,7 @@ static int sdi_display_enable(struct omap_dss_device *dssdev)
131{ 131{
132 struct omap_dss_device *out = &sdi.output; 132 struct omap_dss_device *out = &sdi.output;
133 enum omap_channel channel = dssdev->dispc_channel; 133 enum omap_channel channel = dssdev->dispc_channel;
134 struct omap_video_timings *t = &sdi.timings; 134 struct videomode *vm = &sdi.vm;
135 unsigned long fck; 135 unsigned long fck;
136 struct dispc_clock_info dispc_cinfo; 136 struct dispc_clock_info dispc_cinfo;
137 unsigned long pck; 137 unsigned long pck;
@@ -151,10 +151,9 @@ static int sdi_display_enable(struct omap_dss_device *dssdev)
151 goto err_get_dispc; 151 goto err_get_dispc;
152 152
153 /* 15.5.9.1.2 */ 153 /* 15.5.9.1.2 */
154 t->data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE; 154 vm->flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE | DISPLAY_FLAGS_SYNC_POSEDGE;
155 t->sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
156 155
157 r = sdi_calc_clock_div(t->pixelclock, &fck, &dispc_cinfo); 156 r = sdi_calc_clock_div(vm->pixelclock, &fck, &dispc_cinfo);
158 if (r) 157 if (r)
159 goto err_calc_clock_div; 158 goto err_calc_clock_div;
160 159
@@ -162,15 +161,15 @@ static int sdi_display_enable(struct omap_dss_device *dssdev)
162 161
163 pck = fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div; 162 pck = fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div;
164 163
165 if (pck != t->pixelclock) { 164 if (pck != vm->pixelclock) {
166 DSSWARN("Could not find exact pixel clock. Requested %d Hz, got %lu Hz\n", 165 DSSWARN("Could not find exact pixel clock. Requested %lu Hz, got %lu Hz\n",
167 t->pixelclock, pck); 166 vm->pixelclock, pck);
168 167
169 t->pixelclock = pck; 168 vm->pixelclock = pck;
170 } 169 }
171 170
172 171
173 dss_mgr_set_timings(channel, t); 172 dss_mgr_set_timings(channel, vm);
174 173
175 r = dss_set_fck_rate(fck); 174 r = dss_set_fck_rate(fck);
176 if (r) 175 if (r)
@@ -229,26 +228,26 @@ static void sdi_display_disable(struct omap_dss_device *dssdev)
229} 228}
230 229
231static void sdi_set_timings(struct omap_dss_device *dssdev, 230static void sdi_set_timings(struct omap_dss_device *dssdev,
232 struct omap_video_timings *timings) 231 struct videomode *vm)
233{ 232{
234 sdi.timings = *timings; 233 sdi.vm = *vm;
235} 234}
236 235
237static void sdi_get_timings(struct omap_dss_device *dssdev, 236static void sdi_get_timings(struct omap_dss_device *dssdev,
238 struct omap_video_timings *timings) 237 struct videomode *vm)
239{ 238{
240 *timings = sdi.timings; 239 *vm = sdi.vm;
241} 240}
242 241
243static int sdi_check_timings(struct omap_dss_device *dssdev, 242static int sdi_check_timings(struct omap_dss_device *dssdev,
244 struct omap_video_timings *timings) 243 struct videomode *vm)
245{ 244{
246 enum omap_channel channel = dssdev->dispc_channel; 245 enum omap_channel channel = dssdev->dispc_channel;
247 246
248 if (!dispc_mgr_timings_ok(channel, timings)) 247 if (!dispc_mgr_timings_ok(channel, vm))
249 return -EINVAL; 248 return -EINVAL;
250 249
251 if (timings->pixelclock == 0) 250 if (vm->pixelclock == 0)
252 return -EINVAL; 251 return -EINVAL;
253 252
254 return 0; 253 return 0;
diff --git a/drivers/gpu/drm/omapdrm/dss/venc.c b/drivers/gpu/drm/omapdrm/dss/venc.c
index 6eedf2118708..d74f7fcc2e46 100644
--- a/drivers/gpu/drm/omapdrm/dss/venc.c
+++ b/drivers/gpu/drm/omapdrm/dss/venc.c
@@ -262,47 +262,41 @@ static const struct venc_config venc_config_pal_bdghi = {
262 .fid_ext_start_y__fid_ext_offset_y = 0x01380005, 262 .fid_ext_start_y__fid_ext_offset_y = 0x01380005,
263}; 263};
264 264
265const struct omap_video_timings omap_dss_pal_timings = { 265const struct videomode omap_dss_pal_vm = {
266 .x_res = 720, 266 .hactive = 720,
267 .y_res = 574, 267 .vactive = 574,
268 .pixelclock = 13500000, 268 .pixelclock = 13500000,
269 .hsw = 64, 269 .hsync_len = 64,
270 .hfp = 12, 270 .hfront_porch = 12,
271 .hbp = 68, 271 .hback_porch = 68,
272 .vsw = 5, 272 .vsync_len = 5,
273 .vfp = 5, 273 .vfront_porch = 5,
274 .vbp = 41, 274 .vback_porch = 41,
275 275
276 .interlace = true, 276 .flags = DISPLAY_FLAGS_INTERLACED | DISPLAY_FLAGS_HSYNC_LOW |
277 277 DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_DE_HIGH |
278 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW, 278 DISPLAY_FLAGS_PIXDATA_POSEDGE |
279 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW, 279 DISPLAY_FLAGS_SYNC_NEGEDGE,
280 .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
281 .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
282 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
283}; 280};
284EXPORT_SYMBOL(omap_dss_pal_timings); 281EXPORT_SYMBOL(omap_dss_pal_vm);
285 282
286const struct omap_video_timings omap_dss_ntsc_timings = { 283const struct videomode omap_dss_ntsc_vm = {
287 .x_res = 720, 284 .hactive = 720,
288 .y_res = 482, 285 .vactive = 482,
289 .pixelclock = 13500000, 286 .pixelclock = 13500000,
290 .hsw = 64, 287 .hsync_len = 64,
291 .hfp = 16, 288 .hfront_porch = 16,
292 .hbp = 58, 289 .hback_porch = 58,
293 .vsw = 6, 290 .vsync_len = 6,
294 .vfp = 6, 291 .vfront_porch = 6,
295 .vbp = 31, 292 .vback_porch = 31,
296 293
297 .interlace = true, 294 .flags = DISPLAY_FLAGS_INTERLACED | DISPLAY_FLAGS_HSYNC_LOW |
298 295 DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_DE_HIGH |
299 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW, 296 DISPLAY_FLAGS_PIXDATA_POSEDGE |
300 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW, 297 DISPLAY_FLAGS_SYNC_NEGEDGE,
301 .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
302 .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
303 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
304}; 298};
305EXPORT_SYMBOL(omap_dss_ntsc_timings); 299EXPORT_SYMBOL(omap_dss_ntsc_vm);
306 300
307static struct { 301static struct {
308 struct platform_device *pdev; 302 struct platform_device *pdev;
@@ -313,7 +307,7 @@ static struct {
313 307
314 struct clk *tv_dac_clk; 308 struct clk *tv_dac_clk;
315 309
316 struct omap_video_timings timings; 310 struct videomode vm;
317 enum omap_dss_venc_type type; 311 enum omap_dss_venc_type type;
318 bool invert_polarity; 312 bool invert_polarity;
319 313
@@ -427,13 +421,12 @@ static void venc_runtime_put(void)
427 WARN_ON(r < 0 && r != -ENOSYS); 421 WARN_ON(r < 0 && r != -ENOSYS);
428} 422}
429 423
430static const struct venc_config *venc_timings_to_config( 424static const struct venc_config *venc_timings_to_config(struct videomode *vm)
431 struct omap_video_timings *timings)
432{ 425{
433 if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0) 426 if (memcmp(&omap_dss_pal_vm, vm, sizeof(*vm)) == 0)
434 return &venc_config_pal_trm; 427 return &venc_config_pal_trm;
435 428
436 if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0) 429 if (memcmp(&omap_dss_ntsc_vm, vm, sizeof(*vm)) == 0)
437 return &venc_config_ntsc_trm; 430 return &venc_config_ntsc_trm;
438 431
439 BUG(); 432 BUG();
@@ -451,7 +444,7 @@ static int venc_power_on(struct omap_dss_device *dssdev)
451 goto err0; 444 goto err0;
452 445
453 venc_reset(); 446 venc_reset();
454 venc_write_config(venc_timings_to_config(&venc.timings)); 447 venc_write_config(venc_timings_to_config(&venc.vm));
455 448
456 dss_set_venc_output(venc.type); 449 dss_set_venc_output(venc.type);
457 dss_set_dac_pwrdn_bgz(1); 450 dss_set_dac_pwrdn_bgz(1);
@@ -468,7 +461,7 @@ static int venc_power_on(struct omap_dss_device *dssdev)
468 461
469 venc_write_reg(VENC_OUTPUT_CONTROL, l); 462 venc_write_reg(VENC_OUTPUT_CONTROL, l);
470 463
471 dss_mgr_set_timings(channel, &venc.timings); 464 dss_mgr_set_timings(channel, &venc.vm);
472 465
473 r = regulator_enable(venc.vdda_dac_reg); 466 r = regulator_enable(venc.vdda_dac_reg);
474 if (r) 467 if (r)
@@ -546,17 +539,17 @@ static void venc_display_disable(struct omap_dss_device *dssdev)
546} 539}
547 540
548static void venc_set_timings(struct omap_dss_device *dssdev, 541static void venc_set_timings(struct omap_dss_device *dssdev,
549 struct omap_video_timings *timings) 542 struct videomode *vm)
550{ 543{
551 DSSDBG("venc_set_timings\n"); 544 DSSDBG("venc_set_timings\n");
552 545
553 mutex_lock(&venc.venc_lock); 546 mutex_lock(&venc.venc_lock);
554 547
555 /* Reset WSS data when the TV standard changes. */ 548 /* Reset WSS data when the TV standard changes. */
556 if (memcmp(&venc.timings, timings, sizeof(*timings))) 549 if (memcmp(&venc.vm, vm, sizeof(*vm)))
557 venc.wss_data = 0; 550 venc.wss_data = 0;
558 551
559 venc.timings = *timings; 552 venc.vm = *vm;
560 553
561 dispc_set_tv_pclk(13500000); 554 dispc_set_tv_pclk(13500000);
562 555
@@ -564,25 +557,25 @@ static void venc_set_timings(struct omap_dss_device *dssdev,
564} 557}
565 558
566static int venc_check_timings(struct omap_dss_device *dssdev, 559static int venc_check_timings(struct omap_dss_device *dssdev,
567 struct omap_video_timings *timings) 560 struct videomode *vm)
568{ 561{
569 DSSDBG("venc_check_timings\n"); 562 DSSDBG("venc_check_timings\n");
570 563
571 if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0) 564 if (memcmp(&omap_dss_pal_vm, vm, sizeof(*vm)) == 0)
572 return 0; 565 return 0;
573 566
574 if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0) 567 if (memcmp(&omap_dss_ntsc_vm, vm, sizeof(*vm)) == 0)
575 return 0; 568 return 0;
576 569
577 return -EINVAL; 570 return -EINVAL;
578} 571}
579 572
580static void venc_get_timings(struct omap_dss_device *dssdev, 573static void venc_get_timings(struct omap_dss_device *dssdev,
581 struct omap_video_timings *timings) 574 struct videomode *vm)
582{ 575{
583 mutex_lock(&venc.venc_lock); 576 mutex_lock(&venc.venc_lock);
584 577
585 *timings = venc.timings; 578 *vm = venc.vm;
586 579
587 mutex_unlock(&venc.venc_lock); 580 mutex_unlock(&venc.venc_lock);
588} 581}
@@ -602,7 +595,7 @@ static int venc_set_wss(struct omap_dss_device *dssdev, u32 wss)
602 595
603 mutex_lock(&venc.venc_lock); 596 mutex_lock(&venc.venc_lock);
604 597
605 config = venc_timings_to_config(&venc.timings); 598 config = venc_timings_to_config(&venc.vm);
606 599
607 /* Invert due to VENC_L21_WC_CTL:INV=1 */ 600 /* Invert due to VENC_L21_WC_CTL:INV=1 */
608 venc.wss_data = (wss ^ 0xfffff) << 8; 601 venc.wss_data = (wss ^ 0xfffff) << 8;
diff --git a/drivers/gpu/drm/omapdrm/omap_connector.c b/drivers/gpu/drm/omapdrm/omap_connector.c
index 137fe690a0da..2580e8673908 100644
--- a/drivers/gpu/drm/omapdrm/omap_connector.c
+++ b/drivers/gpu/drm/omapdrm/omap_connector.c
@@ -42,73 +42,6 @@ bool omap_connector_get_hdmi_mode(struct drm_connector *connector)
42 return omap_connector->hdmi_mode; 42 return omap_connector->hdmi_mode;
43} 43}
44 44
45void copy_timings_omap_to_drm(struct drm_display_mode *mode,
46 struct omap_video_timings *timings)
47{
48 mode->clock = timings->pixelclock / 1000;
49
50 mode->hdisplay = timings->x_res;
51 mode->hsync_start = mode->hdisplay + timings->hfp;
52 mode->hsync_end = mode->hsync_start + timings->hsw;
53 mode->htotal = mode->hsync_end + timings->hbp;
54
55 mode->vdisplay = timings->y_res;
56 mode->vsync_start = mode->vdisplay + timings->vfp;
57 mode->vsync_end = mode->vsync_start + timings->vsw;
58 mode->vtotal = mode->vsync_end + timings->vbp;
59
60 mode->flags = 0;
61
62 if (timings->interlace)
63 mode->flags |= DRM_MODE_FLAG_INTERLACE;
64
65 if (timings->double_pixel)
66 mode->flags |= DRM_MODE_FLAG_DBLCLK;
67
68 if (timings->hsync_level == OMAPDSS_SIG_ACTIVE_HIGH)
69 mode->flags |= DRM_MODE_FLAG_PHSYNC;
70 else
71 mode->flags |= DRM_MODE_FLAG_NHSYNC;
72
73 if (timings->vsync_level == OMAPDSS_SIG_ACTIVE_HIGH)
74 mode->flags |= DRM_MODE_FLAG_PVSYNC;
75 else
76 mode->flags |= DRM_MODE_FLAG_NVSYNC;
77}
78
79void copy_timings_drm_to_omap(struct omap_video_timings *timings,
80 struct drm_display_mode *mode)
81{
82 timings->pixelclock = mode->clock * 1000;
83
84 timings->x_res = mode->hdisplay;
85 timings->hfp = mode->hsync_start - mode->hdisplay;
86 timings->hsw = mode->hsync_end - mode->hsync_start;
87 timings->hbp = mode->htotal - mode->hsync_end;
88
89 timings->y_res = mode->vdisplay;
90 timings->vfp = mode->vsync_start - mode->vdisplay;
91 timings->vsw = mode->vsync_end - mode->vsync_start;
92 timings->vbp = mode->vtotal - mode->vsync_end;
93
94 timings->interlace = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
95 timings->double_pixel = !!(mode->flags & DRM_MODE_FLAG_DBLCLK);
96
97 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
98 timings->hsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
99 else
100 timings->hsync_level = OMAPDSS_SIG_ACTIVE_LOW;
101
102 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
103 timings->vsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
104 else
105 timings->vsync_level = OMAPDSS_SIG_ACTIVE_LOW;
106
107 timings->data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
108 timings->de_level = OMAPDSS_SIG_ACTIVE_HIGH;
109 timings->sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE;
110}
111
112static enum drm_connector_status omap_connector_detect( 45static enum drm_connector_status omap_connector_detect(
113 struct drm_connector *connector, bool force) 46 struct drm_connector *connector, bool force)
114{ 47{
@@ -185,11 +118,11 @@ static int omap_connector_get_modes(struct drm_connector *connector)
185 kfree(edid); 118 kfree(edid);
186 } else { 119 } else {
187 struct drm_display_mode *mode = drm_mode_create(dev); 120 struct drm_display_mode *mode = drm_mode_create(dev);
188 struct omap_video_timings timings = {0}; 121 struct videomode vm = {0};
189 122
190 dssdrv->get_timings(dssdev, &timings); 123 dssdrv->get_timings(dssdev, &vm);
191 124
192 copy_timings_omap_to_drm(mode, &timings); 125 drm_display_mode_from_videomode(&vm, mode);
193 126
194 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; 127 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
195 drm_mode_set_name(mode); 128 drm_mode_set_name(mode);
@@ -207,12 +140,14 @@ static int omap_connector_mode_valid(struct drm_connector *connector,
207 struct omap_connector *omap_connector = to_omap_connector(connector); 140 struct omap_connector *omap_connector = to_omap_connector(connector);
208 struct omap_dss_device *dssdev = omap_connector->dssdev; 141 struct omap_dss_device *dssdev = omap_connector->dssdev;
209 struct omap_dss_driver *dssdrv = dssdev->driver; 142 struct omap_dss_driver *dssdrv = dssdev->driver;
210 struct omap_video_timings timings = {0}; 143 struct videomode vm = {0};
211 struct drm_device *dev = connector->dev; 144 struct drm_device *dev = connector->dev;
212 struct drm_display_mode *new_mode; 145 struct drm_display_mode *new_mode;
213 int r, ret = MODE_BAD; 146 int r, ret = MODE_BAD;
214 147
215 copy_timings_drm_to_omap(&timings, mode); 148 drm_display_mode_to_videomode(mode, &vm);
149 vm.flags |= DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
150 DISPLAY_FLAGS_SYNC_NEGEDGE;
216 mode->vrefresh = drm_mode_vrefresh(mode); 151 mode->vrefresh = drm_mode_vrefresh(mode);
217 152
218 /* 153 /*
@@ -221,13 +156,13 @@ static int omap_connector_mode_valid(struct drm_connector *connector,
221 * panel's timings 156 * panel's timings
222 */ 157 */
223 if (dssdrv->check_timings) { 158 if (dssdrv->check_timings) {
224 r = dssdrv->check_timings(dssdev, &timings); 159 r = dssdrv->check_timings(dssdev, &vm);
225 } else { 160 } else {
226 struct omap_video_timings t = {0}; 161 struct videomode t = {0};
227 162
228 dssdrv->get_timings(dssdev, &t); 163 dssdrv->get_timings(dssdev, &t);
229 164
230 if (memcmp(&timings, &t, sizeof(struct omap_video_timings))) 165 if (memcmp(&vm, &t, sizeof(struct videomode)))
231 r = -EINVAL; 166 r = -EINVAL;
232 else 167 else
233 r = 0; 168 r = 0;
@@ -236,7 +171,7 @@ static int omap_connector_mode_valid(struct drm_connector *connector,
236 if (!r) { 171 if (!r) {
237 /* check if vrefresh is still valid */ 172 /* check if vrefresh is still valid */
238 new_mode = drm_mode_duplicate(dev, mode); 173 new_mode = drm_mode_duplicate(dev, mode);
239 new_mode->clock = timings.pixelclock / 1000; 174 new_mode->clock = vm.pixelclock / 1000;
240 new_mode->vrefresh = 0; 175 new_mode->vrefresh = 0;
241 if (mode->vrefresh == drm_mode_vrefresh(new_mode)) 176 if (mode->vrefresh == drm_mode_vrefresh(new_mode))
242 ret = MODE_OK; 177 ret = MODE_OK;
diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.c b/drivers/gpu/drm/omapdrm/omap_crtc.c
index 16c691dbc372..8dea89030e66 100644
--- a/drivers/gpu/drm/omapdrm/omap_crtc.c
+++ b/drivers/gpu/drm/omapdrm/omap_crtc.c
@@ -34,7 +34,7 @@ struct omap_crtc {
34 const char *name; 34 const char *name;
35 enum omap_channel channel; 35 enum omap_channel channel;
36 36
37 struct omap_video_timings timings; 37 struct videomode vm;
38 38
39 struct omap_drm_irq vblank_irq; 39 struct omap_drm_irq vblank_irq;
40 struct omap_drm_irq error_irq; 40 struct omap_drm_irq error_irq;
@@ -56,10 +56,10 @@ uint32_t pipe2vbl(struct drm_crtc *crtc)
56 return dispc_mgr_get_vsync_irq(omap_crtc->channel); 56 return dispc_mgr_get_vsync_irq(omap_crtc->channel);
57} 57}
58 58
59struct omap_video_timings *omap_crtc_timings(struct drm_crtc *crtc) 59struct videomode *omap_crtc_timings(struct drm_crtc *crtc)
60{ 60{
61 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 61 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
62 return &omap_crtc->timings; 62 return &omap_crtc->vm;
63} 63}
64 64
65enum omap_channel omap_crtc_channel(struct drm_crtc *crtc) 65enum omap_channel omap_crtc_channel(struct drm_crtc *crtc)
@@ -201,7 +201,7 @@ static int omap_crtc_dss_enable(enum omap_channel channel)
201 201
202 dispc_mgr_setup(omap_crtc->channel, &info); 202 dispc_mgr_setup(omap_crtc->channel, &info);
203 dispc_mgr_set_timings(omap_crtc->channel, 203 dispc_mgr_set_timings(omap_crtc->channel,
204 &omap_crtc->timings); 204 &omap_crtc->vm);
205 omap_crtc_set_enabled(&omap_crtc->base, true); 205 omap_crtc_set_enabled(&omap_crtc->base, true);
206 206
207 return 0; 207 return 0;
@@ -215,11 +215,11 @@ static void omap_crtc_dss_disable(enum omap_channel channel)
215} 215}
216 216
217static void omap_crtc_dss_set_timings(enum omap_channel channel, 217static void omap_crtc_dss_set_timings(enum omap_channel channel,
218 const struct omap_video_timings *timings) 218 const struct videomode *vm)
219{ 219{
220 struct omap_crtc *omap_crtc = omap_crtcs[channel]; 220 struct omap_crtc *omap_crtc = omap_crtcs[channel];
221 DBG("%s", omap_crtc->name); 221 DBG("%s", omap_crtc->name);
222 omap_crtc->timings = *timings; 222 omap_crtc->vm = *vm;
223} 223}
224 224
225static void omap_crtc_dss_set_lcd_config(enum omap_channel channel, 225static void omap_crtc_dss_set_lcd_config(enum omap_channel channel,
@@ -369,7 +369,10 @@ static void omap_crtc_mode_set_nofb(struct drm_crtc *crtc)
369 mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal, 369 mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal,
370 mode->type, mode->flags); 370 mode->type, mode->flags);
371 371
372 copy_timings_drm_to_omap(&omap_crtc->timings, mode); 372 drm_display_mode_to_videomode(mode, &omap_crtc->vm);
373 omap_crtc->vm.flags |= DISPLAY_FLAGS_DE_HIGH |
374 DISPLAY_FLAGS_PIXDATA_POSEDGE |
375 DISPLAY_FLAGS_SYNC_NEGEDGE;
373} 376}
374 377
375static int omap_crtc_atomic_check(struct drm_crtc *crtc, 378static int omap_crtc_atomic_check(struct drm_crtc *crtc,
@@ -411,19 +414,6 @@ static void omap_crtc_atomic_flush(struct drm_crtc *crtc,
411 dispc_mgr_set_gamma(omap_crtc->channel, lut, length); 414 dispc_mgr_set_gamma(omap_crtc->channel, lut, length);
412 } 415 }
413 416
414 if (crtc->state->color_mgmt_changed) {
415 struct drm_color_lut *lut = NULL;
416 uint length = 0;
417
418 if (crtc->state->gamma_lut) {
419 lut = (struct drm_color_lut *)
420 crtc->state->gamma_lut->data;
421 length = crtc->state->gamma_lut->length /
422 sizeof(*lut);
423 }
424 dispc_mgr_set_gamma(omap_crtc->channel, lut, length);
425 }
426
427 if (dispc_mgr_is_enabled(omap_crtc->channel)) { 417 if (dispc_mgr_is_enabled(omap_crtc->channel)) {
428 418
429 DBG("%s: GO", omap_crtc->name); 419 DBG("%s: GO", omap_crtc->name);
diff --git a/drivers/gpu/drm/omapdrm/omap_drv.h b/drivers/gpu/drm/omapdrm/omap_drv.h
index dcc30a98b9d4..4c51135eb9a6 100644
--- a/drivers/gpu/drm/omapdrm/omap_drv.h
+++ b/drivers/gpu/drm/omapdrm/omap_drv.h
@@ -148,7 +148,7 @@ static inline void omap_fbdev_free(struct drm_device *dev)
148} 148}
149#endif 149#endif
150 150
151struct omap_video_timings *omap_crtc_timings(struct drm_crtc *crtc); 151struct videomode *omap_crtc_timings(struct drm_crtc *crtc);
152enum omap_channel omap_crtc_channel(struct drm_crtc *crtc); 152enum omap_channel omap_crtc_channel(struct drm_crtc *crtc);
153void omap_crtc_pre_init(void); 153void omap_crtc_pre_init(void);
154void omap_crtc_pre_uninit(void); 154void omap_crtc_pre_uninit(void);
@@ -171,11 +171,6 @@ struct drm_encoder *omap_connector_attached_encoder(
171 struct drm_connector *connector); 171 struct drm_connector *connector);
172bool omap_connector_get_hdmi_mode(struct drm_connector *connector); 172bool omap_connector_get_hdmi_mode(struct drm_connector *connector);
173 173
174void copy_timings_omap_to_drm(struct drm_display_mode *mode,
175 struct omap_video_timings *timings);
176void copy_timings_drm_to_omap(struct omap_video_timings *timings,
177 struct drm_display_mode *mode);
178
179uint32_t omap_framebuffer_get_formats(uint32_t *pixel_formats, 174uint32_t omap_framebuffer_get_formats(uint32_t *pixel_formats,
180 uint32_t max_formats, enum omap_color_mode supported_modes); 175 uint32_t max_formats, enum omap_color_mode supported_modes);
181struct drm_framebuffer *omap_framebuffer_create(struct drm_device *dev, 176struct drm_framebuffer *omap_framebuffer_create(struct drm_device *dev,
diff --git a/drivers/gpu/drm/omapdrm/omap_encoder.c b/drivers/gpu/drm/omapdrm/omap_encoder.c
index 0bbb9c59622e..a20f30039aee 100644
--- a/drivers/gpu/drm/omapdrm/omap_encoder.c
+++ b/drivers/gpu/drm/omapdrm/omap_encoder.c
@@ -102,7 +102,7 @@ static void omap_encoder_disable(struct drm_encoder *encoder)
102 102
103static int omap_encoder_update(struct drm_encoder *encoder, 103static int omap_encoder_update(struct drm_encoder *encoder,
104 enum omap_channel channel, 104 enum omap_channel channel,
105 struct omap_video_timings *timings) 105 struct videomode *vm)
106{ 106{
107 struct drm_device *dev = encoder->dev; 107 struct drm_device *dev = encoder->dev;
108 struct omap_encoder *omap_encoder = to_omap_encoder(encoder); 108 struct omap_encoder *omap_encoder = to_omap_encoder(encoder);
@@ -111,13 +111,13 @@ static int omap_encoder_update(struct drm_encoder *encoder,
111 int ret; 111 int ret;
112 112
113 if (dssdrv->check_timings) { 113 if (dssdrv->check_timings) {
114 ret = dssdrv->check_timings(dssdev, timings); 114 ret = dssdrv->check_timings(dssdev, vm);
115 } else { 115 } else {
116 struct omap_video_timings t = {0}; 116 struct videomode t = {0};
117 117
118 dssdrv->get_timings(dssdev, &t); 118 dssdrv->get_timings(dssdev, &t);
119 119
120 if (memcmp(timings, &t, sizeof(struct omap_video_timings))) 120 if (memcmp(vm, &t, sizeof(struct videomode)))
121 ret = -EINVAL; 121 ret = -EINVAL;
122 else 122 else
123 ret = 0; 123 ret = 0;
@@ -129,7 +129,7 @@ static int omap_encoder_update(struct drm_encoder *encoder,
129 } 129 }
130 130
131 if (dssdrv->set_timings) 131 if (dssdrv->set_timings)
132 dssdrv->set_timings(dssdev, timings); 132 dssdrv->set_timings(dssdev, vm);
133 133
134 return 0; 134 return 0;
135} 135}
diff --git a/drivers/gpu/drm/omapdrm/omap_gem.c b/drivers/gpu/drm/omapdrm/omap_gem.c
index 505dee0db973..d4e1e11466f8 100644
--- a/drivers/gpu/drm/omapdrm/omap_gem.c
+++ b/drivers/gpu/drm/omapdrm/omap_gem.c
@@ -336,8 +336,10 @@ static void omap_gem_detach_pages(struct drm_gem_object *obj)
336 if (omap_obj->flags & (OMAP_BO_WC|OMAP_BO_UNCACHED)) { 336 if (omap_obj->flags & (OMAP_BO_WC|OMAP_BO_UNCACHED)) {
337 int i, npages = obj->size >> PAGE_SHIFT; 337 int i, npages = obj->size >> PAGE_SHIFT;
338 for (i = 0; i < npages; i++) { 338 for (i = 0; i < npages; i++) {
339 dma_unmap_page(obj->dev->dev, omap_obj->addrs[i], 339 if (omap_obj->addrs[i])
340 PAGE_SIZE, DMA_BIDIRECTIONAL); 340 dma_unmap_page(obj->dev->dev,
341 omap_obj->addrs[i],
342 PAGE_SIZE, DMA_BIDIRECTIONAL);
341 } 343 }
342 } 344 }
343 345
diff --git a/drivers/gpu/drm/omapdrm/omap_plane.c b/drivers/gpu/drm/omapdrm/omap_plane.c
index 0ffd5b930ec0..9c43cb481e62 100644
--- a/drivers/gpu/drm/omapdrm/omap_plane.c
+++ b/drivers/gpu/drm/omapdrm/omap_plane.c
@@ -131,7 +131,9 @@ static void omap_plane_atomic_update(struct drm_plane *plane,
131 /* and finally, update omapdss: */ 131 /* and finally, update omapdss: */
132 ret = dispc_ovl_setup(omap_plane->id, &info, false, 132 ret = dispc_ovl_setup(omap_plane->id, &info, false,
133 omap_crtc_timings(state->crtc), false); 133 omap_crtc_timings(state->crtc), false);
134 if (WARN_ON(ret)) { 134 if (ret) {
135 dev_err(plane->dev->dev, "Failed to setup plane %s\n",
136 omap_plane->name);
135 dispc_ovl_enable(omap_plane->id, false); 137 dispc_ovl_enable(omap_plane->id, false);
136 return; 138 return;
137 } 139 }
@@ -157,12 +159,20 @@ static int omap_plane_atomic_check(struct drm_plane *plane,
157{ 159{
158 struct drm_crtc_state *crtc_state; 160 struct drm_crtc_state *crtc_state;
159 161
160 if (!state->crtc) 162 if (!state->fb)
161 return 0; 163 return 0;
162 164
163 crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc); 165 /* crtc should only be NULL when disabling (i.e., !state->fb) */
164 if (IS_ERR(crtc_state)) 166 if (WARN_ON(!state->crtc))
165 return PTR_ERR(crtc_state); 167 return 0;
168
169 crtc_state = drm_atomic_get_existing_crtc_state(state->state, state->crtc);
170 /* we should have a crtc state if the plane is attached to a crtc */
171 if (WARN_ON(!crtc_state))
172 return 0;
173
174 if (!crtc_state->enable)
175 return 0;
166 176
167 if (state->crtc_x < 0 || state->crtc_y < 0) 177 if (state->crtc_x < 0 || state->crtc_y < 0)
168 return -EINVAL; 178 return -EINVAL;
@@ -173,11 +183,9 @@ static int omap_plane_atomic_check(struct drm_plane *plane,
173 if (state->crtc_y + state->crtc_h > crtc_state->adjusted_mode.vdisplay) 183 if (state->crtc_y + state->crtc_h > crtc_state->adjusted_mode.vdisplay)
174 return -EINVAL; 184 return -EINVAL;
175 185
176 if (state->fb) { 186 if (state->rotation != DRM_ROTATE_0 &&
177 if (state->rotation != DRM_ROTATE_0 && 187 !omap_framebuffer_supports_rotation(state->fb))
178 !omap_framebuffer_supports_rotation(state->fb)) 188 return -EINVAL;
179 return -EINVAL;
180 }
181 189
182 return 0; 190 return 0;
183} 191}
diff --git a/drivers/video/of_display_timing.c b/drivers/video/of_display_timing.c
index 8a1076beecd3..db992c684f09 100644
--- a/drivers/video/of_display_timing.c
+++ b/drivers/video/of_display_timing.c
@@ -88,6 +88,15 @@ static int of_parse_display_timing(const struct device_node *np,
88 dt->flags |= val ? DISPLAY_FLAGS_PIXDATA_POSEDGE : 88 dt->flags |= val ? DISPLAY_FLAGS_PIXDATA_POSEDGE :
89 DISPLAY_FLAGS_PIXDATA_NEGEDGE; 89 DISPLAY_FLAGS_PIXDATA_NEGEDGE;
90 90
91 if (!of_property_read_u32(np, "syncclk-active", &val))
92 dt->flags |= val ? DISPLAY_FLAGS_SYNC_POSEDGE :
93 DISPLAY_FLAGS_SYNC_NEGEDGE;
94 else if (dt->flags & (DISPLAY_FLAGS_PIXDATA_POSEDGE |
95 DISPLAY_FLAGS_PIXDATA_NEGEDGE))
96 dt->flags |= dt->flags & DISPLAY_FLAGS_PIXDATA_POSEDGE ?
97 DISPLAY_FLAGS_SYNC_POSEDGE :
98 DISPLAY_FLAGS_SYNC_NEGEDGE;
99
91 if (of_property_read_bool(np, "interlaced")) 100 if (of_property_read_bool(np, "interlaced"))
92 dt->flags |= DISPLAY_FLAGS_INTERLACED; 101 dt->flags |= DISPLAY_FLAGS_INTERLACED;
93 if (of_property_read_bool(np, "doublescan")) 102 if (of_property_read_bool(np, "doublescan"))
diff --git a/include/video/display_timing.h b/include/video/display_timing.h
index 28d9d0d566ca..3d289e990aca 100644
--- a/include/video/display_timing.h
+++ b/include/video/display_timing.h
@@ -28,6 +28,10 @@ enum display_flags {
28 DISPLAY_FLAGS_INTERLACED = BIT(8), 28 DISPLAY_FLAGS_INTERLACED = BIT(8),
29 DISPLAY_FLAGS_DOUBLESCAN = BIT(9), 29 DISPLAY_FLAGS_DOUBLESCAN = BIT(9),
30 DISPLAY_FLAGS_DOUBLECLK = BIT(10), 30 DISPLAY_FLAGS_DOUBLECLK = BIT(10),
31 /* drive sync on pos. edge */
32 DISPLAY_FLAGS_SYNC_POSEDGE = BIT(11),
33 /* drive sync on neg. edge */
34 DISPLAY_FLAGS_SYNC_NEGEDGE = BIT(12),
31}; 35};
32 36
33/* 37/*
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 10:02:50 -0400