Merge tag 'drm-fixes-for-v4.12-rc6' of git://people.freedesktop.org/~airlied/linux

Pull drm fixes from Dave Airlie:
 "This is the main fixes pull for 4.12-rc6, all pretty normal for this
  stage, nothing really stands out. The mxsfb one is probably the
  largest and it's for a black screen boot problem.

  AMD, i915, mgag200, msxfb, tegra fixes"

* tag 'drm-fixes-for-v4.12-rc6' of git://people.freedesktop.org/~airlied/linux:
  drm: mxsfb_crtc: Reset the eLCDIF controller
  drm/mgag200: Fix to always set HiPri for G200e4 V2
  drm/tegra: Correct idr_alloc() minimum id
  drm/tegra: Fix lockup on a use of staging API
  gpu: host1x: Fix error handling
  drm/radeon: Fix overflow of watermark calcs at > 4k resolutions.
  drm/amdgpu: Fix overflow of watermark calcs at > 4k resolutions.
  drm/radeon: fix "force the UVD DPB into VRAM as well"
  drm/i915: Fix GVT-g PVINFO version compatibility check
  drm/i915: Fix SKL+ watermarks for 90/270 rotation
  drm/i915: Fix scaling check for 90/270 degree plane rotation
  drm: dw-hdmi: Fix compilation breakage by selecting REGMAP_MMIO

17 files changed, 131 insertions, 64 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 0cdeb6a2e4a0..5dffa27afa45 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -1207,8 +1207,11 @@ static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
         u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
 
         if (amdgpu_crtc->base.enabled && num_heads && mode) {
-                active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
-                line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
+                active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
+                                            (u32)mode->clock);
+                line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
+                                          (u32)mode->clock);
+                line_time = min(line_time, (u32)65535);
 
                 /* watermark for high clocks */
                 if (adev->pm.dpm_enabled) {
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 773654a19749..47bbc87f96d2 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -1176,8 +1176,11 @@ static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
         u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
 
         if (amdgpu_crtc->base.enabled && num_heads && mode) {
-                active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
-                line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
+                active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
+                                            (u32)mode->clock);
+                line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
+                                          (u32)mode->clock);
+                line_time = min(line_time, (u32)65535);
 
                 /* watermark for high clocks */
                 if (adev->pm.dpm_enabled) {
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index 1f3552967ba3..d8c9a959493e 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -983,8 +983,11 @@ static void dce_v6_0_program_watermarks(struct amdgpu_device *adev,
         fixed20_12 a, b, c;
 
         if (amdgpu_crtc->base.enabled && num_heads && mode) {
-                active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
-                line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
+                active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
+                                            (u32)mode->clock);
+                line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
+                                          (u32)mode->clock);
+                line_time = min(line_time, (u32)65535);
                 priority_a_cnt = 0;
                 priority_b_cnt = 0;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index 3c558c170e5e..db30c6ba563a 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -1091,8 +1091,11 @@ static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
         u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
 
         if (amdgpu_crtc->base.enabled && num_heads && mode) {
-                active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
-                line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
+                active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
+                                            (u32)mode->clock);
+                line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
+                                          (u32)mode->clock);
+                line_time = min(line_time, (u32)65535);
 
                 /* watermark for high clocks */
                 if (adev->pm.dpm_enabled) {
diff --git a/drivers/gpu/drm/bridge/synopsys/Kconfig b/drivers/gpu/drm/bridge/synopsys/Kconfig
index 40d2827a6d19..53e78d092d18 100644
--- a/drivers/gpu/drm/bridge/synopsys/Kconfig
+++ b/drivers/gpu/drm/bridge/synopsys/Kconfig
@@ -1,6 +1,7 @@
 config DRM_DW_HDMI
         tristate
         select DRM_KMS_HELPER
+        select REGMAP_MMIO
 
 config DRM_DW_HDMI_AHB_AUDIO
         tristate "Synopsys Designware AHB Audio interface"
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
index c0cb2974caac..2cfe96d3e5d1 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -36,10 +36,6 @@
 #define VGT_VERSION_MAJOR 1
 #define VGT_VERSION_MINOR 0
 
-#define INTEL_VGT_IF_VERSION_ENCODE(major, minor) ((major) << 16 | (minor))
-#define INTEL_VGT_IF_VERSION \
-        INTEL_VGT_IF_VERSION_ENCODE(VGT_VERSION_MAJOR, VGT_VERSION_MINOR)
-
 /*
  * notifications from guest to vgpu device model
  */
@@ -55,8 +51,8 @@ enum vgt_g2v_type {
 
 struct vgt_if {
         u64 magic;              /* VGT_MAGIC */
-        uint16_t version_major;
-        uint16_t version_minor;
+        u16 version_major;
+        u16 version_minor;
         u32 vgt_id;             /* ID of vGT instance */
         u32 rsv1[12];           /* pad to offset 0x40 */
         /*
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 4ab8a973b61f..2e739018fb4c 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -60,8 +60,8 @@
  */
 void i915_check_vgpu(struct drm_i915_private *dev_priv)
 {
-        uint64_t magic;
-        uint32_t version;
+        u64 magic;
+        u16 version_major;
 
         BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
 
@@ -69,10 +69,8 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
         if (magic != VGT_MAGIC)
                 return;
 
-        version = INTEL_VGT_IF_VERSION_ENCODE(
-                __raw_i915_read16(dev_priv, vgtif_reg(version_major)),
-                __raw_i915_read16(dev_priv, vgtif_reg(version_minor)));
-        if (version != INTEL_VGT_IF_VERSION) {
+        version_major = __raw_i915_read16(dev_priv, vgtif_reg(version_major));
+        if (version_major < VGT_VERSION_MAJOR) {
                 DRM_INFO("VGT interface version mismatch!\n");
                 return;
         }
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 569717a12723..96b0b01677e2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4598,7 +4598,7 @@ static void cpt_verify_modeset(struct drm_device *dev, int pipe)
 
 static int
 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
-                  unsigned scaler_user, int *scaler_id, unsigned int rotation,
+                  unsigned int scaler_user, int *scaler_id,
                   int src_w, int src_h, int dst_w, int dst_h)
 {
         struct intel_crtc_scaler_state *scaler_state =
@@ -4607,9 +4607,12 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
                 to_intel_crtc(crtc_state->base.crtc);
         int need_scaling;
 
-        need_scaling = drm_rotation_90_or_270(rotation) ?
-                (src_h != dst_w || src_w != dst_h):
-                (src_w != dst_w || src_h != dst_h);
+        /*
+         * Src coordinates are already rotated by 270 degrees for
+         * the 90/270 degree plane rotation cases (to match the
+         * GTT mapping), hence no need to account for rotation here.
+         */
+        need_scaling = src_w != dst_w || src_h != dst_h;
 
         /*
          * if plane is being disabled or scaler is no more required or force detach
@@ -4671,7 +4674,7 @@ int skl_update_scaler_crtc(struct intel_crtc_state *state)
         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
 
         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
-                &state->scaler_state.scaler_id, DRM_ROTATE_0,
+                &state->scaler_state.scaler_id,
                 state->pipe_src_w, state->pipe_src_h,
                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
 }
@@ -4700,7 +4703,6 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
         ret = skl_update_scaler(crtc_state, force_detach,
                                 drm_plane_index(&intel_plane->base),
                                 &plane_state->scaler_id,
-                                plane_state->base.rotation,
                                 drm_rect_width(&plane_state->base.src) >> 16,
                                 drm_rect_height(&plane_state->base.src) >> 16,
                                 drm_rect_width(&plane_state->base.dst),
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2ca481b5aa69..078fd1bfa5ea 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3373,20 +3373,26 @@ skl_plane_downscale_amount(const struct intel_crtc_state *cstate,
 
         /* n.b., src is 16.16 fixed point, dst is whole integer */
         if (plane->id == PLANE_CURSOR) {
+                /*
+                 * Cursors only support 0/180 degree rotation,
+                 * hence no need to account for rotation here.
+                 */
                 src_w = pstate->base.src_w;
                 src_h = pstate->base.src_h;
                 dst_w = pstate->base.crtc_w;
                 dst_h = pstate->base.crtc_h;
         } else {
+                /*
+                 * Src coordinates are already rotated by 270 degrees for
+                 * the 90/270 degree plane rotation cases (to match the
+                 * GTT mapping), hence no need to account for rotation here.
+                 */
                 src_w = drm_rect_width(&pstate->base.src);
                 src_h = drm_rect_height(&pstate->base.src);
                 dst_w = drm_rect_width(&pstate->base.dst);
                 dst_h = drm_rect_height(&pstate->base.dst);
         }
 
-        if (drm_rotation_90_or_270(pstate->base.rotation))
-                swap(dst_w, dst_h);
-
         downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
         downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
 
@@ -3417,12 +3423,14 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
         if (y && format != DRM_FORMAT_NV12)
                 return 0;
 
+        /*
+         * Src coordinates are already rotated by 270 degrees for
+         * the 90/270 degree plane rotation cases (to match the
+         * GTT mapping), hence no need to account for rotation here.
+         */
         width = drm_rect_width(&intel_pstate->base.src) >> 16;
         height = drm_rect_height(&intel_pstate->base.src) >> 16;
 
-        if (drm_rotation_90_or_270(pstate->rotation))
-                swap(width, height);
-
         /* for planar format */
         if (format == DRM_FORMAT_NV12) {
                 if (y)  /* y-plane data rate */
@@ -3505,12 +3513,14 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate,
             fb->modifier != I915_FORMAT_MOD_Yf_TILED)
                 return 8;
 
+        /*
+         * Src coordinates are already rotated by 270 degrees for
+         * the 90/270 degree plane rotation cases (to match the
+         * GTT mapping), hence no need to account for rotation here.
+         */
         src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
         src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
 
-        if (drm_rotation_90_or_270(pstate->rotation))
-                swap(src_w, src_h);
-
         /* Halve UV plane width and height for NV12 */
         if (fb->format->format == DRM_FORMAT_NV12 && !y) {
                 src_w /= 2;
@@ -3794,13 +3804,15 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
                 width = intel_pstate->base.crtc_w;
                 height = intel_pstate->base.crtc_h;
         } else {
+                /*
+                 * Src coordinates are already rotated by 270 degrees for
+                 * the 90/270 degree plane rotation cases (to match the
+                 * GTT mapping), hence no need to account for rotation here.
+                 */
                 width = drm_rect_width(&intel_pstate->base.src) >> 16;
                 height = drm_rect_height(&intel_pstate->base.src) >> 16;
         }
 
-        if (drm_rotation_90_or_270(pstate->rotation))
-                swap(width, height);
-
         cpp = fb->format->cpp[0];
         plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
 
diff --git a/drivers/gpu/drm/mgag200/mgag200_mode.c b/drivers/gpu/drm/mgag200/mgag200_mode.c
index adb411a078e8..f4b53588e071 100644
--- a/drivers/gpu/drm/mgag200/mgag200_mode.c
+++ b/drivers/gpu/drm/mgag200/mgag200_mode.c
@@ -1173,7 +1173,10 @@ static int mga_crtc_mode_set(struct drm_crtc *crtc,
 
 
         if (IS_G200_SE(mdev)) {
-                if (mdev->unique_rev_id >= 0x02) {
+                if  (mdev->unique_rev_id >= 0x04) {
+                        WREG8(MGAREG_CRTCEXT_INDEX, 0x06);
+                        WREG8(MGAREG_CRTCEXT_DATA, 0);
+                } else if (mdev->unique_rev_id >= 0x02) {
                         u8 hi_pri_lvl;
                         u32 bpp;
                         u32 mb;
@@ -1639,6 +1642,10 @@ static int mga_vga_mode_valid(struct drm_connector *connector,
                         if (mga_vga_calculate_mode_bandwidth(mode, bpp)
                                 > (30100 * 1024))
                                 return MODE_BANDWIDTH;
+                } else {
+                        if (mga_vga_calculate_mode_bandwidth(mode, bpp)
+                                > (55000 * 1024))
+                                return MODE_BANDWIDTH;
                 }
         } else if (mdev->type == G200_WB) {
                 if (mode->hdisplay > 1280)
diff --git a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
index 1144e0c9e894..0abe77675b76 100644
--- a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
+++ b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
@@ -35,6 +35,13 @@
 #include "mxsfb_drv.h"
 #include "mxsfb_regs.h"
 
+#define MXS_SET_ADDR            0x4
+#define MXS_CLR_ADDR            0x8
+#define MODULE_CLKGATE          BIT(30)
+#define MODULE_SFTRST           BIT(31)
+/* 1 second delay should be plenty of time for block reset */
+#define RESET_TIMEOUT           1000000
+
 static u32 set_hsync_pulse_width(struct mxsfb_drm_private *mxsfb, u32 val)
 {
         return (val & mxsfb->devdata->hs_wdth_mask) <<
@@ -159,6 +166,36 @@ static void mxsfb_disable_controller(struct mxsfb_drm_private *mxsfb)
                 clk_disable_unprepare(mxsfb->clk_disp_axi);
 }
 
+/*
+ * Clear the bit and poll it cleared.  This is usually called with
+ * a reset address and mask being either SFTRST(bit 31) or CLKGATE
+ * (bit 30).
+ */
+static int clear_poll_bit(void __iomem *addr, u32 mask)
+{
+        u32 reg;
+
+        writel(mask, addr + MXS_CLR_ADDR);
+        return readl_poll_timeout(addr, reg, !(reg & mask), 0, RESET_TIMEOUT);
+}
+
+static int mxsfb_reset_block(void __iomem *reset_addr)
+{
+        int ret;
+
+        ret = clear_poll_bit(reset_addr, MODULE_SFTRST);
+        if (ret)
+                return ret;
+
+        writel(MODULE_CLKGATE, reset_addr + MXS_CLR_ADDR);
+
+        ret = clear_poll_bit(reset_addr, MODULE_SFTRST);
+        if (ret)
+                return ret;
+
+        return clear_poll_bit(reset_addr, MODULE_CLKGATE);
+}
+
 static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb)
 {
         struct drm_display_mode *m = &mxsfb->pipe.crtc.state->adjusted_mode;
@@ -173,6 +210,11 @@ static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb)
          */
         mxsfb_enable_axi_clk(mxsfb);
 
+        /* Mandatory eLCDIF reset as per the Reference Manual */
+        err = mxsfb_reset_block(mxsfb->base);
+        if (err)
+                return;
+
         /* Clear the FIFOs */
         writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_SET);
 
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 008c145b7f29..ca44233ceacc 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -9267,8 +9267,11 @@ static void dce8_program_watermarks(struct radeon_device *rdev,
         u32 tmp, wm_mask;
 
         if (radeon_crtc->base.enabled && num_heads && mode) {
-                active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
-                line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
+                active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
+                                            (u32)mode->clock);
+                line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
+                                          (u32)mode->clock);
+                line_time = min(line_time, (u32)65535);
 
                 /* watermark for high clocks */
                 if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 0bf103536404..534637203e70 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -2266,8 +2266,11 @@ static void evergreen_program_watermarks(struct radeon_device *rdev,
         fixed20_12 a, b, c;
 
         if (radeon_crtc->base.enabled && num_heads && mode) {
-                active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
-                line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
+                active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
+                                            (u32)mode->clock);
+                line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
+                                          (u32)mode->clock);
+                line_time = min(line_time, (u32)65535);
                 priority_a_cnt = 0;
                 priority_b_cnt = 0;
                 dram_channels = evergreen_get_number_of_dram_channels(rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c b/drivers/gpu/drm/radeon/radeon_uvd.c
index 7431eb4a11b7..d34d1cf33895 100644
--- a/drivers/gpu/drm/radeon/radeon_uvd.c
+++ b/drivers/gpu/drm/radeon/radeon_uvd.c
@@ -621,7 +621,7 @@ static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p,
         }
 
         /* TODO: is this still necessary on NI+ ? */
-        if ((cmd == 0 || cmd == 1 || cmd == 0x3) &&
+        if ((cmd == 0 || cmd == 0x3) &&
             (start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) {
                 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
                           start, end);
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 76d1888528e6..5303f25d5280 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -2284,8 +2284,11 @@ static void dce6_program_watermarks(struct radeon_device *rdev,
         fixed20_12 a, b, c;
 
         if (radeon_crtc->base.enabled && num_heads && mode) {
-                active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
-                line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
+                active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
+                                            (u32)mode->clock);
+                line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
+                                          (u32)mode->clock);
+                line_time = min(line_time, (u32)65535);
                 priority_a_cnt = 0;
                 priority_b_cnt = 0;
 
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index 9a1e34e48f64..81f86a67c10d 100644
--- a/drivers/gpu/drm/tegra/drm.c
+++ b/drivers/gpu/drm/tegra/drm.c
@@ -451,18 +451,6 @@ fail:
 
 
 #ifdef CONFIG_DRM_TEGRA_STAGING
-static struct tegra_drm_context *
-tegra_drm_file_get_context(struct tegra_drm_file *file, u32 id)
-{
-        struct tegra_drm_context *context;
-
-        mutex_lock(&file->lock);
-        context = idr_find(&file->contexts, id);
-        mutex_unlock(&file->lock);
-
-        return context;
-}
-
 static int tegra_gem_create(struct drm_device *drm, void *data,
                             struct drm_file *file)
 {
@@ -551,7 +539,7 @@ static int tegra_client_open(struct tegra_drm_file *fpriv,
         if (err < 0)
                 return err;
 
-        err = idr_alloc(&fpriv->contexts, context, 0, 0, GFP_KERNEL);
+        err = idr_alloc(&fpriv->contexts, context, 1, 0, GFP_KERNEL);
         if (err < 0) {
                 client->ops->close_channel(context);
                 return err;
@@ -606,7 +594,7 @@ static int tegra_close_channel(struct drm_device *drm, void *data,
 
         mutex_lock(&fpriv->lock);
 
-        context = tegra_drm_file_get_context(fpriv, args->context);
+        context = idr_find(&fpriv->contexts, args->context);
         if (!context) {
                 err = -EINVAL;
                 goto unlock;
@@ -631,7 +619,7 @@ static int tegra_get_syncpt(struct drm_device *drm, void *data,
 
         mutex_lock(&fpriv->lock);
 
-        context = tegra_drm_file_get_context(fpriv, args->context);
+        context = idr_find(&fpriv->contexts, args->context);
         if (!context) {
                 err = -ENODEV;
                 goto unlock;
@@ -660,7 +648,7 @@ static int tegra_submit(struct drm_device *drm, void *data,
 
         mutex_lock(&fpriv->lock);
 
-        context = tegra_drm_file_get_context(fpriv, args->context);
+        context = idr_find(&fpriv->contexts, args->context);
         if (!context) {
                 err = -ENODEV;
                 goto unlock;
@@ -685,7 +673,7 @@ static int tegra_get_syncpt_base(struct drm_device *drm, void *data,
 
         mutex_lock(&fpriv->lock);
 
-        context = tegra_drm_file_get_context(fpriv, args->context);
+        context = idr_find(&fpriv->contexts, args->context);
         if (!context) {
                 err = -ENODEV;
                 goto unlock;
diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c
index f05ebb14fa63..ac65f52850a6 100644
--- a/drivers/gpu/host1x/dev.c
+++ b/drivers/gpu/host1x/dev.c
@@ -172,7 +172,7 @@ static int host1x_probe(struct platform_device *pdev)
 
         host->rst = devm_reset_control_get(&pdev->dev, "host1x");
         if (IS_ERR(host->rst)) {
-                err = PTR_ERR(host->clk);
+                err = PTR_ERR(host->rst);
                 dev_err(&pdev->dev, "failed to get reset: %d\n", err);
                 return err;
         }