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authorEric Yang <Eric.Yang2@amd.com>2018-02-21 16:37:16 -0500
committerAlex Deucher <alexander.deucher@amd.com>2018-03-07 16:27:57 -0500
commitdb941f2412882b05b8bcdc26c75860dfa0e08d2e (patch)
tree12bfc5b4aceadc9e3d2ef9558048a57831f4c53e
parent8378fc7e48f2f2b167b5eff9de2d4a76cc1d0ca9 (diff)
drm/amd/display: update infoframe after dig fe is turned on
Before dig fe is enabled, infoframe can't be programmed. So in suspend resume case our infoframe programmming was not going through. This change changes the sequence so that infoframe is programmed after. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c23
1 files changed, 13 insertions, 10 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index dd1f206332ef..6f382a3ac90f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -688,15 +688,22 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
688 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 688 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
689 struct dc_link *link = pipe_ctx->stream->sink->link; 689 struct dc_link *link = pipe_ctx->stream->sink->link;
690 690
691 /* 1. update AVI info frame (HDMI, DP) 691
692 * we always need to update info frame
693 */
694 uint32_t active_total_with_borders; 692 uint32_t active_total_with_borders;
695 uint32_t early_control = 0; 693 uint32_t early_control = 0;
696 struct timing_generator *tg = pipe_ctx->stream_res.tg; 694 struct timing_generator *tg = pipe_ctx->stream_res.tg;
697 695
698 /* TODOFPGA may change to hwss.update_info_frame */ 696 /* For MST, there are multiply stream go to only one link.
697 * connect DIG back_end to front_end while enable_stream and
698 * disconnect them during disable_stream
699 * BY this, it is logic clean to separate stream and link */
700 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
701 pipe_ctx->stream_res.stream_enc->id, true);
702
703 /* update AVI info frame (HDMI, DP)*/
704 /* TODO: FPGA may change to hwss.update_info_frame */
699 dce110_update_info_frame(pipe_ctx); 705 dce110_update_info_frame(pipe_ctx);
706
700 /* enable early control to avoid corruption on DP monitor*/ 707 /* enable early control to avoid corruption on DP monitor*/
701 active_total_with_borders = 708 active_total_with_borders =
702 timing->h_addressable 709 timing->h_addressable
@@ -717,12 +724,8 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
717 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc); 724 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
718 } 725 }
719 726
720 /* For MST, there are multiply stream go to only one link. 727
721 * connect DIG back_end to front_end while enable_stream and 728
722 * disconnect them during disable_stream
723 * BY this, it is logic clean to separate stream and link */
724 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
725 pipe_ctx->stream_res.stream_enc->id, true);
726 729
727} 730}
728 731