drm/i915/guc: Exclude the upper end of the Global GTT for the GuC

The GuC uses a special mapping for the upper end of the Global GTT,
similar to the way it uses a special mapping for the lower end, so
exclude it from our drm_mm to prevent us using it.

v2: Rename to reflect that it is unmappable similar to the region at the
bottom of the GGTT, and couple it into the assertion that we don't feed
unmappable addresses to the GuC.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170105153023.30575-5-chris@chris-wilson.co.uk

3 files changed, 14 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 6af9311f72f5..bc2b4421cbd6 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3176,6 +3176,16 @@ int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv)
         if (ret)
                 return ret;
 
+        /* Trim the GGTT to fit the GuC mappable upper range (when enabled).
+         * This is easier than doing range restriction on the fly, as we
+         * currently don't have any bits spare to pass in this upper
+         * restriction!
+         */
+        if (HAS_GUC(dev_priv) && i915.enable_guc_loading) {
+                ggtt->base.total = min_t(u64, ggtt->base.total, GUC_GGTT_TOP);
+                ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total);
+        }
+
         if ((ggtt->base.total - 1) >> 32) {
                 DRM_ERROR("We never expected a Global GTT with more than 32bits"
                           " of address space! Found %lldM!\n",
diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
index 5e638fc37208..6a0adafe0523 100644
--- a/drivers/gpu/drm/i915/i915_guc_reg.h
+++ b/drivers/gpu/drm/i915/i915_guc_reg.h
@@ -73,6 +73,9 @@
 #define   GUC_WOPCM_TOP                   (0x80 << 12)  /* 512KB */
 #define   BXT_GUC_WOPCM_RC6_RESERVED      (0x10 << 12)  /* 64KB  */
 
+/* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */
+#define GUC_GGTT_TOP                    0xFEE00000
+
 #define GEN8_GT_PM_CONFIG               _MMIO(0x138140)
 #define GEN9LP_GT_PM_CONFIG             _MMIO(0x138140)
 #define GEN9_GT_PM_CONFIG               _MMIO(0x13816c)
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 3b1e39b0f3ab..9490a8e049c3 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -203,6 +203,7 @@ static inline u32 guc_ggtt_offset(struct i915_vma *vma)
 {
         u32 offset = i915_ggtt_offset(vma);
         GEM_BUG_ON(offset < GUC_WOPCM_TOP);
+        GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
         return offset;
 }