MIPS: document mixing "slightly different CCAs"

Based on an email from Paul Burton, quoting section 4.8 "Cacheability and
Coherency Attributes and Access Types" of "MIPS Architecture Volume 1:
Introduction to the MIPS32 Architecture" (MD00080, revision 6.01).

Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Paul Burton <paul.burton@mips.com>

1 files changed, 7 insertions, 0 deletions

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index fc88f68ea1ee..aff1cadeea43 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1119,6 +1119,13 @@ config DMA_PERDEV_COHERENT
 
 config DMA_NONCOHERENT
         bool
+        #
+        # MIPS allows mixing "slightly different" Cacheability and Coherency
+        # Attribute bits.  It is believed that the uncached access through
+        # KSEG1 and the implementation specific "uncached accelerated" used
+        # by pgprot_writcombine can be mixed, and the latter sometimes provides
+        # significant advantages.
+        #
         select ARCH_HAS_DMA_WRITE_COMBINE
         select ARCH_HAS_SYNC_DMA_FOR_DEVICE
         select ARCH_HAS_UNCACHED_SEGMENT