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authorStephen Boyd <sboyd@kernel.org>2018-03-14 17:37:27 -0400
committerStephen Boyd <sboyd@kernel.org>2018-03-14 17:37:27 -0400
commitdb4d52d31b21ad87b1f8d5388f5d39d58cacdbd5 (patch)
tree70fb30c5be8fe9f1471df120a0b2f3f959d3840b
parent7928b2cbe55b2a410a0f5c1f154610059c57b1b2 (diff)
parent7ce36da900c0a2ff4777d9ba51c4f1cb74205463 (diff)
Merge tag 'clk-renesas-for-v4.17-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull renesas clk driver updates for v4.17 from Geert Uytterhoeven: - Update legacy DT Kconfig default, - Add support for CPU (Z/Z2) clocks on R-Car H3 and M3-W, - Add support for the watchdog module clocks on R-Car Gen2 and RZ/G1, - Add support for the new R-Car M3-N and V3H SoCs. * tag 'clk-renesas-for-v4.17-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: cpg-mssr: Add support for R-Car M3-N clk: renesas: cpg-mssr: add R8A77980 support dt-bindings: clock: add R8A77980 CPG core clock definitions clk: renesas: r8a7792: Add rwdt clock clk: renesas: r8a7794: Add rwdt clock clk: renesas: r8a7791/r8a7793: Add rwdt clock clk: renesas: r8a7790: Add rwdt clock clk: renesas: r8a7745: Add rwdt clock clk: renesas: r8a7743: Add rwdt clock clk: renesas: r8a7796: Add Z2 clock clk: renesas: r8a7796: Add Z clock clk: renesas: r8a7795: Add Z2 clock clk: renesas: r8a7795: Add Z clock clk: renesas: rcar-gen3: Add Z2 clock divider support clk: renesas: rcar-gen3: Add Z clock divider support clk: renesas: Stop enabling legacy DT clock support by default
Diffstat
-rw-r--r--Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt6
-rw-r--r--drivers/clk/renesas/Kconfig13
-rw-r--r--drivers/clk/renesas/Makefile2
-rw-r--r--drivers/clk/renesas/r8a7743-cpg-mssr.c2
-rw-r--r--drivers/clk/renesas/r8a7745-cpg-mssr.c2
-rw-r--r--drivers/clk/renesas/r8a7790-cpg-mssr.c2
-rw-r--r--drivers/clk/renesas/r8a7791-cpg-mssr.c2
-rw-r--r--drivers/clk/renesas/r8a7792-cpg-mssr.c2
-rw-r--r--drivers/clk/renesas/r8a7794-cpg-mssr.c2
-rw-r--r--drivers/clk/renesas/r8a7795-cpg-mssr.c2
-rw-r--r--drivers/clk/renesas/r8a7796-cpg-mssr.c2
-rw-r--r--drivers/clk/renesas/r8a77965-cpg-mssr.c334
-rw-r--r--drivers/clk/renesas/r8a77980-cpg-mssr.c227
-rw-r--r--drivers/clk/renesas/rcar-gen3-cpg.c143
-rw-r--r--drivers/clk/renesas/rcar-gen3-cpg.h2
-rw-r--r--drivers/clk/renesas/renesas-cpg-mssr.c12
-rw-r--r--drivers/clk/renesas/renesas-cpg-mssr.h2
-rw-r--r--include/dt-bindings/clock/r8a77965-cpg-mssr.h62
-rw-r--r--include/dt-bindings/clock/r8a77980-cpg-mssr.h51
19 files changed, 867 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
index f1890d0777a6..773a5226342f 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
@@ -22,7 +22,9 @@ Required Properties:
22 - "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2) 22 - "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)
23 - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3) 23 - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
24 - "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W) 24 - "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
25 - "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N)
25 - "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M) 26 - "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)
27 - "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H)
26 - "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3) 28 - "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
27 29
28 - reg: Base address and length of the memory resource used by the CPG/MSSR 30 - reg: Base address and length of the memory resource used by the CPG/MSSR
@@ -32,8 +34,8 @@ Required Properties:
32 clock-names 34 clock-names
33 - clock-names: List of external parent clock names. Valid names are: 35 - clock-names: List of external parent clock names. Valid names are:
34 - "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794, 36 - "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
35 r8a7795, r8a7796, r8a77970, r8a77995) 37 r8a7795, r8a7796, r8a77965, r8a77970, r8a77980, r8a77995)
36 - "extalr" (r8a7795, r8a7796, r8a77970) 38 - "extalr" (r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)
37 - "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794) 39 - "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)
38 40
39 - #clock-cells: Must be 2 41 - #clock-cells: Must be 2
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 43b5a89c4b28..ef76c861ec84 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -15,7 +15,9 @@ config CLK_RENESAS
15 select CLK_R8A7794 if ARCH_R8A7794 15 select CLK_R8A7794 if ARCH_R8A7794
16 select CLK_R8A7795 if ARCH_R8A7795 16 select CLK_R8A7795 if ARCH_R8A7795
17 select CLK_R8A7796 if ARCH_R8A7796 17 select CLK_R8A7796 if ARCH_R8A7796
18 select CLK_R8A77965 if ARCH_R8A77965
18 select CLK_R8A77970 if ARCH_R8A77970 19 select CLK_R8A77970 if ARCH_R8A77970
20 select CLK_R8A77980 if ARCH_R8A77980
19 select CLK_R8A77995 if ARCH_R8A77995 21 select CLK_R8A77995 if ARCH_R8A77995
20 select CLK_SH73A0 if ARCH_SH73A0 22 select CLK_SH73A0 if ARCH_SH73A0
21 23
@@ -24,12 +26,13 @@ if CLK_RENESAS
24config CLK_RENESAS_LEGACY 26config CLK_RENESAS_LEGACY
25 bool "Legacy DT clock support" 27 bool "Legacy DT clock support"
26 depends on CLK_R8A7790 || CLK_R8A7791 || CLK_R8A7792 || CLK_R8A7794 28 depends on CLK_R8A7790 || CLK_R8A7791 || CLK_R8A7792 || CLK_R8A7794
27 default y
28 help 29 help
29 Enable backward compatibility with old device trees describing a 30 Enable backward compatibility with old device trees describing a
30 hierarchical representation of the various CPG and MSTP clocks. 31 hierarchical representation of the various CPG and MSTP clocks.
31 32
32 Say Y if you want your kernel to work with old DTBs. 33 Say Y if you want your kernel to work with old DTBs.
34 It is safe to say N if you use the DTS that is supplied with the
35 current kernel source tree.
33 36
34# SoC 37# SoC
35config CLK_EMEV2 38config CLK_EMEV2
@@ -96,10 +99,18 @@ config CLK_R8A7796
96 bool "R-Car M3-W clock support" if COMPILE_TEST 99 bool "R-Car M3-W clock support" if COMPILE_TEST
97 select CLK_RCAR_GEN3_CPG 100 select CLK_RCAR_GEN3_CPG
98 101
102config CLK_R8A77965
103 bool "R-Car M3-N clock support" if COMPILE_TEST
104 select CLK_RCAR_GEN3_CPG
105
99config CLK_R8A77970 106config CLK_R8A77970
100 bool "R-Car V3M clock support" if COMPILE_TEST 107 bool "R-Car V3M clock support" if COMPILE_TEST
101 select CLK_RCAR_GEN3_CPG 108 select CLK_RCAR_GEN3_CPG
102 109
110config CLK_R8A77980
111 bool "R-Car V3H clock support" if COMPILE_TEST
112 select CLK_RCAR_GEN3_CPG
113
103config CLK_R8A77995 114config CLK_R8A77995
104 bool "R-Car D3 clock support" if COMPILE_TEST 115 bool "R-Car D3 clock support" if COMPILE_TEST
105 select CLK_RCAR_GEN3_CPG 116 select CLK_RCAR_GEN3_CPG
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index 34c4e0b37afa..6c0f19636e3e 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -14,7 +14,9 @@ obj-$(CONFIG_CLK_R8A7792) += r8a7792-cpg-mssr.o
14obj-$(CONFIG_CLK_R8A7794) += r8a7794-cpg-mssr.o 14obj-$(CONFIG_CLK_R8A7794) += r8a7794-cpg-mssr.o
15obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o 15obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o
16obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o 16obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o
17obj-$(CONFIG_CLK_R8A77965) += r8a77965-cpg-mssr.o
17obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o 18obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o
19obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o
18obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o 20obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
19obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o 21obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
20 22
diff --git a/drivers/clk/renesas/r8a7743-cpg-mssr.c b/drivers/clk/renesas/r8a7743-cpg-mssr.c
index 6dc0b3082aa6..d3c8b1e2969f 100644
--- a/drivers/clk/renesas/r8a7743-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7743-cpg-mssr.c
@@ -117,6 +117,7 @@ static const struct mssr_mod_clk r8a7743_mod_clks[] __initconst = {
117 DEF_MOD("cmt1", 329, R8A7743_CLK_R), 117 DEF_MOD("cmt1", 329, R8A7743_CLK_R),
118 DEF_MOD("usbhs-dmac0", 330, R8A7743_CLK_HP), 118 DEF_MOD("usbhs-dmac0", 330, R8A7743_CLK_HP),
119 DEF_MOD("usbhs-dmac1", 331, R8A7743_CLK_HP), 119 DEF_MOD("usbhs-dmac1", 331, R8A7743_CLK_HP),
120 DEF_MOD("rwdt", 402, R8A7743_CLK_R),
120 DEF_MOD("irqc", 407, R8A7743_CLK_CP), 121 DEF_MOD("irqc", 407, R8A7743_CLK_CP),
121 DEF_MOD("intc-sys", 408, R8A7743_CLK_ZS), 122 DEF_MOD("intc-sys", 408, R8A7743_CLK_ZS),
122 DEF_MOD("audio-dmac1", 501, R8A7743_CLK_HP), 123 DEF_MOD("audio-dmac1", 501, R8A7743_CLK_HP),
@@ -195,6 +196,7 @@ static const struct mssr_mod_clk r8a7743_mod_clks[] __initconst = {
195}; 196};
196 197
197static const unsigned int r8a7743_crit_mod_clks[] __initconst = { 198static const unsigned int r8a7743_crit_mod_clks[] __initconst = {
199 MOD_CLK_ID(402), /* RWDT */
198 MOD_CLK_ID(408), /* INTC-SYS (GIC) */ 200 MOD_CLK_ID(408), /* INTC-SYS (GIC) */
199}; 201};
200 202
diff --git a/drivers/clk/renesas/r8a7745-cpg-mssr.c b/drivers/clk/renesas/r8a7745-cpg-mssr.c
index 2859504cc866..87f5a3619e4f 100644
--- a/drivers/clk/renesas/r8a7745-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7745-cpg-mssr.c
@@ -114,6 +114,7 @@ static const struct mssr_mod_clk r8a7745_mod_clks[] __initconst = {
114 DEF_MOD("cmt1", 329, R8A7745_CLK_R), 114 DEF_MOD("cmt1", 329, R8A7745_CLK_R),
115 DEF_MOD("usbhs-dmac0", 330, R8A7745_CLK_HP), 115 DEF_MOD("usbhs-dmac0", 330, R8A7745_CLK_HP),
116 DEF_MOD("usbhs-dmac1", 331, R8A7745_CLK_HP), 116 DEF_MOD("usbhs-dmac1", 331, R8A7745_CLK_HP),
117 DEF_MOD("rwdt", 402, R8A7745_CLK_R),
117 DEF_MOD("irqc", 407, R8A7745_CLK_CP), 118 DEF_MOD("irqc", 407, R8A7745_CLK_CP),
118 DEF_MOD("intc-sys", 408, R8A7745_CLK_ZS), 119 DEF_MOD("intc-sys", 408, R8A7745_CLK_ZS),
119 DEF_MOD("audio-dmac0", 502, R8A7745_CLK_HP), 120 DEF_MOD("audio-dmac0", 502, R8A7745_CLK_HP),
@@ -180,6 +181,7 @@ static const struct mssr_mod_clk r8a7745_mod_clks[] __initconst = {
180}; 181};
181 182
182static const unsigned int r8a7745_crit_mod_clks[] __initconst = { 183static const unsigned int r8a7745_crit_mod_clks[] __initconst = {
184 MOD_CLK_ID(402), /* RWDT */
183 MOD_CLK_ID(408), /* INTC-SYS (GIC) */ 185 MOD_CLK_ID(408), /* INTC-SYS (GIC) */
184}; 186};
185 187
diff --git a/drivers/clk/renesas/r8a7790-cpg-mssr.c b/drivers/clk/renesas/r8a7790-cpg-mssr.c
index 46bb55bb223d..f936cb74b681 100644
--- a/drivers/clk/renesas/r8a7790-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7790-cpg-mssr.c
@@ -140,6 +140,7 @@ static const struct mssr_mod_clk r8a7790_mod_clks[] __initconst = {
140 DEF_MOD("cmt1", 329, R8A7790_CLK_R), 140 DEF_MOD("cmt1", 329, R8A7790_CLK_R),
141 DEF_MOD("usbhs-dmac0", 330, R8A7790_CLK_HP), 141 DEF_MOD("usbhs-dmac0", 330, R8A7790_CLK_HP),
142 DEF_MOD("usbhs-dmac1", 331, R8A7790_CLK_HP), 142 DEF_MOD("usbhs-dmac1", 331, R8A7790_CLK_HP),
143 DEF_MOD("rwdt", 402, R8A7790_CLK_R),
143 DEF_MOD("irqc", 407, R8A7790_CLK_CP), 144 DEF_MOD("irqc", 407, R8A7790_CLK_CP),
144 DEF_MOD("intc-sys", 408, R8A7790_CLK_ZS), 145 DEF_MOD("intc-sys", 408, R8A7790_CLK_ZS),
145 DEF_MOD("audio-dmac1", 501, R8A7790_CLK_HP), 146 DEF_MOD("audio-dmac1", 501, R8A7790_CLK_HP),
@@ -211,6 +212,7 @@ static const struct mssr_mod_clk r8a7790_mod_clks[] __initconst = {
211}; 212};
212 213
213static const unsigned int r8a7790_crit_mod_clks[] __initconst = { 214static const unsigned int r8a7790_crit_mod_clks[] __initconst = {
215 MOD_CLK_ID(402), /* RWDT */
214 MOD_CLK_ID(408), /* INTC-SYS (GIC) */ 216 MOD_CLK_ID(408), /* INTC-SYS (GIC) */
215}; 217};
216 218
diff --git a/drivers/clk/renesas/r8a7791-cpg-mssr.c b/drivers/clk/renesas/r8a7791-cpg-mssr.c
index c0b51f9bb278..820b220b09cc 100644
--- a/drivers/clk/renesas/r8a7791-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7791-cpg-mssr.c
@@ -128,6 +128,7 @@ static const struct mssr_mod_clk r8a7791_mod_clks[] __initconst = {
128 DEF_MOD("cmt1", 329, R8A7791_CLK_R), 128 DEF_MOD("cmt1", 329, R8A7791_CLK_R),
129 DEF_MOD("usbhs-dmac0", 330, R8A7791_CLK_HP), 129 DEF_MOD("usbhs-dmac0", 330, R8A7791_CLK_HP),
130 DEF_MOD("usbhs-dmac1", 331, R8A7791_CLK_HP), 130 DEF_MOD("usbhs-dmac1", 331, R8A7791_CLK_HP),
131 DEF_MOD("rwdt", 402, R8A7791_CLK_R),
131 DEF_MOD("irqc", 407, R8A7791_CLK_CP), 132 DEF_MOD("irqc", 407, R8A7791_CLK_CP),
132 DEF_MOD("intc-sys", 408, R8A7791_CLK_ZS), 133 DEF_MOD("intc-sys", 408, R8A7791_CLK_ZS),
133 DEF_MOD("audio-dmac1", 501, R8A7791_CLK_HP), 134 DEF_MOD("audio-dmac1", 501, R8A7791_CLK_HP),
@@ -209,6 +210,7 @@ static const struct mssr_mod_clk r8a7791_mod_clks[] __initconst = {
209}; 210};
210 211
211static const unsigned int r8a7791_crit_mod_clks[] __initconst = { 212static const unsigned int r8a7791_crit_mod_clks[] __initconst = {
213 MOD_CLK_ID(402), /* RWDT */
212 MOD_CLK_ID(408), /* INTC-SYS (GIC) */ 214 MOD_CLK_ID(408), /* INTC-SYS (GIC) */
213}; 215};
214 216
diff --git a/drivers/clk/renesas/r8a7792-cpg-mssr.c b/drivers/clk/renesas/r8a7792-cpg-mssr.c
index 7f85bbf20bf7..609a54080496 100644
--- a/drivers/clk/renesas/r8a7792-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7792-cpg-mssr.c
@@ -98,6 +98,7 @@ static const struct mssr_mod_clk r8a7792_mod_clks[] __initconst = {
98 DEF_MOD("tpu0", 304, R8A7792_CLK_CP), 98 DEF_MOD("tpu0", 304, R8A7792_CLK_CP),
99 DEF_MOD("sdhi0", 314, R8A7792_CLK_SD), 99 DEF_MOD("sdhi0", 314, R8A7792_CLK_SD),
100 DEF_MOD("cmt1", 329, R8A7792_CLK_R), 100 DEF_MOD("cmt1", 329, R8A7792_CLK_R),
101 DEF_MOD("rwdt", 402, R8A7792_CLK_R),
101 DEF_MOD("irqc", 407, R8A7792_CLK_CP), 102 DEF_MOD("irqc", 407, R8A7792_CLK_CP),
102 DEF_MOD("intc-sys", 408, R8A7792_CLK_ZS), 103 DEF_MOD("intc-sys", 408, R8A7792_CLK_ZS),
103 DEF_MOD("audio-dmac0", 502, R8A7792_CLK_HP), 104 DEF_MOD("audio-dmac0", 502, R8A7792_CLK_HP),
@@ -154,6 +155,7 @@ static const struct mssr_mod_clk r8a7792_mod_clks[] __initconst = {
154}; 155};
155 156
156static const unsigned int r8a7792_crit_mod_clks[] __initconst = { 157static const unsigned int r8a7792_crit_mod_clks[] __initconst = {
158 MOD_CLK_ID(402), /* RWDT */
157 MOD_CLK_ID(408), /* INTC-SYS (GIC) */ 159 MOD_CLK_ID(408), /* INTC-SYS (GIC) */
158}; 160};
159 161
diff --git a/drivers/clk/renesas/r8a7794-cpg-mssr.c b/drivers/clk/renesas/r8a7794-cpg-mssr.c
index ec091a42da54..2a40bbeaeeaf 100644
--- a/drivers/clk/renesas/r8a7794-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7794-cpg-mssr.c
@@ -121,6 +121,7 @@ static const struct mssr_mod_clk r8a7794_mod_clks[] __initconst = {
121 DEF_MOD("cmt1", 329, R8A7794_CLK_R), 121 DEF_MOD("cmt1", 329, R8A7794_CLK_R),
122 DEF_MOD("usbhs-dmac0", 330, R8A7794_CLK_HP), 122 DEF_MOD("usbhs-dmac0", 330, R8A7794_CLK_HP),
123 DEF_MOD("usbhs-dmac1", 331, R8A7794_CLK_HP), 123 DEF_MOD("usbhs-dmac1", 331, R8A7794_CLK_HP),
124 DEF_MOD("rwdt", 402, R8A7794_CLK_R),
124 DEF_MOD("irqc", 407, R8A7794_CLK_CP), 125 DEF_MOD("irqc", 407, R8A7794_CLK_CP),
125 DEF_MOD("intc-sys", 408, R8A7794_CLK_ZS), 126 DEF_MOD("intc-sys", 408, R8A7794_CLK_ZS),
126 DEF_MOD("audio-dmac0", 502, R8A7794_CLK_HP), 127 DEF_MOD("audio-dmac0", 502, R8A7794_CLK_HP),
@@ -190,6 +191,7 @@ static const struct mssr_mod_clk r8a7794_mod_clks[] __initconst = {
190}; 191};
191 192
192static const unsigned int r8a7794_crit_mod_clks[] __initconst = { 193static const unsigned int r8a7794_crit_mod_clks[] __initconst = {
194 MOD_CLK_ID(402), /* RWDT */
193 MOD_CLK_ID(408), /* INTC-SYS (GIC) */ 195 MOD_CLK_ID(408), /* INTC-SYS (GIC) */
194}; 196};
195 197
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index b1d9f48eae9e..775b0ceaa337 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -74,6 +74,8 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = {
74 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), 74 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
75 75
76 /* Core Clock Outputs */ 76 /* Core Clock Outputs */
77 DEF_BASE("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
78 DEF_BASE("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2),
77 DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), 79 DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
78 DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), 80 DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
79 DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1), 81 DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index 41e29734126b..dfb267a92f2a 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -74,6 +74,8 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
74 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), 74 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
75 75
76 /* Core Clock Outputs */ 76 /* Core Clock Outputs */
77 DEF_BASE("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
78 DEF_BASE("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2),
77 DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), 79 DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
78 DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), 80 DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
79 DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1), 81 DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c
new file mode 100644
index 000000000000..41e506ab557d
--- /dev/null
+++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
@@ -0,0 +1,334 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * r8a77965 Clock Pulse Generator / Module Standby and Software Reset
4 *
5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
6 *
7 * Based on r8a7795-cpg-mssr.c
8 *
9 * Copyright (C) 2015 Glider bvba
10 * Copyright (C) 2015 Renesas Electronics Corp.
11 */
12
13#include <linux/device.h>
14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/soc/renesas/rcar-rst.h>
17
18#include <dt-bindings/clock/r8a77965-cpg-mssr.h>
19
20#include "renesas-cpg-mssr.h"
21#include "rcar-gen3-cpg.h"
22
23enum clk_ids {
24 /* Core Clock Outputs exported to DT */
25 LAST_DT_CORE_CLK = R8A77965_CLK_OSC,
26
27 /* External Input Clocks */
28 CLK_EXTAL,
29 CLK_EXTALR,
30
31 /* Internal Core Clocks */
32 CLK_MAIN,
33 CLK_PLL0,
34 CLK_PLL1,
35 CLK_PLL3,
36 CLK_PLL4,
37 CLK_PLL1_DIV2,
38 CLK_PLL1_DIV4,
39 CLK_S0,
40 CLK_S1,
41 CLK_S2,
42 CLK_S3,
43 CLK_SDSRC,
44 CLK_SSPSRC,
45 CLK_RINT,
46
47 /* Module Clocks */
48 MOD_CLK_BASE
49};
50
51static const struct cpg_core_clk r8a77965_core_clks[] __initconst = {
52 /* External Clock Inputs */
53 DEF_INPUT("extal", CLK_EXTAL),
54 DEF_INPUT("extalr", CLK_EXTALR),
55
56 /* Internal Core Clocks */
57 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
58 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
59 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
60 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
61 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
62
63 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
64 DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
65 DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
66 DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
67 DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
68 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
69 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
70
71 /* Core Clock Outputs */
72 DEF_BASE("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
73 DEF_FIXED("ztr", R8A77965_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
74 DEF_FIXED("ztrd2", R8A77965_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
75 DEF_FIXED("zt", R8A77965_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
76 DEF_FIXED("zx", R8A77965_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
77 DEF_FIXED("s0d1", R8A77965_CLK_S0D1, CLK_S0, 1, 1),
78 DEF_FIXED("s0d2", R8A77965_CLK_S0D2, CLK_S0, 2, 1),
79 DEF_FIXED("s0d3", R8A77965_CLK_S0D3, CLK_S0, 3, 1),
80 DEF_FIXED("s0d4", R8A77965_CLK_S0D4, CLK_S0, 4, 1),
81 DEF_FIXED("s0d6", R8A77965_CLK_S0D6, CLK_S0, 6, 1),
82 DEF_FIXED("s0d8", R8A77965_CLK_S0D8, CLK_S0, 8, 1),
83 DEF_FIXED("s0d12", R8A77965_CLK_S0D12, CLK_S0, 12, 1),
84 DEF_FIXED("s1d1", R8A77965_CLK_S1D1, CLK_S1, 1, 1),
85 DEF_FIXED("s1d2", R8A77965_CLK_S1D2, CLK_S1, 2, 1),
86 DEF_FIXED("s1d4", R8A77965_CLK_S1D4, CLK_S1, 4, 1),
87 DEF_FIXED("s2d1", R8A77965_CLK_S2D1, CLK_S2, 1, 1),
88 DEF_FIXED("s2d2", R8A77965_CLK_S2D2, CLK_S2, 2, 1),
89 DEF_FIXED("s2d4", R8A77965_CLK_S2D4, CLK_S2, 4, 1),
90 DEF_FIXED("s3d1", R8A77965_CLK_S3D1, CLK_S3, 1, 1),
91 DEF_FIXED("s3d2", R8A77965_CLK_S3D2, CLK_S3, 2, 1),
92 DEF_FIXED("s3d4", R8A77965_CLK_S3D4, CLK_S3, 4, 1),
93
94 DEF_GEN3_SD("sd0", R8A77965_CLK_SD0, CLK_SDSRC, 0x074),
95 DEF_GEN3_SD("sd1", R8A77965_CLK_SD1, CLK_SDSRC, 0x078),
96 DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, CLK_SDSRC, 0x268),
97 DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, CLK_SDSRC, 0x26c),
98
99 DEF_FIXED("cl", R8A77965_CLK_CL, CLK_PLL1_DIV2, 48, 1),
100 DEF_FIXED("cp", R8A77965_CLK_CP, CLK_EXTAL, 2, 1),
101
102 DEF_DIV6P1("canfd", R8A77965_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
103 DEF_DIV6P1("csi0", R8A77965_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
104 DEF_DIV6P1("mso", R8A77965_CLK_MSO, CLK_PLL1_DIV4, 0x014),
105 DEF_DIV6P1("hdmi", R8A77965_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
106
107 DEF_DIV6_RO("osc", R8A77965_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
108 DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
109
110 DEF_BASE("r", R8A77965_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
111};
112
113static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
114 DEF_MOD("scif5", 202, R8A77965_CLK_S3D4),
115 DEF_MOD("scif4", 203, R8A77965_CLK_S3D4),
116 DEF_MOD("scif3", 204, R8A77965_CLK_S3D4),
117 DEF_MOD("scif1", 206, R8A77965_CLK_S3D4),
118 DEF_MOD("scif0", 207, R8A77965_CLK_S3D4),
119 DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S0D3),
120 DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S0D3),
121 DEF_MOD("sys-dmac0", 219, R8A77965_CLK_S0D3),
122
123 DEF_MOD("cmt3", 300, R8A77965_CLK_R),
124 DEF_MOD("cmt2", 301, R8A77965_CLK_R),
125 DEF_MOD("cmt1", 302, R8A77965_CLK_R),
126 DEF_MOD("cmt0", 303, R8A77965_CLK_R),
127 DEF_MOD("scif2", 310, R8A77965_CLK_S3D4),
128 DEF_MOD("sdif3", 311, R8A77965_CLK_SD3),
129 DEF_MOD("sdif2", 312, R8A77965_CLK_SD2),
130 DEF_MOD("sdif1", 313, R8A77965_CLK_SD1),
131 DEF_MOD("sdif0", 314, R8A77965_CLK_SD0),
132 DEF_MOD("pcie1", 318, R8A77965_CLK_S3D1),
133 DEF_MOD("pcie0", 319, R8A77965_CLK_S3D1),
134 DEF_MOD("usb3-if0", 328, R8A77965_CLK_S3D1),
135 DEF_MOD("usb-dmac0", 330, R8A77965_CLK_S3D1),
136 DEF_MOD("usb-dmac1", 331, R8A77965_CLK_S3D1),
137
138 DEF_MOD("rwdt", 402, R8A77965_CLK_R),
139 DEF_MOD("intc-ex", 407, R8A77965_CLK_CP),
140 DEF_MOD("intc-ap", 408, R8A77965_CLK_S0D3),
141
142 DEF_MOD("audmac1", 501, R8A77965_CLK_S0D3),
143 DEF_MOD("audmac0", 502, R8A77965_CLK_S0D3),
144 DEF_MOD("drif7", 508, R8A77965_CLK_S3D2),
145 DEF_MOD("drif6", 509, R8A77965_CLK_S3D2),
146 DEF_MOD("drif5", 510, R8A77965_CLK_S3D2),
147 DEF_MOD("drif4", 511, R8A77965_CLK_S3D2),
148 DEF_MOD("drif3", 512, R8A77965_CLK_S3D2),
149 DEF_MOD("drif2", 513, R8A77965_CLK_S3D2),
150 DEF_MOD("drif1", 514, R8A77965_CLK_S3D2),
151 DEF_MOD("drif0", 515, R8A77965_CLK_S3D2),
152 DEF_MOD("hscif4", 516, R8A77965_CLK_S3D1),
153 DEF_MOD("hscif3", 517, R8A77965_CLK_S3D1),
154 DEF_MOD("hscif2", 518, R8A77965_CLK_S3D1),
155 DEF_MOD("hscif1", 519, R8A77965_CLK_S3D1),
156 DEF_MOD("hscif0", 520, R8A77965_CLK_S3D1),
157 DEF_MOD("thermal", 522, R8A77965_CLK_CP),
158 DEF_MOD("pwm", 523, R8A77965_CLK_S0D12),
159
160 DEF_MOD("fcpvd1", 602, R8A77965_CLK_S0D2),
161 DEF_MOD("fcpvd0", 603, R8A77965_CLK_S0D2),
162 DEF_MOD("fcpvb0", 607, R8A77965_CLK_S0D1),
163 DEF_MOD("fcpvi0", 611, R8A77965_CLK_S0D1),
164 DEF_MOD("fcpf0", 615, R8A77965_CLK_S0D1),
165 DEF_MOD("fcpcs", 619, R8A77965_CLK_S0D2),
166 DEF_MOD("vspd1", 622, R8A77965_CLK_S0D2),
167 DEF_MOD("vspd0", 623, R8A77965_CLK_S0D2),
168 DEF_MOD("vspb", 626, R8A77965_CLK_S0D1),
169 DEF_MOD("vspi0", 631, R8A77965_CLK_S0D1),
170
171 DEF_MOD("ehci1", 702, R8A77965_CLK_S3D4),
172 DEF_MOD("ehci0", 703, R8A77965_CLK_S3D4),
173 DEF_MOD("hsusb", 704, R8A77965_CLK_S3D4),
174 DEF_MOD("csi20", 714, R8A77965_CLK_CSI0),
175 DEF_MOD("csi40", 716, R8A77965_CLK_CSI0),
176 DEF_MOD("du2", 722, R8A77965_CLK_S2D1),
177 DEF_MOD("du1", 723, R8A77965_CLK_S2D1),
178 DEF_MOD("du0", 724, R8A77965_CLK_S2D1),
179 DEF_MOD("lvds", 727, R8A77965_CLK_S2D1),
180 DEF_MOD("hdmi0", 729, R8A77965_CLK_HDMI),
181
182 DEF_MOD("vin7", 804, R8A77965_CLK_S0D2),
183 DEF_MOD("vin6", 805, R8A77965_CLK_S0D2),
184 DEF_MOD("vin5", 806, R8A77965_CLK_S0D2),
185 DEF_MOD("vin4", 807, R8A77965_CLK_S0D2),
186 DEF_MOD("vin3", 808, R8A77965_CLK_S0D2),
187 DEF_MOD("vin2", 809, R8A77965_CLK_S0D2),
188 DEF_MOD("vin1", 810, R8A77965_CLK_S0D2),
189 DEF_MOD("vin0", 811, R8A77965_CLK_S0D2),
190 DEF_MOD("etheravb", 812, R8A77965_CLK_S0D6),
191 DEF_MOD("imr1", 822, R8A77965_CLK_S0D2),
192 DEF_MOD("imr0", 823, R8A77965_CLK_S0D2),
193
194 DEF_MOD("gpio7", 905, R8A77965_CLK_S3D4),
195 DEF_MOD("gpio6", 906, R8A77965_CLK_S3D4),
196 DEF_MOD("gpio5", 907, R8A77965_CLK_S3D4),
197 DEF_MOD("gpio4", 908, R8A77965_CLK_S3D4),
198 DEF_MOD("gpio3", 909, R8A77965_CLK_S3D4),
199 DEF_MOD("gpio2", 910, R8A77965_CLK_S3D4),
200 DEF_MOD("gpio1", 911, R8A77965_CLK_S3D4),
201 DEF_MOD("gpio0", 912, R8A77965_CLK_S3D4),
202 DEF_MOD("can-fd", 914, R8A77965_CLK_S3D2),
203 DEF_MOD("can-if1", 915, R8A77965_CLK_S3D4),
204 DEF_MOD("can-if0", 916, R8A77965_CLK_S3D4),
205 DEF_MOD("i2c6", 918, R8A77965_CLK_S0D6),
206 DEF_MOD("i2c5", 919, R8A77965_CLK_S0D6),
207 DEF_MOD("i2c-dvfs", 926, R8A77965_CLK_CP),
208 DEF_MOD("i2c4", 927, R8A77965_CLK_S0D6),
209 DEF_MOD("i2c3", 928, R8A77965_CLK_S0D6),
210 DEF_MOD("i2c2", 929, R8A77965_CLK_S3D2),
211 DEF_MOD("i2c1", 930, R8A77965_CLK_S3D2),
212 DEF_MOD("i2c0", 931, R8A77965_CLK_S3D2),
213
214 DEF_MOD("ssi-all", 1005, R8A77965_CLK_S3D4),
215 DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
216 DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
217 DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
218 DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
219 DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
220 DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
221 DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
222 DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
223 DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
224 DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
225 DEF_MOD("scu-all", 1017, R8A77965_CLK_S3D4),
226 DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
227 DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
228 DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
229 DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
230 DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
231 DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
232 DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
233 DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
234 DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
235 DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
236 DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
237 DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
238 DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
239 DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
240};
241
242static const unsigned int r8a77965_crit_mod_clks[] __initconst = {
243 MOD_CLK_ID(408), /* INTC-AP (GIC) */
244};
245
246/*
247 * CPG Clock Data
248 */
249
250/*
251 * MD EXTAL PLL0 PLL1 PLL3 PLL4
252 * 14 13 19 17 (MHz)
253 *-----------------------------------------------------------
254 * 0 0 0 0 16.66 x 1 x180 x192 x192 x144
255 * 0 0 0 1 16.66 x 1 x180 x192 x128 x144
256 * 0 0 1 0 Prohibited setting
257 * 0 0 1 1 16.66 x 1 x180 x192 x192 x144
258 * 0 1 0 0 20 x 1 x150 x160 x160 x120
259 * 0 1 0 1 20 x 1 x150 x160 x106 x120
260 * 0 1 1 0 Prohibited setting
261 * 0 1 1 1 20 x 1 x150 x160 x160 x120
262 * 1 0 0 0 25 x 1 x120 x128 x128 x96
263 * 1 0 0 1 25 x 1 x120 x128 x84 x96
264 * 1 0 1 0 Prohibited setting
265 * 1 0 1 1 25 x 1 x120 x128 x128 x96
266 * 1 1 0 0 33.33 / 2 x180 x192 x192 x144
267 * 1 1 0 1 33.33 / 2 x180 x192 x128 x144
268 * 1 1 1 0 Prohibited setting
269 * 1 1 1 1 33.33 / 2 x180 x192 x192 x144
270 */
271#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
272 (((md) & BIT(13)) >> 11) | \
273 (((md) & BIT(19)) >> 18) | \
274 (((md) & BIT(17)) >> 17))
275
276static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
277 /* EXTAL div PLL1 mult/div PLL3 mult/div */
278 { 1, 192, 1, 192, 1, },
279 { 1, 192, 1, 128, 1, },
280 { 0, /* Prohibited setting */ },
281 { 1, 192, 1, 192, 1, },
282 { 1, 160, 1, 160, 1, },
283 { 1, 160, 1, 106, 1, },
284 { 0, /* Prohibited setting */ },
285 { 1, 160, 1, 160, 1, },
286 { 1, 128, 1, 128, 1, },
287 { 1, 128, 1, 84, 1, },
288 { 0, /* Prohibited setting */ },
289 { 1, 128, 1, 128, 1, },
290 { 2, 192, 1, 192, 1, },
291 { 2, 192, 1, 128, 1, },
292 { 0, /* Prohibited setting */ },
293 { 2, 192, 1, 192, 1, },
294};
295
296static int __init r8a77965_cpg_mssr_init(struct device *dev)
297{
298 const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
299 u32 cpg_mode;
300 int error;
301
302 error = rcar_rst_read_mode_pins(&cpg_mode);
303 if (error)
304 return error;
305
306 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
307 if (!cpg_pll_config->extal_div) {
308 dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
309 return -EINVAL;
310 }
311
312 return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
313};
314
315const struct cpg_mssr_info r8a77965_cpg_mssr_info __initconst = {
316 /* Core Clocks */
317 .core_clks = r8a77965_core_clks,
318 .num_core_clks = ARRAY_SIZE(r8a77965_core_clks),
319 .last_dt_core_clk = LAST_DT_CORE_CLK,
320 .num_total_core_clks = MOD_CLK_BASE,
321
322 /* Module Clocks */
323 .mod_clks = r8a77965_mod_clks,
324 .num_mod_clks = ARRAY_SIZE(r8a77965_mod_clks),
325 .num_hw_mod_clks = 12 * 32,
326
327 /* Critical Module Clocks */
328 .crit_mod_clks = r8a77965_crit_mod_clks,
329 .num_crit_mod_clks = ARRAY_SIZE(r8a77965_crit_mod_clks),
330
331 /* Callbacks */
332 .init = r8a77965_cpg_mssr_init,
333 .cpg_clk_register = rcar_gen3_cpg_clk_register,
334};
diff --git a/drivers/clk/renesas/r8a77980-cpg-mssr.c b/drivers/clk/renesas/r8a77980-cpg-mssr.c
new file mode 100644
index 000000000000..7aaae73a321a
--- /dev/null
+++ b/drivers/clk/renesas/r8a77980-cpg-mssr.c
@@ -0,0 +1,227 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * r8a77980 Clock Pulse Generator / Module Standby and Software Reset
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc.
7 *
8 * Based on r8a7795-cpg-mssr.c
9 *
10 * Copyright (C) 2015 Glider bvba
11 */
12
13#include <linux/device.h>
14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/soc/renesas/rcar-rst.h>
17#include <linux/sys_soc.h>
18
19#include <dt-bindings/clock/r8a77980-cpg-mssr.h>
20
21#include "renesas-cpg-mssr.h"
22#include "rcar-gen3-cpg.h"
23
24enum clk_ids {
25 /* Core Clock Outputs exported to DT */
26 LAST_DT_CORE_CLK = R8A77980_CLK_OSC,
27
28 /* External Input Clocks */
29 CLK_EXTAL,
30 CLK_EXTALR,
31
32 /* Internal Core Clocks */
33 CLK_MAIN,
34 CLK_PLL1,
35 CLK_PLL2,
36 CLK_PLL3,
37 CLK_PLL1_DIV2,
38 CLK_PLL1_DIV4,
39 CLK_S0,
40 CLK_S1,
41 CLK_S2,
42 CLK_S3,
43 CLK_SDSRC,
44
45 /* Module Clocks */
46 MOD_CLK_BASE
47};
48
49static const struct cpg_core_clk r8a77980_core_clks[] __initconst = {
50 /* External Clock Inputs */
51 DEF_INPUT("extal", CLK_EXTAL),
52 DEF_INPUT("extalr", CLK_EXTALR),
53
54 /* Internal Core Clocks */
55 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
56 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
57 DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
58 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
59
60 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
61 DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
62 DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
63 DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
64 DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
65 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
66 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
67
68 /* Core Clock Outputs */
69 DEF_FIXED("ztr", R8A77980_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
70 DEF_FIXED("ztrd2", R8A77980_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
71 DEF_FIXED("zt", R8A77980_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
72 DEF_FIXED("zx", R8A77980_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
73 DEF_FIXED("s0d1", R8A77980_CLK_S0D1, CLK_S0, 1, 1),
74 DEF_FIXED("s0d2", R8A77980_CLK_S0D2, CLK_S0, 2, 1),
75 DEF_FIXED("s0d3", R8A77980_CLK_S0D3, CLK_S0, 3, 1),
76 DEF_FIXED("s0d4", R8A77980_CLK_S0D4, CLK_S0, 4, 1),
77 DEF_FIXED("s0d6", R8A77980_CLK_S0D6, CLK_S0, 6, 1),
78 DEF_FIXED("s0d12", R8A77980_CLK_S0D12, CLK_S0, 12, 1),
79 DEF_FIXED("s0d24", R8A77980_CLK_S0D24, CLK_S0, 24, 1),
80 DEF_FIXED("s1d1", R8A77980_CLK_S1D1, CLK_S1, 1, 1),
81 DEF_FIXED("s1d2", R8A77980_CLK_S1D2, CLK_S1, 2, 1),
82 DEF_FIXED("s1d4", R8A77980_CLK_S1D4, CLK_S1, 4, 1),
83 DEF_FIXED("s2d1", R8A77980_CLK_S2D1, CLK_S2, 1, 1),
84 DEF_FIXED("s2d2", R8A77980_CLK_S2D2, CLK_S2, 2, 1),
85 DEF_FIXED("s2d4", R8A77980_CLK_S2D4, CLK_S2, 4, 1),
86 DEF_FIXED("s3d1", R8A77980_CLK_S3D1, CLK_S3, 1, 1),
87 DEF_FIXED("s3d2", R8A77980_CLK_S3D2, CLK_S3, 2, 1),
88 DEF_FIXED("s3d4", R8A77980_CLK_S3D4, CLK_S3, 4, 1),
89
90 DEF_GEN3_SD("sd0", R8A77980_CLK_SD0, CLK_SDSRC, 0x0074),
91
92 DEF_FIXED("cl", R8A77980_CLK_CL, CLK_PLL1_DIV2, 48, 1),
93 DEF_FIXED("cp", R8A77980_CLK_CP, CLK_EXTAL, 2, 1),
94 DEF_FIXED("cpex", R8A77980_CLK_CPEX, CLK_EXTAL, 2, 1),
95
96 DEF_DIV6P1("canfd", R8A77980_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
97 DEF_DIV6P1("csi0", R8A77980_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
98 DEF_DIV6P1("mso", R8A77980_CLK_MSO, CLK_PLL1_DIV4, 0x014),
99};
100
101static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = {
102 DEF_MOD("tmu4", 121, R8A77980_CLK_S0D6),
103 DEF_MOD("tmu3", 122, R8A77980_CLK_S0D6),
104 DEF_MOD("tmu2", 123, R8A77980_CLK_S0D6),
105 DEF_MOD("tmu1", 124, R8A77980_CLK_S0D6),
106 DEF_MOD("tmu0", 125, R8A77980_CLK_CP),
107 DEF_MOD("scif4", 203, R8A77980_CLK_S3D4),
108 DEF_MOD("scif3", 204, R8A77980_CLK_S3D4),
109 DEF_MOD("scif1", 206, R8A77980_CLK_S3D4),
110 DEF_MOD("scif0", 207, R8A77980_CLK_S3D4),
111 DEF_MOD("msiof3", 208, R8A77980_CLK_MSO),
112 DEF_MOD("msiof2", 209, R8A77980_CLK_MSO),
113 DEF_MOD("msiof1", 210, R8A77980_CLK_MSO),
114 DEF_MOD("msiof0", 211, R8A77980_CLK_MSO),
115 DEF_MOD("sys-dmac2", 217, R8A77980_CLK_S0D3),
116 DEF_MOD("sys-dmac1", 218, R8A77980_CLK_S0D3),
117 DEF_MOD("tpu0", 304, R8A77980_CLK_S3D4),
118 DEF_MOD("sdif", 314, R8A77980_CLK_SD0),
119 DEF_MOD("pciec0", 319, R8A77980_CLK_S3D1),
120 DEF_MOD("intc-ex", 407, R8A77980_CLK_CP),
121 DEF_MOD("intc-ap", 408, R8A77980_CLK_S0D3),
122 DEF_MOD("hscif3", 517, R8A77980_CLK_S3D1),
123 DEF_MOD("hscif2", 518, R8A77980_CLK_S3D1),
124 DEF_MOD("hscif1", 519, R8A77980_CLK_S3D1),
125 DEF_MOD("hscif0", 520, R8A77980_CLK_S3D1),
126 DEF_MOD("imp4", 521, R8A77980_CLK_S1D1),
127 DEF_MOD("thermal", 522, R8A77980_CLK_CP),
128 DEF_MOD("pwm", 523, R8A77980_CLK_S0D12),
129 DEF_MOD("impdma1", 526, R8A77980_CLK_S1D1),
130 DEF_MOD("impdma0", 527, R8A77980_CLK_S1D1),
131 DEF_MOD("imp-ocv4", 528, R8A77980_CLK_S1D1),
132 DEF_MOD("imp-ocv3", 529, R8A77980_CLK_S1D1),
133 DEF_MOD("imp-ocv2", 531, R8A77980_CLK_S1D1),
134 DEF_MOD("fcpvd0", 603, R8A77980_CLK_S3D1),
135 DEF_MOD("vspd0", 623, R8A77980_CLK_S3D1),
136 DEF_MOD("csi41", 715, R8A77980_CLK_CSI0),
137 DEF_MOD("csi40", 716, R8A77980_CLK_CSI0),
138 DEF_MOD("du0", 724, R8A77980_CLK_S2D1),
139 DEF_MOD("lvds", 727, R8A77980_CLK_S2D1),
140 DEF_MOD("etheravb", 812, R8A77980_CLK_S3D2),
141 DEF_MOD("gether", 813, R8A77980_CLK_S3D2),
142 DEF_MOD("imp3", 824, R8A77980_CLK_S1D1),
143 DEF_MOD("imp2", 825, R8A77980_CLK_S1D1),
144 DEF_MOD("imp1", 826, R8A77980_CLK_S1D1),
145 DEF_MOD("imp0", 827, R8A77980_CLK_S1D1),
146 DEF_MOD("imp-ocv1", 828, R8A77980_CLK_S1D1),
147 DEF_MOD("imp-ocv0", 829, R8A77980_CLK_S1D1),
148 DEF_MOD("impram", 830, R8A77980_CLK_S1D1),
149 DEF_MOD("impcnn", 831, R8A77980_CLK_S1D1),
150 DEF_MOD("gpio5", 907, R8A77980_CLK_CP),
151 DEF_MOD("gpio4", 908, R8A77980_CLK_CP),
152 DEF_MOD("gpio3", 909, R8A77980_CLK_CP),
153 DEF_MOD("gpio2", 910, R8A77980_CLK_CP),
154 DEF_MOD("gpio1", 911, R8A77980_CLK_CP),
155 DEF_MOD("gpio0", 912, R8A77980_CLK_CP),
156 DEF_MOD("can-fd", 914, R8A77980_CLK_S3D2),
157 DEF_MOD("i2c4", 927, R8A77980_CLK_S0D6),
158 DEF_MOD("i2c3", 928, R8A77980_CLK_S0D6),
159 DEF_MOD("i2c2", 929, R8A77980_CLK_S3D2),
160 DEF_MOD("i2c1", 930, R8A77980_CLK_S3D2),
161 DEF_MOD("i2c0", 931, R8A77980_CLK_S3D2),
162};
163
164static const unsigned int r8a77980_crit_mod_clks[] __initconst = {
165 MOD_CLK_ID(408), /* INTC-AP (GIC) */
166};
167
168
169/*
170 * CPG Clock Data
171 */
172
173/*
174 * MD EXTAL PLL2 PLL1 PLL3
175 * 14 13 (MHz)
176 * --------------------------------------------------
177 * 0 0 16.66 x 1 x240 x192 x192
178 * 0 1 20 x 1 x200 x160 x160
179 * 1 0 27 x 1 x148 x118 x118
180 * 1 1 33.33 / 2 x240 x192 x192
181 */
182#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
183 (((md) & BIT(13)) >> 13))
184
185static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] __initconst = {
186 /* EXTAL div PLL1 mult/div PLL3 mult/div */
187 { 1, 192, 1, 192, 1, },
188 { 1, 160, 1, 160, 1, },
189 { 1, 118, 1, 118, 1, },
190 { 2, 192, 1, 192, 1, },
191};
192
193static int __init r8a77980_cpg_mssr_init(struct device *dev)
194{
195 const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
196 u32 cpg_mode;
197 int error;
198
199 error = rcar_rst_read_mode_pins(&cpg_mode);
200 if (error)
201 return error;
202
203 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
204
205 return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
206}
207
208const struct cpg_mssr_info r8a77980_cpg_mssr_info __initconst = {
209 /* Core Clocks */
210 .core_clks = r8a77980_core_clks,
211 .num_core_clks = ARRAY_SIZE(r8a77980_core_clks),
212 .last_dt_core_clk = LAST_DT_CORE_CLK,
213 .num_total_core_clks = MOD_CLK_BASE,
214
215 /* Module Clocks */
216 .mod_clks = r8a77980_mod_clks,
217 .num_mod_clks = ARRAY_SIZE(r8a77980_mod_clks),
218 .num_hw_mod_clks = 12 * 32,
219
220 /* Critical Module Clocks */
221 .crit_mod_clks = r8a77980_crit_mod_clks,
222 .num_crit_mod_clks = ARRAY_SIZE(r8a77980_crit_mod_clks),
223
224 /* Callbacks */
225 .init = r8a77980_cpg_mssr_init,
226 .cpg_clk_register = rcar_gen3_cpg_clk_register,
227};
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index 0904886f5501..0c8fe10d57fe 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -13,6 +13,7 @@
13 */ 13 */
14 14
15#include <linux/bug.h> 15#include <linux/bug.h>
16#include <linux/bitfield.h>
16#include <linux/clk.h> 17#include <linux/clk.h>
17#include <linux/clk-provider.h> 18#include <linux/clk-provider.h>
18#include <linux/device.h> 19#include <linux/device.h>
@@ -62,6 +63,140 @@ static void cpg_simple_notifier_register(struct raw_notifier_head *notifiers,
62} 63}
63 64
64/* 65/*
66 * Z Clock & Z2 Clock
67 *
68 * Traits of this clock:
69 * prepare - clk_prepare only ensures that parents are prepared
70 * enable - clk_enable only ensures that parents are enabled
71 * rate - rate is adjustable. clk->rate = (parent->rate * mult / 32 ) / 2
72 * parent - fixed parent. No clk_set_parent support
73 */
74#define CPG_FRQCRB 0x00000004
75#define CPG_FRQCRB_KICK BIT(31)
76#define CPG_FRQCRC 0x000000e0
77#define CPG_FRQCRC_ZFC_MASK GENMASK(12, 8)
78#define CPG_FRQCRC_Z2FC_MASK GENMASK(4, 0)
79
80struct cpg_z_clk {
81 struct clk_hw hw;
82 void __iomem *reg;
83 void __iomem *kick_reg;
84 unsigned long mask;
85};
86
87#define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw)
88
89static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
90 unsigned long parent_rate)
91{
92 struct cpg_z_clk *zclk = to_z_clk(hw);
93 unsigned int mult;
94 u32 val;
95
96 val = clk_readl(zclk->reg) & zclk->mask;
97 mult = 32 - (val >> __ffs(zclk->mask));
98
99 /* Factor of 2 is for fixed divider */
100 return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, 32 * 2);
101}
102
103static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate,
104 unsigned long *parent_rate)
105{
106 /* Factor of 2 is for fixed divider */
107 unsigned long prate = *parent_rate / 2;
108 unsigned int mult;
109
110 mult = div_u64(rate * 32ULL, prate);
111 mult = clamp(mult, 1U, 32U);
112
113 return (u64)prate * mult / 32;
114}
115
116static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
117 unsigned long parent_rate)
118{
119 struct cpg_z_clk *zclk = to_z_clk(hw);
120 unsigned int mult;
121 unsigned int i;
122 u32 val, kick;
123
124 /* Factor of 2 is for fixed divider */
125 mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL * 2, parent_rate);
126 mult = clamp(mult, 1U, 32U);
127
128 if (clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
129 return -EBUSY;
130
131 val = clk_readl(zclk->reg) & ~zclk->mask;
132 val |= ((32 - mult) << __ffs(zclk->mask)) & zclk->mask;
133 clk_writel(val, zclk->reg);
134
135 /*
136 * Set KICK bit in FRQCRB to update hardware setting and wait for
137 * clock change completion.
138 */
139 kick = clk_readl(zclk->kick_reg);
140 kick |= CPG_FRQCRB_KICK;
141 clk_writel(kick, zclk->kick_reg);
142
143 /*
144 * Note: There is no HW information about the worst case latency.
145 *
146 * Using experimental measurements, it seems that no more than
147 * ~10 iterations are needed, independently of the CPU rate.
148 * Since this value might be dependent of external xtal rate, pll1
149 * rate or even the other emulation clocks rate, use 1000 as a
150 * "super" safe value.
151 */
152 for (i = 1000; i; i--) {
153 if (!(clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
154 return 0;
155
156 cpu_relax();
157 }
158
159 return -ETIMEDOUT;
160}
161
162static const struct clk_ops cpg_z_clk_ops = {
163 .recalc_rate = cpg_z_clk_recalc_rate,
164 .round_rate = cpg_z_clk_round_rate,
165 .set_rate = cpg_z_clk_set_rate,
166};
167
168static struct clk * __init cpg_z_clk_register(const char *name,
169 const char *parent_name,
170 void __iomem *reg,
171 unsigned long mask)
172{
173 struct clk_init_data init;
174 struct cpg_z_clk *zclk;
175 struct clk *clk;
176
177 zclk = kzalloc(sizeof(*zclk), GFP_KERNEL);
178 if (!zclk)
179 return ERR_PTR(-ENOMEM);
180
181 init.name = name;
182 init.ops = &cpg_z_clk_ops;
183 init.flags = 0;
184 init.parent_names = &parent_name;
185 init.num_parents = 1;
186
187 zclk->reg = reg + CPG_FRQCRC;
188 zclk->kick_reg = reg + CPG_FRQCRB;
189 zclk->hw.init = &init;
190 zclk->mask = mask;
191
192 clk = clk_register(NULL, &zclk->hw);
193 if (IS_ERR(clk))
194 kfree(zclk);
195
196 return clk;
197}
198
199/*
65 * SDn Clock 200 * SDn Clock
66 */ 201 */
67#define CPG_SD_STP_HCK BIT(9) 202#define CPG_SD_STP_HCK BIT(9)
@@ -420,6 +555,14 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
420 mult = 1; 555 mult = 1;
421 break; 556 break;
422 557
558 case CLK_TYPE_GEN3_Z:
559 return cpg_z_clk_register(core->name, __clk_get_name(parent),
560 base, CPG_FRQCRC_ZFC_MASK);
561
562 case CLK_TYPE_GEN3_Z2:
563 return cpg_z_clk_register(core->name, __clk_get_name(parent),
564 base, CPG_FRQCRC_Z2FC_MASK);
565
423 default: 566 default:
424 return ERR_PTR(-EINVAL); 567 return ERR_PTR(-EINVAL);
425 } 568 }
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h
index 2e4284399f53..ea4f8fc3c4c9 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -21,6 +21,8 @@ enum rcar_gen3_clk_types {
21 CLK_TYPE_GEN3_SD, 21 CLK_TYPE_GEN3_SD,
22 CLK_TYPE_GEN3_R, 22 CLK_TYPE_GEN3_R,
23 CLK_TYPE_GEN3_PE, 23 CLK_TYPE_GEN3_PE,
24 CLK_TYPE_GEN3_Z,
25 CLK_TYPE_GEN3_Z2,
24}; 26};
25 27
26#define DEF_GEN3_SD(_name, _id, _parent, _offset) \ 28#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index e3cc72c81311..96c678799623 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -693,12 +693,24 @@ static const struct of_device_id cpg_mssr_match[] = {
693 .data = &r8a7796_cpg_mssr_info, 693 .data = &r8a7796_cpg_mssr_info,
694 }, 694 },
695#endif 695#endif
696#ifdef CONFIG_CLK_R8A77965
697 {
698 .compatible = "renesas,r8a77965-cpg-mssr",
699 .data = &r8a77965_cpg_mssr_info,
700 },
701#endif
696#ifdef CONFIG_CLK_R8A77970 702#ifdef CONFIG_CLK_R8A77970
697 { 703 {
698 .compatible = "renesas,r8a77970-cpg-mssr", 704 .compatible = "renesas,r8a77970-cpg-mssr",
699 .data = &r8a77970_cpg_mssr_info, 705 .data = &r8a77970_cpg_mssr_info,
700 }, 706 },
701#endif 707#endif
708#ifdef CONFIG_ARCH_R8A77980
709 {
710 .compatible = "renesas,r8a77980-cpg-mssr",
711 .data = &r8a77980_cpg_mssr_info,
712 },
713#endif
702#ifdef CONFIG_CLK_R8A77995 714#ifdef CONFIG_CLK_R8A77995
703 { 715 {
704 .compatible = "renesas,r8a77995-cpg-mssr", 716 .compatible = "renesas,r8a77995-cpg-mssr",
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
index 0745b0930308..97ccb093c10f 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.h
+++ b/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -139,7 +139,9 @@ extern const struct cpg_mssr_info r8a7792_cpg_mssr_info;
139extern const struct cpg_mssr_info r8a7794_cpg_mssr_info; 139extern const struct cpg_mssr_info r8a7794_cpg_mssr_info;
140extern const struct cpg_mssr_info r8a7795_cpg_mssr_info; 140extern const struct cpg_mssr_info r8a7795_cpg_mssr_info;
141extern const struct cpg_mssr_info r8a7796_cpg_mssr_info; 141extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;
142extern const struct cpg_mssr_info r8a77965_cpg_mssr_info;
142extern const struct cpg_mssr_info r8a77970_cpg_mssr_info; 143extern const struct cpg_mssr_info r8a77970_cpg_mssr_info;
144extern const struct cpg_mssr_info r8a77980_cpg_mssr_info;
143extern const struct cpg_mssr_info r8a77995_cpg_mssr_info; 145extern const struct cpg_mssr_info r8a77995_cpg_mssr_info;
144 146
145 147
diff --git a/include/dt-bindings/clock/r8a77965-cpg-mssr.h b/include/dt-bindings/clock/r8a77965-cpg-mssr.h
new file mode 100644
index 000000000000..6d3b5a9a6084
--- /dev/null
+++ b/include/dt-bindings/clock/r8a77965-cpg-mssr.h
@@ -0,0 +1,62 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
4 */
5#ifndef __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__
6#define __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__
7
8#include <dt-bindings/clock/renesas-cpg-mssr.h>
9
10/* r8a77965 CPG Core Clocks */
11#define R8A77965_CLK_Z 0
12#define R8A77965_CLK_ZR 1
13#define R8A77965_CLK_ZG 2
14#define R8A77965_CLK_ZTR 3
15#define R8A77965_CLK_ZTRD2 4
16#define R8A77965_CLK_ZT 5
17#define R8A77965_CLK_ZX 6
18#define R8A77965_CLK_S0D1 7
19#define R8A77965_CLK_S0D2 8
20#define R8A77965_CLK_S0D3 9
21#define R8A77965_CLK_S0D4 10
22#define R8A77965_CLK_S0D6 11
23#define R8A77965_CLK_S0D8 12
24#define R8A77965_CLK_S0D12 13
25#define R8A77965_CLK_S1D1 14
26#define R8A77965_CLK_S1D2 15
27#define R8A77965_CLK_S1D4 16
28#define R8A77965_CLK_S2D1 17
29#define R8A77965_CLK_S2D2 18
30#define R8A77965_CLK_S2D4 19
31#define R8A77965_CLK_S3D1 20
32#define R8A77965_CLK_S3D2 21
33#define R8A77965_CLK_S3D4 22
34#define R8A77965_CLK_LB 23
35#define R8A77965_CLK_CL 24
36#define R8A77965_CLK_ZB3 25
37#define R8A77965_CLK_ZB3D2 26
38#define R8A77965_CLK_CR 27
39#define R8A77965_CLK_CRD2 28
40#define R8A77965_CLK_SD0H 29
41#define R8A77965_CLK_SD0 30
42#define R8A77965_CLK_SD1H 31
43#define R8A77965_CLK_SD1 32
44#define R8A77965_CLK_SD2H 33
45#define R8A77965_CLK_SD2 34
46#define R8A77965_CLK_SD3H 35
47#define R8A77965_CLK_SD3 36
48#define R8A77965_CLK_SSP2 37
49#define R8A77965_CLK_SSP1 38
50#define R8A77965_CLK_SSPRS 39
51#define R8A77965_CLK_RPC 40
52#define R8A77965_CLK_RPCD2 41
53#define R8A77965_CLK_MSO 42
54#define R8A77965_CLK_CANFD 43
55#define R8A77965_CLK_HDMI 44
56#define R8A77965_CLK_CSI0 45
57#define R8A77965_CLK_CP 46
58#define R8A77965_CLK_CPEX 47
59#define R8A77965_CLK_R 48
60#define R8A77965_CLK_OSC 49
61
62#endif /* __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a77980-cpg-mssr.h b/include/dt-bindings/clock/r8a77980-cpg-mssr.h
new file mode 100644
index 000000000000..a4c0d76c392e
--- /dev/null
+++ b/include/dt-bindings/clock/r8a77980-cpg-mssr.h
@@ -0,0 +1,51 @@
1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2018 Renesas Electronics Corp.
4 * Copyright (C) 2018 Cogent Embedded, Inc.
5 */
6#ifndef __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__
7#define __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__
8
9#include <dt-bindings/clock/renesas-cpg-mssr.h>
10
11/* r8a77980 CPG Core Clocks */
12#define R8A77980_CLK_Z2 0
13#define R8A77980_CLK_ZR 1
14#define R8A77980_CLK_ZTR 2
15#define R8A77980_CLK_ZTRD2 3
16#define R8A77980_CLK_ZT 4
17#define R8A77980_CLK_ZX 5
18#define R8A77980_CLK_S0D1 6
19#define R8A77980_CLK_S0D2 7
20#define R8A77980_CLK_S0D3 8
21#define R8A77980_CLK_S0D4 9
22#define R8A77980_CLK_S0D6 10
23#define R8A77980_CLK_S0D12 11
24#define R8A77980_CLK_S0D24 12
25#define R8A77980_CLK_S1D1 13
26#define R8A77980_CLK_S1D2 14
27#define R8A77980_CLK_S1D4 15
28#define R8A77980_CLK_S2D1 16
29#define R8A77980_CLK_S2D2 17
30#define R8A77980_CLK_S2D4 18
31#define R8A77980_CLK_S3D1 19
32#define R8A77980_CLK_S3D2 20
33#define R8A77980_CLK_S3D4 21
34#define R8A77980_CLK_LB 22
35#define R8A77980_CLK_CL 23
36#define R8A77980_CLK_ZB3 24
37#define R8A77980_CLK_ZB3D2 25
38#define R8A77980_CLK_ZB3D4 26
39#define R8A77980_CLK_SD0H 27
40#define R8A77980_CLK_SD0 28
41#define R8A77980_CLK_RPC 29
42#define R8A77980_CLK_RPCD2 30
43#define R8A77980_CLK_MSO 31
44#define R8A77980_CLK_CANFD 32
45#define R8A77980_CLK_CSI0 33
46#define R8A77980_CLK_CP 34
47#define R8A77980_CLK_CPEX 35
48#define R8A77980_CLK_R 36
49#define R8A77980_CLK_OSC 37
50
51#endif /* __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-06-01 12:28:00 -0400