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authorDavid S. Miller <davem@davemloft.net>2015-06-02 01:14:35 -0400
committerDavid S. Miller <davem@davemloft.net>2015-06-02 01:14:35 -0400
commitdb3397b9aa30d334be237170e048dcd96e1e951d (patch)
tree119132fcc78cc27155b4954d7bc9a55fee046838
parentd89511251f6519599b109dc6cda87a6ab314ed8c (diff)
parent41fc2e41d348a7bca768815adf033bbf00de220f (diff)
Merge branch 'cxgb4-next'
Hariprasad Shenai says: ==================== cxgb4/cxgb4vf: Adds support for Chelsio T6 adapter This patch series adds the following: Adds NIC driver support for T6 adapter Adds vNIC driver support for T6 adapter This patch series has been created against net-next tree and includes patches on cxgb4 and cxgb4vf driver. We have included all the maintainers of respective drivers. Kindly review the change and let us know in case of any review comments. Thanks V2: Fixed compilation issue, when CHELSIO_T4_FCOE is set ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/cxgb4.h21
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c180
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c47
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/sge.c47
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/t4_hw.c562
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/t4_msg.h3
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/t4_regs.h105
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/t4_values.h1
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h56
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/t4fw_version.h5
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4vf/sge.c45
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4vf/t4vf_common.h8
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c24
13 files changed, 932 insertions, 172 deletions
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
index 15cca3013de2..4d3a8c20eb12 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
@@ -224,7 +224,6 @@ struct sge_params {
224}; 224};
225 225
226struct tp_params { 226struct tp_params {
227 unsigned int ntxchan; /* # of Tx channels */
228 unsigned int tre; /* log2 of core clocks per TP tick */ 227 unsigned int tre; /* log2 of core clocks per TP tick */
229 unsigned int la_mask; /* what events are recorded by TP LA */ 228 unsigned int la_mask; /* what events are recorded by TP LA */
230 unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 229 unsigned short tx_modq_map; /* TX modulation scheduler queue to */
@@ -273,6 +272,7 @@ struct pci_params {
273 272
274#define CHELSIO_T4 0x4 273#define CHELSIO_T4 0x4
275#define CHELSIO_T5 0x5 274#define CHELSIO_T5 0x5
275#define CHELSIO_T6 0x6
276 276
277enum chip_type { 277enum chip_type {
278 T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1), 278 T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
@@ -284,6 +284,10 @@ enum chip_type {
284 T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1), 284 T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
285 T5_FIRST_REV = T5_A0, 285 T5_FIRST_REV = T5_A0,
286 T5_LAST_REV = T5_A1, 286 T5_LAST_REV = T5_A1,
287
288 T6_A0 = CHELSIO_CHIP_CODE(CHELSIO_T6, 0),
289 T6_FIRST_REV = T6_A0,
290 T6_LAST_REV = T6_A0,
287}; 291};
288 292
289struct devlog_params { 293struct devlog_params {
@@ -292,6 +296,15 @@ struct devlog_params {
292 u32 size; /* size of log */ 296 u32 size; /* size of log */
293}; 297};
294 298
299/* Stores chip specific parameters */
300struct arch_specific_params {
301 u8 nchan;
302 u16 mps_rplc_size;
303 u16 vfcount;
304 u32 sge_fl_db;
305 u16 mps_tcam_size;
306};
307
295struct adapter_params { 308struct adapter_params {
296 struct sge_params sge; 309 struct sge_params sge;
297 struct tp_params tp; 310 struct tp_params tp;
@@ -317,6 +330,7 @@ struct adapter_params {
317 unsigned char nports; /* # of ethernet ports */ 330 unsigned char nports; /* # of ethernet ports */
318 unsigned char portvec; 331 unsigned char portvec;
319 enum chip_type chip; /* chip code */ 332 enum chip_type chip; /* chip code */
333 struct arch_specific_params arch; /* chip specific params */
320 unsigned char offload; 334 unsigned char offload;
321 335
322 unsigned char bypass; 336 unsigned char bypass;
@@ -850,6 +864,11 @@ enum {
850 VLAN_REWRITE 864 VLAN_REWRITE
851}; 865};
852 866
867static inline int is_t6(enum chip_type chip)
868{
869 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6;
870}
871
853static inline int is_t5(enum chip_type chip) 872static inline int is_t5(enum chip_type chip)
854{ 873{
855 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5; 874 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5;
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
index 7cb423745974..3719807efddd 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
@@ -1084,41 +1084,89 @@ static inline void tcamxy2valmask(u64 x, u64 y, u8 *addr, u64 *mask)
1084 1084
1085static int mps_tcam_show(struct seq_file *seq, void *v) 1085static int mps_tcam_show(struct seq_file *seq, void *v)
1086{ 1086{
1087 if (v == SEQ_START_TOKEN) 1087 struct adapter *adap = seq->private;
1088 seq_puts(seq, "Idx Ethernet address Mask Vld Ports PF" 1088 unsigned int chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip);
1089 " VF Replication " 1089
1090 "P0 P1 P2 P3 ML\n"); 1090 if (v == SEQ_START_TOKEN) {
1091 else { 1091 if (adap->params.arch.mps_rplc_size > 128)
1092 seq_puts(seq, "Idx Ethernet address Mask "
1093 "Vld Ports PF VF "
1094 "Replication "
1095 " P0 P1 P2 P3 ML\n");
1096 else
1097 seq_puts(seq, "Idx Ethernet address Mask "
1098 "Vld Ports PF VF Replication"
1099 " P0 P1 P2 P3 ML\n");
1100 } else {
1092 u64 mask; 1101 u64 mask;
1093 u8 addr[ETH_ALEN]; 1102 u8 addr[ETH_ALEN];
1094 struct adapter *adap = seq->private; 1103 bool replicate;
1095 unsigned int idx = (uintptr_t)v - 2; 1104 unsigned int idx = (uintptr_t)v - 2;
1096 u64 tcamy = t4_read_reg64(adap, MPS_CLS_TCAM_Y_L(idx)); 1105 u64 tcamy, tcamx, val;
1097 u64 tcamx = t4_read_reg64(adap, MPS_CLS_TCAM_X_L(idx)); 1106 u32 cls_lo, cls_hi, ctl;
1098 u32 cls_lo = t4_read_reg(adap, MPS_CLS_SRAM_L(idx)); 1107 u32 rplc[8] = {0};
1099 u32 cls_hi = t4_read_reg(adap, MPS_CLS_SRAM_H(idx)); 1108
1100 u32 rplc[4] = {0, 0, 0, 0}; 1109 if (chip_ver > CHELSIO_T5) {
1110 /* CtlCmdType - 0: Read, 1: Write
1111 * CtlTcamSel - 0: TCAM0, 1: TCAM1
1112 * CtlXYBitSel- 0: Y bit, 1: X bit
1113 */
1114
1115 /* Read tcamy */
1116 ctl = CTLCMDTYPE_V(0) | CTLXYBITSEL_V(0);
1117 if (idx < 256)
1118 ctl |= CTLTCAMINDEX_V(idx) | CTLTCAMSEL_V(0);
1119 else
1120 ctl |= CTLTCAMINDEX_V(idx - 256) |
1121 CTLTCAMSEL_V(1);
1122 t4_write_reg(adap, MPS_CLS_TCAM_DATA2_CTL_A, ctl);
1123 val = t4_read_reg(adap, MPS_CLS_TCAM_DATA1_A);
1124 tcamy = DMACH_G(val) << 32;
1125 tcamy |= t4_read_reg(adap, MPS_CLS_TCAM_DATA0_A);
1126
1127 /* Read tcamx. Change the control param */
1128 ctl |= CTLXYBITSEL_V(1);
1129 t4_write_reg(adap, MPS_CLS_TCAM_DATA2_CTL_A, ctl);
1130 val = t4_read_reg(adap, MPS_CLS_TCAM_DATA1_A);
1131 tcamx = DMACH_G(val) << 32;
1132 tcamx |= t4_read_reg(adap, MPS_CLS_TCAM_DATA0_A);
1133 } else {
1134 tcamy = t4_read_reg64(adap, MPS_CLS_TCAM_Y_L(idx));
1135 tcamx = t4_read_reg64(adap, MPS_CLS_TCAM_X_L(idx));
1136 }
1137
1138 cls_lo = t4_read_reg(adap, MPS_CLS_SRAM_L(idx));
1139 cls_hi = t4_read_reg(adap, MPS_CLS_SRAM_H(idx));
1101 1140
1102 if (tcamx & tcamy) { 1141 if (tcamx & tcamy) {
1103 seq_printf(seq, "%3u -\n", idx); 1142 seq_printf(seq, "%3u -\n", idx);
1104 goto out; 1143 goto out;
1105 } 1144 }
1106 1145
1107 if (cls_lo & REPLICATE_F) { 1146 rplc[0] = rplc[1] = rplc[2] = rplc[3] = 0;
1147 if (chip_ver > CHELSIO_T5)
1148 replicate = (cls_lo & T6_REPLICATE_F);
1149 else
1150 replicate = (cls_lo & REPLICATE_F);
1151
1152 if (replicate) {
1108 struct fw_ldst_cmd ldst_cmd; 1153 struct fw_ldst_cmd ldst_cmd;
1109 int ret; 1154 int ret;
1155 struct fw_ldst_mps_rplc mps_rplc;
1156 u32 ldst_addrspc;
1110 1157
1111 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 1158 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
1159 ldst_addrspc =
1160 FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MPS);
1112 ldst_cmd.op_to_addrspace = 1161 ldst_cmd.op_to_addrspace =
1113 htonl(FW_CMD_OP_V(FW_LDST_CMD) | 1162 htonl(FW_CMD_OP_V(FW_LDST_CMD) |
1114 FW_CMD_REQUEST_F | 1163 FW_CMD_REQUEST_F |
1115 FW_CMD_READ_F | 1164 FW_CMD_READ_F |
1116 FW_LDST_CMD_ADDRSPACE_V( 1165 ldst_addrspc);
1117 FW_LDST_ADDRSPC_MPS));
1118 ldst_cmd.cycles_to_len16 = htonl(FW_LEN16(ldst_cmd)); 1166 ldst_cmd.cycles_to_len16 = htonl(FW_LEN16(ldst_cmd));
1119 ldst_cmd.u.mps.fid_ctl = 1167 ldst_cmd.u.mps.rplc.fid_idx =
1120 htons(FW_LDST_CMD_FID_V(FW_LDST_MPS_RPLC) | 1168 htons(FW_LDST_CMD_FID_V(FW_LDST_MPS_RPLC) |
1121 FW_LDST_CMD_CTL_V(idx)); 1169 FW_LDST_CMD_IDX_V(idx));
1122 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, 1170 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd,
1123 sizeof(ldst_cmd), &ldst_cmd); 1171 sizeof(ldst_cmd), &ldst_cmd);
1124 if (ret) 1172 if (ret)
@@ -1126,30 +1174,69 @@ static int mps_tcam_show(struct seq_file *seq, void *v)
1126 "replication map for idx %d: %d\n", 1174 "replication map for idx %d: %d\n",
1127 idx, -ret); 1175 idx, -ret);
1128 else { 1176 else {
1129 rplc[0] = ntohl(ldst_cmd.u.mps.rplc31_0); 1177 mps_rplc = ldst_cmd.u.mps.rplc;
1130 rplc[1] = ntohl(ldst_cmd.u.mps.rplc63_32); 1178 rplc[0] = ntohl(mps_rplc.rplc31_0);
1131 rplc[2] = ntohl(ldst_cmd.u.mps.rplc95_64); 1179 rplc[1] = ntohl(mps_rplc.rplc63_32);
1132 rplc[3] = ntohl(ldst_cmd.u.mps.rplc127_96); 1180 rplc[2] = ntohl(mps_rplc.rplc95_64);
1181 rplc[3] = ntohl(mps_rplc.rplc127_96);
1182 if (adap->params.arch.mps_rplc_size > 128) {
1183 rplc[4] = ntohl(mps_rplc.rplc159_128);
1184 rplc[5] = ntohl(mps_rplc.rplc191_160);
1185 rplc[6] = ntohl(mps_rplc.rplc223_192);
1186 rplc[7] = ntohl(mps_rplc.rplc255_224);
1187 }
1133 } 1188 }
1134 } 1189 }
1135 1190
1136 tcamxy2valmask(tcamx, tcamy, addr, &mask); 1191 tcamxy2valmask(tcamx, tcamy, addr, &mask);
1137 seq_printf(seq, "%3u %02x:%02x:%02x:%02x:%02x:%02x %012llx" 1192 if (chip_ver > CHELSIO_T5)
1138 "%3c %#x%4u%4d", 1193 seq_printf(seq, "%3u %02x:%02x:%02x:%02x:%02x:%02x "
1139 idx, addr[0], addr[1], addr[2], addr[3], addr[4], 1194 "%012llx%3c %#x%4u%4d",
1140 addr[5], (unsigned long long)mask, 1195 idx, addr[0], addr[1], addr[2], addr[3],
1141 (cls_lo & SRAM_VLD_F) ? 'Y' : 'N', PORTMAP_G(cls_hi), 1196 addr[4], addr[5], (unsigned long long)mask,
1142 PF_G(cls_lo), 1197 (cls_lo & T6_SRAM_VLD_F) ? 'Y' : 'N',
1143 (cls_lo & VF_VALID_F) ? VF_G(cls_lo) : -1); 1198 PORTMAP_G(cls_hi),
1144 if (cls_lo & REPLICATE_F) 1199 T6_PF_G(cls_lo),
1145 seq_printf(seq, " %08x %08x %08x %08x", 1200 (cls_lo & T6_VF_VALID_F) ?
1146 rplc[3], rplc[2], rplc[1], rplc[0]); 1201 T6_VF_G(cls_lo) : -1);
1147 else 1202 else
1148 seq_printf(seq, "%36c", ' '); 1203 seq_printf(seq, "%3u %02x:%02x:%02x:%02x:%02x:%02x "
1149 seq_printf(seq, "%4u%3u%3u%3u %#x\n", 1204 "%012llx%3c %#x%4u%4d",
1150 SRAM_PRIO0_G(cls_lo), SRAM_PRIO1_G(cls_lo), 1205 idx, addr[0], addr[1], addr[2], addr[3],
1151 SRAM_PRIO2_G(cls_lo), SRAM_PRIO3_G(cls_lo), 1206 addr[4], addr[5], (unsigned long long)mask,
1152 (cls_lo >> MULTILISTEN0_S) & 0xf); 1207 (cls_lo & SRAM_VLD_F) ? 'Y' : 'N',
1208 PORTMAP_G(cls_hi),
1209 PF_G(cls_lo),
1210 (cls_lo & VF_VALID_F) ? VF_G(cls_lo) : -1);
1211
1212 if (replicate) {
1213 if (adap->params.arch.mps_rplc_size > 128)
1214 seq_printf(seq, " %08x %08x %08x %08x "
1215 "%08x %08x %08x %08x",
1216 rplc[7], rplc[6], rplc[5], rplc[4],
1217 rplc[3], rplc[2], rplc[1], rplc[0]);
1218 else
1219 seq_printf(seq, " %08x %08x %08x %08x",
1220 rplc[3], rplc[2], rplc[1], rplc[0]);
1221 } else {
1222 if (adap->params.arch.mps_rplc_size > 128)
1223 seq_printf(seq, "%72c", ' ');
1224 else
1225 seq_printf(seq, "%36c", ' ');
1226 }
1227
1228 if (chip_ver > CHELSIO_T5)
1229 seq_printf(seq, "%4u%3u%3u%3u %#x\n",
1230 T6_SRAM_PRIO0_G(cls_lo),
1231 T6_SRAM_PRIO1_G(cls_lo),
1232 T6_SRAM_PRIO2_G(cls_lo),
1233 T6_SRAM_PRIO3_G(cls_lo),
1234 (cls_lo >> T6_MULTILISTEN0_S) & 0xf);
1235 else
1236 seq_printf(seq, "%4u%3u%3u%3u %#x\n",
1237 SRAM_PRIO0_G(cls_lo), SRAM_PRIO1_G(cls_lo),
1238 SRAM_PRIO2_G(cls_lo), SRAM_PRIO3_G(cls_lo),
1239 (cls_lo >> MULTILISTEN0_S) & 0xf);
1153 } 1240 }
1154out: return 0; 1241out: return 0;
1155} 1242}
@@ -1416,6 +1503,9 @@ static int rss_config_show(struct seq_file *seq, void *v)
1416 seq_printf(seq, " HashDelay: %3d\n", HASHDELAY_G(rssconf)); 1503 seq_printf(seq, " HashDelay: %3d\n", HASHDELAY_G(rssconf));
1417 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) 1504 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
1418 seq_printf(seq, " VfWrAddr: %3d\n", VFWRADDR_G(rssconf)); 1505 seq_printf(seq, " VfWrAddr: %3d\n", VFWRADDR_G(rssconf));
1506 else
1507 seq_printf(seq, " VfWrAddr: %3d\n",
1508 T6_VFWRADDR_G(rssconf));
1419 seq_printf(seq, " KeyMode: %s\n", keymode[KEYMODE_G(rssconf)]); 1509 seq_printf(seq, " KeyMode: %s\n", keymode[KEYMODE_G(rssconf)]);
1420 seq_printf(seq, " VfWrEn: %3s\n", yesno(rssconf & VFWREN_F)); 1510 seq_printf(seq, " VfWrEn: %3s\n", yesno(rssconf & VFWREN_F));
1421 seq_printf(seq, " KeyWrEn: %3s\n", yesno(rssconf & KEYWREN_F)); 1511 seq_printf(seq, " KeyWrEn: %3s\n", yesno(rssconf & KEYWREN_F));
@@ -1634,14 +1724,14 @@ static int rss_vf_config_open(struct inode *inode, struct file *file)
1634 struct adapter *adapter = inode->i_private; 1724 struct adapter *adapter = inode->i_private;
1635 struct seq_tab *p; 1725 struct seq_tab *p;
1636 struct rss_vf_conf *vfconf; 1726 struct rss_vf_conf *vfconf;
1637 int vf; 1727 int vf, vfcount = adapter->params.arch.vfcount;
1638 1728
1639 p = seq_open_tab(file, 128, sizeof(*vfconf), 1, rss_vf_config_show); 1729 p = seq_open_tab(file, vfcount, sizeof(*vfconf), 1, rss_vf_config_show);
1640 if (!p) 1730 if (!p)
1641 return -ENOMEM; 1731 return -ENOMEM;
1642 1732
1643 vfconf = (struct rss_vf_conf *)p->data; 1733 vfconf = (struct rss_vf_conf *)p->data;
1644 for (vf = 0; vf < 128; vf++) { 1734 for (vf = 0; vf < vfcount; vf++) {
1645 t4_read_rss_vf_config(adapter, vf, &vfconf[vf].rss_vf_vfl, 1735 t4_read_rss_vf_config(adapter, vf, &vfconf[vf].rss_vf_vfl,
1646 &vfconf[vf].rss_vf_vfh); 1736 &vfconf[vf].rss_vf_vfh);
1647 } 1737 }
@@ -2033,7 +2123,7 @@ void add_debugfs_files(struct adapter *adap,
2033int t4_setup_debugfs(struct adapter *adap) 2123int t4_setup_debugfs(struct adapter *adap)
2034{ 2124{
2035 int i; 2125 int i;
2036 u32 size; 2126 u32 size = 0;
2037 struct dentry *de; 2127 struct dentry *de;
2038 2128
2039 static struct t4_debugfs_entry t4_debugfs_files[] = { 2129 static struct t4_debugfs_entry t4_debugfs_files[] = {
@@ -2104,12 +2194,7 @@ int t4_setup_debugfs(struct adapter *adap)
2104 size = t4_read_reg(adap, MA_EDRAM1_BAR_A); 2194 size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
2105 add_debugfs_mem(adap, "edc1", MEM_EDC1, EDRAM1_SIZE_G(size)); 2195 add_debugfs_mem(adap, "edc1", MEM_EDC1, EDRAM1_SIZE_G(size));
2106 } 2196 }
2107 if (is_t4(adap->params.chip)) { 2197 if (is_t5(adap->params.chip)) {
2108 size = t4_read_reg(adap, MA_EXT_MEMORY_BAR_A);
2109 if (i & EXT_MEM_ENABLE_F)
2110 add_debugfs_mem(adap, "mc", MEM_MC,
2111 EXT_MEM_SIZE_G(size));
2112 } else {
2113 if (i & EXT_MEM0_ENABLE_F) { 2198 if (i & EXT_MEM0_ENABLE_F) {
2114 size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A); 2199 size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
2115 add_debugfs_mem(adap, "mc0", MEM_MC0, 2200 add_debugfs_mem(adap, "mc0", MEM_MC0,
@@ -2120,6 +2205,11 @@ int t4_setup_debugfs(struct adapter *adap)
2120 add_debugfs_mem(adap, "mc1", MEM_MC1, 2205 add_debugfs_mem(adap, "mc1", MEM_MC1,
2121 EXT_MEM1_SIZE_G(size)); 2206 EXT_MEM1_SIZE_G(size));
2122 } 2207 }
2208 } else {
2209 if (i & EXT_MEM_ENABLE_F)
2210 size = t4_read_reg(adap, MA_EXT_MEMORY_BAR_A);
2211 add_debugfs_mem(adap, "mc", MEM_MC,
2212 EXT_MEM_SIZE_G(size));
2123 } 2213 }
2124 2214
2125 de = debugfs_create_file_size("flash", S_IRUSR, adap->debugfs_root, adap, 2215 de = debugfs_create_file_size("flash", S_IRUSR, adap->debugfs_root, adap,
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
index 974b27ce6a70..a589591e5b63 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
@@ -135,8 +135,10 @@ struct filter_entry {
135 135
136#define FW4_FNAME "cxgb4/t4fw.bin" 136#define FW4_FNAME "cxgb4/t4fw.bin"
137#define FW5_FNAME "cxgb4/t5fw.bin" 137#define FW5_FNAME "cxgb4/t5fw.bin"
138#define FW6_FNAME "cxgb4/t6fw.bin"
138#define FW4_CFNAME "cxgb4/t4-config.txt" 139#define FW4_CFNAME "cxgb4/t4-config.txt"
139#define FW5_CFNAME "cxgb4/t5-config.txt" 140#define FW5_CFNAME "cxgb4/t5-config.txt"
141#define FW6_CFNAME "cxgb4/t6-config.txt"
140#define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld" 142#define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld"
141#define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin" 143#define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin"
142#define PHY_AQ1202_DEVICEID 0x4409 144#define PHY_AQ1202_DEVICEID 0x4409
@@ -1721,7 +1723,7 @@ static int tid_init(struct tid_info *t)
1721 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids); 1723 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
1722 /* Reserve stid 0 for T4/T5 adapters */ 1724 /* Reserve stid 0 for T4/T5 adapters */
1723 if (!t->stid_base && 1725 if (!t->stid_base &&
1724 (is_t4(adap->params.chip) || is_t5(adap->params.chip))) 1726 (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5))
1725 __set_bit(0, t->stid_bmap); 1727 __set_bit(0, t->stid_bmap);
1726 1728
1727 return 0; 1729 return 0;
@@ -2108,10 +2110,7 @@ int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
2108 if (offset < mc0_end) { 2110 if (offset < mc0_end) {
2109 memtype = MEM_MC0; 2111 memtype = MEM_MC0;
2110 memaddr = offset - edc1_end; 2112 memaddr = offset - edc1_end;
2111 } else if (is_t4(adap->params.chip)) { 2113 } else if (is_t5(adap->params.chip)) {
2112 /* T4 only has a single memory channel */
2113 goto err;
2114 } else {
2115 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A); 2114 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
2116 mc1_size = EXT_MEM1_SIZE_G(size) << 20; 2115 mc1_size = EXT_MEM1_SIZE_G(size) << 20;
2117 mc1_end = mc0_end + mc1_size; 2116 mc1_end = mc0_end + mc1_size;
@@ -2122,6 +2121,9 @@ int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
2122 /* offset beyond the end of any memory */ 2121 /* offset beyond the end of any memory */
2123 goto err; 2122 goto err;
2124 } 2123 }
2124 } else {
2125 /* T4/T6 only has a single memory channel */
2126 goto err;
2125 } 2127 }
2126 } 2128 }
2127 2129
@@ -2286,9 +2288,13 @@ static void process_db_full(struct work_struct *work)
2286 drain_db_fifo(adap, dbfifo_drain_delay); 2288 drain_db_fifo(adap, dbfifo_drain_delay);
2287 enable_dbs(adap); 2289 enable_dbs(adap);
2288 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY); 2290 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2289 t4_set_reg_field(adap, SGE_INT_ENABLE3_A, 2291 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2290 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 2292 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2291 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F); 2293 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F,
2294 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F);
2295 else
2296 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2297 DBFIFO_LP_INT_F, DBFIFO_LP_INT_F);
2292} 2298}
2293 2299
2294static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q) 2300static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
@@ -2350,7 +2356,7 @@ static void process_db_drop(struct work_struct *work)
2350 drain_db_fifo(adap, dbfifo_drain_delay); 2356 drain_db_fifo(adap, dbfifo_drain_delay);
2351 enable_dbs(adap); 2357 enable_dbs(adap);
2352 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY); 2358 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2353 } else { 2359 } else if (is_t5(adap->params.chip)) {
2354 u32 dropped_db = t4_read_reg(adap, 0x010ac); 2360 u32 dropped_db = t4_read_reg(adap, 0x010ac);
2355 u16 qid = (dropped_db >> 15) & 0x1ffff; 2361 u16 qid = (dropped_db >> 15) & 0x1ffff;
2356 u16 pidx_inc = dropped_db & 0x1fff; 2362 u16 pidx_inc = dropped_db & 0x1fff;
@@ -2371,7 +2377,8 @@ static void process_db_drop(struct work_struct *work)
2371 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15); 2377 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
2372 } 2378 }
2373 2379
2374 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0); 2380 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2381 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0);
2375} 2382}
2376 2383
2377void t4_db_full(struct adapter *adap) 2384void t4_db_full(struct adapter *adap)
@@ -3390,6 +3397,9 @@ static int adap_init0_config(struct adapter *adapter, int reset)
3390 case CHELSIO_T5: 3397 case CHELSIO_T5:
3391 fw_config_file = FW5_CFNAME; 3398 fw_config_file = FW5_CFNAME;
3392 break; 3399 break;
3400 case CHELSIO_T6:
3401 fw_config_file = FW6_CFNAME;
3402 break;
3393 default: 3403 default:
3394 dev_err(adapter->pdev_dev, "Device %d is not supported\n", 3404 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
3395 adapter->pdev->device); 3405 adapter->pdev->device);
@@ -3586,7 +3596,24 @@ static struct fw_info fw_info_array[] = {
3586 .intfver_iscsi = FW_INTFVER(T5, ISCSI), 3596 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
3587 .intfver_fcoe = FW_INTFVER(T5, FCOE), 3597 .intfver_fcoe = FW_INTFVER(T5, FCOE),
3588 }, 3598 },
3599 }, {
3600 .chip = CHELSIO_T6,
3601 .fs_name = FW6_CFNAME,
3602 .fw_mod_name = FW6_FNAME,
3603 .fw_hdr = {
3604 .chip = FW_HDR_CHIP_T6,
3605 .fw_ver = __cpu_to_be32(FW_VERSION(T6)),
3606 .intfver_nic = FW_INTFVER(T6, NIC),
3607 .intfver_vnic = FW_INTFVER(T6, VNIC),
3608 .intfver_ofld = FW_INTFVER(T6, OFLD),
3609 .intfver_ri = FW_INTFVER(T6, RI),
3610 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
3611 .intfver_iscsi = FW_INTFVER(T6, ISCSI),
3612 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
3613 .intfver_fcoe = FW_INTFVER(T6, FCOE),
3614 },
3589 } 3615 }
3616
3590}; 3617};
3591 3618
3592static struct fw_info *find_fw_info(int chip) 3619static struct fw_info *find_fw_info(int chip)
diff --git a/drivers/net/ethernet/chelsio/cxgb4/sge.c b/drivers/net/ethernet/chelsio/cxgb4/sge.c
index f9c889e14634..6b7c37fd0252 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/sge.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/sge.c
@@ -522,14 +522,13 @@ static void unmap_rx_buf(struct adapter *adap, struct sge_fl *q)
522 522
523static inline void ring_fl_db(struct adapter *adap, struct sge_fl *q) 523static inline void ring_fl_db(struct adapter *adap, struct sge_fl *q)
524{ 524{
525 u32 val;
526 if (q->pend_cred >= 8) { 525 if (q->pend_cred >= 8) {
526 u32 val = adap->params.arch.sge_fl_db;
527
527 if (is_t4(adap->params.chip)) 528 if (is_t4(adap->params.chip))
528 val = PIDX_V(q->pend_cred / 8); 529 val |= PIDX_V(q->pend_cred / 8);
529 else 530 else
530 val = PIDX_T5_V(q->pend_cred / 8) | 531 val |= PIDX_T5_V(q->pend_cred / 8);
531 DBTYPE_F;
532 val |= DBPRIO_F;
533 532
534 /* Make sure all memory writes to the Free List queue are 533 /* Make sure all memory writes to the Free List queue are
535 * committed before we tell the hardware about them. 534 * committed before we tell the hardware about them.
@@ -1034,7 +1033,7 @@ static void inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q,
1034 * Figure out what HW csum a packet wants and return the appropriate control 1033 * Figure out what HW csum a packet wants and return the appropriate control
1035 * bits. 1034 * bits.
1036 */ 1035 */
1037static u64 hwcsum(const struct sk_buff *skb) 1036static u64 hwcsum(enum chip_type chip, const struct sk_buff *skb)
1038{ 1037{
1039 int csum_type; 1038 int csum_type;
1040 const struct iphdr *iph = ip_hdr(skb); 1039 const struct iphdr *iph = ip_hdr(skb);
@@ -1065,11 +1064,16 @@ nocsum: /*
1065 goto nocsum; 1064 goto nocsum;
1066 } 1065 }
1067 1066
1068 if (likely(csum_type >= TX_CSUM_TCPIP)) 1067 if (likely(csum_type >= TX_CSUM_TCPIP)) {
1069 return TXPKT_CSUM_TYPE_V(csum_type) | 1068 u64 hdr_len = TXPKT_IPHDR_LEN_V(skb_network_header_len(skb));
1070 TXPKT_IPHDR_LEN_V(skb_network_header_len(skb)) | 1069 int eth_hdr_len = skb_network_offset(skb) - ETH_HLEN;
1071 TXPKT_ETHHDR_LEN_V(skb_network_offset(skb) - ETH_HLEN); 1070
1072 else { 1071 if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5)
1072 hdr_len |= TXPKT_ETHHDR_LEN_V(eth_hdr_len);
1073 else
1074 hdr_len |= T6_TXPKT_ETHHDR_LEN_V(eth_hdr_len);
1075 return TXPKT_CSUM_TYPE_V(csum_type) | hdr_len;
1076 } else {
1073 int start = skb_transport_offset(skb); 1077 int start = skb_transport_offset(skb);
1074 1078
1075 return TXPKT_CSUM_TYPE_V(csum_type) | 1079 return TXPKT_CSUM_TYPE_V(csum_type) |
@@ -1237,9 +1241,15 @@ out_free: dev_kfree_skb_any(skb);
1237 else 1241 else
1238 lso->c.len = htonl(LSO_T5_XFER_SIZE_V(skb->len)); 1242 lso->c.len = htonl(LSO_T5_XFER_SIZE_V(skb->len));
1239 cpl = (void *)(lso + 1); 1243 cpl = (void *)(lso + 1);
1240 cntrl = TXPKT_CSUM_TYPE_V(v6 ? TX_CSUM_TCPIP6 : TX_CSUM_TCPIP) | 1244
1241 TXPKT_IPHDR_LEN_V(l3hdr_len) | 1245 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
1242 TXPKT_ETHHDR_LEN_V(eth_xtra_len); 1246 cntrl = TXPKT_ETHHDR_LEN_V(eth_xtra_len);
1247 else
1248 cntrl = T6_TXPKT_ETHHDR_LEN_V(eth_xtra_len);
1249
1250 cntrl |= TXPKT_CSUM_TYPE_V(v6 ?
1251 TX_CSUM_TCPIP6 : TX_CSUM_TCPIP) |
1252 TXPKT_IPHDR_LEN_V(l3hdr_len);
1243 q->tso++; 1253 q->tso++;
1244 q->tx_cso += ssi->gso_segs; 1254 q->tx_cso += ssi->gso_segs;
1245 } else { 1255 } else {
@@ -1248,7 +1258,8 @@ out_free: dev_kfree_skb_any(skb);
1248 FW_WR_IMMDLEN_V(len)); 1258 FW_WR_IMMDLEN_V(len));
1249 cpl = (void *)(wr + 1); 1259 cpl = (void *)(wr + 1);
1250 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1260 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1251 cntrl = hwcsum(skb) | TXPKT_IPCSUM_DIS_F; 1261 cntrl = hwcsum(adap->params.chip, skb) |
1262 TXPKT_IPCSUM_DIS_F;
1252 q->tx_cso++; 1263 q->tx_cso++;
1253 } 1264 }
1254 } 1265 }
@@ -2440,6 +2451,8 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
2440 c.iqns_to_fl0congen = htonl(FW_IQ_CMD_IQFLINTCONGEN_F); 2451 c.iqns_to_fl0congen = htonl(FW_IQ_CMD_IQFLINTCONGEN_F);
2441 2452
2442 if (fl) { 2453 if (fl) {
2454 enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
2455
2443 /* Allocate the ring for the hardware free list (with space 2456 /* Allocate the ring for the hardware free list (with space
2444 * for its status page) along with the associated software 2457 * for its status page) along with the associated software
2445 * descriptor ring. The free list size needs to be a multiple 2458 * descriptor ring. The free list size needs to be a multiple
@@ -2468,7 +2481,9 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
2468 FW_IQ_CMD_FL0CONGEN_F); 2481 FW_IQ_CMD_FL0CONGEN_F);
2469 c.fl0dcaen_to_fl0cidxfthresh = 2482 c.fl0dcaen_to_fl0cidxfthresh =
2470 htons(FW_IQ_CMD_FL0FBMIN_V(FETCHBURSTMIN_64B_X) | 2483 htons(FW_IQ_CMD_FL0FBMIN_V(FETCHBURSTMIN_64B_X) |
2471 FW_IQ_CMD_FL0FBMAX_V(FETCHBURSTMAX_512B_X)); 2484 FW_IQ_CMD_FL0FBMAX_V((chip <= CHELSIO_T5) ?
2485 FETCHBURSTMAX_512B_X :
2486 FETCHBURSTMAX_256B_X));
2472 c.fl0size = htons(flsz); 2487 c.fl0size = htons(flsz);
2473 c.fl0addr = cpu_to_be64(fl->addr); 2488 c.fl0addr = cpu_to_be64(fl->addr);
2474 } 2489 }
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
index 36a858c24305..35a44db29347 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
@@ -150,7 +150,12 @@ void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
150 */ 150 */
151void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val) 151void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
152{ 152{
153 u32 req = ENABLE_F | FUNCTION_V(adap->pf) | REGISTER_V(reg); 153 u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg);
154
155 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
156 req |= ENABLE_F;
157 else
158 req |= T6_ENABLE_F;
154 159
155 if (is_t4(adap->params.chip)) 160 if (is_t4(adap->params.chip))
156 req |= LOCALCFG_F; 161 req |= LOCALCFG_F;
@@ -381,9 +386,8 @@ int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
381 /* Offset into the region of memory which is being accessed 386 /* Offset into the region of memory which is being accessed
382 * MEM_EDC0 = 0 387 * MEM_EDC0 = 0
383 * MEM_EDC1 = 1 388 * MEM_EDC1 = 1
384 * MEM_MC = 2 -- T4 389 * MEM_MC = 2 -- MEM_MC for chips with only 1 memory controller
385 * MEM_MC0 = 2 -- For T5 390 * MEM_MC1 = 3 -- for chips with 2 memory controllers (e.g. T5)
386 * MEM_MC1 = 3 -- For T5
387 */ 391 */
388 edc_size = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A)); 392 edc_size = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
389 if (mtype != MEM_MC1) 393 if (mtype != MEM_MC1)
@@ -634,6 +638,7 @@ unsigned int t4_get_regs_len(struct adapter *adapter)
634 return T4_REGMAP_SIZE; 638 return T4_REGMAP_SIZE;
635 639
636 case CHELSIO_T5: 640 case CHELSIO_T5:
641 case CHELSIO_T6:
637 return T5_REGMAP_SIZE; 642 return T5_REGMAP_SIZE;
638 } 643 }
639 644
@@ -1316,6 +1321,344 @@ void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
1316 0x51300, 0x51308, 1321 0x51300, 0x51308,
1317 }; 1322 };
1318 1323
1324 static const unsigned int t6_reg_ranges[] = {
1325 0x1008, 0x114c,
1326 0x1180, 0x11b4,
1327 0x11fc, 0x1250,
1328 0x1280, 0x133c,
1329 0x1800, 0x18fc,
1330 0x3000, 0x302c,
1331 0x3060, 0x30d8,
1332 0x30e0, 0x30fc,
1333 0x3140, 0x357c,
1334 0x35a8, 0x35cc,
1335 0x35ec, 0x35ec,
1336 0x3600, 0x5624,
1337 0x56cc, 0x575c,
1338 0x580c, 0x5814,
1339 0x5890, 0x58bc,
1340 0x5940, 0x595c,
1341 0x5980, 0x598c,
1342 0x59b0, 0x59dc,
1343 0x59fc, 0x5a18,
1344 0x5a60, 0x5a6c,
1345 0x5a80, 0x5a9c,
1346 0x5b94, 0x5bfc,
1347 0x5c10, 0x5ec0,
1348 0x5ec8, 0x5ec8,
1349 0x6000, 0x6040,
1350 0x6058, 0x6154,
1351 0x7700, 0x7798,
1352 0x77c0, 0x7880,
1353 0x78cc, 0x78fc,
1354 0x7b00, 0x7c54,
1355 0x7d00, 0x7efc,
1356 0x8dc0, 0x8de0,
1357 0x8df8, 0x8e84,
1358 0x8ea0, 0x8f88,
1359 0x8fb8, 0x911c,
1360 0x9400, 0x9470,
1361 0x9600, 0x971c,
1362 0x9800, 0x9808,
1363 0x9820, 0x983c,
1364 0x9850, 0x9864,
1365 0x9c00, 0x9c6c,
1366 0x9c80, 0x9cec,
1367 0x9d00, 0x9d6c,
1368 0x9d80, 0x9dec,
1369 0x9e00, 0x9e6c,
1370 0x9e80, 0x9eec,
1371 0x9f00, 0x9f6c,
1372 0x9f80, 0xa020,
1373 0xd004, 0xd03c,
1374 0xdfc0, 0xdfe0,
1375 0xe000, 0xf008,
1376 0x11000, 0x11014,
1377 0x11048, 0x11110,
1378 0x11118, 0x1117c,
1379 0x11190, 0x11260,
1380 0x11300, 0x1130c,
1381 0x12000, 0x1205c,
1382 0x19040, 0x1906c,
1383 0x19078, 0x19080,
1384 0x1908c, 0x19124,
1385 0x19150, 0x191b0,
1386 0x191d0, 0x191e8,
1387 0x19238, 0x192b8,
1388 0x193f8, 0x19474,
1389 0x19490, 0x194cc,
1390 0x194f0, 0x194f8,
1391 0x19c00, 0x19c80,
1392 0x19c94, 0x19cbc,
1393 0x19ce4, 0x19d28,
1394 0x19d50, 0x19d78,
1395 0x19d94, 0x19dc8,
1396 0x19df0, 0x19e10,
1397 0x19e50, 0x19e6c,
1398 0x19ea0, 0x19f34,
1399 0x19f40, 0x19f50,
1400 0x19f90, 0x19fac,
1401 0x19fc4, 0x19fe4,
1402 0x1a000, 0x1a06c,
1403 0x1a0b0, 0x1a120,
1404 0x1a128, 0x1a138,
1405 0x1a190, 0x1a1c4,
1406 0x1a1fc, 0x1a1fc,
1407 0x1e008, 0x1e00c,
1408 0x1e040, 0x1e04c,
1409 0x1e284, 0x1e290,
1410 0x1e2c0, 0x1e2c0,
1411 0x1e2e0, 0x1e2e0,
1412 0x1e300, 0x1e384,
1413 0x1e3c0, 0x1e3c8,
1414 0x1e408, 0x1e40c,
1415 0x1e440, 0x1e44c,
1416 0x1e684, 0x1e690,
1417 0x1e6c0, 0x1e6c0,
1418 0x1e6e0, 0x1e6e0,
1419 0x1e700, 0x1e784,
1420 0x1e7c0, 0x1e7c8,
1421 0x1e808, 0x1e80c,
1422 0x1e840, 0x1e84c,
1423 0x1ea84, 0x1ea90,
1424 0x1eac0, 0x1eac0,
1425 0x1eae0, 0x1eae0,
1426 0x1eb00, 0x1eb84,
1427 0x1ebc0, 0x1ebc8,
1428 0x1ec08, 0x1ec0c,
1429 0x1ec40, 0x1ec4c,
1430 0x1ee84, 0x1ee90,
1431 0x1eec0, 0x1eec0,
1432 0x1eee0, 0x1eee0,
1433 0x1ef00, 0x1ef84,
1434 0x1efc0, 0x1efc8,
1435 0x1f008, 0x1f00c,
1436 0x1f040, 0x1f04c,
1437 0x1f284, 0x1f290,
1438 0x1f2c0, 0x1f2c0,
1439 0x1f2e0, 0x1f2e0,
1440 0x1f300, 0x1f384,
1441 0x1f3c0, 0x1f3c8,
1442 0x1f408, 0x1f40c,
1443 0x1f440, 0x1f44c,
1444 0x1f684, 0x1f690,
1445 0x1f6c0, 0x1f6c0,
1446 0x1f6e0, 0x1f6e0,
1447 0x1f700, 0x1f784,
1448 0x1f7c0, 0x1f7c8,
1449 0x1f808, 0x1f80c,
1450 0x1f840, 0x1f84c,
1451 0x1fa84, 0x1fa90,
1452 0x1fac0, 0x1fac0,
1453 0x1fae0, 0x1fae0,
1454 0x1fb00, 0x1fb84,
1455 0x1fbc0, 0x1fbc8,
1456 0x1fc08, 0x1fc0c,
1457 0x1fc40, 0x1fc4c,
1458 0x1fe84, 0x1fe90,
1459 0x1fec0, 0x1fec0,
1460 0x1fee0, 0x1fee0,
1461 0x1ff00, 0x1ff84,
1462 0x1ffc0, 0x1ffc8,
1463 0x30000, 0x30070,
1464 0x30100, 0x3015c,
1465 0x30190, 0x301d0,
1466 0x30200, 0x30318,
1467 0x30400, 0x3052c,
1468 0x30540, 0x3061c,
1469 0x30800, 0x3088c,
1470 0x308c0, 0x30908,
1471 0x30910, 0x309b8,
1472 0x30a00, 0x30a04,
1473 0x30a0c, 0x30a2c,
1474 0x30a44, 0x30a50,
1475 0x30a74, 0x30c24,
1476 0x30d00, 0x30d3c,
1477 0x30d44, 0x30d7c,
1478 0x30de0, 0x30de0,
1479 0x30e00, 0x30ed4,
1480 0x30f00, 0x30fa4,
1481 0x30fc0, 0x30fc4,
1482 0x31000, 0x31004,
1483 0x31080, 0x310fc,
1484 0x31208, 0x31220,
1485 0x3123c, 0x31254,
1486 0x31300, 0x31300,
1487 0x31308, 0x3131c,
1488 0x31338, 0x3133c,
1489 0x31380, 0x31380,
1490 0x31388, 0x313a8,
1491 0x313b4, 0x313b4,
1492 0x31400, 0x31420,
1493 0x31438, 0x3143c,
1494 0x31480, 0x31480,
1495 0x314a8, 0x314a8,
1496 0x314b0, 0x314b4,
1497 0x314c8, 0x314d4,
1498 0x31a40, 0x31a4c,
1499 0x31af0, 0x31b20,
1500 0x31b38, 0x31b3c,
1501 0x31b80, 0x31b80,
1502 0x31ba8, 0x31ba8,
1503 0x31bb0, 0x31bb4,
1504 0x31bc8, 0x31bd4,
1505 0x32140, 0x3218c,
1506 0x321f0, 0x32200,
1507 0x32218, 0x32218,
1508 0x32400, 0x32400,
1509 0x32408, 0x3241c,
1510 0x32618, 0x32620,
1511 0x32664, 0x32664,
1512 0x326a8, 0x326a8,
1513 0x326ec, 0x326ec,
1514 0x32a00, 0x32abc,
1515 0x32b00, 0x32b78,
1516 0x32c00, 0x32c00,
1517 0x32c08, 0x32c3c,
1518 0x32e00, 0x32e2c,
1519 0x32f00, 0x32f2c,
1520 0x33000, 0x330ac,
1521 0x330c0, 0x331ac,
1522 0x331c0, 0x332c4,
1523 0x332e4, 0x333c4,
1524 0x333e4, 0x334ac,
1525 0x334c0, 0x335ac,
1526 0x335c0, 0x336c4,
1527 0x336e4, 0x337c4,
1528 0x337e4, 0x337fc,
1529 0x33814, 0x33814,
1530 0x33854, 0x33868,
1531 0x33880, 0x3388c,
1532 0x338c0, 0x338d0,
1533 0x338e8, 0x338ec,
1534 0x33900, 0x339ac,
1535 0x339c0, 0x33ac4,
1536 0x33ae4, 0x33b10,
1537 0x33b24, 0x33b50,
1538 0x33bf0, 0x33c10,
1539 0x33c24, 0x33c50,
1540 0x33cf0, 0x33cfc,
1541 0x34000, 0x34070,
1542 0x34100, 0x3415c,
1543 0x34190, 0x341d0,
1544 0x34200, 0x34318,
1545 0x34400, 0x3452c,
1546 0x34540, 0x3461c,
1547 0x34800, 0x3488c,
1548 0x348c0, 0x34908,
1549 0x34910, 0x349b8,
1550 0x34a00, 0x34a04,
1551 0x34a0c, 0x34a2c,
1552 0x34a44, 0x34a50,
1553 0x34a74, 0x34c24,
1554 0x34d00, 0x34d3c,
1555 0x34d44, 0x34d7c,
1556 0x34de0, 0x34de0,
1557 0x34e00, 0x34ed4,
1558 0x34f00, 0x34fa4,
1559 0x34fc0, 0x34fc4,
1560 0x35000, 0x35004,
1561 0x35080, 0x350fc,
1562 0x35208, 0x35220,
1563 0x3523c, 0x35254,
1564 0x35300, 0x35300,
1565 0x35308, 0x3531c,
1566 0x35338, 0x3533c,
1567 0x35380, 0x35380,
1568 0x35388, 0x353a8,
1569 0x353b4, 0x353b4,
1570 0x35400, 0x35420,
1571 0x35438, 0x3543c,
1572 0x35480, 0x35480,
1573 0x354a8, 0x354a8,
1574 0x354b0, 0x354b4,
1575 0x354c8, 0x354d4,
1576 0x35a40, 0x35a4c,
1577 0x35af0, 0x35b20,
1578 0x35b38, 0x35b3c,
1579 0x35b80, 0x35b80,
1580 0x35ba8, 0x35ba8,
1581 0x35bb0, 0x35bb4,
1582 0x35bc8, 0x35bd4,
1583 0x36140, 0x3618c,
1584 0x361f0, 0x36200,
1585 0x36218, 0x36218,
1586 0x36400, 0x36400,
1587 0x36408, 0x3641c,
1588 0x36618, 0x36620,
1589 0x36664, 0x36664,
1590 0x366a8, 0x366a8,
1591 0x366ec, 0x366ec,
1592 0x36a00, 0x36abc,
1593 0x36b00, 0x36b78,
1594 0x36c00, 0x36c00,
1595 0x36c08, 0x36c3c,
1596 0x36e00, 0x36e2c,
1597 0x36f00, 0x36f2c,
1598 0x37000, 0x370ac,
1599 0x370c0, 0x371ac,
1600 0x371c0, 0x372c4,
1601 0x372e4, 0x373c4,
1602 0x373e4, 0x374ac,
1603 0x374c0, 0x375ac,
1604 0x375c0, 0x376c4,
1605 0x376e4, 0x377c4,
1606 0x377e4, 0x377fc,
1607 0x37814, 0x37814,
1608 0x37854, 0x37868,
1609 0x37880, 0x3788c,
1610 0x378c0, 0x378d0,
1611 0x378e8, 0x378ec,
1612 0x37900, 0x379ac,
1613 0x379c0, 0x37ac4,
1614 0x37ae4, 0x37b10,
1615 0x37b24, 0x37b50,
1616 0x37bf0, 0x37c10,
1617 0x37c24, 0x37c50,
1618 0x37cf0, 0x37cfc,
1619 0x40040, 0x40040,
1620 0x40080, 0x40084,
1621 0x40100, 0x40100,
1622 0x40140, 0x401bc,
1623 0x40200, 0x40214,
1624 0x40228, 0x40228,
1625 0x40240, 0x40258,
1626 0x40280, 0x40280,
1627 0x40304, 0x40304,
1628 0x40330, 0x4033c,
1629 0x41304, 0x413dc,
1630 0x41400, 0x4141c,
1631 0x41480, 0x414d0,
1632 0x44000, 0x4407c,
1633 0x440c0, 0x4427c,
1634 0x442c0, 0x4447c,
1635 0x444c0, 0x4467c,
1636 0x446c0, 0x4487c,
1637 0x448c0, 0x44a7c,
1638 0x44ac0, 0x44c7c,
1639 0x44cc0, 0x44e7c,
1640 0x44ec0, 0x4507c,
1641 0x450c0, 0x451fc,
1642 0x45800, 0x45868,
1643 0x45880, 0x45884,
1644 0x458a0, 0x458b0,
1645 0x45a00, 0x45a68,
1646 0x45a80, 0x45a84,
1647 0x45aa0, 0x45ab0,
1648 0x460c0, 0x460e4,
1649 0x47000, 0x4708c,
1650 0x47200, 0x47250,
1651 0x47400, 0x47420,
1652 0x47600, 0x47618,
1653 0x47800, 0x4782c,
1654 0x50000, 0x500cc,
1655 0x50400, 0x50400,
1656 0x50800, 0x508cc,
1657 0x50c00, 0x50c00,
1658 0x51000, 0x510b0,
1659 0x51300, 0x51324,
1660 };
1661
1319 u32 *buf_end = (u32 *)((char *)buf + buf_size); 1662 u32 *buf_end = (u32 *)((char *)buf + buf_size);
1320 const unsigned int *reg_ranges; 1663 const unsigned int *reg_ranges;
1321 int reg_ranges_size, range; 1664 int reg_ranges_size, range;
@@ -1335,6 +1678,11 @@ void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
1335 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges); 1678 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
1336 break; 1679 break;
1337 1680
1681 case CHELSIO_T6:
1682 reg_ranges = t6_reg_ranges;
1683 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
1684 break;
1685
1338 default: 1686 default:
1339 dev_err(adap->pdev_dev, 1687 dev_err(adap->pdev_dev,
1340 "Unsupported chip version %d\n", chip_version); 1688 "Unsupported chip version %d\n", chip_version);
@@ -1948,7 +2296,8 @@ static bool t4_fw_matches_chip(const struct adapter *adap,
1948 * which will keep us "honest" in the future ... 2296 * which will keep us "honest" in the future ...
1949 */ 2297 */
1950 if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) || 2298 if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
1951 (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5)) 2299 (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) ||
2300 (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6))
1952 return true; 2301 return true;
1953 2302
1954 dev_err(adap->pdev_dev, 2303 dev_err(adap->pdev_dev,
@@ -2488,6 +2837,7 @@ static void tp_intr_handler(struct adapter *adapter)
2488static void sge_intr_handler(struct adapter *adapter) 2837static void sge_intr_handler(struct adapter *adapter)
2489{ 2838{
2490 u64 v; 2839 u64 v;
2840 u32 err;
2491 2841
2492 static const struct intr_info sge_intr_info[] = { 2842 static const struct intr_info sge_intr_info[] = {
2493 { ERR_CPL_EXCEED_IQE_SIZE_F, 2843 { ERR_CPL_EXCEED_IQE_SIZE_F,
@@ -2496,8 +2846,6 @@ static void sge_intr_handler(struct adapter *adapter)
2496 "SGE GTS CIDX increment too large", -1, 0 }, 2846 "SGE GTS CIDX increment too large", -1, 0 },
2497 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 }, 2847 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
2498 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full }, 2848 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },
2499 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
2500 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
2501 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F, 2849 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
2502 "SGE IQID > 1023 received CPL for FL", -1, 0 }, 2850 "SGE IQID > 1023 received CPL for FL", -1, 0 },
2503 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1, 2851 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
@@ -2510,13 +2858,19 @@ static void sge_intr_handler(struct adapter *adapter)
2510 0 }, 2858 0 },
2511 { ERR_ING_CTXT_PRIO_F, 2859 { ERR_ING_CTXT_PRIO_F,
2512 "SGE too many priority ingress contexts", -1, 0 }, 2860 "SGE too many priority ingress contexts", -1, 0 },
2513 { ERR_EGR_CTXT_PRIO_F,
2514 "SGE too many priority egress contexts", -1, 0 },
2515 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 }, 2861 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
2516 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 }, 2862 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
2517 { 0 } 2863 { 0 }
2518 }; 2864 };
2519 2865
2866 static struct intr_info t4t5_sge_intr_info[] = {
2867 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
2868 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
2869 { ERR_EGR_CTXT_PRIO_F,
2870 "SGE too many priority egress contexts", -1, 0 },
2871 { 0 }
2872 };
2873
2520 v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1_A) | 2874 v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1_A) |
2521 ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2_A) << 32); 2875 ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2_A) << 32);
2522 if (v) { 2876 if (v) {
@@ -2526,8 +2880,23 @@ static void sge_intr_handler(struct adapter *adapter)
2526 t4_write_reg(adapter, SGE_INT_CAUSE2_A, v >> 32); 2880 t4_write_reg(adapter, SGE_INT_CAUSE2_A, v >> 32);
2527 } 2881 }
2528 2882
2529 if (t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info) || 2883 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
2530 v != 0) 2884 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
2885 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
2886 t4t5_sge_intr_info);
2887
2888 err = t4_read_reg(adapter, SGE_ERROR_STATS_A);
2889 if (err & ERROR_QID_VALID_F) {
2890 dev_err(adapter->pdev_dev, "SGE error for queue %u\n",
2891 ERROR_QID_G(err));
2892 if (err & UNCAPTURED_ERROR_F)
2893 dev_err(adapter->pdev_dev,
2894 "SGE UNCAPTURED_ERROR set (clearing)\n");
2895 t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F |
2896 UNCAPTURED_ERROR_F);
2897 }
2898
2899 if (v != 0)
2531 t4_fatal_err(adapter); 2900 t4_fatal_err(adapter);
2532} 2901}
2533 2902
@@ -2700,6 +3069,7 @@ static void cplsw_intr_handler(struct adapter *adapter)
2700 */ 3069 */
2701static void le_intr_handler(struct adapter *adap) 3070static void le_intr_handler(struct adapter *adap)
2702{ 3071{
3072 enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
2703 static const struct intr_info le_intr_info[] = { 3073 static const struct intr_info le_intr_info[] = {
2704 { LIPMISS_F, "LE LIP miss", -1, 0 }, 3074 { LIPMISS_F, "LE LIP miss", -1, 0 },
2705 { LIP0_F, "LE 0 LIP error", -1, 0 }, 3075 { LIP0_F, "LE 0 LIP error", -1, 0 },
@@ -2709,7 +3079,18 @@ static void le_intr_handler(struct adapter *adap)
2709 { 0 } 3079 { 0 }
2710 }; 3080 };
2711 3081
2712 if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A, le_intr_info)) 3082 static struct intr_info t6_le_intr_info[] = {
3083 { T6_LIPMISS_F, "LE LIP miss", -1, 0 },
3084 { T6_LIP0_F, "LE 0 LIP error", -1, 0 },
3085 { TCAMINTPERR_F, "LE parity error", -1, 1 },
3086 { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },
3087 { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },
3088 { 0 }
3089 };
3090
3091 if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A,
3092 (chip <= CHELSIO_T5) ?
3093 le_intr_info : t6_le_intr_info))
2713 t4_fatal_err(adap); 3094 t4_fatal_err(adap);
2714} 3095}
2715 3096
@@ -2978,7 +3359,7 @@ int t4_slow_intr_handler(struct adapter *adapter)
2978 pcie_intr_handler(adapter); 3359 pcie_intr_handler(adapter);
2979 if (cause & MC_F) 3360 if (cause & MC_F)
2980 mem_intr_handler(adapter, MEM_MC); 3361 mem_intr_handler(adapter, MEM_MC);
2981 if (!is_t4(adapter->params.chip) && (cause & MC1_S)) 3362 if (is_t5(adapter->params.chip) && (cause & MC1_F))
2982 mem_intr_handler(adapter, MEM_MC1); 3363 mem_intr_handler(adapter, MEM_MC1);
2983 if (cause & EDC0_F) 3364 if (cause & EDC0_F)
2984 mem_intr_handler(adapter, MEM_EDC0); 3365 mem_intr_handler(adapter, MEM_EDC0);
@@ -3024,17 +3405,18 @@ int t4_slow_intr_handler(struct adapter *adapter)
3024 */ 3405 */
3025void t4_intr_enable(struct adapter *adapter) 3406void t4_intr_enable(struct adapter *adapter)
3026{ 3407{
3408 u32 val = 0;
3027 u32 pf = SOURCEPF_G(t4_read_reg(adapter, PL_WHOAMI_A)); 3409 u32 pf = SOURCEPF_G(t4_read_reg(adapter, PL_WHOAMI_A));
3028 3410
3411 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
3412 val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F;
3029 t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F | 3413 t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
3030 ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F | 3414 ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
3031 ERR_DROPPED_DB_F | ERR_DATA_CPL_ON_HIGH_QID1_F | 3415 ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F |
3032 ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F | 3416 ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
3033 ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F | 3417 ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
3034 ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F | 3418 ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
3035 ERR_EGR_CTXT_PRIO_F | INGRESS_SIZE_ERR_F | 3419 DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val);
3036 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F |
3037 EGRESS_SIZE_ERR_F);
3038 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK); 3420 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
3039 t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf); 3421 t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf);
3040} 3422}
@@ -3248,11 +3630,29 @@ void t4_read_rss_key(struct adapter *adap, u32 *key)
3248 */ 3630 */
3249void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx) 3631void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx)
3250{ 3632{
3633 u8 rss_key_addr_cnt = 16;
3634 u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A);
3635
3636 /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
3637 * allows access to key addresses 16-63 by using KeyWrAddrX
3638 * as index[5:4](upper 2) into key table
3639 */
3640 if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
3641 (vrt & KEYEXTEND_F) && (KEYMODE_G(vrt) == 3))
3642 rss_key_addr_cnt = 32;
3643
3251 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10, 3644 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
3252 TP_RSS_SECRET_KEY0_A); 3645 TP_RSS_SECRET_KEY0_A);
3253 if (idx >= 0 && idx < 16) 3646
3254 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A, 3647 if (idx >= 0 && idx < rss_key_addr_cnt) {
3255 KEYWRADDR_V(idx) | KEYWREN_F); 3648 if (rss_key_addr_cnt > 16)
3649 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
3650 KEYWRADDRX_V(idx >> 4) |
3651 T6_VFWRADDR_V(idx) | KEYWREN_F);
3652 else
3653 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
3654 KEYWRADDR_V(idx) | KEYWREN_F);
3655 }
3256} 3656}
3257 3657
3258/** 3658/**
@@ -3286,8 +3686,13 @@ void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
3286{ 3686{
3287 u32 vrt, mask, data; 3687 u32 vrt, mask, data;
3288 3688
3289 mask = VFWRADDR_V(VFWRADDR_M); 3689 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) {
3290 data = VFWRADDR_V(index); 3690 mask = VFWRADDR_V(VFWRADDR_M);
3691 data = VFWRADDR_V(index);
3692 } else {
3693 mask = T6_VFWRADDR_V(T6_VFWRADDR_M);
3694 data = T6_VFWRADDR_V(index);
3695 }
3291 3696
3292 /* Request that the index'th VF Table values be read into VFL/VFH. 3697 /* Request that the index'th VF Table values be read into VFL/VFH.
3293 */ 3698 */
@@ -4798,45 +5203,71 @@ int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
4798 unsigned int viid, bool free, unsigned int naddr, 5203 unsigned int viid, bool free, unsigned int naddr,
4799 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok) 5204 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
4800{ 5205{
4801 int i, ret; 5206 int offset, ret = 0;
4802 struct fw_vi_mac_cmd c; 5207 struct fw_vi_mac_cmd c;
4803 struct fw_vi_mac_exact *p; 5208 unsigned int nfilters = 0;
4804 unsigned int max_naddr = is_t4(adap->params.chip) ? 5209 unsigned int max_naddr = adap->params.arch.mps_tcam_size;
4805 NUM_MPS_CLS_SRAM_L_INSTANCES : 5210 unsigned int rem = naddr;
4806 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
4807 5211
4808 if (naddr > 7) 5212 if (naddr > max_naddr)
4809 return -EINVAL; 5213 return -EINVAL;
4810 5214
4811 memset(&c, 0, sizeof(c)); 5215 for (offset = 0; offset < naddr ; /**/) {
4812 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) | 5216 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) ?
4813 FW_CMD_REQUEST_F | FW_CMD_WRITE_F | 5217 rem : ARRAY_SIZE(c.u.exact));
4814 (free ? FW_CMD_EXEC_F : 0) | 5218 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
4815 FW_VI_MAC_CMD_VIID_V(viid)); 5219 u.exact[fw_naddr]), 16);
4816 c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) | 5220 struct fw_vi_mac_exact *p;
4817 FW_CMD_LEN16_V((naddr + 2) / 2)); 5221 int i;
4818
4819 for (i = 0, p = c.u.exact; i < naddr; i++, p++) {
4820 p->valid_to_idx =
4821 cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
4822 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_ADD_MAC));
4823 memcpy(p->macaddr, addr[i], sizeof(p->macaddr));
4824 }
4825 5222
4826 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok); 5223 memset(&c, 0, sizeof(c));
4827 if (ret) 5224 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
4828 return ret; 5225 FW_CMD_REQUEST_F |
5226 FW_CMD_WRITE_F |
5227 FW_CMD_EXEC_V(free) |
5228 FW_VI_MAC_CMD_VIID_V(viid));
5229 c.freemacs_to_len16 =
5230 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) |
5231 FW_CMD_LEN16_V(len16));
5232
5233 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
5234 p->valid_to_idx =
5235 cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
5236 FW_VI_MAC_CMD_IDX_V(
5237 FW_VI_MAC_ADD_MAC));
5238 memcpy(p->macaddr, addr[offset + i],
5239 sizeof(p->macaddr));
5240 }
4829 5241
4830 for (i = 0, p = c.u.exact; i < naddr; i++, p++) { 5242 /* It's okay if we run out of space in our MAC address arena.
4831 u16 index = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx)); 5243 * Some of the addresses we submit may get stored so we need
5244 * to run through the reply to see what the results were ...
5245 */
5246 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
5247 if (ret && ret != -FW_ENOMEM)
5248 break;
5249
5250 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
5251 u16 index = FW_VI_MAC_CMD_IDX_G(
5252 be16_to_cpu(p->valid_to_idx));
5253
5254 if (idx)
5255 idx[offset + i] = (index >= max_naddr ?
5256 0xffff : index);
5257 if (index < max_naddr)
5258 nfilters++;
5259 else if (hash)
5260 *hash |= (1ULL <<
5261 hash_mac_addr(addr[offset + i]));
5262 }
4832 5263
4833 if (idx) 5264 free = false;
4834 idx[i] = index >= max_naddr ? 0xffff : index; 5265 offset += fw_naddr;
4835 if (index < max_naddr) 5266 rem -= fw_naddr;
4836 ret++;
4837 else if (hash)
4838 *hash |= (1ULL << hash_mac_addr(addr[i]));
4839 } 5267 }
5268
5269 if (ret == 0 || ret == -FW_ENOMEM)
5270 ret = nfilters;
4840 return ret; 5271 return ret;
4841} 5272}
4842 5273
@@ -4865,9 +5296,7 @@ int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
4865 int ret, mode; 5296 int ret, mode;
4866 struct fw_vi_mac_cmd c; 5297 struct fw_vi_mac_cmd c;
4867 struct fw_vi_mac_exact *p = c.u.exact; 5298 struct fw_vi_mac_exact *p = c.u.exact;
4868 unsigned int max_mac_addr = is_t4(adap->params.chip) ? 5299 unsigned int max_mac_addr = adap->params.arch.mps_tcam_size;
4869 NUM_MPS_CLS_SRAM_L_INSTANCES :
4870 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
4871 5300
4872 if (idx < 0) /* new allocation */ 5301 if (idx < 0) /* new allocation */
4873 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC; 5302 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
@@ -5276,9 +5705,30 @@ int t4_prep_adapter(struct adapter *adapter)
5276 switch (ver) { 5705 switch (ver) {
5277 case CHELSIO_T4: 5706 case CHELSIO_T4:
5278 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev); 5707 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
5708 adapter->params.arch.sge_fl_db = DBPRIO_F;
5709 adapter->params.arch.mps_tcam_size =
5710 NUM_MPS_CLS_SRAM_L_INSTANCES;
5711 adapter->params.arch.mps_rplc_size = 128;
5712 adapter->params.arch.nchan = NCHAN;
5713 adapter->params.arch.vfcount = 128;
5279 break; 5714 break;
5280 case CHELSIO_T5: 5715 case CHELSIO_T5:
5281 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev); 5716 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
5717 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
5718 adapter->params.arch.mps_tcam_size =
5719 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
5720 adapter->params.arch.mps_rplc_size = 128;
5721 adapter->params.arch.nchan = NCHAN;
5722 adapter->params.arch.vfcount = 128;
5723 break;
5724 case CHELSIO_T6:
5725 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
5726 adapter->params.arch.sge_fl_db = 0;
5727 adapter->params.arch.mps_tcam_size =
5728 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
5729 adapter->params.arch.mps_rplc_size = 256;
5730 adapter->params.arch.nchan = 2;
5731 adapter->params.arch.vfcount = 256;
5282 break; 5732 break;
5283 default: 5733 default:
5284 dev_err(adapter->pdev_dev, "Device %d is not supported\n", 5734 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_msg.h b/drivers/net/ethernet/chelsio/cxgb4/t4_msg.h
index d90f8a03e378..132cb8fc0bf7 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_msg.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_msg.h
@@ -686,6 +686,9 @@ struct cpl_tx_pkt {
686#define TXPKT_ETHHDR_LEN_S 34 686#define TXPKT_ETHHDR_LEN_S 34
687#define TXPKT_ETHHDR_LEN_V(x) ((__u64)(x) << TXPKT_ETHHDR_LEN_S) 687#define TXPKT_ETHHDR_LEN_V(x) ((__u64)(x) << TXPKT_ETHHDR_LEN_S)
688 688
689#define T6_TXPKT_ETHHDR_LEN_S 32
690#define T6_TXPKT_ETHHDR_LEN_V(x) ((__u64)(x) << T6_TXPKT_ETHHDR_LEN_S)
691
689#define TXPKT_CSUM_TYPE_S 40 692#define TXPKT_CSUM_TYPE_S 40
690#define TXPKT_CSUM_TYPE_V(x) ((__u64)(x) << TXPKT_CSUM_TYPE_S) 693#define TXPKT_CSUM_TYPE_V(x) ((__u64)(x) << TXPKT_CSUM_TYPE_S)
691 694
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h b/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
index 326674b19983..c7fc3d3068f9 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
@@ -418,6 +418,20 @@
418#define SGE_INGRESS_QUEUES_PER_PAGE_PF_A 0x10f4 418#define SGE_INGRESS_QUEUES_PER_PAGE_PF_A 0x10f4
419#define SGE_INGRESS_QUEUES_PER_PAGE_VF_A 0x10f8 419#define SGE_INGRESS_QUEUES_PER_PAGE_VF_A 0x10f8
420 420
421#define SGE_ERROR_STATS_A 0x1100
422
423#define UNCAPTURED_ERROR_S 18
424#define UNCAPTURED_ERROR_V(x) ((x) << UNCAPTURED_ERROR_S)
425#define UNCAPTURED_ERROR_F UNCAPTURED_ERROR_V(1U)
426
427#define ERROR_QID_VALID_S 17
428#define ERROR_QID_VALID_V(x) ((x) << ERROR_QID_VALID_S)
429#define ERROR_QID_VALID_F ERROR_QID_VALID_V(1U)
430
431#define ERROR_QID_S 0
432#define ERROR_QID_M 0x1ffffU
433#define ERROR_QID_G(x) (((x) >> ERROR_QID_S) & ERROR_QID_M)
434
421#define HP_INT_THRESH_S 28 435#define HP_INT_THRESH_S 28
422#define HP_INT_THRESH_M 0xfU 436#define HP_INT_THRESH_M 0xfU
423#define HP_INT_THRESH_V(x) ((x) << HP_INT_THRESH_S) 437#define HP_INT_THRESH_V(x) ((x) << HP_INT_THRESH_S)
@@ -705,6 +719,10 @@
705#define REGISTER_S 0 719#define REGISTER_S 0
706#define REGISTER_V(x) ((x) << REGISTER_S) 720#define REGISTER_V(x) ((x) << REGISTER_S)
707 721
722#define T6_ENABLE_S 31
723#define T6_ENABLE_V(x) ((x) << T6_ENABLE_S)
724#define T6_ENABLE_F T6_ENABLE_V(1U)
725
708#define PFNUM_S 0 726#define PFNUM_S 0
709#define PFNUM_V(x) ((x) << PFNUM_S) 727#define PFNUM_V(x) ((x) << PFNUM_S)
710 728
@@ -2054,6 +2072,11 @@
2054#define VFLKPIDX_M 0xffU 2072#define VFLKPIDX_M 0xffU
2055#define VFLKPIDX_G(x) (((x) >> VFLKPIDX_S) & VFLKPIDX_M) 2073#define VFLKPIDX_G(x) (((x) >> VFLKPIDX_S) & VFLKPIDX_M)
2056 2074
2075#define T6_VFWRADDR_S 8
2076#define T6_VFWRADDR_M 0xffU
2077#define T6_VFWRADDR_V(x) ((x) << T6_VFWRADDR_S)
2078#define T6_VFWRADDR_G(x) (((x) >> T6_VFWRADDR_S) & T6_VFWRADDR_M)
2079
2057#define TP_RSS_CONFIG_CNG_A 0x7e04 2080#define TP_RSS_CONFIG_CNG_A 0x7e04
2058#define TP_RSS_SECRET_KEY0_A 0x40 2081#define TP_RSS_SECRET_KEY0_A 0x40
2059#define TP_RSS_PF0_CONFIG_A 0x30 2082#define TP_RSS_PF0_CONFIG_A 0x30
@@ -2175,7 +2198,28 @@
2175#define MPS_RX_PERR_INT_CAUSE_A 0x11074 2198#define MPS_RX_PERR_INT_CAUSE_A 0x11074
2176 2199
2177#define MPS_CLS_TCAM_Y_L_A 0xf000 2200#define MPS_CLS_TCAM_Y_L_A 0xf000
2201#define MPS_CLS_TCAM_DATA0_A 0xf000
2202#define MPS_CLS_TCAM_DATA1_A 0xf004
2203
2204#define DMACH_S 0
2205#define DMACH_M 0xffffU
2206#define DMACH_G(x) (((x) >> DMACH_S) & DMACH_M)
2207
2178#define MPS_CLS_TCAM_X_L_A 0xf008 2208#define MPS_CLS_TCAM_X_L_A 0xf008
2209#define MPS_CLS_TCAM_DATA2_CTL_A 0xf008
2210
2211#define CTLCMDTYPE_S 31
2212#define CTLCMDTYPE_V(x) ((x) << CTLCMDTYPE_S)
2213#define CTLCMDTYPE_F CTLCMDTYPE_V(1U)
2214
2215#define CTLTCAMSEL_S 25
2216#define CTLTCAMSEL_V(x) ((x) << CTLTCAMSEL_S)
2217
2218#define CTLTCAMINDEX_S 17
2219#define CTLTCAMINDEX_V(x) ((x) << CTLTCAMINDEX_S)
2220
2221#define CTLXYBITSEL_S 16
2222#define CTLXYBITSEL_V(x) ((x) << CTLXYBITSEL_S)
2179 2223
2180#define MPS_CLS_TCAM_Y_L(idx) (MPS_CLS_TCAM_Y_L_A + (idx) * 16) 2224#define MPS_CLS_TCAM_Y_L(idx) (MPS_CLS_TCAM_Y_L_A + (idx) * 16)
2181#define NUM_MPS_CLS_TCAM_Y_L_INSTANCES 512 2225#define NUM_MPS_CLS_TCAM_Y_L_INSTANCES 512
@@ -2184,6 +2228,45 @@
2184#define NUM_MPS_CLS_TCAM_X_L_INSTANCES 512 2228#define NUM_MPS_CLS_TCAM_X_L_INSTANCES 512
2185 2229
2186#define MPS_CLS_SRAM_L_A 0xe000 2230#define MPS_CLS_SRAM_L_A 0xe000
2231
2232#define T6_MULTILISTEN0_S 26
2233
2234#define T6_SRAM_PRIO3_S 23
2235#define T6_SRAM_PRIO3_M 0x7U
2236#define T6_SRAM_PRIO3_G(x) (((x) >> T6_SRAM_PRIO3_S) & T6_SRAM_PRIO3_M)
2237
2238#define T6_SRAM_PRIO2_S 20
2239#define T6_SRAM_PRIO2_M 0x7U
2240#define T6_SRAM_PRIO2_G(x) (((x) >> T6_SRAM_PRIO2_S) & T6_SRAM_PRIO2_M)
2241
2242#define T6_SRAM_PRIO1_S 17
2243#define T6_SRAM_PRIO1_M 0x7U
2244#define T6_SRAM_PRIO1_G(x) (((x) >> T6_SRAM_PRIO1_S) & T6_SRAM_PRIO1_M)
2245
2246#define T6_SRAM_PRIO0_S 14
2247#define T6_SRAM_PRIO0_M 0x7U
2248#define T6_SRAM_PRIO0_G(x) (((x) >> T6_SRAM_PRIO0_S) & T6_SRAM_PRIO0_M)
2249
2250#define T6_SRAM_VLD_S 13
2251#define T6_SRAM_VLD_V(x) ((x) << T6_SRAM_VLD_S)
2252#define T6_SRAM_VLD_F T6_SRAM_VLD_V(1U)
2253
2254#define T6_REPLICATE_S 12
2255#define T6_REPLICATE_V(x) ((x) << T6_REPLICATE_S)
2256#define T6_REPLICATE_F T6_REPLICATE_V(1U)
2257
2258#define T6_PF_S 9
2259#define T6_PF_M 0x7U
2260#define T6_PF_G(x) (((x) >> T6_PF_S) & T6_PF_M)
2261
2262#define T6_VF_VALID_S 8
2263#define T6_VF_VALID_V(x) ((x) << T6_VF_VALID_S)
2264#define T6_VF_VALID_F T6_VF_VALID_V(1U)
2265
2266#define T6_VF_S 0
2267#define T6_VF_M 0xffU
2268#define T6_VF_G(x) (((x) >> T6_VF_S) & T6_VF_M)
2269
2187#define MPS_CLS_SRAM_H_A 0xe004 2270#define MPS_CLS_SRAM_H_A 0xe004
2188 2271
2189#define MPS_CLS_SRAM_L(idx) (MPS_CLS_SRAM_L_A + (idx) * 8) 2272#define MPS_CLS_SRAM_L(idx) (MPS_CLS_SRAM_L_A + (idx) * 8)
@@ -2433,6 +2516,8 @@
2433#define CIM_F CIM_V(1U) 2516#define CIM_F CIM_V(1U)
2434 2517
2435#define MC1_S 31 2518#define MC1_S 31
2519#define MC1_V(x) ((x) << MC1_S)
2520#define MC1_F MC1_V(1U)
2436 2521
2437#define PL_INT_ENABLE_A 0x19410 2522#define PL_INT_ENABLE_A 0x19410
2438#define PL_INT_MAP0_A 0x19414 2523#define PL_INT_MAP0_A 0x19414
@@ -2463,6 +2548,18 @@
2463#define REV_V(x) ((x) << REV_S) 2548#define REV_V(x) ((x) << REV_S)
2464#define REV_G(x) (((x) >> REV_S) & REV_M) 2549#define REV_G(x) (((x) >> REV_S) & REV_M)
2465 2550
2551#define T6_UNKNOWNCMD_S 3
2552#define T6_UNKNOWNCMD_V(x) ((x) << T6_UNKNOWNCMD_S)
2553#define T6_UNKNOWNCMD_F T6_UNKNOWNCMD_V(1U)
2554
2555#define T6_LIP0_S 2
2556#define T6_LIP0_V(x) ((x) << T6_LIP0_S)
2557#define T6_LIP0_F T6_LIP0_V(1U)
2558
2559#define T6_LIPMISS_S 1
2560#define T6_LIPMISS_V(x) ((x) << T6_LIPMISS_S)
2561#define T6_LIPMISS_F T6_LIPMISS_V(1U)
2562
2466#define LE_DB_INT_CAUSE_A 0x19c3c 2563#define LE_DB_INT_CAUSE_A 0x19c3c
2467 2564
2468#define REQQPARERR_S 16 2565#define REQQPARERR_S 16
@@ -2485,6 +2582,14 @@
2485#define LIP0_V(x) ((x) << LIP0_S) 2582#define LIP0_V(x) ((x) << LIP0_S)
2486#define LIP0_F LIP0_V(1U) 2583#define LIP0_F LIP0_V(1U)
2487 2584
2585#define TCAMINTPERR_S 13
2586#define TCAMINTPERR_V(x) ((x) << TCAMINTPERR_S)
2587#define TCAMINTPERR_F TCAMINTPERR_V(1U)
2588
2589#define SSRAMINTPERR_S 10
2590#define SSRAMINTPERR_V(x) ((x) << SSRAMINTPERR_S)
2591#define SSRAMINTPERR_F SSRAMINTPERR_V(1U)
2592
2488#define NCSI_INT_CAUSE_A 0x1a0d8 2593#define NCSI_INT_CAUSE_A 0x1a0d8
2489 2594
2490#define CIM_DM_PRTY_ERR_S 8 2595#define CIM_DM_PRTY_ERR_S 8
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_values.h b/drivers/net/ethernet/chelsio/cxgb4/t4_values.h
index 72ec1f91d29f..7bdee3bf75ec 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_values.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_values.h
@@ -63,6 +63,7 @@
63 63
64#define FETCHBURSTMIN_64B_X 2 64#define FETCHBURSTMIN_64B_X 2
65 65
66#define FETCHBURSTMAX_256B_X 2
66#define FETCHBURSTMAX_512B_X 3 67#define FETCHBURSTMAX_512B_X 3
67 68
68#define HOSTFCMODE_STATUS_PAGE_X 2 69#define HOSTFCMODE_STATUS_PAGE_X 2
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h b/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h
index 0848317e5c4f..aceb1e8cacc8 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h
@@ -788,15 +788,27 @@ struct fw_ldst_cmd {
788 __be16 vctl; 788 __be16 vctl;
789 __be16 rval; 789 __be16 rval;
790 } mdio; 790 } mdio;
791 struct fw_ldst_mps { 791 union fw_ldst_mps {
792 __be16 fid_ctl; 792 struct fw_ldst_mps_rplc {
793 __be16 rplcpf_pkd; 793 __be16 fid_idx;
794 __be32 rplc127_96; 794 __be16 rplcpf_pkd;
795 __be32 rplc95_64; 795 __be32 rplc255_224;
796 __be32 rplc63_32; 796 __be32 rplc223_192;
797 __be32 rplc31_0; 797 __be32 rplc191_160;
798 __be32 atrb; 798 __be32 rplc159_128;
799 __be16 vlan[16]; 799 __be32 rplc127_96;
800 __be32 rplc95_64;
801 __be32 rplc63_32;
802 __be32 rplc31_0;
803 } rplc;
804 struct fw_ldst_mps_atrb {
805 __be16 fid_mpsid;
806 __be16 r2[3];
807 __be32 r3[2];
808 __be32 r4;
809 __be32 atrb;
810 __be16 vlan[16];
811 } atrb;
800 } mps; 812 } mps;
801 struct fw_ldst_func { 813 struct fw_ldst_func {
802 u8 access_ctl; 814 u8 access_ctl;
@@ -831,8 +843,8 @@ struct fw_ldst_cmd {
831#define FW_LDST_CMD_FID_S 15 843#define FW_LDST_CMD_FID_S 15
832#define FW_LDST_CMD_FID_V(x) ((x) << FW_LDST_CMD_FID_S) 844#define FW_LDST_CMD_FID_V(x) ((x) << FW_LDST_CMD_FID_S)
833 845
834#define FW_LDST_CMD_CTL_S 0 846#define FW_LDST_CMD_IDX_S 0
835#define FW_LDST_CMD_CTL_V(x) ((x) << FW_LDST_CMD_CTL_S) 847#define FW_LDST_CMD_IDX_V(x) ((x) << FW_LDST_CMD_IDX_S)
836 848
837#define FW_LDST_CMD_RPLCPF_S 0 849#define FW_LDST_CMD_RPLCPF_S 0
838#define FW_LDST_CMD_RPLCPF_V(x) ((x) << FW_LDST_CMD_RPLCPF_S) 850#define FW_LDST_CMD_RPLCPF_V(x) ((x) << FW_LDST_CMD_RPLCPF_S)
@@ -2536,13 +2548,8 @@ enum fw_port_mod_sub_type {
2536 FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC, 2548 FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
2537}; 2549};
2538 2550
2539/* port stats */
2540#define FW_NUM_PORT_STATS 50
2541#define FW_NUM_PORT_TX_STATS 23
2542#define FW_NUM_PORT_RX_STATS 27
2543
2544enum fw_port_stats_tx_index { 2551enum fw_port_stats_tx_index {
2545 FW_STAT_TX_PORT_BYTES_IX, 2552 FW_STAT_TX_PORT_BYTES_IX = 0,
2546 FW_STAT_TX_PORT_FRAMES_IX, 2553 FW_STAT_TX_PORT_FRAMES_IX,
2547 FW_STAT_TX_PORT_BCAST_IX, 2554 FW_STAT_TX_PORT_BCAST_IX,
2548 FW_STAT_TX_PORT_MCAST_IX, 2555 FW_STAT_TX_PORT_MCAST_IX,
@@ -2564,11 +2571,12 @@ enum fw_port_stats_tx_index {
2564 FW_STAT_TX_PORT_PPP4_IX, 2571 FW_STAT_TX_PORT_PPP4_IX,
2565 FW_STAT_TX_PORT_PPP5_IX, 2572 FW_STAT_TX_PORT_PPP5_IX,
2566 FW_STAT_TX_PORT_PPP6_IX, 2573 FW_STAT_TX_PORT_PPP6_IX,
2567 FW_STAT_TX_PORT_PPP7_IX 2574 FW_STAT_TX_PORT_PPP7_IX,
2575 FW_NUM_PORT_TX_STATS
2568}; 2576};
2569 2577
2570enum fw_port_stat_rx_index { 2578enum fw_port_stat_rx_index {
2571 FW_STAT_RX_PORT_BYTES_IX, 2579 FW_STAT_RX_PORT_BYTES_IX = 0,
2572 FW_STAT_RX_PORT_FRAMES_IX, 2580 FW_STAT_RX_PORT_FRAMES_IX,
2573 FW_STAT_RX_PORT_BCAST_IX, 2581 FW_STAT_RX_PORT_BCAST_IX,
2574 FW_STAT_RX_PORT_MCAST_IX, 2582 FW_STAT_RX_PORT_MCAST_IX,
@@ -2594,9 +2602,14 @@ enum fw_port_stat_rx_index {
2594 FW_STAT_RX_PORT_PPP5_IX, 2602 FW_STAT_RX_PORT_PPP5_IX,
2595 FW_STAT_RX_PORT_PPP6_IX, 2603 FW_STAT_RX_PORT_PPP6_IX,
2596 FW_STAT_RX_PORT_PPP7_IX, 2604 FW_STAT_RX_PORT_PPP7_IX,
2597 FW_STAT_RX_PORT_LESS_64B_IX 2605 FW_STAT_RX_PORT_LESS_64B_IX,
2606 FW_STAT_RX_PORT_MAC_ERROR_IX,
2607 FW_NUM_PORT_RX_STATS
2598}; 2608};
2599 2609
2610/* port stats */
2611#define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + FW_NUM_PORT_RX_STATS)
2612
2600struct fw_port_stats_cmd { 2613struct fw_port_stats_cmd {
2601 __be32 op_to_portid; 2614 __be32 op_to_portid;
2602 __be32 retval_len16; 2615 __be32 retval_len16;
@@ -3025,7 +3038,8 @@ struct fw_hdr {
3025 3038
3026enum fw_hdr_chip { 3039enum fw_hdr_chip {
3027 FW_HDR_CHIP_T4, 3040 FW_HDR_CHIP_T4,
3028 FW_HDR_CHIP_T5 3041 FW_HDR_CHIP_T5,
3042 FW_HDR_CHIP_T6
3029}; 3043};
3030 3044
3031#define FW_HDR_FW_VER_MAJOR_S 24 3045#define FW_HDR_FW_VER_MAJOR_S 24
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4fw_version.h b/drivers/net/ethernet/chelsio/cxgb4/t4fw_version.h
index b9d1cbac0eee..32b213559b02 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4fw_version.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4fw_version.h
@@ -45,4 +45,9 @@
45#define T5FW_VERSION_MICRO 0x20 45#define T5FW_VERSION_MICRO 0x20
46#define T5FW_VERSION_BUILD 0x00 46#define T5FW_VERSION_BUILD 0x00
47 47
48#define T6FW_VERSION_MAJOR 0x01
49#define T6FW_VERSION_MINOR 0x0D
50#define T6FW_VERSION_MICRO 0x2D
51#define T6FW_VERSION_BUILD 0x00
52
48#endif 53#endif
diff --git a/drivers/net/ethernet/chelsio/cxgb4vf/sge.c b/drivers/net/ethernet/chelsio/cxgb4vf/sge.c
index be4ab09d11d7..ad53e5ad2acd 100644
--- a/drivers/net/ethernet/chelsio/cxgb4vf/sge.c
+++ b/drivers/net/ethernet/chelsio/cxgb4vf/sge.c
@@ -524,7 +524,7 @@ static void unmap_rx_buf(struct adapter *adapter, struct sge_fl *fl)
524 */ 524 */
525static inline void ring_fl_db(struct adapter *adapter, struct sge_fl *fl) 525static inline void ring_fl_db(struct adapter *adapter, struct sge_fl *fl)
526{ 526{
527 u32 val; 527 u32 val = adapter->params.arch.sge_fl_db;
528 528
529 /* The SGE keeps track of its Producer and Consumer Indices in terms 529 /* The SGE keeps track of its Producer and Consumer Indices in terms
530 * of Egress Queue Units so we can only tell it about integral numbers 530 * of Egress Queue Units so we can only tell it about integral numbers
@@ -532,11 +532,9 @@ static inline void ring_fl_db(struct adapter *adapter, struct sge_fl *fl)
532 */ 532 */
533 if (fl->pend_cred >= FL_PER_EQ_UNIT) { 533 if (fl->pend_cred >= FL_PER_EQ_UNIT) {
534 if (is_t4(adapter->params.chip)) 534 if (is_t4(adapter->params.chip))
535 val = PIDX_V(fl->pend_cred / FL_PER_EQ_UNIT); 535 val |= PIDX_V(fl->pend_cred / FL_PER_EQ_UNIT);
536 else 536 else
537 val = PIDX_T5_V(fl->pend_cred / FL_PER_EQ_UNIT) | 537 val |= PIDX_T5_V(fl->pend_cred / FL_PER_EQ_UNIT);
538 DBTYPE_F;
539 val |= DBPRIO_F;
540 538
541 /* Make sure all memory writes to the Free List queue are 539 /* Make sure all memory writes to the Free List queue are
542 * committed before we tell the hardware about them. 540 * committed before we tell the hardware about them.
@@ -1084,7 +1082,7 @@ static void inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *tq,
1084 * Figure out what HW csum a packet wants and return the appropriate control 1082 * Figure out what HW csum a packet wants and return the appropriate control
1085 * bits. 1083 * bits.
1086 */ 1084 */
1087static u64 hwcsum(const struct sk_buff *skb) 1085static u64 hwcsum(enum chip_type chip, const struct sk_buff *skb)
1088{ 1086{
1089 int csum_type; 1087 int csum_type;
1090 const struct iphdr *iph = ip_hdr(skb); 1088 const struct iphdr *iph = ip_hdr(skb);
@@ -1116,11 +1114,16 @@ nocsum:
1116 goto nocsum; 1114 goto nocsum;
1117 } 1115 }
1118 1116
1119 if (likely(csum_type >= TX_CSUM_TCPIP)) 1117 if (likely(csum_type >= TX_CSUM_TCPIP)) {
1120 return TXPKT_CSUM_TYPE_V(csum_type) | 1118 u64 hdr_len = TXPKT_IPHDR_LEN_V(skb_network_header_len(skb));
1121 TXPKT_IPHDR_LEN_V(skb_network_header_len(skb)) | 1119 int eth_hdr_len = skb_network_offset(skb) - ETH_HLEN;
1122 TXPKT_ETHHDR_LEN_V(skb_network_offset(skb) - ETH_HLEN); 1120
1123 else { 1121 if (chip <= CHELSIO_T5)
1122 hdr_len |= TXPKT_ETHHDR_LEN_V(eth_hdr_len);
1123 else
1124 hdr_len |= T6_TXPKT_ETHHDR_LEN_V(eth_hdr_len);
1125 return TXPKT_CSUM_TYPE_V(csum_type) | hdr_len;
1126 } else {
1124 int start = skb_transport_offset(skb); 1127 int start = skb_transport_offset(skb);
1125 1128
1126 return TXPKT_CSUM_TYPE_V(csum_type) | 1129 return TXPKT_CSUM_TYPE_V(csum_type) |
@@ -1308,10 +1311,15 @@ int t4vf_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1308 * accounting. 1311 * accounting.
1309 */ 1312 */
1310 cpl = (void *)(lso + 1); 1313 cpl = (void *)(lso + 1);
1311 cntrl = (TXPKT_CSUM_TYPE_V(v6 ? 1314
1315 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
1316 cntrl = TXPKT_ETHHDR_LEN_V(eth_xtra_len);
1317 else
1318 cntrl = T6_TXPKT_ETHHDR_LEN_V(eth_xtra_len);
1319
1320 cntrl |= TXPKT_CSUM_TYPE_V(v6 ?
1312 TX_CSUM_TCPIP6 : TX_CSUM_TCPIP) | 1321 TX_CSUM_TCPIP6 : TX_CSUM_TCPIP) |
1313 TXPKT_IPHDR_LEN_V(l3hdr_len) | 1322 TXPKT_IPHDR_LEN_V(l3hdr_len);
1314 TXPKT_ETHHDR_LEN_V(eth_xtra_len));
1315 txq->tso++; 1323 txq->tso++;
1316 txq->tx_cso += ssi->gso_segs; 1324 txq->tx_cso += ssi->gso_segs;
1317 } else { 1325 } else {
@@ -1328,7 +1336,8 @@ int t4vf_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1328 */ 1336 */
1329 cpl = (void *)(wr + 1); 1337 cpl = (void *)(wr + 1);
1330 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1338 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1331 cntrl = hwcsum(skb) | TXPKT_IPCSUM_DIS_F; 1339 cntrl = hwcsum(adapter->params.chip, skb) |
1340 TXPKT_IPCSUM_DIS_F;
1332 txq->tx_cso++; 1341 txq->tx_cso++;
1333 } else 1342 } else
1334 cntrl = TXPKT_L4CSUM_DIS_F | TXPKT_IPCSUM_DIS_F; 1343 cntrl = TXPKT_L4CSUM_DIS_F | TXPKT_IPCSUM_DIS_F;
@@ -2247,6 +2256,8 @@ int t4vf_sge_alloc_rxq(struct adapter *adapter, struct sge_rspq *rspq,
2247 cmd.iqaddr = cpu_to_be64(rspq->phys_addr); 2256 cmd.iqaddr = cpu_to_be64(rspq->phys_addr);
2248 2257
2249 if (fl) { 2258 if (fl) {
2259 enum chip_type chip =
2260 CHELSIO_CHIP_VERSION(adapter->params.chip);
2250 /* 2261 /*
2251 * Allocate the ring for the hardware free list (with space 2262 * Allocate the ring for the hardware free list (with space
2252 * for its status page) along with the associated software 2263 * for its status page) along with the associated software
@@ -2286,7 +2297,9 @@ int t4vf_sge_alloc_rxq(struct adapter *adapter, struct sge_rspq *rspq,
2286 cmd.fl0dcaen_to_fl0cidxfthresh = 2297 cmd.fl0dcaen_to_fl0cidxfthresh =
2287 cpu_to_be16( 2298 cpu_to_be16(
2288 FW_IQ_CMD_FL0FBMIN_V(SGE_FETCHBURSTMIN_64B) | 2299 FW_IQ_CMD_FL0FBMIN_V(SGE_FETCHBURSTMIN_64B) |
2289 FW_IQ_CMD_FL0FBMAX_V(SGE_FETCHBURSTMAX_512B)); 2300 FW_IQ_CMD_FL0FBMAX_V((chip <= CHELSIO_T5) ?
2301 FETCHBURSTMAX_512B_X :
2302 FETCHBURSTMAX_256B_X));
2290 cmd.fl0size = cpu_to_be16(flsz); 2303 cmd.fl0size = cpu_to_be16(flsz);
2291 cmd.fl0addr = cpu_to_be64(fl->addr); 2304 cmd.fl0addr = cpu_to_be64(fl->addr);
2292 } 2305 }
diff --git a/drivers/net/ethernet/chelsio/cxgb4vf/t4vf_common.h b/drivers/net/ethernet/chelsio/cxgb4vf/t4vf_common.h
index 75df25970d5e..88b8981b4751 100644
--- a/drivers/net/ethernet/chelsio/cxgb4vf/t4vf_common.h
+++ b/drivers/net/ethernet/chelsio/cxgb4vf/t4vf_common.h
@@ -51,6 +51,7 @@
51 */ 51 */
52#define CHELSIO_T4 0x4 52#define CHELSIO_T4 0x4
53#define CHELSIO_T5 0x5 53#define CHELSIO_T5 0x5
54#define CHELSIO_T6 0x6
54 55
55enum chip_type { 56enum chip_type {
56 T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1), 57 T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
@@ -156,6 +157,12 @@ struct vpd_params {
156 u32 cclk; /* Core Clock (KHz) */ 157 u32 cclk; /* Core Clock (KHz) */
157}; 158};
158 159
160/* Stores chip specific parameters */
161struct arch_specific_params {
162 u32 sge_fl_db;
163 u16 mps_tcam_size;
164};
165
159/* 166/*
160 * Global Receive Side Scaling (RSS) parameters in host-native format. 167 * Global Receive Side Scaling (RSS) parameters in host-native format.
161 */ 168 */
@@ -215,6 +222,7 @@ struct adapter_params {
215 struct vpd_params vpd; /* Vital Product Data */ 222 struct vpd_params vpd; /* Vital Product Data */
216 struct rss_params rss; /* Receive Side Scaling */ 223 struct rss_params rss; /* Receive Side Scaling */
217 struct vf_resources vfres; /* Virtual Function Resource limits */ 224 struct vf_resources vfres; /* Virtual Function Resource limits */
225 struct arch_specific_params arch; /* chip specific params */
218 enum chip_type chip; /* chip code */ 226 enum chip_type chip; /* chip code */
219 u8 nports; /* # of Ethernet "ports" */ 227 u8 nports; /* # of Ethernet "ports" */
220}; 228};
diff --git a/drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c b/drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
index 135909ecbc0f..0db6dc9e9ed2 100644
--- a/drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
+++ b/drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
@@ -1191,9 +1191,7 @@ int t4vf_alloc_mac_filt(struct adapter *adapter, unsigned int viid, bool free,
1191 unsigned nfilters = 0; 1191 unsigned nfilters = 0;
1192 unsigned int rem = naddr; 1192 unsigned int rem = naddr;
1193 struct fw_vi_mac_cmd cmd, rpl; 1193 struct fw_vi_mac_cmd cmd, rpl;
1194 unsigned int max_naddr = is_t4(adapter->params.chip) ? 1194 unsigned int max_naddr = adapter->params.arch.mps_tcam_size;
1195 NUM_MPS_CLS_SRAM_L_INSTANCES :
1196 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
1197 1195
1198 if (naddr > max_naddr) 1196 if (naddr > max_naddr)
1199 return -EINVAL; 1197 return -EINVAL;
@@ -1285,9 +1283,7 @@ int t4vf_change_mac(struct adapter *adapter, unsigned int viid,
1285 struct fw_vi_mac_exact *p = &cmd.u.exact[0]; 1283 struct fw_vi_mac_exact *p = &cmd.u.exact[0];
1286 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd, 1284 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
1287 u.exact[1]), 16); 1285 u.exact[1]), 16);
1288 unsigned int max_naddr = is_t4(adapter->params.chip) ? 1286 unsigned int max_mac_addr = adapter->params.arch.mps_tcam_size;
1289 NUM_MPS_CLS_SRAM_L_INSTANCES :
1290 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
1291 1287
1292 /* 1288 /*
1293 * If this is a new allocation, determine whether it should be 1289 * If this is a new allocation, determine whether it should be
@@ -1310,7 +1306,7 @@ int t4vf_change_mac(struct adapter *adapter, unsigned int viid,
1310 if (ret == 0) { 1306 if (ret == 0) {
1311 p = &rpl.u.exact[0]; 1307 p = &rpl.u.exact[0];
1312 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx)); 1308 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
1313 if (ret >= max_naddr) 1309 if (ret >= max_mac_addr)
1314 ret = -ENOMEM; 1310 ret = -ENOMEM;
1315 } 1311 }
1316 return ret; 1312 return ret;
@@ -1590,11 +1586,25 @@ int t4vf_prep_adapter(struct adapter *adapter)
1590 switch (CHELSIO_PCI_ID_VER(adapter->pdev->device)) { 1586 switch (CHELSIO_PCI_ID_VER(adapter->pdev->device)) {
1591 case CHELSIO_T4: 1587 case CHELSIO_T4:
1592 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, 0); 1588 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, 0);
1589 adapter->params.arch.sge_fl_db = DBPRIO_F;
1590 adapter->params.arch.mps_tcam_size =
1591 NUM_MPS_CLS_SRAM_L_INSTANCES;
1593 break; 1592 break;
1594 1593
1595 case CHELSIO_T5: 1594 case CHELSIO_T5:
1596 chipid = REV_G(t4_read_reg(adapter, PL_VF_REV_A)); 1595 chipid = REV_G(t4_read_reg(adapter, PL_VF_REV_A));
1597 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, chipid); 1596 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, chipid);
1597 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
1598 adapter->params.arch.mps_tcam_size =
1599 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
1600 break;
1601
1602 case CHELSIO_T6:
1603 chipid = REV_G(t4_read_reg(adapter, PL_VF_REV_A));
1604 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, chipid);
1605 adapter->params.arch.sge_fl_db = 0;
1606 adapter->params.arch.mps_tcam_size =
1607 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
1598 break; 1608 break;
1599 } 1609 }
1600 1610
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-12 18:21:01 -0400