Merge tag 'davinci-for-v4.11/drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/drivers

Merge "Driver updates for SATA support on DA850." from Sekhar Nori:

These have been acked by SATA maintainer
Tejun Heo. Tejun preferred these be queued
through ARM-SoC because of the dependencies
with platform code.

* tag 'davinci-for-v4.11/drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
  sata: ahci-da850: un-hardcode the MPY bits
  sata: ahci-da850: add a workaround for controller instability
  sata: ahci: export ahci_do_hardreset() locally
  sata: ahci-da850: implement a workaround for the softreset quirk
  sata: ahci-da850: add device tree match table
  sata: ahci-da850: get the sata clock using a connection id

3 files changed, 174 insertions, 22 deletions

diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
index 0cc08f892fea..5db6ab261643 100644
--- a/drivers/ata/ahci.h
+++ b/drivers/ata/ahci.h
@@ -398,6 +398,9 @@ int ahci_do_softreset(struct ata_link *link, unsigned int *class,
                       int pmp, unsigned long deadline,
                       int (*check_ready)(struct ata_link *link));
 
+int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
+                      unsigned long deadline, bool *online);
+
 unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
 int ahci_stop_engine(struct ata_port *ap);
 void ahci_start_fis_rx(struct ata_port *ap);
diff --git a/drivers/ata/ahci_da850.c b/drivers/ata/ahci_da850.c
index 267a3d3e79f4..1a50cd3b4233 100644
--- a/drivers/ata/ahci_da850.c
+++ b/drivers/ata/ahci_da850.c
@@ -16,7 +16,8 @@
 #include <linux/ahci_platform.h>
 #include "ahci.h"
 
-#define DRV_NAME "ahci_da850"
+#define DRV_NAME                "ahci_da850"
+#define HARDRESET_RETRIES       5
 
 /* SATA PHY Control Register offset from AHCI base */
 #define SATA_P0PHYCR_REG        0x178
@@ -28,17 +29,8 @@
 #define SATA_PHY_TXSWING(x)     ((x) << 19)
 #define SATA_PHY_ENPLL(x)       ((x) << 31)
 
-/*
- * The multiplier needed for 1.5GHz PLL output.
- *
- * NOTE: This is currently hardcoded to be suitable for 100MHz crystal
- * frequency (which is used by DA850 EVM board) and may need to be changed
- * if you would like to use this driver on some other board.
- */
-#define DA850_SATA_CLK_MULTIPLIER       7
-
 static void da850_sata_init(struct device *dev, void __iomem *pwrdn_reg,
-                            void __iomem *ahci_base)
+                            void __iomem *ahci_base, u32 mpy)
 {
         unsigned int val;
 
@@ -47,18 +39,122 @@ static void da850_sata_init(struct device *dev, void __iomem *pwrdn_reg,
         val &= ~BIT(0);
         writel(val, pwrdn_reg);
 
-        val = SATA_PHY_MPY(DA850_SATA_CLK_MULTIPLIER + 1) | SATA_PHY_LOS(1) |
-              SATA_PHY_RXCDR(4) | SATA_PHY_RXEQ(1) | SATA_PHY_TXSWING(3) |
-              SATA_PHY_ENPLL(1);
+        val = SATA_PHY_MPY(mpy) | SATA_PHY_LOS(1) | SATA_PHY_RXCDR(4) |
+              SATA_PHY_RXEQ(1) | SATA_PHY_TXSWING(3) | SATA_PHY_ENPLL(1);
 
         writel(val, ahci_base + SATA_P0PHYCR_REG);
 }
 
+static u32 ahci_da850_calculate_mpy(unsigned long refclk_rate)
+{
+        u32 pll_output = 1500000000, needed;
+
+        /*
+         * We need to determine the value of the multiplier (MPY) bits.
+         * In order to include the 12.5 multiplier we need to first divide
+         * the refclk rate by ten.
+         *
+         * __div64_32() turned out to be unreliable, sometimes returning
+         * false results.
+         */
+        WARN((refclk_rate % 10) != 0, "refclk must be divisible by 10");
+        needed = pll_output / (refclk_rate / 10);
+
+        /*
+         * What we have now is (multiplier * 10).
+         *
+         * Let's determine the actual register value we need to write.
+         */
+
+        switch (needed) {
+        case 50:
+                return 0x1;
+        case 60:
+                return 0x2;
+        case 80:
+                return 0x4;
+        case 100:
+                return 0x5;
+        case 120:
+                return 0x6;
+        case 125:
+                return 0x7;
+        case 150:
+                return 0x8;
+        case 200:
+                return 0x9;
+        case 250:
+                return 0xa;
+        default:
+                /*
+                 * We should have divided evenly - if not, return an invalid
+                 * value.
+                 */
+                return 0;
+        }
+}
+
+static int ahci_da850_softreset(struct ata_link *link,
+                                unsigned int *class, unsigned long deadline)
+{
+        int pmp, ret;
+
+        pmp = sata_srst_pmp(link);
+
+        /*
+         * There's an issue with the SATA controller on da850 SoCs: if we
+         * enable Port Multiplier support, but the drive is connected directly
+         * to the board, it can't be detected. As a workaround: if PMP is
+         * enabled, we first call ahci_do_softreset() and pass it the result of
+         * sata_srst_pmp(). If this call fails, we retry with pmp = 0.
+         */
+        ret = ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
+        if (pmp && ret == -EBUSY)
+                return ahci_do_softreset(link, class, 0,
+                                         deadline, ahci_check_ready);
+
+        return ret;
+}
+
+static int ahci_da850_hardreset(struct ata_link *link,
+                                unsigned int *class, unsigned long deadline)
+{
+        int ret, retry = HARDRESET_RETRIES;
+        bool online;
+
+        /*
+         * In order to correctly service the LCD controller of the da850 SoC,
+         * we increased the PLL0 frequency to 456MHz from the default 300MHz.
+         *
+         * This made the SATA controller unstable and the hardreset operation
+         * does not always succeed the first time. Before really giving up to
+         * bring up the link, retry the reset a couple times.
+         */
+        do {
+                ret = ahci_do_hardreset(link, class, deadline, &online);
+                if (online)
+                        return ret;
+        } while (retry--);
+
+        return ret;
+}
+
+static struct ata_port_operations ahci_da850_port_ops = {
+        .inherits = &ahci_platform_ops,
+        .softreset = ahci_da850_softreset,
+        /*
+         * No need to override .pmp_softreset - it's only used for actual
+         * PMP-enabled ports.
+         */
+        .hardreset = ahci_da850_hardreset,
+        .pmp_hardreset = ahci_da850_hardreset,
+};
+
 static const struct ata_port_info ahci_da850_port_info = {
         .flags          = AHCI_FLAG_COMMON,
         .pio_mask       = ATA_PIO4,
         .udma_mask      = ATA_UDMA6,
-        .port_ops       = &ahci_platform_ops,
+        .port_ops       = &ahci_da850_port_ops,
 };
 
 static struct scsi_host_template ahci_platform_sht = {
@@ -69,14 +165,52 @@ static int ahci_da850_probe(struct platform_device *pdev)
 {
         struct device *dev = &pdev->dev;
         struct ahci_host_priv *hpriv;
-        struct resource *res;
         void __iomem *pwrdn_reg;
+        struct resource *res;
+        struct clk *clk;
+        u32 mpy;
         int rc;
 
         hpriv = ahci_platform_get_resources(pdev);
         if (IS_ERR(hpriv))
                 return PTR_ERR(hpriv);
 
+        /*
+         * Internally ahci_platform_get_resources() calls clk_get(dev, NULL)
+         * when trying to obtain the functional clock. This SATA controller
+         * uses two clocks for which we specify two connection ids. If we don't
+         * have the functional clock at this point - call clk_get() again with
+         * con_id = "fck".
+         */
+        if (!hpriv->clks[0]) {
+                clk = clk_get(dev, "fck");
+                if (IS_ERR(clk))
+                        return PTR_ERR(clk);
+
+                hpriv->clks[0] = clk;
+        }
+
+        /*
+         * The second clock used by ahci-da850 is the external REFCLK. If we
+         * didn't get it from ahci_platform_get_resources(), let's try to
+         * specify the con_id in clk_get().
+         */
+        if (!hpriv->clks[1]) {
+                clk = clk_get(dev, "refclk");
+                if (IS_ERR(clk)) {
+                        dev_err(dev, "unable to obtain the reference clock");
+                        return -ENODEV;
+                }
+
+                hpriv->clks[1] = clk;
+        }
+
+        mpy = ahci_da850_calculate_mpy(clk_get_rate(hpriv->clks[1]));
+        if (mpy == 0) {
+                dev_err(dev, "invalid REFCLK multiplier value: 0x%x", mpy);
+                return -EINVAL;
+        }
+
         rc = ahci_platform_enable_resources(hpriv);
         if (rc)
                 return rc;
@@ -89,7 +223,7 @@ static int ahci_da850_probe(struct platform_device *pdev)
         if (!pwrdn_reg)
                 goto disable_resources;
 
-        da850_sata_init(dev, pwrdn_reg, hpriv->mmio);
+        da850_sata_init(dev, pwrdn_reg, hpriv->mmio, mpy);
 
         rc = ahci_platform_init_host(pdev, hpriv, &ahci_da850_port_info,
                                      &ahci_platform_sht);
@@ -105,11 +239,18 @@ disable_resources:
 static SIMPLE_DEV_PM_OPS(ahci_da850_pm_ops, ahci_platform_suspend,
                          ahci_platform_resume);
 
+static const struct of_device_id ahci_da850_of_match[] = {
+        { .compatible = "ti,da850-ahci", },
+        { },
+};
+MODULE_DEVICE_TABLE(of, ahci_da850_of_match);
+
 static struct platform_driver ahci_da850_driver = {
         .probe = ahci_da850_probe,
         .remove = ata_platform_remove_one,
         .driver = {
                 .name = DRV_NAME,
+                .of_match_table = ahci_da850_of_match,
                 .pm = &ahci_da850_pm_ops,
         },
 };
diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c
index ee7db3119b18..3159f9e66d8f 100644
--- a/drivers/ata/libahci.c
+++ b/drivers/ata/libahci.c
@@ -1519,8 +1519,8 @@ static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
         return rc;
 }
 
-static int ahci_hardreset(struct ata_link *link, unsigned int *class,
-                          unsigned long deadline)
+int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
+                      unsigned long deadline, bool *online)
 {
         const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
         struct ata_port *ap = link->ap;
@@ -1528,7 +1528,6 @@ static int ahci_hardreset(struct ata_link *link, unsigned int *class,
         struct ahci_host_priv *hpriv = ap->host->private_data;
         u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
         struct ata_taskfile tf;
-        bool online;
         int rc;
 
         DPRINTK("ENTER\n");
@@ -1540,17 +1539,26 @@ static int ahci_hardreset(struct ata_link *link, unsigned int *class,
         tf.command = ATA_BUSY;
         ata_tf_to_fis(&tf, 0, 0, d2h_fis);
 
-        rc = sata_link_hardreset(link, timing, deadline, &online,
+        rc = sata_link_hardreset(link, timing, deadline, online,
                                  ahci_check_ready);
 
         hpriv->start_engine(ap);
 
-        if (online)
+        if (*online)
                 *class = ahci_dev_classify(ap);
 
         DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
         return rc;
 }
+EXPORT_SYMBOL_GPL(ahci_do_hardreset);
+
+static int ahci_hardreset(struct ata_link *link, unsigned int *class,
+                          unsigned long deadline)
+{
+        bool online;
+
+        return ahci_do_hardreset(link, class, deadline, &online);
+}
 
 static void ahci_postreset(struct ata_link *link, unsigned int *class)
 {