diff options
| author | Feifei Xu <Feifei.Xu@amd.com> | 2017-11-23 02:02:23 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-12-06 12:48:21 -0500 |
| commit | daad67b51e89f50e50ec157bddc57c2c159e43c1 (patch) | |
| tree | ab55e4cd152b22121f5629a0a6e07382f037504a | |
| parent | f0a58aa3f2ca113ff1f435cd186a0d3895a1cafb (diff) | |
drm/amd/include:cleanup vega10 nbif header files.
Cleanup asic_reg/vega10/NBIF folder.
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_offset.h (renamed from drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_offset.h) | 0 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_sh_mask.h (renamed from drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_sh_mask.h) | 0 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_default.h | 1271 |
4 files changed, 1 insertions, 1272 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index 19beff3505fc..c271c6b4b451 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | |||
| @@ -35,7 +35,7 @@ | |||
| 35 | #include "vce/vce_4_0_offset.h" | 35 | #include "vce/vce_4_0_offset.h" |
| 36 | #include "vce/vce_4_0_default.h" | 36 | #include "vce/vce_4_0_default.h" |
| 37 | #include "vce/vce_4_0_sh_mask.h" | 37 | #include "vce/vce_4_0_sh_mask.h" |
| 38 | #include "vega10/NBIF/nbif_6_1_offset.h" | 38 | #include "nbif/nbif_6_1_offset.h" |
| 39 | #include "hdp/hdp_4_0_offset.h" | 39 | #include "hdp/hdp_4_0_offset.h" |
| 40 | #include "mmhub/mmhub_1_0_offset.h" | 40 | #include "mmhub/mmhub_1_0_offset.h" |
| 41 | #include "mmhub/mmhub_1_0_sh_mask.h" | 41 | #include "mmhub/mmhub_1_0_sh_mask.h" |
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_offset.h index 68d0ffad28c7..68d0ffad28c7 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_offset.h | |||
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_sh_mask.h index c7518b84f559..c7518b84f559 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_sh_mask.h | |||
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_default.h deleted file mode 100644 index daa7eaef01b8..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_default.h +++ /dev/null | |||
| @@ -1,1271 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2017 Advanced Micro Devices, Inc. | ||
| 3 | * | ||
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
| 5 | * copy of this software and associated documentation files (the "Software"), | ||
| 6 | * to deal in the Software without restriction, including without limitation | ||
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
| 8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
| 9 | * Software is furnished to do so, subject to the following conditions: | ||
| 10 | * | ||
| 11 | * The above copyright notice and this permission notice shall be included | ||
| 12 | * in all copies or substantial portions of the Software. | ||
| 13 | * | ||
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | ||
| 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
| 17 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN | ||
| 18 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | ||
| 19 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
| 20 | */ | ||
| 21 | #ifndef _nbif_6_1_DEFAULT_HEADER | ||
| 22 | #define _nbif_6_1_DEFAULT_HEADER | ||
| 23 | |||
| 24 | |||
| 25 | // addressBlock: bif_cfg_dev0_epf0_bifcfgdecp | ||
| 26 | // base address: 0x0 | ||
| 27 | #define cfgVENDOR_ID_DEFAULT 0x00000000 | ||
| 28 | #define cfgDEVICE_ID_DEFAULT 0x00000000 | ||
| 29 | #define cfgCOMMAND_DEFAULT 0x00000000 | ||
| 30 | #define cfgSTATUS_DEFAULT 0x00000000 | ||
| 31 | #define cfgREVISION_ID_DEFAULT 0x00000000 | ||
| 32 | #define cfgPROG_INTERFACE_DEFAULT 0x00000000 | ||
| 33 | #define cfgSUB_CLASS_DEFAULT 0x00000000 | ||
| 34 | #define cfgBASE_CLASS_DEFAULT 0x00000000 | ||
| 35 | #define cfgCACHE_LINE_DEFAULT 0x00000000 | ||
| 36 | #define cfgLATENCY_DEFAULT 0x00000000 | ||
| 37 | #define cfgHEADER_DEFAULT 0x00000000 | ||
| 38 | #define cfgBIST_DEFAULT 0x00000000 | ||
| 39 | #define cfgBASE_ADDR_1_DEFAULT 0x00000000 | ||
| 40 | #define cfgBASE_ADDR_2_DEFAULT 0x00000000 | ||
| 41 | #define cfgBASE_ADDR_3_DEFAULT 0x00000000 | ||
| 42 | #define cfgBASE_ADDR_4_DEFAULT 0x00000000 | ||
| 43 | #define cfgBASE_ADDR_5_DEFAULT 0x00000000 | ||
| 44 | #define cfgBASE_ADDR_6_DEFAULT 0x00000000 | ||
| 45 | #define cfgADAPTER_ID_DEFAULT 0x00000000 | ||
| 46 | #define cfgROM_BASE_ADDR_DEFAULT 0x00000000 | ||
| 47 | #define cfgCAP_PTR_DEFAULT 0x00000000 | ||
| 48 | #define cfgINTERRUPT_LINE_DEFAULT 0x000000ff | ||
| 49 | #define cfgINTERRUPT_PIN_DEFAULT 0x00000000 | ||
| 50 | #define cfgMIN_GRANT_DEFAULT 0x00000000 | ||
| 51 | #define cfgMAX_LATENCY_DEFAULT 0x00000000 | ||
| 52 | #define cfgVENDOR_CAP_LIST_DEFAULT 0x00000000 | ||
| 53 | #define cfgADAPTER_ID_W_DEFAULT 0x00000000 | ||
| 54 | #define cfgPMI_CAP_LIST_DEFAULT 0x00000000 | ||
| 55 | #define cfgPMI_CAP_DEFAULT 0x00000000 | ||
| 56 | #define cfgPMI_STATUS_CNTL_DEFAULT 0x00000000 | ||
| 57 | #define cfgPCIE_CAP_LIST_DEFAULT 0x0000a000 | ||
| 58 | #define cfgPCIE_CAP_DEFAULT 0x00000002 | ||
| 59 | #define cfgDEVICE_CAP_DEFAULT 0x10000000 | ||
| 60 | #define cfgDEVICE_CNTL_DEFAULT 0x00002810 | ||
| 61 | #define cfgDEVICE_STATUS_DEFAULT 0x00000000 | ||
| 62 | #define cfgLINK_CAP_DEFAULT 0x00011c03 | ||
| 63 | #define cfgLINK_CNTL_DEFAULT 0x00000000 | ||
| 64 | #define cfgLINK_STATUS_DEFAULT 0x00000001 | ||
| 65 | #define cfgDEVICE_CAP2_DEFAULT 0x00000000 | ||
| 66 | #define cfgDEVICE_CNTL2_DEFAULT 0x00000000 | ||
| 67 | #define cfgDEVICE_STATUS2_DEFAULT 0x00000000 | ||
| 68 | #define cfgLINK_CAP2_DEFAULT 0x0000000e | ||
| 69 | #define cfgLINK_CNTL2_DEFAULT 0x00000003 | ||
| 70 | #define cfgLINK_STATUS2_DEFAULT 0x00000000 | ||
| 71 | #define cfgSLOT_CAP2_DEFAULT 0x00000000 | ||
| 72 | #define cfgSLOT_CNTL2_DEFAULT 0x00000000 | ||
| 73 | #define cfgSLOT_STATUS2_DEFAULT 0x00000000 | ||
| 74 | #define cfgMSI_CAP_LIST_DEFAULT 0x0000c000 | ||
| 75 | #define cfgMSI_MSG_CNTL_DEFAULT 0x00000080 | ||
| 76 | #define cfgMSI_MSG_ADDR_LO_DEFAULT 0x00000000 | ||
| 77 | #define cfgMSI_MSG_ADDR_HI_DEFAULT 0x00000000 | ||
| 78 | #define cfgMSI_MSG_DATA_DEFAULT 0x00000000 | ||
| 79 | #define cfgMSI_MSG_DATA_64_DEFAULT 0x00000000 | ||
| 80 | #define cfgMSI_MASK_DEFAULT 0x00000000 | ||
| 81 | #define cfgMSI_PENDING_DEFAULT 0x00000000 | ||
| 82 | #define cfgMSI_MASK_64_DEFAULT 0x00000000 | ||
| 83 | #define cfgMSI_PENDING_64_DEFAULT 0x00000000 | ||
| 84 | #define cfgMSIX_CAP_LIST_DEFAULT 0x00000000 | ||
| 85 | #define cfgMSIX_MSG_CNTL_DEFAULT 0x00000000 | ||
| 86 | #define cfgMSIX_TABLE_DEFAULT 0x00000000 | ||
| 87 | #define cfgMSIX_PBA_DEFAULT 0x00000000 | ||
| 88 | #define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 | ||
| 89 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 | ||
| 90 | #define cfgPCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 | ||
| 91 | #define cfgPCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 | ||
| 92 | #define cfgPCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 | ||
| 93 | #define cfgPCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 | ||
| 94 | #define cfgPCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 | ||
| 95 | #define cfgPCIE_PORT_VC_CNTL_DEFAULT 0x00000000 | ||
| 96 | #define cfgPCIE_PORT_VC_STATUS_DEFAULT 0x00000000 | ||
| 97 | #define cfgPCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 | ||
| 98 | #define cfgPCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe | ||
| 99 | #define cfgPCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 | ||
| 100 | #define cfgPCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 | ||
| 101 | #define cfgPCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 | ||
| 102 | #define cfgPCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 | ||
| 103 | #define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 | ||
| 104 | #define cfgPCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 | ||
| 105 | #define cfgPCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 | ||
| 106 | #define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 | ||
| 107 | #define cfgPCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 | ||
| 108 | #define cfgPCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 | ||
| 109 | #define cfgPCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 | ||
| 110 | #define cfgPCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 | ||
| 111 | #define cfgPCIE_CORR_ERR_MASK_DEFAULT 0x00002000 | ||
| 112 | #define cfgPCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 | ||
| 113 | #define cfgPCIE_HDR_LOG0_DEFAULT 0x00000000 | ||
| 114 | #define cfgPCIE_HDR_LOG1_DEFAULT 0x00000000 | ||
| 115 | #define cfgPCIE_HDR_LOG2_DEFAULT 0x00000000 | ||
| 116 | #define cfgPCIE_HDR_LOG3_DEFAULT 0x00000000 | ||
| 117 | #define cfgPCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 | ||
| 118 | #define cfgPCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 | ||
| 119 | #define cfgPCIE_ERR_SRC_ID_DEFAULT 0x00000000 | ||
| 120 | #define cfgPCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 | ||
| 121 | #define cfgPCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 | ||
| 122 | #define cfgPCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 | ||
| 123 | #define cfgPCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 | ||
| 124 | #define cfgPCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 | ||
| 125 | #define cfgPCIE_BAR1_CAP_DEFAULT 0x00000000 | ||
| 126 | #define cfgPCIE_BAR1_CNTL_DEFAULT 0x00000020 | ||
| 127 | #define cfgPCIE_BAR2_CAP_DEFAULT 0x00000000 | ||
| 128 | #define cfgPCIE_BAR2_CNTL_DEFAULT 0x00000000 | ||
| 129 | #define cfgPCIE_BAR3_CAP_DEFAULT 0x00000000 | ||
| 130 | #define cfgPCIE_BAR3_CNTL_DEFAULT 0x00000000 | ||
| 131 | #define cfgPCIE_BAR4_CAP_DEFAULT 0x00000000 | ||
| 132 | #define cfgPCIE_BAR4_CNTL_DEFAULT 0x00000000 | ||
| 133 | #define cfgPCIE_BAR5_CAP_DEFAULT 0x00000000 | ||
| 134 | #define cfgPCIE_BAR5_CNTL_DEFAULT 0x00000000 | ||
| 135 | #define cfgPCIE_BAR6_CAP_DEFAULT 0x00000000 | ||
| 136 | #define cfgPCIE_BAR6_CNTL_DEFAULT 0x00000000 | ||
| 137 | #define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 | ||
| 138 | #define cfgPCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 | ||
| 139 | #define cfgPCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 | ||
| 140 | #define cfgPCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 | ||
| 141 | #define cfgPCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 | ||
| 142 | #define cfgPCIE_DPA_CAP_DEFAULT 0x00000000 | ||
| 143 | #define cfgPCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 | ||
| 144 | #define cfgPCIE_DPA_STATUS_DEFAULT 0x00000100 | ||
| 145 | #define cfgPCIE_DPA_CNTL_DEFAULT 0x00000000 | ||
| 146 | #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 | ||
| 147 | #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 | ||
| 148 | #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 | ||
| 149 | #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 | ||
| 150 | #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 | ||
| 151 | #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 | ||
| 152 | #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 | ||
| 153 | #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 | ||
| 154 | #define cfgPCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019 | ||
| 155 | #define cfgPCIE_LINK_CNTL3_DEFAULT 0x00000000 | ||
| 156 | #define cfgPCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 | ||
| 157 | #define cfgPCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00 | ||
| 158 | #define cfgPCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00 | ||
| 159 | #define cfgPCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00 | ||
| 160 | #define cfgPCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00 | ||
| 161 | #define cfgPCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00 | ||
| 162 | #define cfgPCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00 | ||
| 163 | #define cfgPCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00 | ||
| 164 | #define cfgPCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00 | ||
| 165 | #define cfgPCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00 | ||
| 166 | #define cfgPCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00 | ||
| 167 | #define cfgPCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00 | ||
| 168 | #define cfgPCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00 | ||
| 169 | #define cfgPCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00 | ||
| 170 | #define cfgPCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00 | ||
| 171 | #define cfgPCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00 | ||
| 172 | #define cfgPCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00 | ||
| 173 | #define cfgPCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 | ||
| 174 | #define cfgPCIE_ACS_CAP_DEFAULT 0x00000000 | ||
| 175 | #define cfgPCIE_ACS_CNTL_DEFAULT 0x00000000 | ||
| 176 | #define cfgPCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 | ||
| 177 | #define cfgPCIE_ATS_CAP_DEFAULT 0x00000000 | ||
| 178 | #define cfgPCIE_ATS_CNTL_DEFAULT 0x00000000 | ||
| 179 | #define cfgPCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000 | ||
| 180 | #define cfgPCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000 | ||
| 181 | #define cfgPCIE_PAGE_REQ_STATUS_DEFAULT 0x00000000 | ||
| 182 | #define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000 | ||
| 183 | #define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000 | ||
| 184 | #define cfgPCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2e000000 | ||
| 185 | #define cfgPCIE_PASID_CAP_DEFAULT 0x00000000 | ||
| 186 | #define cfgPCIE_PASID_CNTL_DEFAULT 0x00000000 | ||
| 187 | #define cfgPCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x2f000000 | ||
| 188 | #define cfgPCIE_TPH_REQR_CAP_DEFAULT 0x00000000 | ||
| 189 | #define cfgPCIE_TPH_REQR_CNTL_DEFAULT 0x00000000 | ||
| 190 | #define cfgPCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 | ||
| 191 | #define cfgPCIE_MC_CAP_DEFAULT 0x00000000 | ||
| 192 | #define cfgPCIE_MC_CNTL_DEFAULT 0x00000000 | ||
| 193 | #define cfgPCIE_MC_ADDR0_DEFAULT 0x00000000 | ||
| 194 | #define cfgPCIE_MC_ADDR1_DEFAULT 0x00000000 | ||
| 195 | #define cfgPCIE_MC_RCV0_DEFAULT 0x00000000 | ||
| 196 | #define cfgPCIE_MC_RCV1_DEFAULT 0x00000000 | ||
| 197 | #define cfgPCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 | ||
| 198 | #define cfgPCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 | ||
| 199 | #define cfgPCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 | ||
| 200 | #define cfgPCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 | ||
| 201 | #define cfgPCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000 | ||
| 202 | #define cfgPCIE_LTR_CAP_DEFAULT 0x00000000 | ||
| 203 | #define cfgPCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 | ||
| 204 | #define cfgPCIE_ARI_CAP_DEFAULT 0x00000000 | ||
| 205 | #define cfgPCIE_ARI_CNTL_DEFAULT 0x00000000 | ||
| 206 | #define cfgPCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x00000000 | ||
| 207 | #define cfgPCIE_SRIOV_CAP_DEFAULT 0x00000000 | ||
| 208 | #define cfgPCIE_SRIOV_CONTROL_DEFAULT 0x00000000 | ||
| 209 | #define cfgPCIE_SRIOV_STATUS_DEFAULT 0x00000000 | ||
| 210 | #define cfgPCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000 | ||
| 211 | #define cfgPCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000 | ||
| 212 | #define cfgPCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000 | ||
| 213 | #define cfgPCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000 | ||
| 214 | #define cfgPCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000 | ||
| 215 | #define cfgPCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000 | ||
| 216 | #define cfgPCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000 | ||
| 217 | #define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000000 | ||
| 218 | #define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001 | ||
| 219 | #define cfgPCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000 | ||
| 220 | #define cfgPCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000 | ||
| 221 | #define cfgPCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000 | ||
| 222 | #define cfgPCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000 | ||
| 223 | #define cfgPCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000 | ||
| 224 | #define cfgPCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000 | ||
| 225 | #define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000 | ||
| 226 | #define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000 | ||
| 227 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000 | ||
| 228 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000 | ||
| 229 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000 | ||
| 230 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000 | ||
| 231 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000 | ||
| 232 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000 | ||
| 233 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000 | ||
| 234 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000 | ||
| 235 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000 | ||
| 236 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000 | ||
| 237 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x00000000 | ||
| 238 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000 | ||
| 239 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000 | ||
| 240 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000 | ||
| 241 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000 | ||
| 242 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000 | ||
| 243 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000 | ||
| 244 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000 | ||
| 245 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000 | ||
| 246 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000 | ||
| 247 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000 | ||
| 248 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000 | ||
| 249 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000 | ||
| 250 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000 | ||
| 251 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000 | ||
| 252 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000 | ||
| 253 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000 | ||
| 254 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000 | ||
| 255 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000 | ||
| 256 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000 | ||
| 257 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000 | ||
| 258 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000 | ||
| 259 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000 | ||
| 260 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000 | ||
| 261 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000 | ||
| 262 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000 | ||
| 263 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000 | ||
| 264 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000 | ||
| 265 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000 | ||
| 266 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000 | ||
| 267 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000 | ||
| 268 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000 | ||
| 269 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000 | ||
| 270 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000 | ||
| 271 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000 | ||
| 272 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000 | ||
| 273 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000 | ||
| 274 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000 | ||
| 275 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000 | ||
| 276 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000 | ||
| 277 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000 | ||
| 278 | |||
| 279 | |||
| 280 | // addressBlock: bif_cfg_dev0_swds_bifcfgdecp | ||
| 281 | // base address: 0x0 | ||
| 282 | #define mmSUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 | ||
| 283 | #define mmIO_BASE_LIMIT_DEFAULT 0x00000000 | ||
| 284 | #define mmSECONDARY_STATUS_DEFAULT 0x00000000 | ||
| 285 | #define mmMEM_BASE_LIMIT_DEFAULT 0x00000000 | ||
| 286 | #define mmPREF_BASE_LIMIT_DEFAULT 0x00000000 | ||
| 287 | #define mmPREF_BASE_UPPER_DEFAULT 0x00000000 | ||
| 288 | #define mmPREF_LIMIT_UPPER_DEFAULT 0x00000000 | ||
| 289 | #define mmIO_BASE_LIMIT_HI_DEFAULT 0x00000000 | ||
| 290 | #define mmIRQ_BRIDGE_CNTL_DEFAULT 0x00000000 | ||
| 291 | #define mmSLOT_CAP_DEFAULT 0x00000000 | ||
| 292 | #define mmSLOT_CNTL_DEFAULT 0x00000000 | ||
| 293 | #define mmSLOT_STATUS_DEFAULT 0x00000000 | ||
| 294 | #define mmSSID_CAP_LIST_DEFAULT 0x00000000 | ||
| 295 | #define mmSSID_CAP_DEFAULT 0x00000000 | ||
| 296 | |||
| 297 | |||
| 298 | // addressBlock: rcc_shadow_reg_shadowdec | ||
| 299 | // base address: 0x0 | ||
| 300 | #define ixSHADOW_COMMAND_DEFAULT 0x00000000 | ||
| 301 | #define ixSHADOW_BASE_ADDR_1_DEFAULT 0x00000000 | ||
| 302 | #define ixSHADOW_BASE_ADDR_2_DEFAULT 0x00000000 | ||
| 303 | #define ixSHADOW_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 | ||
| 304 | #define ixSHADOW_IO_BASE_LIMIT_DEFAULT 0x00000000 | ||
| 305 | #define ixSHADOW_MEM_BASE_LIMIT_DEFAULT 0x00000000 | ||
| 306 | #define ixSHADOW_PREF_BASE_LIMIT_DEFAULT 0x00000000 | ||
| 307 | #define ixSHADOW_PREF_BASE_UPPER_DEFAULT 0x00000000 | ||
| 308 | #define ixSHADOW_PREF_LIMIT_UPPER_DEFAULT 0x00000000 | ||
| 309 | #define ixSHADOW_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 | ||
| 310 | #define ixSHADOW_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 | ||
| 311 | #define ixSUC_INDEX_DEFAULT 0x00000000 | ||
| 312 | #define ixSUC_DATA_DEFAULT 0x00000000 | ||
| 313 | |||
| 314 | |||
| 315 | // addressBlock: bif_bx_pf_SUMDEC | ||
| 316 | // base address: 0x0 | ||
| 317 | #define ixSUM_INDEX_DEFAULT 0x00000000 | ||
| 318 | #define ixSUM_DATA_DEFAULT 0x00000000 | ||
| 319 | |||
| 320 | |||
| 321 | // addressBlock: gdc_GDCDEC | ||
| 322 | // base address: 0x1400000 | ||
| 323 | #define mmA2S_CNTL_CL0_DEFAULT 0x00280540 | ||
| 324 | #define mmA2S_CNTL_CL1_DEFAULT 0x00282540 | ||
| 325 | #define mmA2S_CNTL_CL2_DEFAULT 0x002825a0 | ||
| 326 | #define mmA2S_CNTL_CL3_DEFAULT 0x00282550 | ||
| 327 | #define mmA2S_CNTL_CL4_DEFAULT 0x00282550 | ||
| 328 | #define mmA2S_CNTL_SW0_DEFAULT 0x08080005 | ||
| 329 | #define mmA2S_CNTL_SW1_DEFAULT 0x08080205 | ||
| 330 | #define mmA2S_CNTL_SW2_DEFAULT 0x08080200 | ||
| 331 | #define mmNGDC_MGCG_CTRL_DEFAULT 0x00000080 | ||
| 332 | #define mmA2S_MISC_CNTL_DEFAULT 0x00000003 | ||
| 333 | #define mmNGDC_SDP_PORT_CTRL_DEFAULT 0x0000000f | ||
| 334 | #define mmNGDC_RESERVED_0_DEFAULT 0x00000000 | ||
| 335 | #define mmNGDC_RESERVED_1_DEFAULT 0x00000000 | ||
| 336 | #define mmBIF_SDMA0_DOORBELL_RANGE_DEFAULT 0x00000000 | ||
| 337 | #define mmBIF_SDMA1_DOORBELL_RANGE_DEFAULT 0x00000000 | ||
| 338 | #define mmBIF_IH_DOORBELL_RANGE_DEFAULT 0x00000000 | ||
| 339 | #define mmBIF_MMSCH0_DOORBELL_RANGE_DEFAULT 0x00000000 | ||
| 340 | #define mmBIF_DOORBELL_FENCE_CNTL_DEFAULT 0x00000000 | ||
| 341 | #define mmS2A_MISC_CNTL_DEFAULT 0x00000000 | ||
| 342 | #define mmA2S_CNTL2_SEC_CL0_DEFAULT 0x00000006 | ||
| 343 | #define mmA2S_CNTL2_SEC_CL1_DEFAULT 0x00000006 | ||
| 344 | #define mmA2S_CNTL2_SEC_CL2_DEFAULT 0x00000006 | ||
| 345 | #define mmA2S_CNTL2_SEC_CL3_DEFAULT 0x00000006 | ||
| 346 | #define mmA2S_CNTL2_SEC_CL4_DEFAULT 0x00000006 | ||
| 347 | |||
| 348 | |||
| 349 | // addressBlock: nbif_sion_SIONDEC | ||
| 350 | // base address: 0x1400000 | ||
| 351 | #define ixSION_CL0_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 | ||
| 352 | #define ixSION_CL0_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 | ||
| 353 | #define ixSION_CL0_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 | ||
| 354 | #define ixSION_CL0_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 | ||
| 355 | #define ixSION_CL0_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 | ||
| 356 | #define ixSION_CL0_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 | ||
| 357 | #define ixSION_CL0_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 | ||
| 358 | #define ixSION_CL0_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 | ||
| 359 | #define ixSION_CL0_Req_BurstTarget_REG0_DEFAULT 0x00000000 | ||
| 360 | #define ixSION_CL0_Req_BurstTarget_REG1_DEFAULT 0x00000000 | ||
| 361 | #define ixSION_CL0_Req_TimeSlot_REG0_DEFAULT 0x00000000 | ||
| 362 | #define ixSION_CL0_Req_TimeSlot_REG1_DEFAULT 0x00000000 | ||
| 363 | #define ixSION_CL0_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 | ||
| 364 | #define ixSION_CL0_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 | ||
| 365 | #define ixSION_CL0_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 | ||
| 366 | #define ixSION_CL0_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 | ||
| 367 | #define ixSION_CL0_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 | ||
| 368 | #define ixSION_CL0_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 | ||
| 369 | #define ixSION_CL0_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 | ||
| 370 | #define ixSION_CL0_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 | ||
| 371 | #define ixSION_CL1_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 | ||
| 372 | #define ixSION_CL1_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 | ||
| 373 | #define ixSION_CL1_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 | ||
| 374 | #define ixSION_CL1_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 | ||
| 375 | #define ixSION_CL1_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 | ||
| 376 | #define ixSION_CL1_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 | ||
| 377 | #define ixSION_CL1_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 | ||
| 378 | #define ixSION_CL1_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 | ||
| 379 | #define ixSION_CL1_Req_BurstTarget_REG0_DEFAULT 0x00000000 | ||
| 380 | #define ixSION_CL1_Req_BurstTarget_REG1_DEFAULT 0x00000000 | ||
| 381 | #define ixSION_CL1_Req_TimeSlot_REG0_DEFAULT 0x00000000 | ||
| 382 | #define ixSION_CL1_Req_TimeSlot_REG1_DEFAULT 0x00000000 | ||
| 383 | #define ixSION_CL1_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 | ||
| 384 | #define ixSION_CL1_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 | ||
| 385 | #define ixSION_CL1_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 | ||
| 386 | #define ixSION_CL1_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 | ||
| 387 | #define ixSION_CL1_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 | ||
| 388 | #define ixSION_CL1_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 | ||
| 389 | #define ixSION_CL1_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 | ||
| 390 | #define ixSION_CL1_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 | ||
| 391 | #define ixSION_CL2_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 | ||
| 392 | #define ixSION_CL2_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 | ||
| 393 | #define ixSION_CL2_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 | ||
| 394 | #define ixSION_CL2_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 | ||
| 395 | #define ixSION_CL2_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 | ||
| 396 | #define ixSION_CL2_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 | ||
| 397 | #define ixSION_CL2_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 | ||
| 398 | #define ixSION_CL2_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 | ||
| 399 | #define ixSION_CL2_Req_BurstTarget_REG0_DEFAULT 0x00000000 | ||
| 400 | #define ixSION_CL2_Req_BurstTarget_REG1_DEFAULT 0x00000000 | ||
| 401 | #define ixSION_CL2_Req_TimeSlot_REG0_DEFAULT 0x00000000 | ||
| 402 | #define ixSION_CL2_Req_TimeSlot_REG1_DEFAULT 0x00000000 | ||
| 403 | #define ixSION_CL2_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 | ||
| 404 | #define ixSION_CL2_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 | ||
| 405 | #define ixSION_CL2_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 | ||
| 406 | #define ixSION_CL2_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 | ||
| 407 | #define ixSION_CL2_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 | ||
| 408 | #define ixSION_CL2_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 | ||
| 409 | #define ixSION_CL2_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 | ||
| 410 | #define ixSION_CL2_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 | ||
| 411 | #define ixSION_CL3_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 | ||
| 412 | #define ixSION_CL3_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 | ||
| 413 | #define ixSION_CL3_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 | ||
| 414 | #define ixSION_CL3_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 | ||
| 415 | #define ixSION_CL3_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 | ||
| 416 | #define ixSION_CL3_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 | ||
| 417 | #define ixSION_CL3_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 | ||
| 418 | #define ixSION_CL3_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 | ||
| 419 | #define ixSION_CL3_Req_BurstTarget_REG0_DEFAULT 0x00000000 | ||
| 420 | #define ixSION_CL3_Req_BurstTarget_REG1_DEFAULT 0x00000000 | ||
| 421 | #define ixSION_CL3_Req_TimeSlot_REG0_DEFAULT 0x00000000 | ||
| 422 | #define ixSION_CL3_Req_TimeSlot_REG1_DEFAULT 0x00000000 | ||
| 423 | #define ixSION_CL3_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 | ||
| 424 | #define ixSION_CL3_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 | ||
| 425 | #define ixSION_CL3_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 | ||
| 426 | #define ixSION_CL3_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 | ||
| 427 | #define ixSION_CL3_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 | ||
| 428 | #define ixSION_CL3_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 | ||
| 429 | #define ixSION_CL3_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 | ||
| 430 | #define ixSION_CL3_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 | ||
| 431 | #define ixSION_CL4_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 | ||
| 432 | #define ixSION_CL4_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 | ||
| 433 | #define ixSION_CL4_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 | ||
| 434 | #define ixSION_CL4_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 | ||
| 435 | #define ixSION_CL4_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 | ||
| 436 | #define ixSION_CL4_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 | ||
| 437 | #define ixSION_CL4_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 | ||
| 438 | #define ixSION_CL4_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 | ||
| 439 | #define ixSION_CL4_Req_BurstTarget_REG0_DEFAULT 0x00000000 | ||
| 440 | #define ixSION_CL4_Req_BurstTarget_REG1_DEFAULT 0x00000000 | ||
| 441 | #define ixSION_CL4_Req_TimeSlot_REG0_DEFAULT 0x00000000 | ||
| 442 | #define ixSION_CL4_Req_TimeSlot_REG1_DEFAULT 0x00000000 | ||
| 443 | #define ixSION_CL4_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 | ||
| 444 | #define ixSION_CL4_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 | ||
| 445 | #define ixSION_CL4_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 | ||
| 446 | #define ixSION_CL4_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 | ||
| 447 | #define ixSION_CL4_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 | ||
| 448 | #define ixSION_CL4_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 | ||
| 449 | #define ixSION_CL4_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 | ||
| 450 | #define ixSION_CL4_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 | ||
| 451 | #define ixSION_CL5_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 | ||
| 452 | #define ixSION_CL5_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 | ||
| 453 | #define ixSION_CL5_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 | ||
| 454 | #define ixSION_CL5_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 | ||
| 455 | #define ixSION_CL5_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 | ||
| 456 | #define ixSION_CL5_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 | ||
| 457 | #define ixSION_CL5_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 | ||
| 458 | #define ixSION_CL5_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 | ||
| 459 | #define ixSION_CL5_Req_BurstTarget_REG0_DEFAULT 0x00000000 | ||
| 460 | #define ixSION_CL5_Req_BurstTarget_REG1_DEFAULT 0x00000000 | ||
| 461 | #define ixSION_CL5_Req_TimeSlot_REG0_DEFAULT 0x00000000 | ||
| 462 | #define ixSION_CL5_Req_TimeSlot_REG1_DEFAULT 0x00000000 | ||
| 463 | #define ixSION_CL5_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 | ||
| 464 | #define ixSION_CL5_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 | ||
| 465 | #define ixSION_CL5_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 | ||
| 466 | #define ixSION_CL5_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 | ||
| 467 | #define ixSION_CL5_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 | ||
| 468 | #define ixSION_CL5_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 | ||
| 469 | #define ixSION_CL5_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 | ||
| 470 | #define ixSION_CL5_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 | ||
| 471 | #define ixSION_CNTL_REG0_DEFAULT 0x00000000 | ||
| 472 | #define ixSION_CNTL_REG1_DEFAULT 0x00000000 | ||
| 473 | |||
| 474 | |||
| 475 | // addressBlock: syshub_mmreg_direct_syshubdirect | ||
| 476 | // base address: 0x1400000 | ||
| 477 | #define ixSYSHUB_DS_CTRL_SOCCLK_DEFAULT 0x00000000 | ||
| 478 | #define ixSYSHUB_DS_CTRL2_SOCCLK_DEFAULT 0x00000100 | ||
| 479 | #define ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK_DEFAULT 0x00000000 | ||
| 480 | #define ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK_DEFAULT 0x00000000 | ||
| 481 | #define ixDMA_CLK0_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e | ||
| 482 | #define ixDMA_CLK0_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e | ||
| 483 | #define ixDMA_CLK0_SW0_CL0_CNTL_DEFAULT 0x20200000 | ||
| 484 | #define ixDMA_CLK0_SW0_CL1_CNTL_DEFAULT 0x20200000 | ||
| 485 | #define ixDMA_CLK0_SW0_CL2_CNTL_DEFAULT 0x20200000 | ||
| 486 | #define ixDMA_CLK0_SW0_CL3_CNTL_DEFAULT 0x20200000 | ||
| 487 | #define ixDMA_CLK0_SW0_CL4_CNTL_DEFAULT 0x20200000 | ||
| 488 | #define ixDMA_CLK0_SW0_CL5_CNTL_DEFAULT 0x20200000 | ||
| 489 | #define ixDMA_CLK0_SW1_CL0_CNTL_DEFAULT 0x20200000 | ||
| 490 | #define ixDMA_CLK0_SW2_CL0_CNTL_DEFAULT 0x20200000 | ||
| 491 | #define ixSYSHUB_CG_CNTL_DEFAULT 0x00082000 | ||
| 492 | #define ixSYSHUB_TRANS_IDLE_DEFAULT 0x00000000 | ||
| 493 | #define ixSYSHUB_HP_TIMER_DEFAULT 0x00000100 | ||
| 494 | #define ixSYSHUB_SCRATCH_DEFAULT 0x00000040 | ||
| 495 | #define ixSYSHUB_DS_CTRL_SHUBCLK_DEFAULT 0x00000000 | ||
| 496 | #define ixSYSHUB_DS_CTRL2_SHUBCLK_DEFAULT 0x00000100 | ||
| 497 | #define ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK_DEFAULT 0x00000000 | ||
| 498 | #define ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK_DEFAULT 0x00000000 | ||
| 499 | #define ixDMA_CLK1_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e | ||
| 500 | #define ixDMA_CLK1_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e | ||
| 501 | #define ixDMA_CLK1_SW0_CL0_CNTL_DEFAULT 0x20200000 | ||
| 502 | #define ixDMA_CLK1_SW0_CL1_CNTL_DEFAULT 0x20200000 | ||
| 503 | #define ixDMA_CLK1_SW0_CL2_CNTL_DEFAULT 0x20200000 | ||
| 504 | #define ixDMA_CLK1_SW0_CL3_CNTL_DEFAULT 0x20200000 | ||
| 505 | #define ixDMA_CLK1_SW0_CL4_CNTL_DEFAULT 0x20200000 | ||
| 506 | #define ixDMA_CLK1_SW1_CL0_CNTL_DEFAULT 0x20200000 | ||
| 507 | #define ixDMA_CLK1_SW1_CL1_CNTL_DEFAULT 0x20200000 | ||
| 508 | #define ixDMA_CLK1_SW1_CL2_CNTL_DEFAULT 0x20200000 | ||
| 509 | #define ixDMA_CLK1_SW1_CL3_CNTL_DEFAULT 0x20200000 | ||
| 510 | #define ixDMA_CLK1_SW1_CL4_CNTL_DEFAULT 0x20200000 | ||
| 511 | |||
| 512 | |||
| 513 | // addressBlock: gdc_ras_gdc_ras_regblk | ||
| 514 | // base address: 0x1400000 | ||
| 515 | #define ixGDC_RAS_LEAF0_CTRL_DEFAULT 0x00000000 | ||
| 516 | #define ixGDC_RAS_LEAF1_CTRL_DEFAULT 0x00000000 | ||
| 517 | #define ixGDC_RAS_LEAF2_CTRL_DEFAULT 0x00000000 | ||
| 518 | #define ixGDC_RAS_LEAF3_CTRL_DEFAULT 0x00000000 | ||
| 519 | #define ixGDC_RAS_LEAF4_CTRL_DEFAULT 0x00000000 | ||
| 520 | #define ixGDC_RAS_LEAF5_CTRL_DEFAULT 0x00000000 | ||
| 521 | |||
| 522 | |||
| 523 | // addressBlock: gdc_rst_GDCRST_DEC | ||
| 524 | // base address: 0x1400000 | ||
| 525 | #define ixSHUB_PF_FLR_RST_DEFAULT 0x00000000 | ||
| 526 | #define ixSHUB_GFX_DRV_MODE1_RST_DEFAULT 0x00000000 | ||
| 527 | #define ixSHUB_LINK_RESET_DEFAULT 0x00000000 | ||
| 528 | #define ixSHUB_PF0_VF_FLR_RST_DEFAULT 0x00000000 | ||
| 529 | #define ixSHUB_HARD_RST_CTRL_DEFAULT 0x0000001b | ||
| 530 | #define ixSHUB_SOFT_RST_CTRL_DEFAULT 0x00000009 | ||
| 531 | #define ixSHUB_SDP_PORT_RST_DEFAULT 0x00000000 | ||
| 532 | |||
| 533 | |||
| 534 | // addressBlock: bif_bx_pf_SYSDEC | ||
| 535 | // base address: 0x0 | ||
| 536 | #define mmSBIOS_SCRATCH_0_DEFAULT 0x00000000 | ||
| 537 | #define mmSBIOS_SCRATCH_1_DEFAULT 0x00000000 | ||
| 538 | #define mmSBIOS_SCRATCH_2_DEFAULT 0x00000000 | ||
| 539 | #define mmSBIOS_SCRATCH_3_DEFAULT 0x00000000 | ||
| 540 | #define mmBIOS_SCRATCH_0_DEFAULT 0x00000000 | ||
| 541 | #define mmBIOS_SCRATCH_1_DEFAULT 0x00000000 | ||
| 542 | #define mmBIOS_SCRATCH_2_DEFAULT 0x00000000 | ||
| 543 | #define mmBIOS_SCRATCH_3_DEFAULT 0x00000000 | ||
| 544 | #define mmBIOS_SCRATCH_4_DEFAULT 0x00000000 | ||
| 545 | #define mmBIOS_SCRATCH_5_DEFAULT 0x00000000 | ||
| 546 | #define mmBIOS_SCRATCH_6_DEFAULT 0x00000000 | ||
| 547 | #define mmBIOS_SCRATCH_7_DEFAULT 0x00000000 | ||
| 548 | #define mmBIOS_SCRATCH_8_DEFAULT 0x00000000 | ||
| 549 | #define mmBIOS_SCRATCH_9_DEFAULT 0x00000000 | ||
| 550 | #define mmBIOS_SCRATCH_10_DEFAULT 0x00000000 | ||
| 551 | #define mmBIOS_SCRATCH_11_DEFAULT 0x00000000 | ||
| 552 | #define mmBIOS_SCRATCH_12_DEFAULT 0x00000000 | ||
| 553 | #define mmBIOS_SCRATCH_13_DEFAULT 0x00000000 | ||
| 554 | #define mmBIOS_SCRATCH_14_DEFAULT 0x00000000 | ||
| 555 | #define mmBIOS_SCRATCH_15_DEFAULT 0x00000000 | ||
| 556 | #define mmBIF_RLC_INTR_CNTL_DEFAULT 0x00000000 | ||
| 557 | #define mmBIF_VCE_INTR_CNTL_DEFAULT 0x00000000 | ||
| 558 | #define mmBIF_UVD_INTR_CNTL_DEFAULT 0x00000000 | ||
| 559 | #define mmGFX_MMIOREG_CAM_ADDR0_DEFAULT 0x00000000 | ||
| 560 | #define mmGFX_MMIOREG_CAM_REMAP_ADDR0_DEFAULT 0x00000000 | ||
| 561 | #define mmGFX_MMIOREG_CAM_ADDR1_DEFAULT 0x00000000 | ||
| 562 | #define mmGFX_MMIOREG_CAM_REMAP_ADDR1_DEFAULT 0x00000000 | ||
| 563 | #define mmGFX_MMIOREG_CAM_ADDR2_DEFAULT 0x00000000 | ||
| 564 | #define mmGFX_MMIOREG_CAM_REMAP_ADDR2_DEFAULT 0x00000000 | ||
| 565 | #define mmGFX_MMIOREG_CAM_ADDR3_DEFAULT 0x00000000 | ||
| 566 | #define mmGFX_MMIOREG_CAM_REMAP_ADDR3_DEFAULT 0x00000000 | ||
| 567 | #define mmGFX_MMIOREG_CAM_ADDR4_DEFAULT 0x00000000 | ||
| 568 | #define mmGFX_MMIOREG_CAM_REMAP_ADDR4_DEFAULT 0x00000000 | ||
| 569 | #define mmGFX_MMIOREG_CAM_ADDR5_DEFAULT 0x00000000 | ||
| 570 | #define mmGFX_MMIOREG_CAM_REMAP_ADDR5_DEFAULT 0x00000000 | ||
| 571 | #define mmGFX_MMIOREG_CAM_ADDR6_DEFAULT 0x00000000 | ||
| 572 | #define mmGFX_MMIOREG_CAM_REMAP_ADDR6_DEFAULT 0x00000000 | ||
| 573 | #define mmGFX_MMIOREG_CAM_ADDR7_DEFAULT 0x00000000 | ||
| 574 | #define mmGFX_MMIOREG_CAM_REMAP_ADDR7_DEFAULT 0x00000000 | ||
| 575 | #define mmGFX_MMIOREG_CAM_CNTL_DEFAULT 0x00000000 | ||
| 576 | #define mmGFX_MMIOREG_CAM_ZERO_CPL_DEFAULT 0x00000000 | ||
| 577 | #define mmGFX_MMIOREG_CAM_ONE_CPL_DEFAULT 0x00000000 | ||
| 578 | #define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_DEFAULT 0x00000000 | ||
| 579 | |||
| 580 | |||
| 581 | // addressBlock: bif_bx_pf_SYSPFVFDEC | ||
| 582 | // base address: 0x0 | ||
| 583 | #define mmMM_INDEX_DEFAULT 0x00000000 | ||
| 584 | #define mmMM_DATA_DEFAULT 0x00000000 | ||
| 585 | #define mmMM_INDEX_HI_DEFAULT 0x00000000 | ||
| 586 | #define mmSYSHUB_INDEX_OVLP_DEFAULT 0x00000000 | ||
| 587 | #define mmSYSHUB_DATA_OVLP_DEFAULT 0x00000000 | ||
| 588 | #define mmPCIE_INDEX_DEFAULT 0x00000000 | ||
| 589 | #define mmPCIE_DATA_DEFAULT 0x00000000 | ||
| 590 | #define mmPCIE_INDEX2_DEFAULT 0x00000000 | ||
| 591 | #define mmPCIE_DATA2_DEFAULT 0x00000000 | ||
| 592 | |||
| 593 | |||
| 594 | // addressBlock: rcc_dwn_BIFDEC1 | ||
| 595 | // base address: 0x0 | ||
| 596 | #define mmDN_PCIE_RESERVED_DEFAULT 0x00000000 | ||
| 597 | #define mmDN_PCIE_SCRATCH_DEFAULT 0x00000000 | ||
| 598 | #define mmDN_PCIE_CNTL_DEFAULT 0x00000000 | ||
| 599 | #define mmDN_PCIE_CONFIG_CNTL_DEFAULT 0x00000000 | ||
| 600 | #define mmDN_PCIE_RX_CNTL2_DEFAULT 0x00000000 | ||
| 601 | #define mmDN_PCIE_BUS_CNTL_DEFAULT 0x00000080 | ||
| 602 | #define mmDN_PCIE_CFG_CNTL_DEFAULT 0x00000000 | ||
| 603 | #define mmDN_PCIE_STRAP_F0_DEFAULT 0x00000001 | ||
| 604 | #define mmDN_PCIE_STRAP_MISC_DEFAULT 0x00000000 | ||
| 605 | #define mmDN_PCIE_STRAP_MISC2_DEFAULT 0x00000000 | ||
| 606 | |||
| 607 | |||
| 608 | // addressBlock: rcc_dwnp_BIFDEC1 | ||
| 609 | // base address: 0x0 | ||
| 610 | #define mmPCIEP_RESERVED_DEFAULT 0x00000000 | ||
| 611 | #define mmPCIEP_SCRATCH_DEFAULT 0x00000000 | ||
| 612 | #define mmPCIE_ERR_CNTL_DEFAULT 0x00000500 | ||
| 613 | #define mmPCIE_RX_CNTL_DEFAULT 0x00000000 | ||
| 614 | #define mmPCIE_LC_SPEED_CNTL_DEFAULT 0x00000000 | ||
| 615 | #define mmPCIE_LC_CNTL2_DEFAULT 0x00000000 | ||
| 616 | #define mmPCIEP_STRAP_MISC_DEFAULT 0x00000000 | ||
| 617 | #define mmLTR_MSG_INFO_FROM_EP_DEFAULT 0x00000000 | ||
| 618 | |||
| 619 | |||
| 620 | // addressBlock: rcc_ep_BIFDEC1 | ||
| 621 | // base address: 0x0 | ||
| 622 | #define mmEP_PCIE_SCRATCH_DEFAULT 0x00000000 | ||
| 623 | #define mmEP_PCIE_CNTL_DEFAULT 0x00000100 | ||
| 624 | #define mmEP_PCIE_INT_CNTL_DEFAULT 0x00000000 | ||
| 625 | #define mmEP_PCIE_INT_STATUS_DEFAULT 0x00000000 | ||
| 626 | #define mmEP_PCIE_RX_CNTL2_DEFAULT 0x00000000 | ||
| 627 | #define mmEP_PCIE_BUS_CNTL_DEFAULT 0x00000080 | ||
| 628 | #define mmEP_PCIE_CFG_CNTL_DEFAULT 0x00000000 | ||
| 629 | #define mmEP_PCIE_OBFF_CNTL_DEFAULT 0x00012774 | ||
| 630 | #define mmEP_PCIE_TX_LTR_CNTL_DEFAULT 0x00003468 | ||
| 631 | #define mmEP_PCIE_STRAP_MISC_DEFAULT 0x00000000 | ||
| 632 | #define mmEP_PCIE_STRAP_MISC2_DEFAULT 0x00000000 | ||
| 633 | #define mmEP_PCIE_STRAP_PI_DEFAULT 0x00000000 | ||
| 634 | #define mmEP_PCIE_F0_DPA_CAP_DEFAULT 0x190a1000 | ||
| 635 | #define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR_DEFAULT 0x000000f0 | ||
| 636 | #define mmEP_PCIE_F0_DPA_CNTL_DEFAULT 0x00000100 | ||
| 637 | #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa | ||
| 638 | #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8 | ||
| 639 | #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096 | ||
| 640 | #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064 | ||
| 641 | #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b | ||
| 642 | #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032 | ||
| 643 | #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019 | ||
| 644 | #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a | ||
| 645 | #define mmEP_PCIE_PME_CONTROL_DEFAULT 0x00000000 | ||
| 646 | #define mmEP_PCIEP_RESERVED_DEFAULT 0x00000000 | ||
| 647 | #define mmEP_PCIE_TX_CNTL_DEFAULT 0x00000000 | ||
| 648 | #define mmEP_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000 | ||
| 649 | #define mmEP_PCIE_ERR_CNTL_DEFAULT 0x00000500 | ||
| 650 | #define mmEP_PCIE_RX_CNTL_DEFAULT 0x01000000 | ||
| 651 | #define mmEP_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000 | ||
| 652 | |||
| 653 | |||
| 654 | // addressBlock: bif_bx_pf_BIFDEC1 | ||
| 655 | // base address: 0x0 | ||
| 656 | #define mmBIF_MM_INDACCESS_CNTL_DEFAULT 0x00000000 | ||
| 657 | #define mmBUS_CNTL_DEFAULT 0x00000000 | ||
| 658 | #define mmBIF_SCRATCH0_DEFAULT 0x00000000 | ||
| 659 | #define mmBIF_SCRATCH1_DEFAULT 0x00000000 | ||
| 660 | #define mmBX_RESET_EN_DEFAULT 0x00010003 | ||
| 661 | #define mmMM_CFGREGS_CNTL_DEFAULT 0x00000000 | ||
| 662 | #define mmBX_RESET_CNTL_DEFAULT 0x00000000 | ||
| 663 | #define mmINTERRUPT_CNTL_DEFAULT 0x00000010 | ||
| 664 | #define mmINTERRUPT_CNTL2_DEFAULT 0x00000000 | ||
| 665 | #define mmCLKREQB_PAD_CNTL_DEFAULT 0x000008e0 | ||
| 666 | #define mmCLKREQB_PERF_COUNTER_DEFAULT 0x00000000 | ||
| 667 | #define mmBIF_CLK_CTRL_DEFAULT 0x00000000 | ||
| 668 | #define mmBIF_FEATURES_CONTROL_MISC_DEFAULT 0x00000000 | ||
| 669 | #define mmBIF_DOORBELL_CNTL_DEFAULT 0x00000000 | ||
| 670 | #define mmBIF_DOORBELL_INT_CNTL_DEFAULT 0x00000000 | ||
| 671 | #define mmBIF_SLVARB_MODE_DEFAULT 0x00000000 | ||
| 672 | #define mmBIF_FB_EN_DEFAULT 0x00000000 | ||
| 673 | #define mmBIF_BUSY_DELAY_CNTR_DEFAULT 0x0000003f | ||
| 674 | #define mmBIF_PERFMON_CNTL_DEFAULT 0x00000000 | ||
| 675 | #define mmBIF_PERFCOUNTER0_RESULT_DEFAULT 0x00000000 | ||
| 676 | #define mmBIF_PERFCOUNTER1_RESULT_DEFAULT 0x00000000 | ||
| 677 | #define mmBIF_MST_TRANS_PENDING_VF_DEFAULT 0x00000000 | ||
| 678 | #define mmBIF_SLV_TRANS_PENDING_VF_DEFAULT 0x00000000 | ||
| 679 | #define mmBACO_CNTL_DEFAULT 0x00000000 | ||
| 680 | #define mmBIF_BACO_EXIT_TIME0_DEFAULT 0x00000100 | ||
| 681 | #define mmBIF_BACO_EXIT_TIMER1_DEFAULT 0x00000100 | ||
| 682 | #define mmBIF_BACO_EXIT_TIMER2_DEFAULT 0x00000300 | ||
| 683 | #define mmBIF_BACO_EXIT_TIMER3_DEFAULT 0x00000400 | ||
| 684 | #define mmBIF_BACO_EXIT_TIMER4_DEFAULT 0x00000100 | ||
| 685 | #define mmMEM_TYPE_CNTL_DEFAULT 0x00000000 | ||
| 686 | #define mmSMU_BIF_VDDGFX_PWR_STATUS_DEFAULT 0x00000000 | ||
| 687 | #define mmBIF_VDDGFX_GFX0_LOWER_DEFAULT 0xc0008000 | ||
| 688 | #define mmBIF_VDDGFX_GFX0_UPPER_DEFAULT 0x0000cffc | ||
| 689 | #define mmBIF_VDDGFX_GFX1_LOWER_DEFAULT 0xc0028000 | ||
| 690 | #define mmBIF_VDDGFX_GFX1_UPPER_DEFAULT 0x00031ffc | ||
| 691 | #define mmBIF_VDDGFX_GFX2_LOWER_DEFAULT 0xc0034000 | ||
| 692 | #define mmBIF_VDDGFX_GFX2_UPPER_DEFAULT 0x00037ffc | ||
| 693 | #define mmBIF_VDDGFX_GFX3_LOWER_DEFAULT 0xc003c000 | ||
| 694 | #define mmBIF_VDDGFX_GFX3_UPPER_DEFAULT 0x0003e1fc | ||
| 695 | #define mmBIF_VDDGFX_GFX4_LOWER_DEFAULT 0xc003ec00 | ||
| 696 | #define mmBIF_VDDGFX_GFX4_UPPER_DEFAULT 0x0003f1fc | ||
| 697 | #define mmBIF_VDDGFX_GFX5_LOWER_DEFAULT 0xc003fc00 | ||
| 698 | #define mmBIF_VDDGFX_GFX5_UPPER_DEFAULT 0x0003fffc | ||
| 699 | #define mmBIF_VDDGFX_RSV1_LOWER_DEFAULT 0x00000000 | ||
| 700 | #define mmBIF_VDDGFX_RSV1_UPPER_DEFAULT 0x00000000 | ||
| 701 | #define mmBIF_VDDGFX_RSV2_LOWER_DEFAULT 0x00000000 | ||
| 702 | #define mmBIF_VDDGFX_RSV2_UPPER_DEFAULT 0x00000000 | ||
| 703 | #define mmBIF_VDDGFX_RSV3_LOWER_DEFAULT 0x00000000 | ||
| 704 | #define mmBIF_VDDGFX_RSV3_UPPER_DEFAULT 0x00000000 | ||
| 705 | #define mmBIF_VDDGFX_RSV4_LOWER_DEFAULT 0x00000000 | ||
| 706 | #define mmBIF_VDDGFX_RSV4_UPPER_DEFAULT 0x00000000 | ||
| 707 | #define mmBIF_VDDGFX_FB_CMP_DEFAULT 0x00000000 | ||
| 708 | #define mmBIF_DOORBELL_GBLAPER1_LOWER_DEFAULT 0x80000780 | ||
| 709 | #define mmBIF_DOORBELL_GBLAPER1_UPPER_DEFAULT 0x000007fc | ||
| 710 | #define mmBIF_DOORBELL_GBLAPER2_LOWER_DEFAULT 0x80000800 | ||
| 711 | #define mmBIF_DOORBELL_GBLAPER2_UPPER_DEFAULT 0x0000087c | ||
| 712 | #define mmREMAP_HDP_MEM_FLUSH_CNTL_DEFAULT 0x0000385c | ||
| 713 | #define mmREMAP_HDP_REG_FLUSH_CNTL_DEFAULT 0x00003858 | ||
| 714 | #define mmBIF_RB_CNTL_DEFAULT 0x00000000 | ||
| 715 | #define mmBIF_RB_BASE_DEFAULT 0x00000000 | ||
| 716 | #define mmBIF_RB_RPTR_DEFAULT 0x00000000 | ||
| 717 | #define mmBIF_RB_WPTR_DEFAULT 0x00000000 | ||
| 718 | #define mmBIF_RB_WPTR_ADDR_HI_DEFAULT 0x00000000 | ||
| 719 | #define mmBIF_RB_WPTR_ADDR_LO_DEFAULT 0x00000000 | ||
| 720 | #define mmMAILBOX_INDEX_DEFAULT 0x00000000 | ||
| 721 | #define mmBIF_GPUIOV_RESET_NOTIFICATION_DEFAULT 0x00000000 | ||
| 722 | #define mmBIF_UVD_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 | ||
| 723 | #define mmBIF_VCE_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 | ||
| 724 | #define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 | ||
| 725 | #define mmBIF_GMI_WRR_WEIGHT_DEFAULT 0x00202020 | ||
| 726 | #define mmNBIF_STRAP_WRITE_CTRL_DEFAULT 0x00000000 | ||
| 727 | #define mmBIF_PERSTB_PAD_CNTL_DEFAULT 0x000000c0 | ||
| 728 | #define mmBIF_PX_EN_PAD_CNTL_DEFAULT 0x00000031 | ||
| 729 | #define mmBIF_REFPADKIN_PAD_CNTL_DEFAULT 0x00000007 | ||
| 730 | #define mmBIF_CLKREQB_PAD_CNTL_DEFAULT 0x00600100 | ||
| 731 | |||
| 732 | |||
| 733 | // addressBlock: rcc_pf_0_BIFDEC1 | ||
| 734 | // base address: 0x0 | ||
| 735 | #define mmRCC_BACO_CNTL_MISC_DEFAULT 0x00000000 | ||
| 736 | #define mmRCC_RESET_EN_DEFAULT 0x00008000 | ||
| 737 | #define mmRCC_VDM_SUPPORT_DEFAULT 0x00000000 | ||
| 738 | #define mmRCC_PEER_REG_RANGE0_DEFAULT 0xffff0000 | ||
| 739 | #define mmRCC_PEER_REG_RANGE1_DEFAULT 0xffff0000 | ||
| 740 | #define mmRCC_BUS_CNTL_DEFAULT 0x00000000 | ||
| 741 | #define mmRCC_CONFIG_CNTL_DEFAULT 0x00000000 | ||
| 742 | #define mmRCC_CONFIG_F0_BASE_DEFAULT 0x00000000 | ||
| 743 | #define mmRCC_CONFIG_APER_SIZE_DEFAULT 0x00000000 | ||
| 744 | #define mmRCC_CONFIG_REG_APER_SIZE_DEFAULT 0x00000000 | ||
| 745 | #define mmRCC_XDMA_LO_DEFAULT 0x00000000 | ||
| 746 | #define mmRCC_XDMA_HI_DEFAULT 0x00000000 | ||
| 747 | #define mmRCC_FEATURES_CONTROL_MISC_DEFAULT 0x00000000 | ||
| 748 | #define mmRCC_BUSNUM_CNTL1_DEFAULT 0x00000000 | ||
| 749 | #define mmRCC_BUSNUM_LIST0_DEFAULT 0x00000000 | ||
| 750 | #define mmRCC_BUSNUM_LIST1_DEFAULT 0x00000000 | ||
| 751 | #define mmRCC_BUSNUM_CNTL2_DEFAULT 0x00000000 | ||
| 752 | #define mmRCC_CAPTURE_HOST_BUSNUM_DEFAULT 0x00000000 | ||
| 753 | #define mmRCC_HOST_BUSNUM_DEFAULT 0x00000000 | ||
| 754 | #define mmRCC_PEER0_FB_OFFSET_HI_DEFAULT 0x00000000 | ||
| 755 | #define mmRCC_PEER0_FB_OFFSET_LO_DEFAULT 0x00000000 | ||
| 756 | #define mmRCC_PEER1_FB_OFFSET_HI_DEFAULT 0x00000000 | ||
| 757 | #define mmRCC_PEER1_FB_OFFSET_LO_DEFAULT 0x00000000 | ||
| 758 | #define mmRCC_PEER2_FB_OFFSET_HI_DEFAULT 0x00000000 | ||
| 759 | #define mmRCC_PEER2_FB_OFFSET_LO_DEFAULT 0x00000000 | ||
| 760 | #define mmRCC_PEER3_FB_OFFSET_HI_DEFAULT 0x00000000 | ||
| 761 | #define mmRCC_PEER3_FB_OFFSET_LO_DEFAULT 0x00000000 | ||
| 762 | #define mmRCC_DEVFUNCNUM_LIST0_DEFAULT 0x00000000 | ||
| 763 | #define mmRCC_DEVFUNCNUM_LIST1_DEFAULT 0x00000000 | ||
| 764 | #define mmRCC_DEV0_LINK_CNTL_DEFAULT 0x00000000 | ||
| 765 | #define mmRCC_CMN_LINK_CNTL_DEFAULT 0x00000000 | ||
| 766 | #define mmRCC_EP_REQUESTERID_RESTORE_DEFAULT 0x00000000 | ||
| 767 | #define mmRCC_LTR_LSWITCH_CNTL_DEFAULT 0x00000000 | ||
| 768 | #define mmRCC_MH_ARB_CNTL_DEFAULT 0x00000000 | ||
| 769 | |||
| 770 | |||
| 771 | // addressBlock: rcc_pf_0_BIFDEC2 | ||
| 772 | // base address: 0x0 | ||
| 773 | #define mmGFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 | ||
| 774 | #define mmGFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 | ||
| 775 | #define mmGFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 | ||
| 776 | #define mmGFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 | ||
| 777 | #define mmGFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 | ||
| 778 | #define mmGFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 | ||
| 779 | #define mmGFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 | ||
| 780 | #define mmGFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 | ||
| 781 | #define mmGFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 | ||
| 782 | #define mmGFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 | ||
| 783 | #define mmGFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 | ||
| 784 | #define mmGFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 | ||
| 785 | #define mmGFXMSIX_PBA_DEFAULT 0x00000000 | ||
| 786 | |||
| 787 | |||
| 788 | // addressBlock: rcc_strap_BIFDEC1 | ||
| 789 | // base address: 0x0 | ||
| 790 | #define mmRCC_DEV0_PORT_STRAP0_DEFAULT 0x54228bc0 | ||
| 791 | #define mmRCC_DEV0_PORT_STRAP1_DEFAULT 0x1022145e | ||
| 792 | #define mmRCC_DEV0_PORT_STRAP2_DEFAULT 0x1c65e009 | ||
| 793 | #define mmRCC_DEV0_PORT_STRAP3_DEFAULT 0x5ffff849 | ||
| 794 | #define mmRCC_DEV0_PORT_STRAP4_DEFAULT 0x00000000 | ||
| 795 | #define mmRCC_DEV0_PORT_STRAP5_DEFAULT 0xaf800000 | ||
| 796 | #define mmRCC_DEV0_PORT_STRAP6_DEFAULT 0x00000002 | ||
| 797 | #define mmRCC_DEV0_PORT_STRAP7_DEFAULT 0x00000000 | ||
| 798 | #define mmRCC_DEV0_EPF0_STRAP0_DEFAULT 0x30000000 | ||
| 799 | #define mmRCC_DEV0_EPF0_STRAP1_DEFAULT 0x05530000 | ||
| 800 | #define mmRCC_DEV0_EPF0_STRAP13_DEFAULT 0x00000000 | ||
| 801 | #define mmRCC_DEV0_EPF0_STRAP2_DEFAULT 0x02000000 | ||
| 802 | #define mmRCC_DEV0_EPF0_STRAP3_DEFAULT 0x08b40001 | ||
| 803 | #define mmRCC_DEV0_EPF0_STRAP4_DEFAULT 0x1f000042 | ||
| 804 | #define mmRCC_DEV0_EPF0_STRAP5_DEFAULT 0x00001022 | ||
| 805 | #define mmRCC_DEV0_EPF0_STRAP8_DEFAULT 0xc8c73002 | ||
| 806 | #define mmRCC_DEV0_EPF0_STRAP9_DEFAULT 0x00000000 | ||
| 807 | #define mmRCC_DEV0_EPF1_STRAP0_DEFAULT 0x30000000 | ||
| 808 | #define mmRCC_DEV0_EPF1_STRAP10_DEFAULT 0x00000000 | ||
| 809 | #define mmRCC_DEV0_EPF1_STRAP11_DEFAULT 0x00000000 | ||
| 810 | #define mmRCC_DEV0_EPF1_STRAP12_DEFAULT 0x00000000 | ||
| 811 | #define mmRCC_DEV0_EPF1_STRAP13_DEFAULT 0x00000000 | ||
| 812 | #define mmRCC_DEV0_EPF1_STRAP2_DEFAULT 0x00000000 | ||
| 813 | #define mmRCC_DEV0_EPF1_STRAP3_DEFAULT 0x08040001 | ||
| 814 | #define mmRCC_DEV0_EPF1_STRAP4_DEFAULT 0x2f000000 | ||
| 815 | #define mmRCC_DEV0_EPF1_STRAP5_DEFAULT 0x00001022 | ||
| 816 | #define mmRCC_DEV0_EPF1_STRAP6_DEFAULT 0x00000000 | ||
| 817 | #define mmRCC_DEV0_EPF1_STRAP7_DEFAULT 0x00000000 | ||
| 818 | |||
| 819 | |||
| 820 | // addressBlock: bif_bx_pf_BIFPFVFDEC1 | ||
| 821 | // base address: 0x0 | ||
| 822 | #define mmBIF_BME_STATUS_DEFAULT 0x00000000 | ||
| 823 | #define mmBIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 | ||
| 824 | #define mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 | ||
| 825 | #define mmDOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 | ||
| 826 | #define mmDOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000000 | ||
| 827 | #define mmHDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 | ||
| 828 | #define mmHDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 | ||
| 829 | #define mmGPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 | ||
| 830 | #define mmGPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 | ||
| 831 | #define mmBIF_TRANS_PENDING_DEFAULT 0x00000000 | ||
| 832 | #define mmMAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 | ||
| 833 | #define mmMAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 | ||
| 834 | #define mmMAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 | ||
| 835 | #define mmMAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 | ||
| 836 | #define mmMAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 | ||
| 837 | #define mmMAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 | ||
| 838 | #define mmMAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 | ||
| 839 | #define mmMAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 | ||
| 840 | #define mmMAILBOX_CONTROL_DEFAULT 0x00000000 | ||
| 841 | #define mmMAILBOX_INT_CNTL_DEFAULT 0x00000000 | ||
| 842 | #define mmBIF_VMHV_MAILBOX_DEFAULT 0x00000000 | ||
| 843 | |||
| 844 | |||
| 845 | // addressBlock: rcc_pf_0_BIFPFVFDEC1 | ||
| 846 | // base address: 0x0 | ||
| 847 | #define mmRCC_DOORBELL_APER_EN_DEFAULT 0x00000000 | ||
| 848 | #define mmRCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 | ||
| 849 | #define mmRCC_CONFIG_RESERVED_DEFAULT 0x00000000 | ||
| 850 | #define mmRCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 | ||
| 851 | |||
| 852 | |||
| 853 | // addressBlock: syshub_mmreg_ind_syshubdec | ||
| 854 | // base address: 0x0 | ||
| 855 | #define mmSYSHUB_INDEX_DEFAULT 0x00000000 | ||
| 856 | #define mmSYSHUB_DATA_DEFAULT 0x00000000 | ||
| 857 | |||
| 858 | |||
| 859 | // addressBlock: rcc_strap_rcc_strap_internal | ||
| 860 | // base address: 0x10100000 | ||
| 861 | #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0_DEFAULT 0x54228bc0 | ||
| 862 | #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1_DEFAULT 0x1022145e | ||
| 863 | #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2_DEFAULT 0x1c65e009 | ||
| 864 | #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3_DEFAULT 0x5ffff849 | ||
| 865 | #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4_DEFAULT 0x00000000 | ||
| 866 | #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5_DEFAULT 0xaf800000 | ||
| 867 | #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6_DEFAULT 0x00000002 | ||
| 868 | #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7_DEFAULT 0x00000000 | ||
| 869 | #define mmRCC_DEV1_PORT_STRAP0_DEFAULT 0x00000000 | ||
| 870 | #define mmRCC_DEV1_PORT_STRAP1_DEFAULT 0x00000000 | ||
| 871 | #define mmRCC_DEV1_PORT_STRAP2_DEFAULT 0x00000000 | ||
| 872 | #define mmRCC_DEV1_PORT_STRAP3_DEFAULT 0x00000000 | ||
| 873 | #define mmRCC_DEV1_PORT_STRAP4_DEFAULT 0x00000000 | ||
| 874 | #define mmRCC_DEV1_PORT_STRAP5_DEFAULT 0x00000000 | ||
| 875 | #define mmRCC_DEV1_PORT_STRAP6_DEFAULT 0x00000000 | ||
| 876 | #define mmRCC_DEV1_PORT_STRAP7_DEFAULT 0x00000000 | ||
| 877 | #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0_DEFAULT 0x30000000 | ||
| 878 | #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1_DEFAULT 0x05530000 | ||
| 879 | #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2_DEFAULT 0x02000000 | ||
| 880 | #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3_DEFAULT 0x08b40001 | ||
| 881 | #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4_DEFAULT 0x1f000042 | ||
| 882 | #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5_DEFAULT 0x00001022 | ||
| 883 | #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8_DEFAULT 0xc8c73002 | ||
| 884 | #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP9_DEFAULT 0x00000000 | ||
| 885 | #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13_DEFAULT 0x00000000 | ||
| 886 | #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0_DEFAULT 0x30000000 | ||
| 887 | #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2_DEFAULT 0x00000000 | ||
| 888 | #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3_DEFAULT 0x08040001 | ||
| 889 | #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4_DEFAULT 0x2f000000 | ||
| 890 | #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5_DEFAULT 0x00001022 | ||
| 891 | #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6_DEFAULT 0x00000000 | ||
| 892 | #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7_DEFAULT 0x00000000 | ||
| 893 | #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10_DEFAULT 0x00000000 | ||
| 894 | #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11_DEFAULT 0x00000000 | ||
| 895 | #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12_DEFAULT 0x00000000 | ||
| 896 | #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13_DEFAULT 0x00000000 | ||
| 897 | #define mmRCC_DEV0_EPF2_STRAP0_DEFAULT 0x00000000 | ||
| 898 | #define mmRCC_DEV0_EPF2_STRAP2_DEFAULT 0x00000000 | ||
| 899 | #define mmRCC_DEV0_EPF2_STRAP3_DEFAULT 0x00000000 | ||
| 900 | #define mmRCC_DEV0_EPF2_STRAP4_DEFAULT 0x00000000 | ||
| 901 | #define mmRCC_DEV0_EPF2_STRAP5_DEFAULT 0x00000000 | ||
| 902 | #define mmRCC_DEV0_EPF2_STRAP6_DEFAULT 0x00000000 | ||
| 903 | #define mmRCC_DEV0_EPF2_STRAP13_DEFAULT 0x00000000 | ||
| 904 | #define mmRCC_DEV0_EPF3_STRAP0_DEFAULT 0x00000000 | ||
| 905 | #define mmRCC_DEV0_EPF3_STRAP2_DEFAULT 0x00000000 | ||
| 906 | #define mmRCC_DEV0_EPF3_STRAP3_DEFAULT 0x00000000 | ||
| 907 | #define mmRCC_DEV0_EPF3_STRAP4_DEFAULT 0x00000000 | ||
| 908 | #define mmRCC_DEV0_EPF3_STRAP5_DEFAULT 0x00000000 | ||
| 909 | #define mmRCC_DEV0_EPF3_STRAP6_DEFAULT 0x00000000 | ||
| 910 | #define mmRCC_DEV0_EPF3_STRAP13_DEFAULT 0x00000000 | ||
| 911 | #define mmRCC_DEV0_EPF4_STRAP0_DEFAULT 0x00000000 | ||
| 912 | #define mmRCC_DEV0_EPF4_STRAP2_DEFAULT 0x00000000 | ||
| 913 | #define mmRCC_DEV0_EPF4_STRAP3_DEFAULT 0x00000000 | ||
| 914 | #define mmRCC_DEV0_EPF4_STRAP4_DEFAULT 0x00000000 | ||
| 915 | #define mmRCC_DEV0_EPF4_STRAP5_DEFAULT 0x00000000 | ||
| 916 | #define mmRCC_DEV0_EPF4_STRAP6_DEFAULT 0x00000000 | ||
| 917 | #define mmRCC_DEV0_EPF4_STRAP13_DEFAULT 0x00000000 | ||
| 918 | #define mmRCC_DEV0_EPF5_STRAP0_DEFAULT 0x00000000 | ||
| 919 | #define mmRCC_DEV0_EPF5_STRAP2_DEFAULT 0x00000000 | ||
| 920 | #define mmRCC_DEV0_EPF5_STRAP3_DEFAULT 0x00000000 | ||
| 921 | #define mmRCC_DEV0_EPF5_STRAP4_DEFAULT 0x00000000 | ||
| 922 | #define mmRCC_DEV0_EPF5_STRAP5_DEFAULT 0x00000000 | ||
| 923 | #define mmRCC_DEV0_EPF5_STRAP6_DEFAULT 0x00000000 | ||
| 924 | #define mmRCC_DEV0_EPF5_STRAP13_DEFAULT 0x00000000 | ||
| 925 | #define mmRCC_DEV0_EPF6_STRAP0_DEFAULT 0x00000000 | ||
| 926 | #define mmRCC_DEV0_EPF6_STRAP2_DEFAULT 0x00000000 | ||
| 927 | #define mmRCC_DEV0_EPF6_STRAP3_DEFAULT 0x00000000 | ||
| 928 | #define mmRCC_DEV0_EPF6_STRAP4_DEFAULT 0x00000000 | ||
| 929 | #define mmRCC_DEV0_EPF6_STRAP5_DEFAULT 0x00000000 | ||
| 930 | #define mmRCC_DEV0_EPF6_STRAP6_DEFAULT 0x00000000 | ||
| 931 | #define mmRCC_DEV0_EPF6_STRAP13_DEFAULT 0x00000000 | ||
| 932 | #define mmRCC_DEV0_EPF7_STRAP0_DEFAULT 0x00000000 | ||
| 933 | #define mmRCC_DEV0_EPF7_STRAP2_DEFAULT 0x00000000 | ||
| 934 | #define mmRCC_DEV0_EPF7_STRAP3_DEFAULT 0x00000000 | ||
| 935 | #define mmRCC_DEV0_EPF7_STRAP4_DEFAULT 0x00000000 | ||
| 936 | #define mmRCC_DEV0_EPF7_STRAP5_DEFAULT 0x00000000 | ||
| 937 | #define mmRCC_DEV0_EPF7_STRAP6_DEFAULT 0x00000000 | ||
| 938 | #define mmRCC_DEV0_EPF7_STRAP13_DEFAULT 0x00000000 | ||
| 939 | #define mmRCC_DEV1_EPF0_STRAP0_DEFAULT 0x00000000 | ||
| 940 | #define mmRCC_DEV1_EPF0_STRAP2_DEFAULT 0x00000000 | ||
| 941 | #define mmRCC_DEV1_EPF0_STRAP3_DEFAULT 0x00000000 | ||
| 942 | #define mmRCC_DEV1_EPF0_STRAP4_DEFAULT 0x00000000 | ||
| 943 | #define mmRCC_DEV1_EPF0_STRAP5_DEFAULT 0x00000000 | ||
| 944 | #define mmRCC_DEV1_EPF0_STRAP6_DEFAULT 0x00000000 | ||
| 945 | #define mmRCC_DEV1_EPF0_STRAP13_DEFAULT 0x00000000 | ||
| 946 | #define mmRCC_DEV1_EPF1_STRAP0_DEFAULT 0x00000000 | ||
| 947 | #define mmRCC_DEV1_EPF1_STRAP2_DEFAULT 0x00000000 | ||
| 948 | #define mmRCC_DEV1_EPF1_STRAP3_DEFAULT 0x00000000 | ||
| 949 | #define mmRCC_DEV1_EPF1_STRAP4_DEFAULT 0x00000000 | ||
| 950 | #define mmRCC_DEV1_EPF1_STRAP5_DEFAULT 0x00000000 | ||
| 951 | #define mmRCC_DEV1_EPF1_STRAP6_DEFAULT 0x00000000 | ||
| 952 | #define mmRCC_DEV1_EPF1_STRAP13_DEFAULT 0x00000000 | ||
| 953 | #define mmRCC_DEV1_EPF2_STRAP0_DEFAULT 0x00000000 | ||
| 954 | #define mmRCC_DEV1_EPF2_STRAP2_DEFAULT 0x00000000 | ||
| 955 | #define mmRCC_DEV1_EPF2_STRAP3_DEFAULT 0x00000000 | ||
| 956 | #define mmRCC_DEV1_EPF2_STRAP4_DEFAULT 0x00000000 | ||
| 957 | #define mmRCC_DEV1_EPF2_STRAP5_DEFAULT 0x00000000 | ||
| 958 | #define mmRCC_DEV1_EPF2_STRAP6_DEFAULT 0x00000000 | ||
| 959 | #define mmRCC_DEV1_EPF2_STRAP13_DEFAULT 0x00000000 | ||
| 960 | |||
| 961 | |||
| 962 | // addressBlock: bif_rst_bif_rst_regblk | ||
| 963 | // base address: 0x10100000 | ||
| 964 | #define ixHARD_RST_CTRL_DEFAULT 0xb0000055 | ||
| 965 | #define ixRSMU_SOFT_RST_CTRL_DEFAULT 0x90000000 | ||
| 966 | #define ixSELF_SOFT_RST_DEFAULT 0x00000000 | ||
| 967 | #define ixGFX_DRV_MODE1_RST_CTRL_DEFAULT 0x000000a9 | ||
| 968 | #define ixBIF_RST_MISC_CTRL_DEFAULT 0x00000644 | ||
| 969 | #define ixBIF_RST_MISC_CTRL2_DEFAULT 0x00000000 | ||
| 970 | #define ixBIF_RST_MISC_CTRL3_DEFAULT 0x00004900 | ||
| 971 | #define ixBIF_RST_GFXVF_FLR_IDLE_DEFAULT 0x00000000 | ||
| 972 | #define ixDEV0_PF0_FLR_RST_CTRL_DEFAULT 0x0206a9a9 | ||
| 973 | #define ixDEV0_PF1_FLR_RST_CTRL_DEFAULT 0x02060009 | ||
| 974 | #define ixDEV0_PF2_FLR_RST_CTRL_DEFAULT 0x02060009 | ||
| 975 | #define ixDEV0_PF3_FLR_RST_CTRL_DEFAULT 0x02060009 | ||
| 976 | #define ixDEV0_PF4_FLR_RST_CTRL_DEFAULT 0x02060009 | ||
| 977 | #define ixDEV0_PF5_FLR_RST_CTRL_DEFAULT 0x02060009 | ||
| 978 | #define ixDEV0_PF6_FLR_RST_CTRL_DEFAULT 0x02060009 | ||
| 979 | #define ixDEV0_PF7_FLR_RST_CTRL_DEFAULT 0x02060009 | ||
| 980 | #define ixBIF_INST_RESET_INTR_STS_DEFAULT 0x00000000 | ||
| 981 | #define ixBIF_PF_FLR_INTR_STS_DEFAULT 0x00000000 | ||
| 982 | #define ixBIF_D3HOTD0_INTR_STS_DEFAULT 0x00000000 | ||
| 983 | #define ixBIF_POWER_INTR_STS_DEFAULT 0x00000000 | ||
| 984 | #define ixBIF_PF_DSTATE_INTR_STS_DEFAULT 0x00000000 | ||
| 985 | #define ixBIF_PF0_VF_FLR_INTR_STS_DEFAULT 0x00000000 | ||
| 986 | #define ixBIF_INST_RESET_INTR_MASK_DEFAULT 0x00000000 | ||
| 987 | #define ixBIF_PF_FLR_INTR_MASK_DEFAULT 0x00000000 | ||
| 988 | #define ixBIF_D3HOTD0_INTR_MASK_DEFAULT 0x000000ff | ||
| 989 | #define ixBIF_POWER_INTR_MASK_DEFAULT 0x00000000 | ||
| 990 | #define ixBIF_PF_DSTATE_INTR_MASK_DEFAULT 0x00000000 | ||
| 991 | #define ixBIF_PF0_VF_FLR_INTR_MASK_DEFAULT 0x00000000 | ||
| 992 | #define ixBIF_PF_FLR_RST_DEFAULT 0x00000000 | ||
| 993 | #define ixBIF_PF0_VF_FLR_RST_DEFAULT 0x00000000 | ||
| 994 | #define ixBIF_DEV0_PF0_DSTATE_VALUE_DEFAULT 0x00000000 | ||
| 995 | #define ixBIF_DEV0_PF1_DSTATE_VALUE_DEFAULT 0x00000000 | ||
| 996 | #define ixBIF_DEV0_PF2_DSTATE_VALUE_DEFAULT 0x00000000 | ||
| 997 | #define ixBIF_DEV0_PF3_DSTATE_VALUE_DEFAULT 0x00000000 | ||
| 998 | #define ixBIF_DEV0_PF4_DSTATE_VALUE_DEFAULT 0x00000000 | ||
| 999 | #define ixBIF_DEV0_PF5_DSTATE_VALUE_DEFAULT 0x00000000 | ||
| 1000 | #define ixBIF_DEV0_PF6_DSTATE_VALUE_DEFAULT 0x00000000 | ||
| 1001 | #define ixBIF_DEV0_PF7_DSTATE_VALUE_DEFAULT 0x00000000 | ||
| 1002 | #define ixDEV0_PF0_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b | ||
| 1003 | #define ixDEV0_PF1_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b | ||
| 1004 | #define ixDEV0_PF2_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b | ||
| 1005 | #define ixDEV0_PF3_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b | ||
| 1006 | #define ixDEV0_PF4_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b | ||
| 1007 | #define ixDEV0_PF5_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b | ||
| 1008 | #define ixDEV0_PF6_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b | ||
| 1009 | #define ixDEV0_PF7_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b | ||
| 1010 | #define ixBIF_PORT0_DSTATE_VALUE_DEFAULT 0x00000000 | ||
| 1011 | |||
| 1012 | |||
| 1013 | // addressBlock: bif_misc_bif_misc_regblk | ||
| 1014 | // base address: 0x10100000 | ||
| 1015 | #define ixMISC_SCRATCH_DEFAULT 0x00000000 | ||
| 1016 | #define ixINTR_LINE_POLARITY_DEFAULT 0x00000000 | ||
| 1017 | #define ixINTR_LINE_ENABLE_DEFAULT 0x00000000 | ||
| 1018 | #define ixOUTSTANDING_VC_ALLOC_DEFAULT 0x6f06c0cf | ||
| 1019 | #define ixBIFC_MISC_CTRL0_DEFAULT 0x08000004 | ||
| 1020 | #define ixBIFC_MISC_CTRL1_DEFAULT 0x00008004 | ||
| 1021 | #define ixBIFC_BME_ERR_LOG_DEFAULT 0x00000000 | ||
| 1022 | #define ixBIFC_RCCBIH_BME_ERR_LOG_DEFAULT 0x00000000 | ||
| 1023 | #define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1_DEFAULT 0x00000000 | ||
| 1024 | #define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3_DEFAULT 0x00000000 | ||
| 1025 | #define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5_DEFAULT 0x00000000 | ||
| 1026 | #define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7_DEFAULT 0x00000000 | ||
| 1027 | #define ixNBIF_VWIRE_CTRL_DEFAULT 0x00000000 | ||
| 1028 | #define ixNBIF_SMN_VWR_VCHG_DIS_CTRL_DEFAULT 0x00000000 | ||
| 1029 | #define ixNBIF_SMN_VWR_VCHG_RST_CTRL0_DEFAULT 0x00000000 | ||
| 1030 | #define ixNBIF_SMN_VWR_VCHG_TRIG_DEFAULT 0x00000000 | ||
| 1031 | #define ixNBIF_SMN_VWR_WTRIG_CNTL_DEFAULT 0x00000000 | ||
| 1032 | #define ixNBIF_SMN_VWR_VCHG_DIS_CTRL_1_DEFAULT 0x00000000 | ||
| 1033 | #define ixNBIF_MGCG_CTRL_DEFAULT 0x00000080 | ||
| 1034 | #define ixNBIF_DS_CTRL_LCLK_DEFAULT 0x01000000 | ||
| 1035 | #define ixSMN_MST_CNTL0_DEFAULT 0x00000001 | ||
| 1036 | #define ixSMN_MST_EP_CNTL1_DEFAULT 0x00000000 | ||
| 1037 | #define ixSMN_MST_EP_CNTL2_DEFAULT 0x00000000 | ||
| 1038 | #define ixNBIF_SDP_VWR_VCHG_DIS_CTRL_DEFAULT 0x00000000 | ||
| 1039 | #define ixNBIF_SDP_VWR_VCHG_RST_CTRL0_DEFAULT 0x00000000 | ||
| 1040 | #define ixNBIF_SDP_VWR_VCHG_RST_CTRL1_DEFAULT 0x00000000 | ||
| 1041 | #define ixNBIF_SDP_VWR_VCHG_TRIG_DEFAULT 0x00000000 | ||
| 1042 | #define ixBME_DUMMY_CNTL_0_DEFAULT 0x0000aaaa | ||
| 1043 | #define ixBIFC_THT_CNTL_DEFAULT 0x00000222 | ||
| 1044 | #define ixBIFC_HSTARB_CNTL_DEFAULT 0x00000000 | ||
| 1045 | #define ixBIFC_GSI_CNTL_DEFAULT 0x000017c0 | ||
| 1046 | #define ixBIFC_PCIEFUNC_CNTL_DEFAULT 0x00000000 | ||
| 1047 | #define ixBIFC_SDP_CNTL_0_DEFAULT 0x003cf3cf | ||
| 1048 | #define ixBIFC_PERF_CNTL_0_DEFAULT 0x00000000 | ||
| 1049 | #define ixBIFC_PERF_CNTL_1_DEFAULT 0x00000000 | ||
| 1050 | #define ixBIFC_PERF_CNT_MMIO_RD_DEFAULT 0x00000000 | ||
| 1051 | #define ixBIFC_PERF_CNT_MMIO_WR_DEFAULT 0x00000000 | ||
| 1052 | #define ixBIFC_PERF_CNT_DMA_RD_DEFAULT 0x00000000 | ||
| 1053 | #define ixBIFC_PERF_CNT_DMA_WR_DEFAULT 0x00000000 | ||
| 1054 | #define ixNBIF_REGIF_ERRSET_CTRL_DEFAULT 0x00000000 | ||
| 1055 | #define ixSMN_MST_EP_CNTL3_DEFAULT 0x00000000 | ||
| 1056 | #define ixSMN_MST_EP_CNTL4_DEFAULT 0x00000000 | ||
| 1057 | #define ixBIF_SELFRING_BUFFER_VID_DEFAULT 0x0000605f | ||
| 1058 | #define ixBIF_SELFRING_VECTOR_CNTL_DEFAULT 0x00000000 | ||
| 1059 | |||
| 1060 | |||
| 1061 | // addressBlock: bif_ras_bif_ras_regblk | ||
| 1062 | // base address: 0x10100000 | ||
| 1063 | #define ixBIF_RAS_LEAF0_CTRL_DEFAULT 0x00000000 | ||
| 1064 | #define ixBIF_RAS_LEAF1_CTRL_DEFAULT 0x00000000 | ||
| 1065 | #define ixBIF_RAS_LEAF2_CTRL_DEFAULT 0x00000000 | ||
| 1066 | #define ixBIF_RAS_MISC_CTRL_DEFAULT 0x00000000 | ||
| 1067 | #define ixBIF_IOHUB_RAS_IH_CNTL_DEFAULT 0x00000000 | ||
| 1068 | #define ixBIF_RAS_VWR_FROM_IOHUB_DEFAULT 0x00000000 | ||
| 1069 | |||
| 1070 | |||
| 1071 | // addressBlock: rcc_pfc_amdgfx_RCCPFCDEC | ||
| 1072 | // base address: 0x10134000 | ||
| 1073 | #define ixRCC_PFC_LTR_CNTL_DEFAULT 0x00000000 | ||
| 1074 | #define ixRCC_PFC_PME_RESTORE_DEFAULT 0x00000000 | ||
| 1075 | #define ixRCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000 | ||
| 1076 | #define ixRCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000 | ||
| 1077 | #define ixRCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000 | ||
| 1078 | #define ixRCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000 | ||
| 1079 | #define ixRCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000 | ||
| 1080 | #define ixRCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000 | ||
| 1081 | #define ixRCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000 | ||
| 1082 | |||
| 1083 | |||
| 1084 | // addressBlock: rcc_pfc_amdgfxaz_RCCPFCDEC | ||
| 1085 | // base address: 0x10134200 | ||
| 1086 | #define ixRCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000 | ||
| 1087 | #define ixRCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000 | ||
| 1088 | #define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000 | ||
| 1089 | #define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000 | ||
| 1090 | #define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000 | ||
| 1091 | #define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000 | ||
| 1092 | #define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000 | ||
| 1093 | #define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000 | ||
| 1094 | #define ixRCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000 | ||
| 1095 | |||
| 1096 | |||
| 1097 | // addressBlock: pciemsix_amdgfx_MSIXTDEC | ||
| 1098 | // base address: 0x10170000 | ||
| 1099 | #define ixPCIEMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 | ||
| 1100 | #define ixPCIEMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 | ||
| 1101 | #define ixPCIEMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 | ||
| 1102 | #define ixPCIEMSIX_VECT0_CONTROL_DEFAULT 0x00000000 | ||
| 1103 | #define ixPCIEMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 | ||
| 1104 | #define ixPCIEMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 | ||
| 1105 | #define ixPCIEMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 | ||
| 1106 | #define ixPCIEMSIX_VECT1_CONTROL_DEFAULT 0x00000000 | ||
| 1107 | #define ixPCIEMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 | ||
| 1108 | #define ixPCIEMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 | ||
| 1109 | #define ixPCIEMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 | ||
| 1110 | #define ixPCIEMSIX_VECT2_CONTROL_DEFAULT 0x00000000 | ||
| 1111 | #define ixPCIEMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 | ||
| 1112 | #define ixPCIEMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 | ||
| 1113 | #define ixPCIEMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 | ||
| 1114 | #define ixPCIEMSIX_VECT3_CONTROL_DEFAULT 0x00000000 | ||
| 1115 | #define ixPCIEMSIX_VECT4_ADDR_LO_DEFAULT 0x00000000 | ||
| 1116 | #define ixPCIEMSIX_VECT4_ADDR_HI_DEFAULT 0x00000000 | ||
| 1117 | #define ixPCIEMSIX_VECT4_MSG_DATA_DEFAULT 0x00000000 | ||
| 1118 | #define ixPCIEMSIX_VECT4_CONTROL_DEFAULT 0x00000000 | ||
| 1119 | #define ixPCIEMSIX_VECT5_ADDR_LO_DEFAULT 0x00000000 | ||
| 1120 | #define ixPCIEMSIX_VECT5_ADDR_HI_DEFAULT 0x00000000 | ||
| 1121 | #define ixPCIEMSIX_VECT5_MSG_DATA_DEFAULT 0x00000000 | ||
| 1122 | #define ixPCIEMSIX_VECT5_CONTROL_DEFAULT 0x00000000 | ||
| 1123 | #define ixPCIEMSIX_VECT6_ADDR_LO_DEFAULT 0x00000000 | ||
| 1124 | #define ixPCIEMSIX_VECT6_ADDR_HI_DEFAULT 0x00000000 | ||
| 1125 | #define ixPCIEMSIX_VECT6_MSG_DATA_DEFAULT 0x00000000 | ||
| 1126 | #define ixPCIEMSIX_VECT6_CONTROL_DEFAULT 0x00000000 | ||
| 1127 | #define ixPCIEMSIX_VECT7_ADDR_LO_DEFAULT 0x00000000 | ||
| 1128 | #define ixPCIEMSIX_VECT7_ADDR_HI_DEFAULT 0x00000000 | ||
| 1129 | #define ixPCIEMSIX_VECT7_MSG_DATA_DEFAULT 0x00000000 | ||
| 1130 | #define ixPCIEMSIX_VECT7_CONTROL_DEFAULT 0x00000000 | ||
| 1131 | #define ixPCIEMSIX_VECT8_ADDR_LO_DEFAULT 0x00000000 | ||
| 1132 | #define ixPCIEMSIX_VECT8_ADDR_HI_DEFAULT 0x00000000 | ||
| 1133 | #define ixPCIEMSIX_VECT8_MSG_DATA_DEFAULT 0x00000000 | ||
| 1134 | #define ixPCIEMSIX_VECT8_CONTROL_DEFAULT 0x00000000 | ||
| 1135 | #define ixPCIEMSIX_VECT9_ADDR_LO_DEFAULT 0x00000000 | ||
| 1136 | #define ixPCIEMSIX_VECT9_ADDR_HI_DEFAULT 0x00000000 | ||
| 1137 | #define ixPCIEMSIX_VECT9_MSG_DATA_DEFAULT 0x00000000 | ||
| 1138 | #define ixPCIEMSIX_VECT9_CONTROL_DEFAULT 0x00000000 | ||
| 1139 | #define ixPCIEMSIX_VECT10_ADDR_LO_DEFAULT 0x00000000 | ||
| 1140 | #define ixPCIEMSIX_VECT10_ADDR_HI_DEFAULT 0x00000000 | ||
| 1141 | #define ixPCIEMSIX_VECT10_MSG_DATA_DEFAULT 0x00000000 | ||
| 1142 | #define ixPCIEMSIX_VECT10_CONTROL_DEFAULT 0x00000000 | ||
| 1143 | #define ixPCIEMSIX_VECT11_ADDR_LO_DEFAULT 0x00000000 | ||
| 1144 | #define ixPCIEMSIX_VECT11_ADDR_HI_DEFAULT 0x00000000 | ||
| 1145 | #define ixPCIEMSIX_VECT11_MSG_DATA_DEFAULT 0x00000000 | ||
| 1146 | #define ixPCIEMSIX_VECT11_CONTROL_DEFAULT 0x00000000 | ||
| 1147 | #define ixPCIEMSIX_VECT12_ADDR_LO_DEFAULT 0x00000000 | ||
| 1148 | #define ixPCIEMSIX_VECT12_ADDR_HI_DEFAULT 0x00000000 | ||
| 1149 | #define ixPCIEMSIX_VECT12_MSG_DATA_DEFAULT 0x00000000 | ||
| 1150 | #define ixPCIEMSIX_VECT12_CONTROL_DEFAULT 0x00000000 | ||
| 1151 | #define ixPCIEMSIX_VECT13_ADDR_LO_DEFAULT 0x00000000 | ||
| 1152 | #define ixPCIEMSIX_VECT13_ADDR_HI_DEFAULT 0x00000000 | ||
| 1153 | #define ixPCIEMSIX_VECT13_MSG_DATA_DEFAULT 0x00000000 | ||
| 1154 | #define ixPCIEMSIX_VECT13_CONTROL_DEFAULT 0x00000000 | ||
| 1155 | #define ixPCIEMSIX_VECT14_ADDR_LO_DEFAULT 0x00000000 | ||
| 1156 | #define ixPCIEMSIX_VECT14_ADDR_HI_DEFAULT 0x00000000 | ||
| 1157 | #define ixPCIEMSIX_VECT14_MSG_DATA_DEFAULT 0x00000000 | ||
| 1158 | #define ixPCIEMSIX_VECT14_CONTROL_DEFAULT 0x00000000 | ||
| 1159 | #define ixPCIEMSIX_VECT15_ADDR_LO_DEFAULT 0x00000000 | ||
| 1160 | #define ixPCIEMSIX_VECT15_ADDR_HI_DEFAULT 0x00000000 | ||
| 1161 | #define ixPCIEMSIX_VECT15_MSG_DATA_DEFAULT 0x00000000 | ||
| 1162 | #define ixPCIEMSIX_VECT15_CONTROL_DEFAULT 0x00000000 | ||
| 1163 | #define ixPCIEMSIX_VECT16_ADDR_LO_DEFAULT 0x00000000 | ||
| 1164 | #define ixPCIEMSIX_VECT16_ADDR_HI_DEFAULT 0x00000000 | ||
| 1165 | #define ixPCIEMSIX_VECT16_MSG_DATA_DEFAULT 0x00000000 | ||
| 1166 | #define ixPCIEMSIX_VECT16_CONTROL_DEFAULT 0x00000000 | ||
| 1167 | #define ixPCIEMSIX_VECT17_ADDR_LO_DEFAULT 0x00000000 | ||
| 1168 | #define ixPCIEMSIX_VECT17_ADDR_HI_DEFAULT 0x00000000 | ||
| 1169 | #define ixPCIEMSIX_VECT17_MSG_DATA_DEFAULT 0x00000000 | ||
| 1170 | #define ixPCIEMSIX_VECT17_CONTROL_DEFAULT 0x00000000 | ||
| 1171 | #define ixPCIEMSIX_VECT18_ADDR_LO_DEFAULT 0x00000000 | ||
| 1172 | #define ixPCIEMSIX_VECT18_ADDR_HI_DEFAULT 0x00000000 | ||
| 1173 | #define ixPCIEMSIX_VECT18_MSG_DATA_DEFAULT 0x00000000 | ||
| 1174 | #define ixPCIEMSIX_VECT18_CONTROL_DEFAULT 0x00000000 | ||
| 1175 | #define ixPCIEMSIX_VECT19_ADDR_LO_DEFAULT 0x00000000 | ||
| 1176 | #define ixPCIEMSIX_VECT19_ADDR_HI_DEFAULT 0x00000000 | ||
| 1177 | #define ixPCIEMSIX_VECT19_MSG_DATA_DEFAULT 0x00000000 | ||
| 1178 | #define ixPCIEMSIX_VECT19_CONTROL_DEFAULT 0x00000000 | ||
| 1179 | #define ixPCIEMSIX_VECT20_ADDR_LO_DEFAULT 0x00000000 | ||
| 1180 | #define ixPCIEMSIX_VECT20_ADDR_HI_DEFAULT 0x00000000 | ||
| 1181 | #define ixPCIEMSIX_VECT20_MSG_DATA_DEFAULT 0x00000000 | ||
| 1182 | #define ixPCIEMSIX_VECT20_CONTROL_DEFAULT 0x00000000 | ||
| 1183 | #define ixPCIEMSIX_VECT21_ADDR_LO_DEFAULT 0x00000000 | ||
| 1184 | #define ixPCIEMSIX_VECT21_ADDR_HI_DEFAULT 0x00000000 | ||
| 1185 | #define ixPCIEMSIX_VECT21_MSG_DATA_DEFAULT 0x00000000 | ||
| 1186 | #define ixPCIEMSIX_VECT21_CONTROL_DEFAULT 0x00000000 | ||
| 1187 | #define ixPCIEMSIX_VECT22_ADDR_LO_DEFAULT 0x00000000 | ||
| 1188 | #define ixPCIEMSIX_VECT22_ADDR_HI_DEFAULT 0x00000000 | ||
| 1189 | #define ixPCIEMSIX_VECT22_MSG_DATA_DEFAULT 0x00000000 | ||
| 1190 | #define ixPCIEMSIX_VECT22_CONTROL_DEFAULT 0x00000000 | ||
| 1191 | #define ixPCIEMSIX_VECT23_ADDR_LO_DEFAULT 0x00000000 | ||
| 1192 | #define ixPCIEMSIX_VECT23_ADDR_HI_DEFAULT 0x00000000 | ||
| 1193 | #define ixPCIEMSIX_VECT23_MSG_DATA_DEFAULT 0x00000000 | ||
| 1194 | #define ixPCIEMSIX_VECT23_CONTROL_DEFAULT 0x00000000 | ||
| 1195 | #define ixPCIEMSIX_VECT24_ADDR_LO_DEFAULT 0x00000000 | ||
| 1196 | #define ixPCIEMSIX_VECT24_ADDR_HI_DEFAULT 0x00000000 | ||
| 1197 | #define ixPCIEMSIX_VECT24_MSG_DATA_DEFAULT 0x00000000 | ||
| 1198 | #define ixPCIEMSIX_VECT24_CONTROL_DEFAULT 0x00000000 | ||
| 1199 | #define ixPCIEMSIX_VECT25_ADDR_LO_DEFAULT 0x00000000 | ||
| 1200 | #define ixPCIEMSIX_VECT25_ADDR_HI_DEFAULT 0x00000000 | ||
| 1201 | #define ixPCIEMSIX_VECT25_MSG_DATA_DEFAULT 0x00000000 | ||
| 1202 | #define ixPCIEMSIX_VECT25_CONTROL_DEFAULT 0x00000000 | ||
| 1203 | #define ixPCIEMSIX_VECT26_ADDR_LO_DEFAULT 0x00000000 | ||
| 1204 | #define ixPCIEMSIX_VECT26_ADDR_HI_DEFAULT 0x00000000 | ||
| 1205 | #define ixPCIEMSIX_VECT26_MSG_DATA_DEFAULT 0x00000000 | ||
| 1206 | #define ixPCIEMSIX_VECT26_CONTROL_DEFAULT 0x00000000 | ||
| 1207 | #define ixPCIEMSIX_VECT27_ADDR_LO_DEFAULT 0x00000000 | ||
| 1208 | #define ixPCIEMSIX_VECT27_ADDR_HI_DEFAULT 0x00000000 | ||
| 1209 | #define ixPCIEMSIX_VECT27_MSG_DATA_DEFAULT 0x00000000 | ||
| 1210 | #define ixPCIEMSIX_VECT27_CONTROL_DEFAULT 0x00000000 | ||
| 1211 | #define ixPCIEMSIX_VECT28_ADDR_LO_DEFAULT 0x00000000 | ||
| 1212 | #define ixPCIEMSIX_VECT28_ADDR_HI_DEFAULT 0x00000000 | ||
| 1213 | #define ixPCIEMSIX_VECT28_MSG_DATA_DEFAULT 0x00000000 | ||
| 1214 | #define ixPCIEMSIX_VECT28_CONTROL_DEFAULT 0x00000000 | ||
| 1215 | #define ixPCIEMSIX_VECT29_ADDR_LO_DEFAULT 0x00000000 | ||
| 1216 | #define ixPCIEMSIX_VECT29_ADDR_HI_DEFAULT 0x00000000 | ||
| 1217 | #define ixPCIEMSIX_VECT29_MSG_DATA_DEFAULT 0x00000000 | ||
| 1218 | #define ixPCIEMSIX_VECT29_CONTROL_DEFAULT 0x00000000 | ||
| 1219 | #define ixPCIEMSIX_VECT30_ADDR_LO_DEFAULT 0x00000000 | ||
| 1220 | #define ixPCIEMSIX_VECT30_ADDR_HI_DEFAULT 0x00000000 | ||
| 1221 | #define ixPCIEMSIX_VECT30_MSG_DATA_DEFAULT 0x00000000 | ||
| 1222 | #define ixPCIEMSIX_VECT30_CONTROL_DEFAULT 0x00000000 | ||
| 1223 | #define ixPCIEMSIX_VECT31_ADDR_LO_DEFAULT 0x00000000 | ||
| 1224 | #define ixPCIEMSIX_VECT31_ADDR_HI_DEFAULT 0x00000000 | ||
| 1225 | #define ixPCIEMSIX_VECT31_MSG_DATA_DEFAULT 0x00000000 | ||
| 1226 | #define ixPCIEMSIX_VECT31_CONTROL_DEFAULT 0x00000000 | ||
| 1227 | |||
| 1228 | |||
| 1229 | // addressBlock: pciemsix_amdgfx_MSIXPDEC | ||
| 1230 | // base address: 0x10171000 | ||
| 1231 | #define ixPCIEMSIX_PBA_DEFAULT 0x00000000 | ||
| 1232 | |||
| 1233 | |||
| 1234 | // addressBlock: syshub_mmreg_ind_syshubind | ||
| 1235 | // base address: 0x0 | ||
| 1236 | #define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK_DEFAULT 0x00000000 | ||
| 1237 | #define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK_DEFAULT 0x00000100 | ||
| 1238 | #define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK_DEFAULT 0x00000000 | ||
| 1239 | #define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK_DEFAULT 0x00000000 | ||
| 1240 | #define ixSYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e | ||
| 1241 | #define ixSYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e | ||
| 1242 | #define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL_DEFAULT 0x20200000 | ||
| 1243 | #define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL_DEFAULT 0x20200000 | ||
| 1244 | #define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL_DEFAULT 0x20200000 | ||
| 1245 | #define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL_DEFAULT 0x20200000 | ||
| 1246 | #define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL_DEFAULT 0x20200000 | ||
| 1247 | #define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL_DEFAULT 0x20200000 | ||
| 1248 | #define ixSYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL_DEFAULT 0x20200000 | ||
| 1249 | #define ixSYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL_DEFAULT 0x20200000 | ||
| 1250 | #define ixSYSHUBMMREGIND_SYSHUB_CG_CNTL_DEFAULT 0x00082000 | ||
| 1251 | #define ixSYSHUBMMREGIND_SYSHUB_TRANS_IDLE_DEFAULT 0x00000000 | ||
| 1252 | #define ixSYSHUBMMREGIND_SYSHUB_HP_TIMER_DEFAULT 0x00000100 | ||
| 1253 | #define ixSYSHUBMMREGIND_SYSHUB_SCRATCH_DEFAULT 0x00000040 | ||
| 1254 | #define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK_DEFAULT 0x00000000 | ||
| 1255 | #define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK_DEFAULT 0x00000100 | ||
| 1256 | #define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK_DEFAULT 0x00000000 | ||
| 1257 | #define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK_DEFAULT 0x00000000 | ||
| 1258 | #define ixSYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e | ||
| 1259 | #define ixSYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e | ||
| 1260 | #define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL_DEFAULT 0x20200000 | ||
| 1261 | #define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL_DEFAULT 0x20200000 | ||
| 1262 | #define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL_DEFAULT 0x20200000 | ||
| 1263 | #define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL_DEFAULT 0x20200000 | ||
| 1264 | #define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL_DEFAULT 0x20200000 | ||
| 1265 | #define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL_DEFAULT 0x20200000 | ||
| 1266 | #define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL_DEFAULT 0x20200000 | ||
| 1267 | #define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL_DEFAULT 0x20200000 | ||
| 1268 | #define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL_DEFAULT 0x20200000 | ||
| 1269 | #define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL_DEFAULT 0x20200000 | ||
| 1270 | |||
| 1271 | #endif | ||