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authorArnd Bergmann <arnd@arndb.de>2017-10-30 09:06:39 -0400
committerArnd Bergmann <arnd@arndb.de>2017-10-30 09:06:39 -0400
commitda7920e31de98a149ab4048d7f05913429b84c2f (patch)
tree3d8b28bd38cba3e9f725892a0dcea473d57296dc
parent0292f8a8f8e9d74ad8519c92d712039edb8f08b4 (diff)
parent27e1acb759e0409ee140f3bdaf5c70c5582ddf91 (diff)
Merge tag 'imx-dt-4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt
Pull "i.MX device tree updates for 4.15" from Shawn Guo: - New board support: i.MX51 ZII RDU1, i.MX53 GE Healthcare PPD, i.MX6 TX modules for MB7 from Ka-Ro Electronics, i.MX6 Wandboard revd1 variants, i.MX6 LWN DISPLAY5 board, Pistachio i.MX6Q board, i.MX6SX Vining-2000 board. - Use the 'vpcie-supply' property for PCIe device for boards imx6qdl-sabresd, imx6q-novena and imx6q-cm-fx6. - A series from Jagan Teki to update imx6qdl-icore board with audio, touch and CAN support. - Switch to nvmem for accessing OCOTP from tempmon for i.MX6SX and add tempmon support for i.MX6UL. - A bunch of patches from Lothar Waßmann updating Ka-Ro i.MX28, i.MX53 and i.MX6 TX modules. - Fix DTC warnings in i.MX device trees, dropping leading zeros from unit address, correcting display nodes notation and display port names, fixing nodes with unit name and no reg property. - Other random device updates for various board support. * tag 'imx-dt-4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (63 commits) ARM: dts: imx53-tx53: fix interrupt flags ARM: dts: imx28-tx28: fix interrupt flags ARM: dts: display5: Device tree description of LWN's DISPLAY5 board ARM: dts: imx53-qsb-common: Fix 'led_gpio7_7@0' node with unit name and no reg property ARM: dts: imx53-m53evk: Fix 'led_gpio@0' node with unit name and no reg property ARM: dts: imx53: Fix 'usbphy@x' node with unit name and no reg property ARM: dts: imx51-ts4800: Fix 'port@0' node with unit name and no reg property ARM: dts: imx51-apf51dev: Fix 'backlight@bl1' node with unit name and no reg property ARM: dts: imx: add ZII RDU1 board ARM: dts: imx: add support for TX6 modules on MB7 baseboard ARM: dts: imx: add support for TX6QP ARM: dts: imx6-tx6: add a .dtsi file for the MB7 baseboard ARM: dts: imx6-tx6: move display configuration to .dtsi file ARM: dts: imx6-tx6: add support for I2C bus recovery ARM: dts: imx6-tx6: convert to using simple-audio-card ARM: dts: imx6-tx6: specify ethernet phy reset post-delay ARM: dts: imx6-tx6: improve ethernet related pinctrl setup ARM: dts: imx6-tx6: add trickle-charge config for DS1339 ARM: dts: imx6-tx6: remove obsolete ipu1 alias ARM: dts: imx6-tx6: remove obsolete eeti,egalax_ts ... [arnd: made sure we have no new leading zeroes in unit address during merge]
Diffstat
-rw-r--r--Documentation/devicetree/bindings/misc/ge-achc.txt26
-rw-r--r--arch/arm/boot/dts/Makefile20
-rw-r--r--arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts2
-rw-r--r--arch/arm/boot/dts/imx25-pdk.dts8
-rw-r--r--arch/arm/boot/dts/imx28-tx28.dts175
-rw-r--r--arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts2
-rw-r--r--arch/arm/boot/dts/imx50.dtsi1
-rw-r--r--arch/arm/boot/dts/imx51-apf51dev.dts10
-rw-r--r--arch/arm/boot/dts/imx51-babbage.dts12
-rw-r--r--arch/arm/boot/dts/imx51-ts4800.dts8
-rw-r--r--arch/arm/boot/dts/imx51-zii-rdu1.dts834
-rw-r--r--arch/arm/boot/dts/imx51.dtsi4
-rw-r--r--arch/arm/boot/dts/imx53-m53evk.dts4
-rw-r--r--arch/arm/boot/dts/imx53-mba53.dts2
-rw-r--r--arch/arm/boot/dts/imx53-ppd.dts1042
-rw-r--r--arch/arm/boot/dts/imx53-qsb-common.dtsi4
-rw-r--r--arch/arm/boot/dts/imx53-tx53-x03x.dts84
-rw-r--r--arch/arm/boot/dts/imx53-tx53-x13x.dts114
-rw-r--r--arch/arm/boot/dts/imx53-tx53.dtsi166
-rw-r--r--arch/arm/boot/dts/imx53.dtsi4
-rw-r--r--arch/arm/boot/dts/imx6dl-aristainetos2_4.dts2
-rw-r--r--arch/arm/boot/dts/imx6dl-aristainetos_4.dts2
-rw-r--r--arch/arm/boot/dts/imx6dl-aristainetos_7.dts2
-rw-r--r--arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts2
-rw-r--r--arch/arm/boot/dts/imx6dl-icore.dts9
-rw-r--r--arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts74
-rw-r--r--arch/arm/boot/dts/imx6dl-tx6s-8034-mb7.dts48
-rw-r--r--arch/arm/boot/dts/imx6dl-tx6s-8034.dts171
-rw-r--r--arch/arm/boot/dts/imx6dl-tx6s-8035-mb7.dts48
-rw-r--r--arch/arm/boot/dts/imx6dl-tx6s-8035.dts171
-rw-r--r--arch/arm/boot/dts/imx6dl-tx6u-801x.dts161
-rw-r--r--arch/arm/boot/dts/imx6dl-tx6u-8033-mb7.dts48
-rw-r--r--arch/arm/boot/dts/imx6dl-tx6u-8033.dts170
-rw-r--r--arch/arm/boot/dts/imx6dl-tx6u-80xx-mb7.dts48
-rw-r--r--arch/arm/boot/dts/imx6dl-tx6u-811x.dts132
-rw-r--r--arch/arm/boot/dts/imx6dl-tx6u-81xx-mb7.dts215
-rw-r--r--arch/arm/boot/dts/imx6dl-wandboard-revd1.dts22
-rw-r--r--arch/arm/boot/dts/imx6q-apalis-eval.dts2
-rw-r--r--arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts2
-rw-r--r--arch/arm/boot/dts/imx6q-apalis-ixora.dts2
-rw-r--r--arch/arm/boot/dts/imx6q-cm-fx6.dts5
-rw-r--r--arch/arm/boot/dts/imx6q-display5-tianma-tm070-1280x768.dts51
-rw-r--r--arch/arm/boot/dts/imx6q-display5.dtsi596
-rw-r--r--arch/arm/boot/dts/imx6q-gw5400-a.dts215
-rw-r--r--arch/arm/boot/dts/imx6q-icore-rqs.dts24
-rw-r--r--arch/arm/boot/dts/imx6q-novena.dts2
-rw-r--r--arch/arm/boot/dts/imx6q-pistachio.dts693
-rw-r--r--arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts74
-rw-r--r--arch/arm/boot/dts/imx6q-tx6q-1010.dts163
-rw-r--r--arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts74
-rw-r--r--arch/arm/boot/dts/imx6q-tx6q-1020.dts162
-rw-r--r--arch/arm/boot/dts/imx6q-tx6q-1036-mb7.dts48
-rw-r--r--arch/arm/boot/dts/imx6q-tx6q-1036.dts170
-rw-r--r--arch/arm/boot/dts/imx6q-tx6q-10x0-mb7.dts48
-rw-r--r--arch/arm/boot/dts/imx6q-tx6q-1110.dts134
-rw-r--r--arch/arm/boot/dts/imx6q-tx6q-11x0-mb7.dts222
-rw-r--r--arch/arm/boot/dts/imx6q-utilite-pro.dts8
-rw-r--r--arch/arm/boot/dts/imx6q-wandboard-revd1.dts26
-rw-r--r--arch/arm/boot/dts/imx6qdl-apf6dev.dtsi2
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw51xx.dtsi300
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw52xx.dtsi370
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw53xx.dtsi356
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw54xx.dtsi384
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw551x.dtsi182
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw552x.dtsi174
-rw-r--r--arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi94
-rw-r--r--arch/arm/boot/dts/imx6qdl-icore.dtsi97
-rw-r--r--arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi2
-rw-r--r--arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi2
-rw-r--r--arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi2
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabrelite.dtsi2
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabresd.dtsi10
-rw-r--r--arch/arm/boot/dts/imx6qdl-tx6-lcd.dtsi252
-rw-r--r--arch/arm/boot/dts/imx6qdl-tx6-lvds.dtsi286
-rw-r--r--arch/arm/boot/dts/imx6qdl-tx6-mb7.dtsi99
-rw-r--r--arch/arm/boot/dts/imx6qdl-tx6.dtsi104
-rw-r--r--arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi196
-rw-r--r--arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi3
-rw-r--r--arch/arm/boot/dts/imx6qdl.dtsi4
-rw-r--r--arch/arm/boot/dts/imx6qp-tx6qp-8037-mb7.dts48
-rw-r--r--arch/arm/boot/dts/imx6qp-tx6qp-8037.dts86
-rw-r--r--arch/arm/boot/dts/imx6qp-tx6qp-8137-mb7.dts57
-rw-r--r--arch/arm/boot/dts/imx6qp-tx6qp-8137.dts90
-rw-r--r--arch/arm/boot/dts/imx6qp-wandboard-revd1.dts26
-rw-r--r--arch/arm/boot/dts/imx6sx-softing-vining-2000.dts572
-rw-r--r--arch/arm/boot/dts/imx6sx.dtsi13
-rw-r--r--arch/arm/boot/dts/imx6ul-14x14-evk.dts2
-rw-r--r--arch/arm/boot/dts/imx6ul-pico-hobbit.dts2
-rw-r--r--arch/arm/boot/dts/imx6ul-tx6ul.dtsi2
-rw-r--r--arch/arm/boot/dts/imx6ul.dtsi19
-rw-r--r--arch/arm/boot/dts/imx7d-pico.dts39
91 files changed, 7094 insertions, 3351 deletions
diff --git a/Documentation/devicetree/bindings/misc/ge-achc.txt b/Documentation/devicetree/bindings/misc/ge-achc.txt
new file mode 100644
index 000000000000..77df94d7a32f
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/ge-achc.txt
@@ -0,0 +1,26 @@
1* GE Healthcare USB Management Controller
2
3A device which handles data aquisition from compatible USB based peripherals.
4SPI is used for device management.
5
6Note: This device does not expose the peripherals as USB devices.
7
8Required properties:
9
10- compatible : Should be "ge,achc"
11
12Required SPI properties:
13
14- reg : Should be address of the device chip select within
15 the controller.
16
17- spi-max-frequency : Maximum SPI clocking speed of device in Hz, should be
18 1MHz for the GE ACHC.
19
20Example:
21
22spidev0: spi@0 {
23 compatible = "ge,achc";
24 reg = <0>;
25 spi-max-frequency = <1000000>;
26};
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 53d03731e845..50acc79fadf7 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -348,12 +348,14 @@ dtb-$(CONFIG_SOC_IMX51) += \
348 imx51-babbage.dtb \ 348 imx51-babbage.dtb \
349 imx51-digi-connectcore-jsk.dtb \ 349 imx51-digi-connectcore-jsk.dtb \
350 imx51-eukrea-mbimxsd51-baseboard.dtb \ 350 imx51-eukrea-mbimxsd51-baseboard.dtb \
351 imx51-ts4800.dtb 351 imx51-ts4800.dtb \
352 imx51-zii-rdu1.dtb
352dtb-$(CONFIG_SOC_IMX53) += \ 353dtb-$(CONFIG_SOC_IMX53) += \
353 imx53-ard.dtb \ 354 imx53-ard.dtb \
354 imx53-cx9020.dtb \ 355 imx53-cx9020.dtb \
355 imx53-m53evk.dtb \ 356 imx53-m53evk.dtb \
356 imx53-mba53.dtb \ 357 imx53-mba53.dtb \
358 imx53-ppd.dtb \
357 imx53-qsb.dtb \ 359 imx53-qsb.dtb \
358 imx53-qsrb.dtb \ 360 imx53-qsrb.dtb \
359 imx53-smd.dtb \ 361 imx53-smd.dtb \
@@ -395,14 +397,19 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
395 imx6dl-ts4900.dtb \ 397 imx6dl-ts4900.dtb \
396 imx6dl-tx6dl-comtft.dtb \ 398 imx6dl-tx6dl-comtft.dtb \
397 imx6dl-tx6s-8034.dtb \ 399 imx6dl-tx6s-8034.dtb \
400 imx6dl-tx6s-8034-mb7.dtb \
398 imx6dl-tx6s-8035.dtb \ 401 imx6dl-tx6s-8035.dtb \
402 imx6dl-tx6s-8035-mb7.dtb \
399 imx6dl-tx6u-801x.dtb \ 403 imx6dl-tx6u-801x.dtb \
404 imx6dl-tx6u-80xx-mb7.dtb \
400 imx6dl-tx6u-8033.dtb \ 405 imx6dl-tx6u-8033.dtb \
406 imx6dl-tx6u-8033-mb7.dtb \
401 imx6dl-tx6u-811x.dtb \ 407 imx6dl-tx6u-811x.dtb \
402 imx6dl-tx6u-81xx-mb7.dtb \ 408 imx6dl-tx6u-81xx-mb7.dtb \
403 imx6dl-udoo.dtb \ 409 imx6dl-udoo.dtb \
404 imx6dl-wandboard.dtb \ 410 imx6dl-wandboard.dtb \
405 imx6dl-wandboard-revb1.dtb \ 411 imx6dl-wandboard-revb1.dtb \
412 imx6dl-wandboard-revd1.dtb \
406 imx6q-apalis-eval.dtb \ 413 imx6q-apalis-eval.dtb \
407 imx6q-apalis-ixora.dtb \ 414 imx6q-apalis-ixora.dtb \
408 imx6q-apalis-ixora-v1.1.dtb \ 415 imx6q-apalis-ixora-v1.1.dtb \
@@ -414,6 +421,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
414 imx6q-cm-fx6.dtb \ 421 imx6q-cm-fx6.dtb \
415 imx6q-cubox-i.dtb \ 422 imx6q-cubox-i.dtb \
416 imx6q-dfi-fs700-m60.dtb \ 423 imx6q-dfi-fs700-m60.dtb \
424 imx6q-display5-tianma-tm070-1280x768.dtb \
417 imx6q-dmo-edmqmx6.dtb \ 425 imx6q-dmo-edmqmx6.dtb \
418 imx6q-evi.dtb \ 426 imx6q-evi.dtb \
419 imx6q-gk802.dtb \ 427 imx6q-gk802.dtb \
@@ -441,6 +449,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
441 imx6q-nitrogen6_som2.dtb \ 449 imx6q-nitrogen6_som2.dtb \
442 imx6q-novena.dtb \ 450 imx6q-novena.dtb \
443 imx6q-phytec-pbab01.dtb \ 451 imx6q-phytec-pbab01.dtb \
452 imx6q-pistachio.dtb \
444 imx6q-rex-pro.dtb \ 453 imx6q-rex-pro.dtb \
445 imx6q-sabreauto.dtb \ 454 imx6q-sabreauto.dtb \
446 imx6q-sabrelite.dtb \ 455 imx6q-sabrelite.dtb \
@@ -454,17 +463,25 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
454 imx6q-tx6q-1020.dtb \ 463 imx6q-tx6q-1020.dtb \
455 imx6q-tx6q-1020-comtft.dtb \ 464 imx6q-tx6q-1020-comtft.dtb \
456 imx6q-tx6q-1036.dtb \ 465 imx6q-tx6q-1036.dtb \
466 imx6q-tx6q-1036-mb7.dtb \
467 imx6q-tx6q-10x0-mb7.dtb \
457 imx6q-tx6q-1110.dtb \ 468 imx6q-tx6q-1110.dtb \
458 imx6q-tx6q-11x0-mb7.dtb \ 469 imx6q-tx6q-11x0-mb7.dtb \
459 imx6q-udoo.dtb \ 470 imx6q-udoo.dtb \
460 imx6q-utilite-pro.dtb \ 471 imx6q-utilite-pro.dtb \
461 imx6q-wandboard.dtb \ 472 imx6q-wandboard.dtb \
462 imx6q-wandboard-revb1.dtb \ 473 imx6q-wandboard-revb1.dtb \
474 imx6q-wandboard-revd1.dtb \
463 imx6q-zii-rdu2.dtb \ 475 imx6q-zii-rdu2.dtb \
464 imx6qp-nitrogen6_max.dtb \ 476 imx6qp-nitrogen6_max.dtb \
465 imx6qp-nitrogen6_som2.dtb \ 477 imx6qp-nitrogen6_som2.dtb \
466 imx6qp-sabreauto.dtb \ 478 imx6qp-sabreauto.dtb \
467 imx6qp-sabresd.dtb \ 479 imx6qp-sabresd.dtb \
480 imx6qp-tx6qp-8037.dtb \
481 imx6qp-tx6qp-8037-mb7.dtb \
482 imx6qp-tx6qp-8137.dtb \
483 imx6qp-tx6qp-8137-mb7.dtb \
484 imx6qp-wandboard-revd1.dtb \
468 imx6qp-zii-rdu2.dtb 485 imx6qp-zii-rdu2.dtb
469dtb-$(CONFIG_SOC_IMX6SL) += \ 486dtb-$(CONFIG_SOC_IMX6SL) += \
470 imx6sl-evk.dtb \ 487 imx6sl-evk.dtb \
@@ -475,6 +492,7 @@ dtb-$(CONFIG_SOC_IMX6SX) += \
475 imx6sx-sdb-reva.dtb \ 492 imx6sx-sdb-reva.dtb \
476 imx6sx-sdb-sai.dtb \ 493 imx6sx-sdb-sai.dtb \
477 imx6sx-sdb.dtb \ 494 imx6sx-sdb.dtb \
495 imx6sx-softing-vining-2000.dtb \
478 imx6sx-udoo-neo-basic.dtb \ 496 imx6sx-udoo-neo-basic.dtb \
479 imx6sx-udoo-neo-extended.dtb \ 497 imx6sx-udoo-neo-extended.dtb \
480 imx6sx-udoo-neo-full.dtb 498 imx6sx-udoo-neo-full.dtb
diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
index db39bd6b8e00..0f053721d80f 100644
--- a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
+++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
@@ -64,7 +64,7 @@
64&esdhc1 { 64&esdhc1 {
65 pinctrl-names = "default"; 65 pinctrl-names = "default";
66 pinctrl-0 = <&pinctrl_esdhc1>; 66 pinctrl-0 = <&pinctrl_esdhc1>;
67 cd-gpios = <&gpio1 20>; 67 cd-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
68 status = "okay"; 68 status = "okay";
69}; 69};
70 70
diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts
index 443e0dc2fd9e..2d15ce72d006 100644
--- a/arch/arm/boot/dts/imx25-pdk.dts
+++ b/arch/arm/boot/dts/imx25-pdk.dts
@@ -295,6 +295,14 @@
295 status = "okay"; 295 status = "okay";
296}; 296};
297 297
298&tsc {
299 status = "okay";
300};
301
302&tscadc {
303 status = "okay";
304};
305
298&uart1 { 306&uart1 {
299 pinctrl-names = "default"; 307 pinctrl-names = "default";
300 pinctrl-0 = <&pinctrl_uart1>; 308 pinctrl-0 = <&pinctrl_uart1>;
diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts
index 4e52be1aa2c3..152621ea37db 100644
--- a/arch/arm/boot/dts/imx28-tx28.dts
+++ b/arch/arm/boot/dts/imx28-tx28.dts
@@ -1,13 +1,43 @@
1/* 1/*
2 * Copyright 2012 Shawn Guo <shawn.guo@linaro.org> 2 * Copyright 2012 Shawn Guo <shawn.guo@linaro.org>
3 * Copyright 2013 Lothar Waßmann <LW@KARO-electronics.de> 3 * Copyright 2013-2017 Lothar Waßmann <LW@KARO-electronics.de>
4 * 4 *
5 * The code contained herein is licensed under the GNU General Public 5 * This file is dual-licensed: you can use it either under the terms
6 * License. You may obtain a copy of the GNU General Public License 6 * of the GPL or the X11 license, at your option. Note that this dual
7 * Version 2 at the following locations: 7 * licensing only applies to this file, and not this project as a
8 * whole.
8 * 9 *
9 * http://www.opensource.org/licenses/gpl-license.html 10 * a) This file is free software; you can redistribute it and/or
10 * http://www.gnu.org/copyleft/gpl.html 11 * modify it under the terms of the GNU General Public License
12 * version 2 as published by the Free Software Foundation.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
11 */ 41 */
12 42
13/dts-v1/; 43/dts-v1/;
@@ -45,82 +75,69 @@
45 status = "disabled"; 75 status = "disabled";
46 }; 76 };
47 77
48 regulators { 78 reg_usb0_vbus: regulator-usb0-vbus {
49 compatible = "simple-bus"; 79 compatible = "regulator-fixed";
50 #address-cells = <1>; 80 regulator-name = "usb0_vbus";
51 #size-cells = <0>; 81 regulator-min-microvolt = <5000000>;
52 82 regulator-max-microvolt = <5000000>;
53 reg_usb0_vbus: regulator@0 { 83 gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>;
54 compatible = "regulator-fixed"; 84 enable-active-high;
55 reg = <0>; 85 };
56 regulator-name = "usb0_vbus";
57 regulator-min-microvolt = <5000000>;
58 regulator-max-microvolt = <5000000>;
59 gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>;
60 enable-active-high;
61 };
62 86
63 reg_usb1_vbus: regulator@1 { 87 reg_usb1_vbus: regulator-usb1-vbus {
64 compatible = "regulator-fixed"; 88 compatible = "regulator-fixed";
65 reg = <1>; 89 regulator-name = "usb1_vbus";
66 regulator-name = "usb1_vbus"; 90 regulator-min-microvolt = <5000000>;
67 regulator-min-microvolt = <5000000>; 91 regulator-max-microvolt = <5000000>;
68 regulator-max-microvolt = <5000000>; 92 gpio = <&gpio3 27 GPIO_ACTIVE_HIGH>;
69 gpio = <&gpio3 27 GPIO_ACTIVE_HIGH>; 93 enable-active-high;
70 enable-active-high; 94 };
71 };
72 95
73 reg_2p5v: regulator@2 { 96 reg_2p5v: regulator-2p5v {
74 compatible = "regulator-fixed"; 97 compatible = "regulator-fixed";
75 reg = <2>; 98 regulator-name = "2P5V";
76 regulator-name = "2P5V"; 99 regulator-min-microvolt = <2500000>;
77 regulator-min-microvolt = <2500000>; 100 regulator-max-microvolt = <2500000>;
78 regulator-max-microvolt = <2500000>; 101 regulator-always-on;
79 regulator-always-on; 102 };
80 };
81 103
82 reg_3p3v: regulator@3 { 104 reg_3p3v: regulator-3p3v {
83 compatible = "regulator-fixed"; 105 compatible = "regulator-fixed";
84 reg = <3>; 106 regulator-name = "3P3V";
85 regulator-name = "3P3V"; 107 regulator-min-microvolt = <3300000>;
86 regulator-min-microvolt = <3300000>; 108 regulator-max-microvolt = <3300000>;
87 regulator-max-microvolt = <3300000>; 109 regulator-always-on;
88 regulator-always-on; 110 };
89 };
90 111
91 reg_can_xcvr: regulator@4 { 112 reg_can_xcvr: regulator-can-xcvr {
92 compatible = "regulator-fixed"; 113 compatible = "regulator-fixed";
93 reg = <4>; 114 regulator-name = "CAN XCVR";
94 regulator-name = "CAN XCVR"; 115 regulator-min-microvolt = <3300000>;
95 regulator-min-microvolt = <3300000>; 116 regulator-max-microvolt = <3300000>;
96 regulator-max-microvolt = <3300000>; 117 gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
97 gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; 118 pinctrl-names = "default";
98 pinctrl-names = "default"; 119 pinctrl-0 = <&tx28_flexcan_xcvr_pins>;
99 pinctrl-0 = <&tx28_flexcan_xcvr_pins>; 120 };
100 };
101 121
102 reg_lcd: regulator@5 { 122 reg_lcd: regulator-lcd-power {
103 compatible = "regulator-fixed"; 123 compatible = "regulator-fixed";
104 reg = <5>; 124 regulator-name = "LCD POWER";
105 regulator-name = "LCD POWER"; 125 regulator-min-microvolt = <3300000>;
106 regulator-min-microvolt = <3300000>; 126 regulator-max-microvolt = <3300000>;
107 regulator-max-microvolt = <3300000>; 127 gpio = <&gpio1 31 GPIO_ACTIVE_HIGH>;
108 gpio = <&gpio1 31 GPIO_ACTIVE_HIGH>; 128 enable-active-high;
109 enable-active-high; 129 };
110 };
111 130
112 reg_lcd_reset: regulator@6 { 131 reg_lcd_reset: regulator-lcd-reset {
113 compatible = "regulator-fixed"; 132 compatible = "regulator-fixed";
114 reg = <6>; 133 regulator-name = "LCD RESET";
115 regulator-name = "LCD RESET"; 134 regulator-min-microvolt = <3300000>;
116 regulator-min-microvolt = <3300000>; 135 regulator-max-microvolt = <3300000>;
117 regulator-max-microvolt = <3300000>; 136 gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
118 gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; 137 startup-delay-us = <300000>;
119 startup-delay-us = <300000>; 138 enable-active-high;
120 enable-active-high; 139 regulator-always-on;
121 regulator-always-on; 140 regulator-boot-on;
122 regulator-boot-on;
123 };
124 }; 141 };
125 142
126 clocks { 143 clocks {
@@ -312,7 +329,7 @@
312 pinctrl-names = "default"; 329 pinctrl-names = "default";
313 pinctrl-0 = <&tx28_pca9554_pins>; 330 pinctrl-0 = <&tx28_pca9554_pins>;
314 interrupt-parent = <&gpio3>; 331 interrupt-parent = <&gpio3>;
315 interrupts = <28 0>; 332 interrupts = <28 IRQ_TYPE_NONE>;
316 gpio-controller; 333 gpio-controller;
317 #gpio-cells = <2>; 334 #gpio-cells = <2>;
318 interrupt-controller; 335 interrupt-controller;
@@ -336,7 +353,7 @@
336 pinctrl-names = "default"; 353 pinctrl-names = "default";
337 pinctrl-0 = <&tx28_tsc2007_pins>; 354 pinctrl-0 = <&tx28_tsc2007_pins>;
338 interrupt-parent = <&gpio3>; 355 interrupt-parent = <&gpio3>;
339 interrupts = <20 0>; 356 interrupts = <20 IRQ_TYPE_EDGE_FALLING>;
340 pendown-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; 357 pendown-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
341 ti,x-plate-ohms = /bits/ 16 <660>; 358 ti,x-plate-ohms = /bits/ 16 <660>;
342 }; 359 };
@@ -344,6 +361,8 @@
344 ds1339: rtc@68 { 361 ds1339: rtc@68 {
345 compatible = "mxim,ds1339"; 362 compatible = "mxim,ds1339";
346 reg = <0x68>; 363 reg = <0x68>;
364 trickle-resistor-ohms = <250>;
365 trickle-diode-disable;
347 }; 366 };
348}; 367};
349 368
diff --git a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts
index e9357131b026..ae98d6759074 100644
--- a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts
+++ b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts
@@ -65,7 +65,7 @@
65&esdhc1 { 65&esdhc1 {
66 pinctrl-names = "default"; 66 pinctrl-names = "default";
67 pinctrl-0 = <&pinctrl_esdhc1>; 67 pinctrl-0 = <&pinctrl_esdhc1>;
68 cd-gpios = <&gpio3 24>; 68 cd-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
69 status = "okay"; 69 status = "okay";
70}; 70};
71 71
diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi
index d85034c0fb83..35955e63d6c5 100644
--- a/arch/arm/boot/dts/imx50.dtsi
+++ b/arch/arm/boot/dts/imx50.dtsi
@@ -443,6 +443,7 @@
443 clocks = <&clks IMX5_CLK_SDMA_GATE>, 443 clocks = <&clks IMX5_CLK_SDMA_GATE>,
444 <&clks IMX5_CLK_SDMA_GATE>; 444 <&clks IMX5_CLK_SDMA_GATE>;
445 clock-names = "ipg", "ahb"; 445 clock-names = "ipg", "ahb";
446 #dma-cells = <3>;
446 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin"; 447 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
447 }; 448 };
448 449
diff --git a/arch/arm/boot/dts/imx51-apf51dev.dts b/arch/arm/boot/dts/imx51-apf51dev.dts
index a5e6091c8729..3e1846a64d93 100644
--- a/arch/arm/boot/dts/imx51-apf51dev.dts
+++ b/arch/arm/boot/dts/imx51-apf51dev.dts
@@ -16,7 +16,7 @@
16 model = "Armadeus Systems APF51Dev docking/development board"; 16 model = "Armadeus Systems APF51Dev docking/development board";
17 compatible = "armadeus,imx51-apf51dev", "armadeus,imx51-apf51", "fsl,imx51"; 17 compatible = "armadeus,imx51-apf51dev", "armadeus,imx51-apf51", "fsl,imx51";
18 18
19 backlight@bl1{ 19 backlight {
20 pinctrl-names = "default"; 20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_backlight>; 21 pinctrl-0 = <&pinctrl_backlight>;
22 compatible = "gpio-backlight"; 22 compatible = "gpio-backlight";
@@ -24,7 +24,7 @@
24 default-on; 24 default-on;
25 }; 25 };
26 26
27 display@di1 { 27 disp1 {
28 compatible = "fsl,imx-parallel-display"; 28 compatible = "fsl,imx-parallel-display";
29 interface-pix-fmt = "bgr666"; 29 interface-pix-fmt = "bgr666";
30 pinctrl-names = "default"; 30 pinctrl-names = "default";
@@ -51,7 +51,7 @@
51 51
52 port { 52 port {
53 display_in: endpoint { 53 display_in: endpoint {
54 remote-endpoint = <&ipu_di0_disp0>; 54 remote-endpoint = <&ipu_di0_disp1>;
55 }; 55 };
56 }; 56 };
57 }; 57 };
@@ -120,7 +120,7 @@
120 pinctrl-0 = <&pinctrl_hog>; 120 pinctrl-0 = <&pinctrl_hog>;
121 121
122 imx51-apf51dev { 122 imx51-apf51dev {
123 pinctrl_backlight: bl1grp { 123 pinctrl_backlight: backlightgrp {
124 fsl,pins = < 124 fsl,pins = <
125 MX51_PAD_DI1_D1_CS__GPIO3_4 0x1F5 125 MX51_PAD_DI1_D1_CS__GPIO3_4 0x1F5
126 >; 126 >;
@@ -218,6 +218,6 @@
218 }; 218 };
219}; 219};
220 220
221&ipu_di0_disp0 { 221&ipu_di0_disp1 {
222 remote-endpoint = <&display_in>; 222 remote-endpoint = <&display_in>;
223}; 223};
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index 55f1de299cac..2a694c5cc8ae 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -39,7 +39,7 @@
39 }; 39 };
40 }; 40 };
41 41
42 display0: display@di0 { 42 display1: disp1 {
43 compatible = "fsl,imx-parallel-display"; 43 compatible = "fsl,imx-parallel-display";
44 interface-pix-fmt = "rgb24"; 44 interface-pix-fmt = "rgb24";
45 pinctrl-names = "default"; 45 pinctrl-names = "default";
@@ -61,12 +61,12 @@
61 61
62 port { 62 port {
63 display0_in: endpoint { 63 display0_in: endpoint {
64 remote-endpoint = <&ipu_di0_disp0>; 64 remote-endpoint = <&ipu_di0_disp1>;
65 }; 65 };
66 }; 66 };
67 }; 67 };
68 68
69 display1: display@di1 { 69 display2: disp2 {
70 compatible = "fsl,imx-parallel-display"; 70 compatible = "fsl,imx-parallel-display";
71 interface-pix-fmt = "rgb565"; 71 interface-pix-fmt = "rgb565";
72 pinctrl-names = "default"; 72 pinctrl-names = "default";
@@ -93,7 +93,7 @@
93 93
94 port { 94 port {
95 display1_in: endpoint { 95 display1_in: endpoint {
96 remote-endpoint = <&ipu_di1_disp1>; 96 remote-endpoint = <&ipu_di1_disp2>;
97 }; 97 };
98 }; 98 };
99 }; 99 };
@@ -348,11 +348,11 @@
348 }; 348 };
349}; 349};
350 350
351&ipu_di0_disp0 { 351&ipu_di0_disp1 {
352 remote-endpoint = <&display0_in>; 352 remote-endpoint = <&display0_in>;
353}; 353};
354 354
355&ipu_di1_disp1 { 355&ipu_di1_disp2 {
356 remote-endpoint = <&display1_in>; 356 remote-endpoint = <&display1_in>;
357}; 357};
358 358
diff --git a/arch/arm/boot/dts/imx51-ts4800.dts b/arch/arm/boot/dts/imx51-ts4800.dts
index ca1cc5eca80f..564233e97412 100644
--- a/arch/arm/boot/dts/imx51-ts4800.dts
+++ b/arch/arm/boot/dts/imx51-ts4800.dts
@@ -50,7 +50,7 @@
50 power-supply = <&backlight_reg>; 50 power-supply = <&backlight_reg>;
51 }; 51 };
52 52
53 display0: display@di0 { 53 display1: disp1 {
54 compatible = "fsl,imx-parallel-display"; 54 compatible = "fsl,imx-parallel-display";
55 interface-pix-fmt = "rgb24"; 55 interface-pix-fmt = "rgb24";
56 pinctrl-names = "default"; 56 pinctrl-names = "default";
@@ -71,9 +71,9 @@
71 }; 71 };
72 }; 72 };
73 73
74 port@0 { 74 port {
75 display0_in: endpoint { 75 display0_in: endpoint {
76 remote-endpoint = <&ipu_di0_disp0>; 76 remote-endpoint = <&ipu_di0_disp1>;
77 }; 77 };
78 }; 78 };
79 }; 79 };
@@ -107,7 +107,7 @@
107 }; 107 };
108}; 108};
109 109
110&ipu_di0_disp0 { 110&ipu_di0_disp1 {
111 remote-endpoint = <&display0_in>; 111 remote-endpoint = <&display0_in>;
112}; 112};
113 113
diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts
new file mode 100644
index 000000000000..49be0e1c812d
--- /dev/null
+++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts
@@ -0,0 +1,834 @@
1/*
2 * Copyright (C) 2017 Zodiac Inflight Innovations
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42/dts-v1/;
43#include "imx51.dtsi"
44#include <dt-bindings/sound/fsl-imx-audmux.h>
45
46/ {
47 model = "ZII RDU1 Board";
48 compatible = "zii,imx51-rdu1", "fsl,imx51";
49
50 chosen {
51 stdout-path = &uart1;
52 };
53
54 aliases {
55 mdio-gpio0 = &mdio_gpio;
56 rtc0 = &ds1341;
57 };
58
59 clk_26M_osc: 26M_osc {
60 compatible = "fixed-clock";
61 #clock-cells = <0>;
62 clock-frequency = <26000000>;
63 };
64
65 clk_26M_osc_gate: 26M_gate {
66 compatible = "gpio-gate-clock";
67 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_clk26mhz>;
69 clocks = <&clk_26M_osc>;
70 #clock-cells = <0>;
71 enable-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>;
72 };
73
74 clk_26M_usb: usbhost_gate {
75 compatible = "gpio-gate-clock";
76 pinctrl-names = "default";
77 pinctrl-0 = <&pinctrl_usbgate26mhz>;
78 clocks = <&clk_26M_osc_gate>;
79 #clock-cells = <0>;
80 enable-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
81 };
82
83 clk_26M_snd: snd_gate {
84 compatible = "gpio-gate-clock";
85 pinctrl-names = "default";
86 pinctrl-0 = <&pinctrl_sndgate26mhz>;
87 clocks = <&clk_26M_osc_gate>;
88 #clock-cells = <0>;
89 enable-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
90 };
91
92 reg_5p0v_main: regulator-5p0v-main {
93 compatible = "regulator-fixed";
94 regulator-name = "5V_MAIN";
95 regulator-min-microvolt = <5000000>;
96 regulator-max-microvolt = <5000000>;
97 regulator-always-on;
98 };
99
100 reg_3p3v: regulator-3p3v {
101 compatible = "regulator-fixed";
102 regulator-name = "3.3V";
103 regulator-min-microvolt = <3300000>;
104 regulator-max-microvolt = <3300000>;
105 regulator-always-on;
106 };
107
108 disp0 {
109 compatible = "fsl,imx-parallel-display";
110 pinctrl-names = "default";
111 pinctrl-0 = <&pinctrl_ipu_disp1>;
112
113 #address-cells = <1>;
114 #size-cells = <0>;
115
116 port@0 {
117 reg = <0>;
118
119 display_in: endpoint {
120 remote-endpoint = <&ipu_di0_disp1>;
121 };
122 };
123
124 port@1 {
125 reg = <1>;
126
127 display_out: endpoint {
128 remote-endpoint = <&panel_in>;
129 };
130 };
131 };
132
133 panel {
134 /* no compatible here, bootloader will patch in correct one */
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_panel>;
137 power-supply = <&reg_3p3v>;
138 enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
139 status = "disabled";
140
141 port {
142 panel_in: endpoint {
143 remote-endpoint = <&display_out>;
144 };
145 };
146 };
147
148 i2c_gpio: i2c-gpio {
149 compatible = "i2c-gpio";
150 pinctrl-names = "default";
151 pinctrl-0 = <&pinctrl_swi2c>;
152 gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>, /* sda */
153 <&gpio3 4 GPIO_ACTIVE_HIGH>; /* scl */
154 i2c-gpio,delay-us = <50>;
155 status = "okay";
156
157 #address-cells = <1>;
158 #size-cells = <0>;
159
160 sgtl5000: codec@a {
161 compatible = "fsl,sgtl5000";
162 reg = <0x0a>;
163 clocks = <&clk_26M_snd>;
164 VDDA-supply = <&vdig_reg>;
165 VDDIO-supply = <&vvideo_reg>;
166 #sound-dai-cells = <0>;
167 };
168 };
169
170 spi_gpio: spi-gpio {
171 compatible = "spi-gpio";
172 #address-cells = <1>;
173 #size-cells = <0>;
174 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_gpiospi0>;
176 status = "okay";
177
178 gpio-sck = <&gpio4 15 GPIO_ACTIVE_HIGH>;
179 gpio-mosi = <&gpio4 12 GPIO_ACTIVE_HIGH>;
180 gpio-miso = <&gpio4 11 GPIO_ACTIVE_HIGH>;
181 num-chipselects = <1>;
182 cs-gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>;
183
184 eeprom@0 {
185 compatible = "eeprom-93xx46";
186 reg = <0>;
187 spi-max-frequency = <1000000>;
188 spi-cs-high;
189 data-size = <8>;
190 };
191 };
192
193 mdio_gpio: mdio-gpio {
194 compatible = "virtual,mdio-gpio";
195 pinctrl-names = "default";
196 pinctrl-0 = <&pinctrl_swmdio>;
197 gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>, /* mdc */
198 <&gpio3 25 GPIO_ACTIVE_HIGH>; /* mdio */
199
200 #address-cells = <1>;
201 #size-cells = <0>;
202
203 switch@0 {
204 compatible = "marvell,mv88e6085";
205 #address-cells = <1>;
206 #size-cells = <0>;
207 reg = <0>;
208 dsa,member = <0 0>;
209
210 ports {
211 #address-cells = <1>;
212 #size-cells = <0>;
213
214 port@0 {
215 reg = <0>;
216 label = "cpu";
217 ethernet = <&fec>;
218
219 fixed-link {
220 speed = <100>;
221 full-duplex;
222 };
223 };
224
225 port@1 {
226 reg = <1>;
227 label = "netaux";
228 };
229
230 port@3 {
231 reg = <3>;
232 label = "netright";
233 };
234
235 port@4 {
236 reg = <4>;
237 label = "netleft";
238 };
239 };
240 };
241 };
242
243 sound {
244 compatible = "simple-audio-card";
245 simple-audio-card,name = "RDU1 audio";
246 simple-audio-card,format = "i2s";
247 simple-audio-card,bitclock-master = <&sound_codec>;
248 simple-audio-card,frame-master = <&sound_codec>;
249 simple-audio-card,widgets =
250 "Headphone", "Headphone Jack";
251 simple-audio-card,routing =
252 "Headphone Jack", "HPLEFT",
253 "Headphone Jack", "HPRIGHT";
254 simple-audio-card,aux-devs = <&tpa6130a2>;
255
256 sound_cpu: simple-audio-card,cpu {
257 sound-dai = <&ssi2>;
258 };
259
260 sound_codec: simple-audio-card,codec {
261 sound-dai = <&sgtl5000>;
262 clocks = <&clk_26M_snd>;
263 };
264 };
265
266 usbh1phy: usbphy1 {
267 compatible = "usb-nop-xceiv";
268 pinctrl-names = "default";
269 pinctrl-0 = <&pinctrl_usbh1phy>;
270 clocks = <&clk_26M_usb>;
271 clock-names = "main_clk";
272 reset-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
273 vcc-supply = <&vusb_reg>;
274 };
275
276 usbh2phy: usbphy2 {
277 compatible = "usb-nop-xceiv";
278 pinctrl-names = "default";
279 pinctrl-0 = <&pinctrl_usbh2phy>;
280 clocks = <&clk_26M_usb>;
281 clock-names = "main_clk";
282 reset-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
283 vcc-supply = <&vusb_reg>;
284 };
285};
286
287&audmux {
288 pinctrl-names = "default";
289 pinctrl-0 = <&pinctrl_audmux>;
290 status = "okay";
291
292 ssi2 {
293 fsl,audmux-port = <1>;
294 fsl,port-config = <
295 (IMX_AUDMUX_V2_PTCR_SYN |
296 IMX_AUDMUX_V2_PTCR_TFSEL(2) |
297 IMX_AUDMUX_V2_PTCR_TCSEL(2) |
298 IMX_AUDMUX_V2_PTCR_TFSDIR |
299 IMX_AUDMUX_V2_PTCR_TCLKDIR)
300 IMX_AUDMUX_V2_PDCR_RXDSEL(2)
301 >;
302 };
303
304 aud3 {
305 fsl,audmux-port = <2>;
306 fsl,port-config = <
307 IMX_AUDMUX_V2_PTCR_SYN
308 IMX_AUDMUX_V2_PDCR_RXDSEL(1)
309 >;
310 };
311};
312
313&cpu {
314 cpu-supply = <&sw1_reg>;
315};
316
317&ecspi1 {
318 pinctrl-names = "default";
319 pinctrl-0 = <&pinctrl_ecspi1>;
320 cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
321 <&gpio4 25 GPIO_ACTIVE_LOW>;
322 status = "okay";
323
324 pmic@0 {
325 compatible = "fsl,mc13892";
326 pinctrl-names = "default";
327 pinctrl-0 = <&pinctrl_pmic>;
328 spi-max-frequency = <6000000>;
329 spi-cs-high;
330 reg = <0>;
331 interrupt-parent = <&gpio1>;
332 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
333 fsl,mc13xxx-uses-adc;
334
335 regulators {
336 sw1_reg: sw1 {
337 regulator-min-microvolt = <600000>;
338 regulator-max-microvolt = <1375000>;
339 regulator-boot-on;
340 regulator-always-on;
341 };
342
343 sw2_reg: sw2 {
344 regulator-min-microvolt = <900000>;
345 regulator-max-microvolt = <1850000>;
346 regulator-boot-on;
347 regulator-always-on;
348 };
349
350 sw3_reg: sw3 {
351 regulator-min-microvolt = <1100000>;
352 regulator-max-microvolt = <1850000>;
353 regulator-boot-on;
354 regulator-always-on;
355 };
356
357 sw4_reg: sw4 {
358 regulator-min-microvolt = <1100000>;
359 regulator-max-microvolt = <1850000>;
360 regulator-boot-on;
361 regulator-always-on;
362 };
363
364 vpll_reg: vpll {
365 regulator-min-microvolt = <1050000>;
366 regulator-max-microvolt = <1800000>;
367 regulator-boot-on;
368 regulator-always-on;
369 };
370
371 vdig_reg: vdig {
372 regulator-min-microvolt = <1650000>;
373 regulator-max-microvolt = <1650000>;
374 regulator-boot-on;
375 };
376
377 vsd_reg: vsd {
378 regulator-min-microvolt = <1800000>;
379 regulator-max-microvolt = <3150000>;
380 };
381
382 vusb_reg: vusb {
383 regulator-always-on;
384 };
385
386 vusb2_reg: vusb2 {
387 regulator-min-microvolt = <2400000>;
388 regulator-max-microvolt = <2775000>;
389 regulator-boot-on;
390 regulator-always-on;
391 };
392
393 vvideo_reg: vvideo {
394 regulator-min-microvolt = <2775000>;
395 regulator-max-microvolt = <2775000>;
396 };
397
398 vaudio_reg: vaudio {
399 regulator-min-microvolt = <2300000>;
400 regulator-max-microvolt = <3000000>;
401 };
402
403 vcam_reg: vcam {
404 regulator-min-microvolt = <2500000>;
405 regulator-max-microvolt = <3000000>;
406 };
407
408 vgen1_reg: vgen1 {
409 regulator-min-microvolt = <1200000>;
410 regulator-max-microvolt = <1200000>;
411 };
412
413 vgen2_reg: vgen2 {
414 regulator-min-microvolt = <1200000>;
415 regulator-max-microvolt = <3150000>;
416 regulator-always-on;
417 };
418
419 vgen3_reg: vgen3 {
420 regulator-min-microvolt = <1800000>;
421 regulator-max-microvolt = <2900000>;
422 regulator-always-on;
423 };
424 };
425
426 leds {
427 #address-cells = <1>;
428 #size-cells = <0>;
429 led-control = <0x0 0x0 0x3f83f8 0x0>;
430
431 sysled0 {
432 reg = <3>;
433 label = "system:green:status";
434 linux,default-trigger = "default-on";
435 };
436
437 sysled1 {
438 reg = <4>;
439 label = "system:green:act";
440 linux,default-trigger = "heartbeat";
441 };
442 };
443 };
444
445 flash@1 {
446 #address-cells = <1>;
447 #size-cells = <1>;
448 compatible = "atmel,at45db642d", "atmel,at45", "atmel,dataflash";
449 spi-max-frequency = <25000000>;
450 reg = <1>;
451 };
452};
453
454&esdhc1 {
455 pinctrl-names = "default";
456 pinctrl-0 = <&pinctrl_esdhc1>;
457 bus-width = <4>;
458 non-removable;
459 status = "okay";
460};
461
462&fec {
463 pinctrl-names = "default";
464 pinctrl-0 = <&pinctrl_fec>;
465 phy-mode = "mii";
466 phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
467 phy-supply = <&vgen3_reg>;
468 status = "okay";
469};
470
471&i2c2 {
472 pinctrl-names = "default";
473 pinctrl-0 = <&pinctrl_i2c2>;
474 status = "okay";
475
476 eeprom@50 {
477 compatible = "atmel,24c04";
478 pagesize = <16>;
479 reg = <0x50>;
480 };
481
482 tpa6130a2: amp@60 {
483 compatible = "ti,tpa6130a2";
484 reg = <0x60>;
485 pinctrl-names = "default";
486 pinctrl-0 = <&pinctrl_ampgpio>;
487 power-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
488 Vdd-supply = <&reg_3p3v>;
489 };
490
491 ds1341: rtc@68 {
492 compatible = "maxim,ds1341";
493 reg = <0x68>;
494 };
495
496 /* touch nodes default disabled, bootloader will enable the right one */
497
498 touchscreen@4b {
499 compatible = "atmel,maxtouch";
500 reg = <0x4b>;
501 pinctrl-names = "default";
502 pinctrl-0 = <&pinctrl_ts>;
503 interrupt-parent = <&gpio3>;
504 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
505 status = "disabled";
506 };
507
508 touchscreen@4c {
509 compatible = "atmel,maxtouch";
510 reg = <0x4c>;
511 pinctrl-names = "default";
512 pinctrl-0 = <&pinctrl_ts>;
513 interrupt-parent = <&gpio3>;
514 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
515 status = "disabled";
516 };
517
518 touchscreen@20 {
519 compatible = "syna,rmi4_i2c";
520 reg = <0x20>;
521 pinctrl-names = "default";
522 pinctrl-0 = <&pinctrl_ts>;
523 interrupt-parent = <&gpio3>;
524 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
525 status = "disabled";
526
527 #address-cells = <1>;
528 #size-cells = <0>;
529
530 rmi4-f01@1 {
531 reg = <0x1>;
532 syna,nosleep-mode = <2>;
533 };
534
535 rmi4-f11@11 {
536 reg = <0x11>;
537 touch-inverted-y;
538 touch-swapped-x-y;
539 syna,sensor-type = <1>;
540 };
541 };
542
543};
544
545&ipu_di0_disp1 {
546 remote-endpoint = <&display_in>;
547};
548
549&ssi2 {
550 status = "okay";
551};
552
553&uart1 {
554 pinctrl-names = "default";
555 pinctrl-0 = <&pinctrl_uart1>;
556 status = "okay";
557};
558
559&uart2 {
560 pinctrl-names = "default";
561 pinctrl-0 = <&pinctrl_uart2>;
562 status = "okay";
563};
564
565&uart3 {
566 pinctrl-names = "default";
567 pinctrl-0 = <&pinctrl_uart3>;
568 status = "okay";
569};
570
571&usbh1 {
572 pinctrl-names = "default";
573 pinctrl-0 = <&pinctrl_usbh1>;
574 dr_mode = "host";
575 phy_type = "ulpi";
576 fsl,usbphy = <&usbh1phy>;
577 disable-over-current;
578 vbus-supply = <&reg_5p0v_main>;
579 status = "okay";
580};
581
582&usbh2 {
583 pinctrl-names = "default";
584 pinctrl-0 = <&pinctrl_usbh2>;
585 dr_mode = "host";
586 phy_type = "ulpi";
587 fsl,usbphy = <&usbh2phy>;
588 disable-over-current;
589 vbus-supply = <&reg_5p0v_main>;
590 status = "okay";
591};
592
593&usbphy0 {
594 vcc-supply = <&vusb_reg>;
595};
596
597&usbotg {
598 dr_mode = "host";
599 disable-over-current;
600 phy_type = "utmi_wide";
601 vbus-supply = <&reg_5p0v_main>;
602 status = "okay";
603};
604
605&iomuxc {
606 pinctrl_ampgpio: ampgpiogrp {
607 fsl,pins = <
608 MX51_PAD_GPIO1_9__GPIO1_9 0x5e
609 >;
610 };
611
612 pinctrl_audmux: audmuxgrp {
613 fsl,pins = <
614 MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0xa5
615 MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x85
616 MX51_PAD_AUD3_BB_CK__AUD3_TXC 0xa5
617 MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x85
618 >;
619 };
620
621 pinctrl_clk26mhz: clk26mhzgrp {
622 fsl,pins = <
623 MX51_PAD_DI1_PIN12__GPIO3_1 0x85
624 >;
625 };
626
627 pinctrl_ecspi1: ecspi1grp {
628 fsl,pins = <
629 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
630 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
631 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
632 MX51_PAD_CSPI1_SS0__GPIO4_24 0x85
633 MX51_PAD_CSPI1_SS1__GPIO4_25 0x85
634 >;
635 };
636
637 pinctrl_esdhc1: esdhc1grp {
638 fsl,pins = <
639 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
640 MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
641 MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
642 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
643 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
644 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
645 >;
646 };
647
648 pinctrl_fec: fecgrp {
649 fsl,pins = <
650 MX51_PAD_EIM_EB2__FEC_MDIO 0x1f5
651 MX51_PAD_NANDF_D9__FEC_RDATA0 0x2180
652 MX51_PAD_EIM_EB3__FEC_RDATA1 0x180
653 MX51_PAD_EIM_CS2__FEC_RDATA2 0x180
654 MX51_PAD_EIM_CS3__FEC_RDATA3 0x180
655 MX51_PAD_EIM_CS4__FEC_RX_ER 0x180
656 MX51_PAD_NANDF_D11__FEC_RX_DV 0x2084
657 MX51_PAD_EIM_CS5__FEC_CRS 0x180
658 MX51_PAD_NANDF_RB2__FEC_COL 0x2180
659 MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x2180
660 MX51_PAD_NANDF_CS2__FEC_TX_ER 0x2004
661 MX51_PAD_NANDF_CS3__FEC_MDC 0x2004
662 MX51_PAD_NANDF_D8__FEC_TDATA0 0x2180
663 MX51_PAD_NANDF_CS4__FEC_TDATA1 0x2004
664 MX51_PAD_NANDF_CS5__FEC_TDATA2 0x2004
665 MX51_PAD_NANDF_CS6__FEC_TDATA3 0x2004
666 MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x2004
667 MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x2180
668 MX51_PAD_EIM_A20__GPIO2_14 0x85
669 >;
670 };
671
672 pinctrl_gpiospi0: gpiospi0grp {
673 fsl,pins = <
674 MX51_PAD_CSI2_D18__GPIO4_11 0x85
675 MX51_PAD_CSI2_D19__GPIO4_12 0x85
676 MX51_PAD_CSI2_HSYNC__GPIO4_14 0x85
677 MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x85
678 >;
679 };
680
681 pinctrl_i2c2: i2c2grp {
682 fsl,pins = <
683 MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
684 MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
685 >;
686 };
687
688 pinctrl_ipu_disp1: ipudisp1grp {
689 fsl,pins = <
690 MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
691 MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
692 MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
693 MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
694 MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
695 MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
696 MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
697 MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
698 MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
699 MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
700 MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
701 MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
702 MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
703 MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
704 MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
705 MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
706 MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
707 MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
708 MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
709 MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
710 MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
711 MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
712 MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
713 MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
714 MX51_PAD_DI1_PIN2__DI1_PIN2 0x5
715 MX51_PAD_DI1_PIN3__DI1_PIN3 0x5
716 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
717 >;
718 };
719
720 pinctrl_panel: panelgrp {
721 fsl,pins = <
722 MX51_PAD_DI1_D0_CS__GPIO3_3 0x85
723 >;
724 };
725
726 pinctrl_pmic: pmicgrp {
727 fsl,pins = <
728 MX51_PAD_GPIO1_4__GPIO1_4 0x1e0
729 MX51_PAD_GPIO1_8__GPIO1_8 0x21e2
730 >;
731 };
732
733 pinctrl_sndgate26mhz: sndgate26mhzgrp {
734 fsl,pins = <
735 MX51_PAD_CSPI1_RDY__GPIO4_26 0x85
736 >;
737 };
738
739 pinctrl_swi2c: swi2cgrp {
740 fsl,pins = <
741 MX51_PAD_GPIO1_2__GPIO1_2 0xc5
742 MX51_PAD_DI1_D1_CS__GPIO3_4 0x400001f5
743 >;
744 };
745
746 pinctrl_swmdio: swmdiogrp {
747 fsl,pins = <
748 MX51_PAD_NANDF_D14__GPIO3_26 0x21e6
749 MX51_PAD_NANDF_D15__GPIO3_25 0x21e6
750 >;
751 };
752
753 pinctrl_ts: tsgrp {
754 fsl,pins = <
755 MX51_PAD_CSI1_D8__GPIO3_12 0x85
756 MX51_PAD_CSI1_D9__GPIO3_13 0x85
757 >;
758 };
759
760 pinctrl_uart1: uart1grp {
761 fsl,pins = <
762 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
763 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
764 MX51_PAD_UART1_RTS__UART1_RTS 0x1c4
765 MX51_PAD_UART1_CTS__UART1_CTS 0x1c4
766 >;
767 };
768
769 pinctrl_uart2: uart2grp {
770 fsl,pins = <
771 MX51_PAD_UART2_RXD__UART2_RXD 0xc5
772 MX51_PAD_UART2_TXD__UART2_TXD 0xc5
773 >;
774 };
775
776 pinctrl_uart3: uart3grp {
777 fsl,pins = <
778 MX51_PAD_EIM_D25__UART3_RXD 0x1c5
779 MX51_PAD_EIM_D26__UART3_TXD 0x1c5
780 >;
781 };
782
783 pinctrl_usbgate26mhz: usbgate26mhzgrp {
784 fsl,pins = <
785 MX51_PAD_DISP2_DAT6__GPIO1_19 0x85
786 >;
787 };
788
789 pinctrl_usbh1: usbh1grp {
790 fsl,pins = <
791 MX51_PAD_USBH1_STP__USBH1_STP 0x0
792 MX51_PAD_USBH1_CLK__USBH1_CLK 0x0
793 MX51_PAD_USBH1_DIR__USBH1_DIR 0x0
794 MX51_PAD_USBH1_NXT__USBH1_NXT 0x0
795 MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x0
796 MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x0
797 MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x0
798 MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x0
799 MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x0
800 MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x0
801 MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x0
802 MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x0
803 >;
804 };
805
806 pinctrl_usbh1phy: usbh1phygrp {
807 fsl,pins = <
808 MX51_PAD_NANDF_D0__GPIO4_8 0x85
809 >;
810 };
811
812 pinctrl_usbh2: usbh2grp {
813 fsl,pins = <
814 MX51_PAD_EIM_A26__USBH2_STP 0x0
815 MX51_PAD_EIM_A24__USBH2_CLK 0x0
816 MX51_PAD_EIM_A25__USBH2_DIR 0x0
817 MX51_PAD_EIM_A27__USBH2_NXT 0x0
818 MX51_PAD_EIM_D16__USBH2_DATA0 0x0
819 MX51_PAD_EIM_D17__USBH2_DATA1 0x0
820 MX51_PAD_EIM_D18__USBH2_DATA2 0x0
821 MX51_PAD_EIM_D19__USBH2_DATA3 0x0
822 MX51_PAD_EIM_D20__USBH2_DATA4 0x0
823 MX51_PAD_EIM_D21__USBH2_DATA5 0x0
824 MX51_PAD_EIM_D22__USBH2_DATA6 0x0
825 MX51_PAD_EIM_D23__USBH2_DATA7 0x0
826 >;
827 };
828
829 pinctrl_usbh2phy: usbh2phygrp {
830 fsl,pins = <
831 MX51_PAD_NANDF_D1__GPIO4_7 0x85
832 >;
833 };
834};
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 1ee1d542d9ad..378be720b3c7 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -148,14 +148,14 @@
148 ipu_di0: port@2 { 148 ipu_di0: port@2 {
149 reg = <2>; 149 reg = <2>;
150 150
151 ipu_di0_disp0: endpoint { 151 ipu_di0_disp1: endpoint {
152 }; 152 };
153 }; 153 };
154 154
155 ipu_di1: port@3 { 155 ipu_di1: port@3 {
156 reg = <3>; 156 reg = <3>;
157 157
158 ipu_di1_disp1: endpoint { 158 ipu_di1_disp2: endpoint {
159 }; 159 };
160 }; 160 };
161 }; 161 };
diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts
index 2cb5d460f784..e48525763b1b 100644
--- a/arch/arm/boot/dts/imx53-m53evk.dts
+++ b/arch/arm/boot/dts/imx53-m53evk.dts
@@ -16,7 +16,7 @@
16 model = "Aries/DENX M53EVK"; 16 model = "Aries/DENX M53EVK";
17 compatible = "aries,imx53-m53evk", "denx,imx53-m53evk", "fsl,imx53"; 17 compatible = "aries,imx53-m53evk", "denx,imx53-m53evk", "fsl,imx53";
18 18
19 display1: display@di1 { 19 display1: disp1 {
20 compatible = "fsl,imx-parallel-display"; 20 compatible = "fsl,imx-parallel-display";
21 interface-pix-fmt = "bgr666"; 21 interface-pix-fmt = "bgr666";
22 pinctrl-names = "default"; 22 pinctrl-names = "default";
@@ -183,7 +183,7 @@
183 >; 183 >;
184 }; 184 };
185 185
186 led_pin_gpio: led_gpio@0 { 186 led_pin_gpio: led_gpio {
187 fsl,pins = < 187 fsl,pins = <
188 MX53_PAD_PATA_DATA8__GPIO2_8 0x80000000 188 MX53_PAD_PATA_DATA8__GPIO2_8 0x80000000
189 MX53_PAD_PATA_DATA9__GPIO2_9 0x80000000 189 MX53_PAD_PATA_DATA9__GPIO2_9 0x80000000
diff --git a/arch/arm/boot/dts/imx53-mba53.dts b/arch/arm/boot/dts/imx53-mba53.dts
index df705ba48897..296dd74fc246 100644
--- a/arch/arm/boot/dts/imx53-mba53.dts
+++ b/arch/arm/boot/dts/imx53-mba53.dts
@@ -30,7 +30,7 @@
30 power-supply = <&reg_backlight>; 30 power-supply = <&reg_backlight>;
31 }; 31 };
32 32
33 disp1: display@disp1 { 33 disp1: disp1 {
34 compatible = "fsl,imx-parallel-display"; 34 compatible = "fsl,imx-parallel-display";
35 pinctrl-names = "default"; 35 pinctrl-names = "default";
36 pinctrl-0 = <&pinctrl_disp1_1>; 36 pinctrl-0 = <&pinctrl_disp1_1>;
diff --git a/arch/arm/boot/dts/imx53-ppd.dts b/arch/arm/boot/dts/imx53-ppd.dts
new file mode 100644
index 000000000000..cce959438a79
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-ppd.dts
@@ -0,0 +1,1042 @@
1/*
2 * Copyright 2014 General Electric Company
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42/dts-v1/;
43
44#include "imx53.dtsi"
45#include <dt-bindings/input/input.h>
46
47/ {
48 model = "General Electric CS ONE";
49 compatible = "ge,imx53-cpuvo", "fsl,imx53";
50
51 aliases {
52 spi0 = &cspi;
53 spi1 = &ecspi1;
54 spi2 = &ecspi2;
55 };
56
57 chosen {
58 stdout-path = "&uart1:115200n8";
59 };
60
61 memory@70000000 {
62 device_type = "memory";
63 reg = <0x70000000 0x20000000>,
64 <0xb0000000 0x20000000>;
65 };
66
67 cko2_11M: sgtl-clock-cko2 {
68 compatible = "fixed-clock";
69 #clock-cells = <0>;
70 clock-frequency = <11289600>;
71 };
72
73 sgtlsound: sound {
74 compatible = "fsl,imx53-cpuvo-sgtl5000",
75 "fsl,imx-audio-sgtl5000";
76 model = "imx53-cpuvo-sgtl5000";
77 ssi-controller = <&ssi2>;
78 audio-codec = <&sgtl5000>;
79 audio-routing =
80 "MIC_IN", "Mic Jack",
81 "Mic Jack", "Mic Bias",
82 "Headphone Jack", "HP_OUT";
83 mux-int-port = <2>;
84 mux-ext-port = <6>;
85 };
86
87 reg_sgtl5k: regulator-sgtl5k {
88 compatible = "regulator-fixed";
89 regulator-name = "regulator-sgtl5k";
90 regulator-min-microvolt = <3300000>;
91 regulator-max-microvolt = <3300000>;
92 regulator-always-on;
93 };
94
95 reg_usb_otg_vbus: regulator-usb-otg-vbus {
96 compatible = "regulator-fixed";
97 regulator-name = "usbotg_vbus";
98 regulator-min-microvolt = <5000000>;
99 regulator-max-microvolt = <5000000>;
100 pinctrl-0 = <&pinctrl_usb_otg_vbus>;
101 gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
102 enable-active-high;
103 };
104
105 reg_usb_vbus: regulator-usb-vbus {
106 compatible = "regulator-fixed";
107 regulator-name = "usbh1_vbus";
108 regulator-min-microvolt = <5000000>;
109 regulator-max-microvolt = <5000000>;
110 regulator-always-on;
111 };
112
113 reg_usbh2_vbus: regulator-usbh2-vbus {
114 compatible = "regulator-fixed";
115 regulator-name = "usbh2_vbus";
116 regulator-min-microvolt = <5000000>;
117 regulator-max-microvolt = <5000000>;
118 pinctrl-names = "default";
119 pinctrl-0 = <&pinctrl_usbh2_vbus>;
120 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
121 enable-active-high;
122 };
123
124 reg_usbh3_vbus: regulator-usbh3-vbus {
125 compatible = "regulator-fixed";
126 regulator-name = "usbh3_vbus";
127 regulator-min-microvolt = <5000000>;
128 regulator-max-microvolt = <5000000>;
129 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_usbh3_vbus>;
131 gpio = <&gpio5 27 GPIO_ACTIVE_HIGH>;
132 enable-active-high;
133 };
134
135 pwm_bl: backlight {
136 compatible = "pwm-backlight";
137 pwms = <&pwm2 0 50000>;
138 brightness-levels = <0 2 5 7 10 12 15 17 20 22 25 28 30 33 35
139 38 40 43 45 48 51 53 56 58 61 63 66 68 71
140 73 76 79 81 84 86 89 91 94 96 99 102 104
141 107 109 112 114 117 119 122 124 127 130
142 132 135 137 140 142 145 147 150 153 155
143 158 160 163 165 168 170 173 175 178 181
144 183 186 188 191 193 196 198 201 204 206
145 209 211 214 216 219 221 224 226 229 232
146 234 237 239 242 244 247 249 252 255>;
147 default-brightness-level = <0>;
148 enable-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
149 };
150
151 leds {
152 compatible = "pwm-leds";
153
154 alarm-brightness {
155 pwms = <&pwm1 0 100000>;
156 max-brightness = <255>;
157 };
158 };
159
160 gpio-poweroff {
161 compatible = "gpio-poweroff";
162 gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>;
163 };
164
165 gpio-restart {
166 compatible = "gpio-restart";
167 gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;
168 active-delay = <100>;
169 inactive-delay = <10>;
170 wait-delay = <100>;
171 };
172
173 power-gpio-keys {
174 compatible = "gpio-keys";
175 #address-cells = <1>;
176 #size-cells = <0>;
177
178 power-button {
179 label = "Power button";
180 gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
181 linux,code = <KEY_POWER>;
182 };
183 };
184
185 touch-lock-key {
186 compatible = "gpio-keys";
187 #address-cells = <1>;
188 #size-cells = <0>;
189
190 touch-lock-button {
191 label = "Touch lock button";
192 gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
193 linux,code = <KEY_F12>;
194 };
195 };
196
197 usbphy2: usbphy2 {
198 compatible = "usb-nop-xceiv";
199 reset-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>;
200 clock-names = "main_clk";
201 clock-frequency = <24000000>;
202 clocks = <&clks IMX5_CLK_CKO2>;
203 assigned-clocks = <&clks IMX5_CLK_CKO2_SEL>, <&clks IMX5_CLK_OSC>;
204 assigned-clock-parents = <&clks IMX5_CLK_OSC>;
205 };
206
207 usbphy3: usbphy3 {
208 compatible = "usb-nop-xceiv";
209 reset-gpios = <&gpio2 19 GPIO_ACTIVE_LOW>;
210 clock-names = "main_clk";
211
212 clock-frequency = <24000000>;
213 clocks = <&clks IMX5_CLK_CKO2>;
214 assigned-clocks = <&clks IMX5_CLK_CKO2_SEL>, <&clks IMX5_CLK_OSC>;
215 assigned-clock-parents = <&clks IMX5_CLK_OSC>;
216 };
217
218 panel-lvds0 {
219 compatible = "nvd,9128";
220
221 port {
222 panel_in_lvds0: endpoint {
223 remote-endpoint = <&lvds0_out>;
224 };
225 };
226 };
227};
228
229&audmux {
230 pinctrl-names = "default";
231 pinctrl-0 = <&pinctrl_audmux>;
232 status = "okay";
233};
234
235&cpu0 {
236 /* CPU rated to 1GHz, not 1.2GHz as per the default settings */
237 operating-points = <
238 /* kHz uV */
239 166666 850000
240 400000 900000
241 800000 1050000
242 1000000 1200000
243 >;
244};
245
246&ecspi1 {
247 pinctrl-names = "default";
248 pinctrl-0 = <&pinctrl_ecspi1>;
249 cs-gpios = <&gpio5 17 GPIO_ACTIVE_LOW
250 &gpio4 10 GPIO_ACTIVE_LOW
251 &gpio4 11 GPIO_ACTIVE_LOW
252 &gpio4 12 GPIO_ACTIVE_LOW>;
253 status = "okay";
254
255 spidev0: spi@0 {
256 compatible = "ge,achc";
257 reg = <0>;
258 spi-max-frequency = <1000000>;
259 };
260
261 spidev1: spi@1 {
262 compatible = "ge,achc";
263 reg = <1>;
264 spi-max-frequency = <1000000>;
265 };
266
267 gpioxra0: gpio@2 {
268 compatible = "exar,xra1403";
269 reg = <2>;
270 gpio-controller;
271 #gpio-cells = <2>;
272 spi-max-frequency = <1000000>;
273 };
274
275 gpioxra1: gpio@3 {
276 compatible = "exar,xra1403";
277 reg = <3>;
278 gpio-controller;
279 #gpio-cells = <2>;
280 spi-max-frequency = <1000000>;
281 };
282};
283
284&ecspi2 {
285 pinctrl-names = "default";
286 pinctrl-0 = <&pinctrl_ecspi2>;
287 num-chipselects = <1>;
288 cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
289 status = "okay";
290
291 da9053@0 {
292 compatible = "dlg,da9053-aa";
293 reg = <0>;
294 interrupt-parent = <&gpio3>;
295 interrupts = <12 0x8>;
296 spi-max-frequency = <1000000>;
297
298 regulators {
299 buck1_reg: buck1 {
300 regulator-name = "BUCKCORE";
301 regulator-min-microvolt = <500000>;
302 regulator-max-microvolt = <2075000>;
303 regulator-always-on;
304 };
305
306 buck2_reg: buck2 {
307 regulator-name = "BUCKPRO";
308 regulator-min-microvolt = <500000>;
309 regulator-max-microvolt = <2075000>;
310 regulator-always-on;
311 };
312
313 buck3_reg: buck3 {
314 regulator-name = "BUCKMEM";
315 regulator-min-microvolt = <925000>;
316 regulator-max-microvolt = <2500000>;
317 regulator-always-on;
318 };
319
320 buck4_reg: buck4 {
321 regulator-name = "BUCKPERI";
322 regulator-min-microvolt = <1800000>;
323 regulator-max-microvolt = <3600000>;
324 regulator-always-on;
325 };
326
327 ldo1_reg: ldo1 {
328 regulator-name = "ldo1_1v3";
329 regulator-min-microvolt = <600000>;
330 regulator-max-microvolt = <1800000>;
331 regulator-always-on;
332 };
333
334 ldo2_reg: ldo2 {
335 regulator-name = "ldo2_1v3";
336 regulator-min-microvolt = <600000>;
337 regulator-max-microvolt = <1800000>;
338 regulator-always-on;
339 };
340
341 ldo3_reg: ldo3 {
342 regulator-name = "ldo3_3v3";
343 regulator-min-microvolt = <1725000>;
344 regulator-max-microvolt = <3300000>;
345 regulator-always-on;
346 };
347
348 ldo4_reg: ldo4 {
349 regulator-name = "ldo4_2v775";
350 regulator-min-microvolt = <1725000>;
351 regulator-max-microvolt = <3300000>;
352 regulator-always-on;
353 };
354
355 ldo5_reg: ldo5 {
356 regulator-name = "ldo5_3v3";
357 regulator-min-microvolt = <1200000>;
358 regulator-max-microvolt = <3600000>;
359 regulator-always-on;
360 };
361
362 ldo6_reg: ldo6 {
363 regulator-name = "ldo6_1v3";
364 regulator-min-microvolt = <1200000>;
365 regulator-max-microvolt = <3600000>;
366 regulator-always-on;
367 };
368
369 ldo7_reg: ldo7 {
370 regulator-name = "ldo7_2v75";
371 regulator-min-microvolt = <1200000>;
372 regulator-max-microvolt = <3600000>;
373 regulator-always-on;
374 };
375
376 ldo8_reg: ldo8 {
377 regulator-name = "ldo8_1v8";
378 regulator-min-microvolt = <1200000>;
379 regulator-max-microvolt = <3600000>;
380 regulator-always-on;
381 };
382
383 ldo9_reg: ldo9 {
384 regulator-name = "ldo9_1v5";
385 regulator-min-microvolt = <1250000>;
386 regulator-max-microvolt = <3650000>;
387 regulator-always-on;
388 };
389
390 ldo10_reg: ldo10 {
391 regulator-name = "ldo10_1v3";
392 regulator-min-microvolt = <1200000>;
393 regulator-max-microvolt = <3600000>;
394 regulator-always-on;
395 };
396 };
397 };
398
399};
400
401&esdhc3 {
402 pinctrl-names = "default";
403 pinctrl-0 = <&pinctrl_esdhc3>;
404 bus-width = <8>;
405 status = "okay";
406};
407
408&fec {
409 pinctrl-names = "default";
410 pinctrl-0 = <&pinctrl_fec>;
411 phy-mode = "rmii";
412 phy-reset-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>;
413 status = "okay";
414};
415
416&i2c1 {
417 pinctrl-names = "default", "gpio";
418 pinctrl-0 = <&pinctrl_i2c1>;
419 pinctrl-1 = <&pinctrl_i2c1_gpio>;
420 sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
421 scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
422 status = "okay";
423
424 i2c-switch@70 {
425 compatible = "nxp,pca9547";
426 #address-cells = <1>;
427 #size-cells = <0>;
428 reg = <0x70>;
429 reset-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>;
430
431 i2c4: i2c@0 {
432 #address-cells = <1>;
433 #size-cells = <0>;
434 reg = <0>;
435
436 sgtl5000: codec@a {
437 compatible = "fsl,sgtl5000";
438 reg = <0xa>;
439 VDDA-supply = <&reg_sgtl5k>;
440 VDDIO-supply = <&reg_sgtl5k>;
441 clocks = <&cko2_11M>;
442 status = "okay";
443 };
444 };
445
446 i2c5: i2c@1 {
447 #address-cells = <1>;
448 #size-cells = <0>;
449 reg = <1>;
450
451 rtc@30 {
452 compatible = "sii,s35390a";
453 reg = <0x30>;
454 };
455
456 temp@48 {
457 compatible = "ti,tmp112";
458 reg = <0x48>;
459 };
460
461 mma8453q: accelerometer@1c {
462 compatible = "fsl,mma8453";
463 reg = <0x1c>;
464 interrupt-parent = <&gpio1>;
465 interrupts = <6 0>;
466 interrupt-names = "INT1";
467 };
468
469 mpl3115: pressure-sensor@60 {
470 compatible = "fsl,mpl3115";
471 reg = <0x60>;
472 };
473
474 eeprom: eeprom@50 {
475 compatible = "atmel,24c08";
476 reg = <0x50>;
477 };
478 };
479
480 i2c6: i2c@2 {
481 #address-cells = <1>;
482 #size-cells = <0>;
483 reg = <2>;
484 };
485
486 i2c7: i2c@3 {
487 #address-cells = <1>;
488 #size-cells = <0>;
489 reg = <3>;
490 };
491
492 i2c8: i2c@4 {
493 #address-cells = <1>;
494 #size-cells = <0>;
495 reg = <4>;
496 };
497
498 i2c9: i2c@5 {
499 #address-cells = <1>;
500 #size-cells = <0>;
501 reg = <5>;
502 };
503
504 i2c10: i2c@6 {
505 #address-cells = <1>;
506 #size-cells = <0>;
507 reg = <6>;
508 };
509
510 i2c11: i2c@7 {
511 #address-cells = <1>;
512 #size-cells = <0>;
513 reg = <7>;
514 };
515 };
516};
517
518&i2c2 {
519 pinctrl-names = "default", "gpio";
520 pinctrl-0 = <&pinctrl_i2c2>;
521 pinctrl-1 = <&pinctrl_i2c2_gpio>;
522 sda-gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
523 scl-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
524 status = "okay";
525
526 touchscreen@4b {
527 compatible = "atmel,maxtouch";
528 reg = <0x4b>;
529 interrupt-parent = <&gpio5>;
530 interrupts = <4 0x8>;
531 };
532};
533
534&i2c3 {
535 pinctrl-names = "default", "gpio";
536 pinctrl-0 = <&pinctrl_i2c3>;
537 pinctrl-1 = <&pinctrl_i2c3_gpio>;
538 sda-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
539 scl-gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
540 status = "okay";
541};
542
543&ldb {
544 status = "okay";
545
546 lvds0: lvds-channel@0 {
547 status = "okay";
548
549 port@2 {
550 reg = <2>;
551
552 lvds0_out: endpoint {
553 remote-endpoint = <&panel_in_lvds0>;
554 };
555 };
556 };
557};
558
559&pwm1 {
560 pinctrl-names = "default";
561 pinctrl-0 = <&pinctrl_pwm1>;
562 status = "okay";
563};
564
565&pwm2 {
566 pinctrl-names = "default";
567 pinctrl-0 = <&pinctrl_pwm2>;
568 status = "okay";
569};
570
571&ssi2 {
572 status = "okay";
573};
574
575&uart1 {
576 pinctrl-names = "default";
577 pinctrl-0 = <&pinctrl_uart1>;
578 status = "okay";
579};
580
581&uart2 {
582 pinctrl-names = "default";
583 pinctrl-0 = <&pinctrl_uart2>;
584 status = "okay";
585};
586
587&uart3 {
588 pinctrl-names = "default";
589 pinctrl-0 = <&pinctrl_uart3>;
590 uart-has-rtscts;
591 status = "okay";
592};
593
594&uart4 {
595 pinctrl-names = "default";
596 pinctrl-0 = <&pinctrl_uart4>;
597 status = "okay";
598};
599
600&uart5 {
601 pinctrl-names = "default";
602 pinctrl-0 = <&pinctrl_uart5>;
603 status = "okay";
604};
605
606&usbotg {
607 dr_mode = "otg";
608 phy_type = "utmi";
609 vbus-supply = <&reg_usb_otg_vbus>;
610 pinctrl-0 = <&pinctrl_usb_otg>;
611 status = "okay";
612};
613
614&usbh1 {
615 vbus-supply = <&reg_usb_vbus>;
616 phy_type = "utmi";
617 dr_mode = "host";
618 status = "okay";
619};
620
621&usbh2 {
622 pinctrl-names = "default";
623 pinctrl-0 = <&pinctrl_usbh2>;
624 phy_type = "ulpi";
625 dr_mode = "host";
626 fsl,usbphy = <&usbphy2>;
627 vbus-supply = <&reg_usbh2_vbus>;
628 status = "okay";
629};
630
631&usbh3 {
632 pinctrl-names = "default";
633 pinctrl-0 = <&pinctrl_usbh3>;
634 phy_type = "ulpi";
635 dr_mode = "host";
636 vbus-supply = <&reg_usbh3_vbus>;
637 fsl,usbphy = <&usbphy3>;
638 status = "okay";
639};
640
641&iomuxc {
642 pinctrl-names = "default";
643 pinctrl-0 = <&pinctrl_hog_rev6>;
644
645 pinctrl_audmux: audmuxgrp {
646 fsl,pins = <
647 MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD 0x400
648 MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD 0x400
649 MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC 0x400
650 MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS 0x400
651 MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC 0x400
652 MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS 0x400
653 MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD 0x400
654 MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD 0x400
655 >;
656 };
657
658 pinctrl_ecspi1: ecspi1grp {
659 fsl,pins = <
660 MX53_PAD_DISP0_DAT21__ECSPI1_MOSI 0x400
661 MX53_PAD_DISP0_DAT22__ECSPI1_MISO 0x400
662 MX53_PAD_DISP0_DAT20__ECSPI1_SCLK 0x400
663 /* ECSPI1_SS0, must treat as GPIO for EzPort */
664 MX53_PAD_DISP0_DAT23__GPIO5_17 0x400
665 MX53_PAD_KEY_COL2__GPIO4_10 0x0
666 MX53_PAD_KEY_ROW2__GPIO4_11 0x0
667 MX53_PAD_KEY_COL3__GPIO4_12 0x0
668 >;
669 };
670
671 pinctrl_ecspi2: ecspi2grp {
672 fsl,pins = <
673 MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x0
674 MX53_PAD_EIM_OE__ECSPI2_MISO 0x0
675 MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x0
676 MX53_PAD_EIM_RW__GPIO2_26 0x0
677 >;
678 };
679
680 pinctrl_esdhc1: esdhc1grp {
681 fsl,pins = <
682 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
683 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
684 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
685 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
686 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
687 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
688 >;
689 };
690
691 pinctrl_esdhc3: esdhc3grp {
692 fsl,pins = <
693 MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
694 MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
695 MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
696 MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
697 MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
698 MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
699 MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
700 MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
701 MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
702 MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
703 >;
704 };
705
706 pinctrl_fec: fecgrp {
707 fsl,pins = <
708 MX53_PAD_FEC_MDC__FEC_MDC 0x0
709 MX53_PAD_FEC_MDIO__FEC_MDIO 0x0
710 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x0
711 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x0
712 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x0
713 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x0
714 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x0
715 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x0
716 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x0
717 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x0
718 >;
719 };
720
721 pinctrl_hog_rev6: hoggrp {
722 fsl,pins = <
723 /* CKO2 */
724 MX53_PAD_GPIO_3__CCM_CLKO2 0x4
725 /* DEFIB_SYNC_MARKER_IN_IRQ */
726 MX53_PAD_GPIO_5__GPIO1_5 0x0
727 /* ACCELEROMETER_DATA_RDY_N */
728 MX53_PAD_GPIO_6__GPIO1_6 0x0
729 /* TEMPERATURE_ALERT_N */
730 MX53_PAD_GPIO_7__GPIO1_7 0x0
731 /* BAROMETRIC_PRESSURE_DATA_RDY_N */
732 MX53_PAD_GPIO_8__GPIO1_8 0x0
733 /* DOCKING_I2C_INTERFACE_IRQ_N */
734 MX53_PAD_PATA_DATA4__GPIO2_4 0x0
735 /* PWR_OUT_TO_DOCK_FAULT_N */
736 MX53_PAD_PATA_DATA5__GPIO2_5 0x0
737 /* ENABLE_PWR_TO_DOCK_N */
738 MX53_PAD_PATA_DATA6__GPIO2_6 0x0
739 /* HOST_CONTROLLED_RESET_TO_DOCKING_CONNECTOR_N */
740 MX53_PAD_PATA_DATA7__GPIO2_7 0x0
741 /* REMOTE_ON_REQUEST_FROM_DOCKING_CONNECTOR_IS_ACTIVE_N */
742 MX53_PAD_PATA_DATA12__GPIO2_12 0x0
743 /* DOCK_PRESENT_N */
744 MX53_PAD_PATA_DATA13__GPIO2_13 0x0
745 /* ECG_MARKER_IN_FROM_DOCKING_CONNECTOR_IRQ */
746 MX53_PAD_PATA_DATA14__GPIO2_14 0x0
747 /* ENABLE_ECG_MARKER_INTERFACE_TO_DOCKING_CONNECTOR */
748 MX53_PAD_PATA_DATA15__GPIO2_15 0x0
749 /* RESET_IMX535_ETHERNET_PHY_N */
750 MX53_PAD_EIM_A22__GPIO2_16 0x0
751 /* ENABLE_PWR_TO_LCD_AND_UI_INTERFACE */
752 MX53_PAD_EIM_A21__GPIO2_17 0x0
753 /* RESET_I2C1_BUS_SEGMENT_MUX_N */
754 MX53_PAD_EIM_A20__GPIO2_18 0x0
755 /* RESET_IMX535_USB_HOST3_PHY_N */
756 MX53_PAD_EIM_A19__GPIO2_19 0x0
757 /* ESDHC3_EMMC_NAND_RST_N */
758 MX53_PAD_EIM_A18__GPIO2_20 0x0
759 /* LCD_AND_UI_INTERFACE_PWR_FAULT_N */
760 MX53_PAD_EIM_A17__GPIO2_21 0x0
761 /* POWER_DOWN_LVDS0_DESERIALIZER_N */
762 MX53_PAD_EIM_A16__GPIO2_22 0x0
763 /* POWER_DOWN_LVDS1_DESERIALIZER_N */
764 MX53_PAD_EIM_LBA__GPIO2_27 0x0
765 /* RESET_DP0_TRANSMITTER_N */
766 MX53_PAD_EIM_EB0__GPIO2_28 0x0
767 /* RESET_DP1_TRANSMITTER_N */
768 MX53_PAD_EIM_EB1__GPIO2_29 0x0
769 /* ENABLE_SPDIF_AUDIO_TO_DP0 */
770 MX53_PAD_EIM_DA0__GPIO3_0 0x0
771 /* ENABLE_SPDIF_AUDIO_TO_DP1 */
772 MX53_PAD_EIM_DA1__GPIO3_1 0x0
773 /* LVDS1_MUX_CTRL */
774 MX53_PAD_EIM_DA2__GPIO3_2 0x0
775 /* LVDS0_MUX_CTRL */
776 MX53_PAD_EIM_DA3__GPIO3_3 0x0
777 /* DP1_TRANSMITTER_IRQ */
778 MX53_PAD_EIM_DA4__GPIO3_4 0x0
779 /* DP0_TRANSMITTER_IRQ */
780 MX53_PAD_EIM_DA5__GPIO3_5 0x0
781 /* USB_RESET_N */
782 MX53_PAD_EIM_DA6__GPIO3_6 0x0
783 /* ENABLE_BATTERY_CHARGER */
784 MX53_PAD_EIM_DA7__GPIO3_7 0x0
785 /* SOFTWARE_CONTROLLED_PWR_CYCLE */
786 MX53_PAD_EIM_DA8__GPIO3_8 0x0
787 /* SOFTWARE_CONTROLLED_POWERDOWN */
788 MX53_PAD_EIM_DA9__GPIO3_9 0x0
789 /* DC_PWR_IN_OK */
790 MX53_PAD_EIM_DA10__GPIO3_10 0x0
791 /* BATT_PRESENT_N */
792 MX53_PAD_EIM_DA11__GPIO3_11 0xe4
793 /* PMIC_IRQ_N */
794 MX53_PAD_EIM_DA12__GPIO3_12 0x0
795 /* PMIC_VDD_FAULT_STATUS_N */
796 MX53_PAD_EIM_DA13__GPIO3_13 0x0
797 /* IMX535_ETHERNET_PHY_STATUS_IRQ_N */
798 MX53_PAD_EIM_DA14__GPIO3_14 0x0
799 /* NOT USED - AVAILABLE 3.3V GPIO */
800 MX53_PAD_EIM_DA15__GPIO3_15 0x0
801 /* NOT USED - AVAILABLE 3.3V GPIO */
802 MX53_PAD_EIM_D22__GPIO3_22 0x0
803 /* NOT USED - AVAILABLE 3.3V GPIO */
804 MX53_PAD_EIM_D24__GPIO3_24 0x0
805 /* NBP_PUMP_VALVE_PWR_ENABLE */
806 MX53_PAD_EIM_D25__GPIO3_25 0x0
807 /* NIBP_RESET_N */
808 MX53_PAD_EIM_D26__GPIO3_26 0x0
809 /* LATCHED_OVERPRESSURE_N */
810 MX53_PAD_EIM_D27__GPIO3_27 0x0
811 /* NBP_SBWTCLK */
812 MX53_PAD_EIM_D29__GPIO3_29 0x0
813 /* ENABLE_WIFI_MODULE */
814 MX53_PAD_GPIO_11__GPIO4_1 0x400
815 /* WIFI_MODULE_IRQ_N */
816 MX53_PAD_GPIO_12__GPIO4_2 0x400
817 /* ENABLE_BLUETOOTH_MODULE */
818 MX53_PAD_GPIO_13__GPIO4_3 0x400
819 /* RESET_IMX535_USB_HOST2_PHY_N */
820 MX53_PAD_GPIO_14__GPIO4_4 0x400
821 /* ONKEY_IS_DEPRESSED */
822 MX53_PAD_KEY_ROW3__GPIO4_13 0x0
823 /* UNUSED_GPIO_TO_ALARM_LIGHT_BOARD */
824 MX53_PAD_EIM_WAIT__GPIO5_0 0x0
825 /* DISPLAY_LOCK_BUTTON_IS_DEPRESSED_N */
826 MX53_PAD_EIM_A25__GPIO5_2 0x0
827 /* I2C_PCAP_TOUCHSCREEN_IRQ_N */
828 MX53_PAD_EIM_A24__GPIO5_4 0x0
829 /* NOT USED - AVAILABLE 1.8V GPIO */
830 MX53_PAD_DISP0_DAT13__GPIO5_7 0x400
831 /* NOT USED - AVAILABLE 1.8V GPIO */
832 MX53_PAD_DISP0_DAT14__GPIO5_8 0x400
833 /* NOT USED - AVAILABLE 1.8V GPIO */
834 MX53_PAD_DISP0_DAT15__GPIO5_9 0x400
835 /* HOST_CONTROLLED_RESET_TO_LCD_N */
836 MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x0
837 /* HOST_CONTROLLED_RESET_TO_PCAP_N */
838 MX53_PAD_CSI0_MCLK__GPIO5_19 0x0
839 /* LR_SCAN_CTRL */
840 MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x0
841 /* UD_SCAN_CTRL */
842 MX53_PAD_CSI0_VSYNC__GPIO5_21 0x0
843 /* DATA_WIDTH_CTRL */
844 MX53_PAD_CSI0_DAT10__GPIO5_28 0x0
845 /* BACKLIGHT_ENABLE */
846 MX53_PAD_CSI0_DAT11__GPIO5_29 0x0
847 /* MED_USB_PORT_1_HOST_SELECT */
848 MX53_PAD_EIM_A23__GPIO6_6 0x0
849 /* MED_USB_PORT_2_HOST_SELECT */
850 MX53_PAD_NANDF_CLE__GPIO6_7 0x0
851 /* MED_USB_PORT_3_HOST_SELECT */
852 MX53_PAD_NANDF_ALE__GPIO6_8 0x0
853 /* MED_USB_PORT_4_HOST_SELECT */
854 MX53_PAD_NANDF_WP_B__GPIO6_9 0x0
855 /* MED_USB_PORT_5_HOST_SELECT */
856 MX53_PAD_NANDF_RB0__GPIO6_10 0x0
857 /* MED_USB_PORT_6_HOST_SELECT */
858 MX53_PAD_NANDF_CS0__GPIO6_11 0x0
859 /* MED_USB_PORT_7_HOST_SELECT */
860 MX53_PAD_NANDF_WE_B__GPIO6_12 0x0
861 /* MED_USB_PORT_8_HOST_SELECT */
862 MX53_PAD_NANDF_RE_B__GPIO6_13 0x0
863 /* MED_USB_PORT_TO_IMX_SELECT_0 */
864 MX53_PAD_NANDF_CS1__GPIO6_14 0x0
865 /* MED_USB_PORT_TO_IMX_SELECT_1 */
866 MX53_PAD_NANDF_CS2__GPIO6_15 0x0
867 /* MED_USB_PORT_TO_IMX_SELECT_2 */
868 MX53_PAD_NANDF_CS3__GPIO6_16 0x0
869 /* POWER_AND_BOOT_STATUS_INDICATOR */
870 MX53_PAD_PATA_INTRQ__GPIO7_2 0x1e4
871 /* ACTIVATE_ALARM_LIGHT_RED */
872 MX53_PAD_PATA_DIOR__GPIO7_3 0x0
873 /* ACTIVATE_ALARM_LIGHT_YELLOW */
874 MX53_PAD_PATA_DA_1__GPIO7_7 0x0
875 /* ACTIVATE_ALARM_LIGHT_CYAN */
876 MX53_PAD_PATA_DA_2__GPIO7_8 0x0
877 /* RUNNING_ON_BATTERY_INDICATOR_GREEN */
878 MX53_PAD_GPIO_16__GPIO7_11 0x0
879 /* BATTERY_STATUS_INDICATOR_AMBER */
880 MX53_PAD_GPIO_17__GPIO7_12 0x0
881 /* AUDIO_ALARMS_SILENCED_INDICATOR */
882 MX53_PAD_GPIO_18__GPIO7_13 0x0
883 >;
884 };
885
886 pinctrl_i2c1: i2c1grp {
887 fsl,pins = <
888 MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4
889 MX53_PAD_EIM_D28__I2C1_SDA 0x400001e4
890 >;
891 };
892
893 pinctrl_i2c1_gpio: i2c1gpiogrp {
894 fsl,pins = <
895 MX53_PAD_EIM_D28__GPIO3_28 0x1e4
896 MX53_PAD_EIM_D21__GPIO3_21 0x1e4
897 >;
898 };
899
900 pinctrl_i2c2: i2c2grp {
901 fsl,pins = <
902 MX53_PAD_EIM_EB2__I2C2_SCL 0x400001e4
903 MX53_PAD_EIM_D16__I2C2_SDA 0x400001e4
904 >;
905 };
906
907 pinctrl_i2c2_gpio: i2c2gpiogrp {
908 fsl,pins = <
909 MX53_PAD_EIM_D16__GPIO3_16 0x1e4
910 MX53_PAD_EIM_EB2__GPIO2_30 0x1e4
911 >;
912 };
913
914 pinctrl_i2c3: i2c3grp {
915 fsl,pins = <
916 MX53_PAD_EIM_D17__I2C3_SCL 0x400001e4
917 MX53_PAD_EIM_D18__I2C3_SDA 0x400001e4
918 >;
919 };
920
921 pinctrl_i2c3_gpio: i2c3gpiogrp {
922 fsl,pins = <
923 MX53_PAD_EIM_D18__GPIO3_18 0x1e4
924 MX53_PAD_EIM_D17__GPIO3_17 0x1e4
925 >;
926 };
927
928 pinctrl_pwm1: pwm1grp {
929 fsl,pins = <
930 MX53_PAD_GPIO_9__PWM1_PWMO 0x5
931 >;
932 };
933
934 pinctrl_pwm2: pwm2grp {
935 fsl,pins = <
936 MX53_PAD_DISP0_DAT9__PWM2_PWMO 0x5
937 >;
938 };
939
940 pinctrl_uart1: uart1grp {
941 fsl,pins = <
942 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
943 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
944 >;
945 };
946
947 pinctrl_uart2: uart2grp {
948 fsl,pins = <
949 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
950 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
951 >;
952 };
953
954 pinctrl_uart3: uart3grp {
955 fsl,pins = <
956 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
957 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
958 MX53_PAD_EIM_D23__UART3_CTS 0x1e4
959 MX53_PAD_EIM_EB3__UART3_RTS 0x1e4
960 >;
961 };
962
963 pinctrl_uart4: uart4grp {
964 fsl,pins = <
965 MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1e4
966 MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1e4
967 >;
968 };
969
970 pinctrl_uart5: uart5grp {
971 fsl,pins = <
972 MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1e4
973 MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1e4
974 >;
975 };
976
977 pinctrl_usb_otg_vbus: usb-otg-vbusgrp {
978 fsl,pins = <
979 /* USB_HS_OTG_VBUS_ENABLE */
980 MX53_PAD_KEY_ROW4__GPIO4_15 0x1c4
981 >;
982 };
983
984 pinctrl_usbh2: usbh2grp {
985 fsl,pins = <
986 /* USB H2 */
987 MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 0x180
988 MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 0x180
989 MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 0x180
990 MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 0x180
991 MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 0x180
992 MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 0x180
993 MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 0x180
994 MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 0x180
995 MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP 0x180
996 MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT 0x180
997 MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK 0x180
998 MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR 0x5
999 MX53_PAD_EIM_D30__USBOH3_USBH2_OC 0x180
1000 >;
1001 };
1002
1003 pinctrl_usbh2_vbus: usbh2-vbusgrp {
1004 fsl,pins = <
1005 /* USB_HS_HOST2_VBUS_ENABLE */
1006 MX53_PAD_EIM_D31__GPIO3_31 0x0
1007 >;
1008 };
1009
1010 pinctrl_usbh3_vbus: usbh3-vbusgrp {
1011 fsl,pins = <
1012 /* USB_HS_HOST3_VBUS_ENABLE */
1013 MX53_PAD_CSI0_DAT9__GPIO5_27 0x0
1014 >;
1015 };
1016
1017 pinctrl_usbh3: usbh3grp {
1018 fsl,pins = <
1019 /* USB H3 */
1020 MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 0x180
1021 MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 0x180
1022 MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 0x180
1023 MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 0x180
1024 MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 0x180
1025 MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 0x180
1026 MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 0x180
1027 MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 0x180
1028 MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR 0x5
1029 MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK 0x180
1030 MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT 0x180
1031 MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP 0x180
1032 MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC 0x180
1033 >;
1034 };
1035
1036 pinctrl_usb_otg: usbotggrp {
1037 fsl,pins = <
1038 /* USB_OTG_FAULT_N */
1039 MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC 0x180
1040 >;
1041 };
1042};
diff --git a/arch/arm/boot/dts/imx53-qsb-common.dtsi b/arch/arm/boot/dts/imx53-qsb-common.dtsi
index 5e364a6672c0..41a2e2a2b079 100644
--- a/arch/arm/boot/dts/imx53-qsb-common.dtsi
+++ b/arch/arm/boot/dts/imx53-qsb-common.dtsi
@@ -22,7 +22,7 @@
22 <0xb0000000 0x20000000>; 22 <0xb0000000 0x20000000>;
23 }; 23 };
24 24
25 display0: display@di0 { 25 display0: disp0 {
26 compatible = "fsl,imx-parallel-display"; 26 compatible = "fsl,imx-parallel-display";
27 interface-pix-fmt = "rgb565"; 27 interface-pix-fmt = "rgb565";
28 pinctrl-names = "default"; 28 pinctrl-names = "default";
@@ -172,7 +172,7 @@
172 >; 172 >;
173 }; 173 };
174 174
175 led_pin_gpio7_7: led_gpio7_7@0 { 175 led_pin_gpio7_7: led_gpio7_7 {
176 fsl,pins = < 176 fsl,pins = <
177 MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 177 MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000
178 >; 178 >;
diff --git a/arch/arm/boot/dts/imx53-tx53-x03x.dts b/arch/arm/boot/dts/imx53-tx53-x03x.dts
index 96eb33c65c92..7eb53e48c2f4 100644
--- a/arch/arm/boot/dts/imx53-tx53-x03x.dts
+++ b/arch/arm/boot/dts/imx53-tx53-x03x.dts
@@ -1,12 +1,42 @@
1/* 1/*
2 * Copyright 2013 Lothar Waßmann <LW@KARO-electronics.de> 2 * Copyright 2013-2017 Lothar Waßmann <LW@KARO-electronics.de>
3 * 3 *
4 * The code contained herein is licensed under the GNU General Public 4 * This file is dual-licensed: you can use it either under the terms
5 * License. You may obtain a copy of the GNU General Public License 5 * of the GPL or the X11 license, at your option. Note that this dual
6 * Version 2 at the following locations: 6 * licensing only applies to this file, and not this project as a
7 * whole.
7 * 8 *
8 * http://www.opensource.org/licenses/gpl-license.html 9 * a) This file is free software; you can redistribute it and/or
9 * http://www.gnu.org/copyleft/gpl.html 10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
10 */ 40 */
11 41
12/dts-v1/; 42/dts-v1/;
@@ -24,7 +54,7 @@
24 }; 54 };
25 55
26 soc { 56 soc {
27 display: display@di0 { 57 display: disp0 {
28 compatible = "fsl,imx-parallel-display"; 58 compatible = "fsl,imx-parallel-display";
29 interface-pix-fmt = "rgb24"; 59 interface-pix-fmt = "rgb24";
30 pinctrl-names = "default"; 60 pinctrl-names = "default";
@@ -173,28 +203,24 @@
173 default-brightness-level = <50>; 203 default-brightness-level = <50>;
174 }; 204 };
175 205
176 regulators { 206 reg_lcd_pwr: regulator-lcd-pwr {
177 reg_lcd_pwr: regulator@5 { 207 compatible = "regulator-fixed";
178 compatible = "regulator-fixed"; 208 regulator-name = "LCD POWER";
179 reg = <5>; 209 regulator-min-microvolt = <3300000>;
180 regulator-name = "LCD POWER"; 210 regulator-max-microvolt = <3300000>;
181 regulator-min-microvolt = <3300000>; 211 gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
182 regulator-max-microvolt = <3300000>; 212 enable-active-high;
183 gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; 213 regulator-boot-on;
184 enable-active-high; 214 };
185 regulator-boot-on;
186 };
187 215
188 reg_lcd_reset: regulator@6 { 216 reg_lcd_reset: regulator-lcd-reset {
189 compatible = "regulator-fixed"; 217 compatible = "regulator-fixed";
190 reg = <6>; 218 regulator-name = "LCD RESET";
191 regulator-name = "LCD RESET"; 219 regulator-min-microvolt = <3300000>;
192 regulator-min-microvolt = <3300000>; 220 regulator-max-microvolt = <3300000>;
193 regulator-max-microvolt = <3300000>; 221 gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
194 gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; 222 enable-active-high;
195 enable-active-high; 223 regulator-boot-on;
196 regulator-boot-on;
197 };
198 }; 224 };
199}; 225};
200 226
@@ -228,7 +254,7 @@
228 pinctrl-names = "default"; 254 pinctrl-names = "default";
229 pinctrl-0 = <&pinctrl_tsc2007>; 255 pinctrl-0 = <&pinctrl_tsc2007>;
230 interrupt-parent = <&gpio3>; 256 interrupt-parent = <&gpio3>;
231 interrupts = <26 0>; 257 interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
232 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; 258 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
233 ti,x-plate-ohms = <660>; 259 ti,x-plate-ohms = <660>;
234 wakeup-source; 260 wakeup-source;
diff --git a/arch/arm/boot/dts/imx53-tx53-x13x.dts b/arch/arm/boot/dts/imx53-tx53-x13x.dts
index be31c5d1db05..f2b2ad3ce9e5 100644
--- a/arch/arm/boot/dts/imx53-tx53-x13x.dts
+++ b/arch/arm/boot/dts/imx53-tx53-x13x.dts
@@ -1,6 +1,42 @@
1/* 1/*
2 * Copyright 2013 Lothar Waßmann <LW@KARO-electronics.de> 2 * Copyright 2013-2017 Lothar Waßmann <LW@KARO-electronics.de>
3 * 3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
4 * The code contained herein is licensed under the GNU General Public 40 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License 41 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 at the following locations: 42 * Version 2 at the following locations:
@@ -63,51 +99,33 @@
63 default-brightness-level = <50>; 99 default-brightness-level = <50>;
64 }; 100 };
65 101
66 regulators { 102 reg_lcd_pwr0: regulator-lvds0-pwr {
67 reg_lcd_pwr0: regulator@5 { 103 compatible = "regulator-fixed";
68 compatible = "regulator-fixed"; 104 regulator-name = "LVDS0 POWER";
69 reg = <5>; 105 regulator-min-microvolt = <3300000>;
70 regulator-name = "LVDS0 POWER"; 106 regulator-max-microvolt = <3300000>;
71 regulator-min-microvolt = <3300000>; 107 gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
72 regulator-max-microvolt = <3300000>; 108 enable-active-high;
73 gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; 109 regulator-boot-on;
74 enable-active-high;
75 regulator-boot-on;
76 };
77
78 reg_lcd_pwr1: regulator@6 {
79 compatible = "regulator-fixed";
80 reg = <6>;
81 regulator-name = "LVDS1 POWER";
82 regulator-min-microvolt = <3300000>;
83 regulator-max-microvolt = <3300000>;
84 gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
85 enable-active-high;
86 regulator-boot-on;
87 };
88 }; 110 };
89};
90 111
91&i2c2 { 112 reg_lcd_pwr1: regulator-lvds1-pwr {
92 pinctrl-names = "default"; 113 compatible = "regulator-fixed";
93 pinctrl-0 = <&pinctrl_i2c2>; 114 regulator-name = "LVDS1 POWER";
94 status = "okay"; 115 regulator-min-microvolt = <3300000>;
95 116 regulator-max-microvolt = <3300000>;
96 touchscreen2: eeti@4 { 117 gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
97 compatible = "eeti,egalax_ts"; 118 enable-active-high;
98 reg = <0x04>; 119 regulator-boot-on;
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_eeti2>;
101 interrupt-parent = <&gpio3>;
102 interrupts = <23 0>;
103 wakeup-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
104 wakeup-source;
105 }; 120 };
106}; 121};
107 122
108&i2c3 { 123&i2c3 {
109 pinctrl-names = "default"; 124 pinctrl-names = "default", "gpio";
110 pinctrl-0 = <&pinctrl_i2c3>; 125 pinctrl-0 = <&pinctrl_i2c3>;
126 pinctrl-1 = <&pinctrl_i2c3_gpio>;
127 scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
128 sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
111 status = "okay"; 129 status = "okay";
112 130
113 sgtl5000: codec@a { 131 sgtl5000: codec@a {
@@ -117,28 +135,10 @@
117 VDDIO-supply = <&reg_3v3>; 135 VDDIO-supply = <&reg_3v3>;
118 clocks = <&mclk>; 136 clocks = <&mclk>;
119 }; 137 };
120
121 touchscreen1: eeti@4 {
122 compatible = "eeti,egalax_ts";
123 reg = <0x04>;
124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_eeti1>;
126 interrupt-parent = <&gpio3>;
127 interrupts = <22 0>;
128 wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
129 wakeup-source;
130 };
131}; 138};
132 139
133&iomuxc { 140&iomuxc {
134 imx53-tx53-x13x { 141 imx53-tx53-x13x {
135 pinctrl_i2c2: i2c2-grp1 {
136 fsl,pins = <
137 MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
138 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
139 >;
140 };
141
142 pinctrl_lvds0: lvds0grp { 142 pinctrl_lvds0: lvds0grp {
143 fsl,pins = < 143 fsl,pins = <
144 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 144 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi b/arch/arm/boot/dts/imx53-tx53.dtsi
index 7807c1fa1101..71b58b6933e1 100644
--- a/arch/arm/boot/dts/imx53-tx53.dtsi
+++ b/arch/arm/boot/dts/imx53-tx53.dtsi
@@ -1,15 +1,45 @@
1/* 1/*
2 * Copyright 2012 <LW@KARO-electronics.de> 2 * Copyright 2012-2017 <LW@KARO-electronics.de>
3 * based on imx53-qsb.dts 3 * based on imx53-qsb.dts
4 * Copyright 2011 Freescale Semiconductor, Inc. 4 * Copyright 2011 Freescale Semiconductor, Inc.
5 * Copyright 2011 Linaro Ltd. 5 * Copyright 2011 Linaro Ltd.
6 * 6 *
7 * The code contained herein is licensed under the GNU General Public 7 * This file is dual-licensed: you can use it either under the terms
8 * License. You may obtain a copy of the GNU General Public License 8 * of the GPL or the X11 license, at your option. Note that this dual
9 * Version 2 at the following locations: 9 * licensing only applies to this file, and not this project as a
10 * whole.
10 * 11 *
11 * http://www.opensource.org/licenses/gpl-license.html 12 * a) This file is free software; you can redistribute it and/or
12 * http://www.gnu.org/copyleft/gpl.html 13 * modify it under the terms of the GNU General Public License
14 * version 2 as published by the Free Software Foundation.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
13 */ 43 */
14 44
15#include "imx53.dtsi" 45#include "imx53.dtsi"
@@ -66,61 +96,50 @@
66 }; 96 };
67 }; 97 };
68 98
69 regulators { 99 reg_2v5: regulator-2v5 {
70 compatible = "simple-bus"; 100 compatible = "regulator-fixed";
71 #address-cells = <1>; 101 regulator-name = "2V5";
72 #size-cells = <0>; 102 regulator-min-microvolt = <2500000>;
73 103 regulator-max-microvolt = <2500000>;
74 reg_2v5: regulator@0 { 104 };
75 compatible = "regulator-fixed";
76 reg = <0>;
77 regulator-name = "2V5";
78 regulator-min-microvolt = <2500000>;
79 regulator-max-microvolt = <2500000>;
80 };
81 105
82 reg_3v3: regulator@1 { 106 reg_3v3: regulator-3v3 {
83 compatible = "regulator-fixed"; 107 compatible = "regulator-fixed";
84 reg = <1>; 108 regulator-name = "3V3";
85 regulator-name = "3V3"; 109 regulator-min-microvolt = <3300000>;
86 regulator-min-microvolt = <3300000>; 110 regulator-max-microvolt = <3300000>;
87 regulator-max-microvolt = <3300000>; 111 };
88 };
89 112
90 reg_can_xcvr: regulator@2 { 113 reg_can_xcvr: regulator-can-xcvr {
91 compatible = "regulator-fixed"; 114 compatible = "regulator-fixed";
92 reg = <2>; 115 regulator-name = "CAN XCVR";
93 regulator-name = "CAN XCVR"; 116 regulator-min-microvolt = <3300000>;
94 regulator-min-microvolt = <3300000>; 117 regulator-max-microvolt = <3300000>;
95 regulator-max-microvolt = <3300000>; 118 pinctrl-names = "default";
96 pinctrl-names = "default"; 119 pinctrl-0 = <&pinctrl_can_xcvr>;
97 pinctrl-0 = <&pinctrl_can_xcvr>; 120 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
98 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; 121 };
99 };
100 122
101 reg_usbh1_vbus: regulator@3 { 123 reg_usbh1_vbus: regulator-usbh1-vbus {
102 compatible = "regulator-fixed"; 124 compatible = "regulator-fixed";
103 reg = <3>; 125 regulator-name = "usbh1_vbus";
104 regulator-name = "usbh1_vbus"; 126 regulator-min-microvolt = <5000000>;
105 regulator-min-microvolt = <5000000>; 127 regulator-max-microvolt = <5000000>;
106 regulator-max-microvolt = <5000000>; 128 pinctrl-names = "default";
107 pinctrl-names = "default"; 129 pinctrl-0 = <&pinctrl_usbh1_vbus>;
108 pinctrl-0 = <&pinctrl_usbh1_vbus>; 130 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
109 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; 131 enable-active-high;
110 enable-active-high; 132 };
111 };
112 133
113 reg_usbotg_vbus: regulator@4 { 134 reg_usbotg_vbus: regulator-usbotg-vbus {
114 compatible = "regulator-fixed"; 135 compatible = "regulator-fixed";
115 reg = <4>; 136 regulator-name = "usbotg_vbus";
116 regulator-name = "usbotg_vbus"; 137 regulator-min-microvolt = <5000000>;
117 regulator-min-microvolt = <5000000>; 138 regulator-max-microvolt = <5000000>;
118 regulator-max-microvolt = <5000000>; 139 pinctrl-names = "default";
119 pinctrl-names = "default"; 140 pinctrl-0 = <&pinctrl_usbotg_vbus>;
120 pinctrl-0 = <&pinctrl_usbotg_vbus>; 141 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
121 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; 142 enable-active-high;
122 enable-active-high;
123 };
124 }; 143 };
125 144
126 sound { 145 sound {
@@ -208,14 +227,17 @@
208 227
209 phy0: ethernet-phy@0 { 228 phy0: ethernet-phy@0 {
210 interrupt-parent = <&gpio2>; 229 interrupt-parent = <&gpio2>;
211 interrupts = <4>; 230 interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
212 device_type = "ethernet-phy"; 231 device_type = "ethernet-phy";
213 }; 232 };
214}; 233};
215 234
216&i2c1 { 235&i2c1 {
217 pinctrl-names = "default"; 236 pinctrl-names = "default", "gpio";
218 pinctrl-0 = <&pinctrl_i2c1>; 237 pinctrl-0 = <&pinctrl_i2c1>;
238 pinctrl-0 = <&pinctrl_i2c1_gpio>;
239 scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
240 sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
219 clock-frequency = <400000>; 241 clock-frequency = <400000>;
220 status = "okay"; 242 status = "okay";
221 243
@@ -225,7 +247,9 @@
225 pinctrl-names = "default"; 247 pinctrl-names = "default";
226 pinctrl-0 = <&pinctrl_ds1339>; 248 pinctrl-0 = <&pinctrl_ds1339>;
227 interrupt-parent = <&gpio4>; 249 interrupt-parent = <&gpio4>;
228 interrupts = <20 0>; 250 interrupts = <20 IRQ_TYPE_EDGE_FALLING>;
251 trickle-resistor-ohms = <250>;
252 trickle-diode-disable;
229 }; 253 };
230}; 254};
231 255
@@ -368,15 +392,29 @@
368 392
369 pinctrl_i2c1: i2c1grp { 393 pinctrl_i2c1: i2c1grp {
370 fsl,pins = < 394 fsl,pins = <
371 MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000 395 MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4
372 MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000 396 MX53_PAD_EIM_D28__I2C1_SDA 0x400001e4
397 >;
398 };
399
400 pinctrl_i2c1_gpio: i2c1-gpiogrp {
401 fsl,pins = <
402 MX53_PAD_EIM_D21__GPIO3_21 0x400001e6
403 MX53_PAD_EIM_D28__GPIO3_28 0x400001e6
373 >; 404 >;
374 }; 405 };
375 406
376 pinctrl_i2c3: i2c3grp { 407 pinctrl_i2c3: i2c3grp {
377 fsl,pins = < 408 fsl,pins = <
378 MX53_PAD_GPIO_3__I2C3_SCL 0xc0000000 409 MX53_PAD_GPIO_3__I2C3_SCL 0x400001e4
379 MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 410 MX53_PAD_GPIO_6__I2C3_SDA 0x400001e4
411 >;
412 };
413
414 pinctrl_i2c3_gpio: i2c3-gpiogrp {
415 fsl,pins = <
416 MX53_PAD_GPIO_3__GPIO1_3 0x400001e6
417 MX53_PAD_GPIO_6__GPIO1_6 0x400001e6
380 >; 418 >;
381 }; 419 };
382 420
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 690b1a049f7e..589a67c5f796 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -299,14 +299,14 @@
299 reg = <0x53f00000 0x60>; 299 reg = <0x53f00000 0x60>;
300 }; 300 };
301 301
302 usbphy0: usbphy@0 { 302 usbphy0: usbphy-0 {
303 compatible = "usb-nop-xceiv"; 303 compatible = "usb-nop-xceiv";
304 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; 304 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
305 clock-names = "main_clk"; 305 clock-names = "main_clk";
306 status = "okay"; 306 status = "okay";
307 }; 307 };
308 308
309 usbphy1: usbphy@1 { 309 usbphy1: usbphy-1 {
310 compatible = "usb-nop-xceiv"; 310 compatible = "usb-nop-xceiv";
311 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; 311 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
312 clock-names = "main_clk"; 312 clock-names = "main_clk";
diff --git a/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts b/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts
index 0677625463d6..5f0d196495d0 100644
--- a/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts
+++ b/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts
@@ -52,7 +52,7 @@
52 reg = <0x10000000 0x40000000>; 52 reg = <0x10000000 0x40000000>;
53 }; 53 };
54 54
55 display0: display@di0 { 55 display0: disp0 {
56 #address-cells = <1>; 56 #address-cells = <1>;
57 #size-cells = <0>; 57 #size-cells = <0>;
58 compatible = "fsl,imx-parallel-display"; 58 compatible = "fsl,imx-parallel-display";
diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts
index 32a812b1839e..cc418cecabdb 100644
--- a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts
+++ b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts
@@ -32,7 +32,7 @@
32 }; 32 };
33 33
34 soc { 34 soc {
35 display0: display@di0 { 35 display0: disp0 {
36 compatible = "fsl,imx-parallel-display"; 36 compatible = "fsl,imx-parallel-display";
37 interface-pix-fmt = "rgb24"; 37 interface-pix-fmt = "rgb24";
38 pinctrl-names = "default"; 38 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts
index 15203f0e9725..126ff964eded 100644
--- a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts
+++ b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts
@@ -21,7 +21,7 @@
21 }; 21 };
22 22
23 soc { 23 soc {
24 display0: display@di0 { 24 display0: disp0 {
25 compatible = "fsl,imx-parallel-display"; 25 compatible = "fsl,imx-parallel-display";
26 interface-pix-fmt = "rgb24"; 26 interface-pix-fmt = "rgb24";
27 pinctrl-names = "default"; 27 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
index 26541538562c..5705ebee0595 100644
--- a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
@@ -88,7 +88,7 @@
88 }; 88 };
89 }; 89 };
90 90
91 lcd_display: display@di0 { 91 lcd_display: disp0 {
92 compatible = "fsl,imx-parallel-display"; 92 compatible = "fsl,imx-parallel-display";
93 #address-cells = <1>; 93 #address-cells = <1>;
94 #size-cells = <0>; 94 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/imx6dl-icore.dts b/arch/arm/boot/dts/imx6dl-icore.dts
index 6de83c72bd72..971f9fc39c66 100644
--- a/arch/arm/boot/dts/imx6dl-icore.dts
+++ b/arch/arm/boot/dts/imx6dl-icore.dts
@@ -57,3 +57,12 @@
57&can2 { 57&can2 {
58 status = "okay"; 58 status = "okay";
59}; 59};
60
61&i2c1 {
62 max11801: touchscreen@48 {
63 compatible = "maxim,max11801";
64 reg = <0x48>;
65 interrupt-parent = <&gpio3>;
66 interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
67 };
68};
diff --git a/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts b/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts
index aac42ac465b6..51a9bb9d6bc2 100644
--- a/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts
+++ b/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> 2 * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de>
3 * 3 *
4 * This file is dual-licensed: you can use it either under the terms 4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual 5 * of the GPL or the X11 license, at your option. Note that this dual
@@ -42,70 +42,16 @@
42/dts-v1/; 42/dts-v1/;
43#include "imx6dl.dtsi" 43#include "imx6dl.dtsi"
44#include "imx6qdl-tx6.dtsi" 44#include "imx6qdl-tx6.dtsi"
45#include "imx6qdl-tx6-lcd.dtsi"
45 46
46/ { 47/ {
47 model = "Ka-Ro electronics TX6DL Module on CoMpact TFT"; 48 model = "Ka-Ro electronics TX6DL Module on CoMpact TFT";
48 compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; 49 compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl";
50};
49 51
50 aliases { 52&backlight {
51 display = &display; 53 pwms = <&pwm2 0 500000 0>;
52 }; 54 /delete-property/ turn-on-delay-ms;
53
54 backlight: backlight {
55 compatible = "pwm-backlight";
56 pwms = <&pwm2 0 500000 0>;
57 power-supply = <&reg_3v3>;
58 /*
59 * a poor man's way to create a 1:1 relationship between
60 * the PWM value and the actual duty cycle
61 */
62 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
63 10 11 12 13 14 15 16 17 18 19
64 20 21 22 23 24 25 26 27 28 29
65 30 31 32 33 34 35 36 37 38 39
66 40 41 42 43 44 45 46 47 48 49
67 50 51 52 53 54 55 56 57 58 59
68 60 61 62 63 64 65 66 67 68 69
69 70 71 72 73 74 75 76 77 78 79
70 80 81 82 83 84 85 86 87 88 89
71 90 91 92 93 94 95 96 97 98 99
72 100>;
73 default-brightness-level = <50>;
74 };
75
76 display: display@di0 {
77 compatible = "fsl,imx-parallel-display";
78 interface-pix-fmt = "rgb24";
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_disp0_1>;
81 status = "okay";
82
83 port {
84 display0_in: endpoint {
85 remote-endpoint = <&ipu1_di0_disp0>;
86 };
87 };
88
89 display-timings {
90 native-mode = <&ET070001DM6>;
91
92 ET070001DM6: CoMTFT { /* same as ET0700 but with inverted pixel clock */
93 clock-frequency = <33264000>;
94 hactive = <800>;
95 vactive = <480>;
96 hback-porch = <88>;
97 hsync-len = <128>;
98 hfront-porch = <40>;
99 vback-porch = <33>;
100 vsync-len = <2>;
101 vfront-porch = <10>;
102 hsync-active = <0>;
103 vsync-active = <0>;
104 de-active = <1>;
105 pixelclk-active = <1>;
106 };
107 };
108 };
109}; 55};
110 56
111&can1 { 57&can1 {
@@ -116,14 +62,14 @@
116 xceiver-supply = <&reg_3v3>; 62 xceiver-supply = <&reg_3v3>;
117}; 63};
118 64
119&ipu1_di0_disp0 {
120 remote-endpoint = <&display0_in>;
121};
122
123&kpp { 65&kpp {
124 status = "disabled"; 66 status = "disabled";
125}; 67};
126 68
69&lcd_panel {
70 compatible = "edt,etm0700g0edh6";
71};
72
127&reg_can_xcvr { 73&reg_can_xcvr {
128 status = "disabled"; 74 status = "disabled";
129}; 75};
diff --git a/arch/arm/boot/dts/imx6dl-tx6s-8034-mb7.dts b/arch/arm/boot/dts/imx6dl-tx6s-8034-mb7.dts
new file mode 100644
index 000000000000..fc23b4d291a1
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-tx6s-8034-mb7.dts
@@ -0,0 +1,48 @@
1/*
2 * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42/dts-v1/;
43#include "imx6dl-tx6s-8034.dts"
44#include "imx6qdl-tx6-mb7.dtsi"
45
46/ {
47 model = "Ka-Ro electronics TX6S-8034 Module on MB7 baseboard";
48};
diff --git a/arch/arm/boot/dts/imx6dl-tx6s-8034.dts b/arch/arm/boot/dts/imx6dl-tx6s-8034.dts
index ff8f7b1c4282..9eb2ef17339c 100644
--- a/arch/arm/boot/dts/imx6dl-tx6s-8034.dts
+++ b/arch/arm/boot/dts/imx6dl-tx6s-8034.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2015-2016 Lothar Waßmann <LW@KARO-electronics.de> 2 * Copyright 2015-2017 Lothar Waßmann <LW@KARO-electronics.de>
3 * 3 *
4 * This file is dual-licensed: you can use it either under the terms 4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual 5 * of the GPL or the X11 license, at your option. Note that this dual
@@ -42,174 +42,15 @@
42/dts-v1/; 42/dts-v1/;
43#include "imx6dl.dtsi" 43#include "imx6dl.dtsi"
44#include "imx6qdl-tx6.dtsi" 44#include "imx6qdl-tx6.dtsi"
45#include "imx6qdl-tx6-lcd.dtsi"
45 46
46/ { 47/ {
47 model = "Ka-Ro electronics TX6S-8034 Module"; 48 model = "Ka-Ro electronics TX6S-8034 Module";
48 compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; 49 compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl";
49 50
50 aliases {
51 display = &display;
52 ipu1 = &ipu1;
53 };
54
55 cpus { 51 cpus {
56 /delete-node/ cpu@1; 52 /delete-node/ cpu@1;
57 }; 53 };
58
59 backlight: backlight {
60 compatible = "pwm-backlight";
61 pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
62 pinctrl-names = "default";
63 pinctrl-0 = <&pinctrl_lcd0_pwr>;
64 enable-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
65 power-supply = <&reg_lcd1_pwr>;
66 /*
67 * a poor man's way to create a 1:1 relationship between
68 * the PWM value and the actual duty cycle
69 */
70 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
71 10 11 12 13 14 15 16 17 18 19
72 20 21 22 23 24 25 26 27 28 29
73 30 31 32 33 34 35 36 37 38 39
74 40 41 42 43 44 45 46 47 48 49
75 50 51 52 53 54 55 56 57 58 59
76 60 61 62 63 64 65 66 67 68 69
77 70 71 72 73 74 75 76 77 78 79
78 80 81 82 83 84 85 86 87 88 89
79 90 91 92 93 94 95 96 97 98 99
80 100>;
81 default-brightness-level = <50>;
82 };
83
84 display: display@di0 {
85 compatible = "fsl,imx-parallel-display";
86 pinctrl-names = "default";
87 pinctrl-0 = <&pinctrl_disp0_2>;
88 interface-pix-fmt = "rgb24";
89 status = "okay";
90
91 port {
92 display0_in: endpoint {
93 remote-endpoint = <&ipu1_di0_disp0>;
94 };
95 };
96
97 display-timings {
98 native-mode = <&vga>;
99
100 vga: VGA {
101 clock-frequency = <25200000>;
102 hactive = <640>;
103 vactive = <480>;
104 hback-porch = <48>;
105 hsync-len = <96>;
106 hfront-porch = <16>;
107 vback-porch = <31>;
108 vsync-len = <2>;
109 vfront-porch = <12>;
110 hsync-active = <0>;
111 vsync-active = <0>;
112 de-active = <1>;
113 pixelclk-active = <0>;
114 };
115
116 ETV570 {
117 clock-frequency = <25200000>;
118 hactive = <640>;
119 vactive = <480>;
120 hback-porch = <114>;
121 hsync-len = <30>;
122 hfront-porch = <16>;
123 vback-porch = <32>;
124 vsync-len = <3>;
125 vfront-porch = <10>;
126 hsync-active = <0>;
127 vsync-active = <0>;
128 de-active = <1>;
129 pixelclk-active = <0>;
130 };
131
132 ET0350 {
133 clock-frequency = <6413760>;
134 hactive = <320>;
135 vactive = <240>;
136 hback-porch = <34>;
137 hsync-len = <34>;
138 hfront-porch = <20>;
139 vback-porch = <15>;
140 vsync-len = <3>;
141 vfront-porch = <4>;
142 hsync-active = <0>;
143 vsync-active = <0>;
144 de-active = <1>;
145 pixelclk-active = <0>;
146 };
147
148 ET0430 {
149 clock-frequency = <9009000>;
150 hactive = <480>;
151 vactive = <272>;
152 hback-porch = <2>;
153 hsync-len = <41>;
154 hfront-porch = <2>;
155 vback-porch = <2>;
156 vsync-len = <10>;
157 vfront-porch = <2>;
158 hsync-active = <0>;
159 vsync-active = <0>;
160 de-active = <1>;
161 pixelclk-active = <1>;
162 };
163
164 ET0500 {
165 clock-frequency = <33264000>;
166 hactive = <800>;
167 vactive = <480>;
168 hback-porch = <88>;
169 hsync-len = <128>;
170 hfront-porch = <40>;
171 vback-porch = <33>;
172 vsync-len = <2>;
173 vfront-porch = <10>;
174 hsync-active = <0>;
175 vsync-active = <0>;
176 de-active = <1>;
177 pixelclk-active = <0>;
178 };
179
180 ET0700 { /* same as ET0500 */
181 clock-frequency = <33264000>;
182 hactive = <800>;
183 vactive = <480>;
184 hback-porch = <88>;
185 hsync-len = <128>;
186 hfront-porch = <40>;
187 vback-porch = <33>;
188 vsync-len = <2>;
189 vfront-porch = <10>;
190 hsync-active = <0>;
191 vsync-active = <0>;
192 de-active = <1>;
193 pixelclk-active = <0>;
194 };
195
196 ETQ570 {
197 clock-frequency = <6596040>;
198 hactive = <320>;
199 vactive = <240>;
200 hback-porch = <38>;
201 hsync-len = <30>;
202 hfront-porch = <30>;
203 vback-porch = <16>;
204 vsync-len = <3>;
205 vfront-porch = <4>;
206 hsync-active = <0>;
207 vsync-active = <0>;
208 de-active = <1>;
209 pixelclk-active = <0>;
210 };
211 };
212 };
213}; 54};
214 55
215&ds1339 { 56&ds1339 {
@@ -227,11 +68,3 @@
227 MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x170b0 /* SD1 CD */ 68 MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x170b0 /* SD1 CD */
228 >; 69 >;
229}; 70};
230
231&ipu1_di0_disp0 {
232 remote-endpoint = <&display0_in>;
233};
234
235&reg_lcd0_pwr {
236 status = "disabled";
237};
diff --git a/arch/arm/boot/dts/imx6dl-tx6s-8035-mb7.dts b/arch/arm/boot/dts/imx6dl-tx6s-8035-mb7.dts
new file mode 100644
index 000000000000..4101c6597721
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-tx6s-8035-mb7.dts
@@ -0,0 +1,48 @@
1/*
2 * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42/dts-v1/;
43#include "imx6dl-tx6s-8035.dts"
44#include "imx6qdl-tx6-mb7.dtsi"
45
46/ {
47 model = "Ka-Ro electronics TX6U-8035 Module on MB7 baseboard";
48};
diff --git a/arch/arm/boot/dts/imx6dl-tx6s-8035.dts b/arch/arm/boot/dts/imx6dl-tx6s-8035.dts
index f988950e9443..a5532ecc18c5 100644
--- a/arch/arm/boot/dts/imx6dl-tx6s-8035.dts
+++ b/arch/arm/boot/dts/imx6dl-tx6s-8035.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2015-2016 Lothar Waßmann <LW@KARO-electronics.de> 2 * Copyright 2015-2017 Lothar Waßmann <LW@KARO-electronics.de>
3 * 3 *
4 * This file is dual-licensed: you can use it either under the terms 4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual 5 * of the GPL or the X11 license, at your option. Note that this dual
@@ -42,174 +42,15 @@
42/dts-v1/; 42/dts-v1/;
43#include "imx6dl.dtsi" 43#include "imx6dl.dtsi"
44#include "imx6qdl-tx6.dtsi" 44#include "imx6qdl-tx6.dtsi"
45#include "imx6qdl-tx6-lcd.dtsi"
45 46
46/ { 47/ {
47 model = "Ka-Ro electronics TX6S-8035 Module"; 48 model = "Ka-Ro electronics TX6S-8035 Module";
48 compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; 49 compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl";
49 50
50 aliases {
51 display = &display;
52 ipu1 = &ipu1;
53 };
54
55 cpus { 51 cpus {
56 /delete-node/ cpu@1; 52 /delete-node/ cpu@1;
57 }; 53 };
58
59 backlight: backlight {
60 compatible = "pwm-backlight";
61 pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
62 pinctrl-names = "default";
63 pinctrl-0 = <&pinctrl_lcd0_pwr>;
64 enable-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
65 power-supply = <&reg_lcd1_pwr>;
66 /*
67 * a poor man's way to create a 1:1 relationship between
68 * the PWM value and the actual duty cycle
69 */
70 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
71 10 11 12 13 14 15 16 17 18 19
72 20 21 22 23 24 25 26 27 28 29
73 30 31 32 33 34 35 36 37 38 39
74 40 41 42 43 44 45 46 47 48 49
75 50 51 52 53 54 55 56 57 58 59
76 60 61 62 63 64 65 66 67 68 69
77 70 71 72 73 74 75 76 77 78 79
78 80 81 82 83 84 85 86 87 88 89
79 90 91 92 93 94 95 96 97 98 99
80 100>;
81 default-brightness-level = <50>;
82 };
83
84 display: display@di0 {
85 compatible = "fsl,imx-parallel-display";
86 pinctrl-names = "default";
87 pinctrl-0 = <&pinctrl_disp0_2>;
88 interface-pix-fmt = "rgb24";
89 status = "okay";
90
91 port {
92 display0_in: endpoint {
93 remote-endpoint = <&ipu1_di0_disp0>;
94 };
95 };
96
97 display-timings {
98 native-mode = <&vga>;
99
100 vga: VGA {
101 clock-frequency = <25200000>;
102 hactive = <640>;
103 vactive = <480>;
104 hback-porch = <48>;
105 hsync-len = <96>;
106 hfront-porch = <16>;
107 vback-porch = <31>;
108 vsync-len = <2>;
109 vfront-porch = <12>;
110 hsync-active = <0>;
111 vsync-active = <0>;
112 de-active = <1>;
113 pixelclk-active = <0>;
114 };
115
116 ETV570 {
117 clock-frequency = <25200000>;
118 hactive = <640>;
119 vactive = <480>;
120 hback-porch = <114>;
121 hsync-len = <30>;
122 hfront-porch = <16>;
123 vback-porch = <32>;
124 vsync-len = <3>;
125 vfront-porch = <10>;
126 hsync-active = <0>;
127 vsync-active = <0>;
128 de-active = <1>;
129 pixelclk-active = <0>;
130 };
131
132 ET0350 {
133 clock-frequency = <6413760>;
134 hactive = <320>;
135 vactive = <240>;
136 hback-porch = <34>;
137 hsync-len = <34>;
138 hfront-porch = <20>;
139 vback-porch = <15>;
140 vsync-len = <3>;
141 vfront-porch = <4>;
142 hsync-active = <0>;
143 vsync-active = <0>;
144 de-active = <1>;
145 pixelclk-active = <0>;
146 };
147
148 ET0430 {
149 clock-frequency = <9009000>;
150 hactive = <480>;
151 vactive = <272>;
152 hback-porch = <2>;
153 hsync-len = <41>;
154 hfront-porch = <2>;
155 vback-porch = <2>;
156 vsync-len = <10>;
157 vfront-porch = <2>;
158 hsync-active = <0>;
159 vsync-active = <0>;
160 de-active = <1>;
161 pixelclk-active = <1>;
162 };
163
164 ET0500 {
165 clock-frequency = <33264000>;
166 hactive = <800>;
167 vactive = <480>;
168 hback-porch = <88>;
169 hsync-len = <128>;
170 hfront-porch = <40>;
171 vback-porch = <33>;
172 vsync-len = <2>;
173 vfront-porch = <10>;
174 hsync-active = <0>;
175 vsync-active = <0>;
176 de-active = <1>;
177 pixelclk-active = <0>;
178 };
179
180 ET0700 { /* same as ET0500 */
181 clock-frequency = <33264000>;
182 hactive = <800>;
183 vactive = <480>;
184 hback-porch = <88>;
185 hsync-len = <128>;
186 hfront-porch = <40>;
187 vback-porch = <33>;
188 vsync-len = <2>;
189 vfront-porch = <10>;
190 hsync-active = <0>;
191 vsync-active = <0>;
192 de-active = <1>;
193 pixelclk-active = <0>;
194 };
195
196 ETQ570 {
197 clock-frequency = <6596040>;
198 hactive = <320>;
199 vactive = <240>;
200 hback-porch = <38>;
201 hsync-len = <30>;
202 hfront-porch = <30>;
203 vback-porch = <16>;
204 vsync-len = <3>;
205 vfront-porch = <4>;
206 hsync-active = <0>;
207 vsync-active = <0>;
208 de-active = <1>;
209 pixelclk-active = <0>;
210 };
211 };
212 };
213}; 54};
214 55
215&ds1339 { 56&ds1339 {
@@ -220,14 +61,6 @@
220 status = "disabled"; 61 status = "disabled";
221}; 62};
222 63
223&ipu1_di0_disp0 {
224 remote-endpoint = <&display0_in>;
225};
226
227&reg_lcd0_pwr {
228 status = "disabled";
229};
230
231&usdhc4 { 64&usdhc4 {
232 pinctrl-names = "default"; 65 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_usdhc4>; 66 pinctrl-0 = <&pinctrl_usdhc4>;
diff --git a/arch/arm/boot/dts/imx6dl-tx6u-801x.dts b/arch/arm/boot/dts/imx6dl-tx6u-801x.dts
index d1f1298ec55a..67ed0452f5de 100644
--- a/arch/arm/boot/dts/imx6dl-tx6u-801x.dts
+++ b/arch/arm/boot/dts/imx6dl-tx6u-801x.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> 2 * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de>
3 * 3 *
4 * This file is dual-licensed: you can use it either under the terms 4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual 5 * of the GPL or the X11 license, at your option. Note that this dual
@@ -42,166 +42,9 @@
42/dts-v1/; 42/dts-v1/;
43#include "imx6dl.dtsi" 43#include "imx6dl.dtsi"
44#include "imx6qdl-tx6.dtsi" 44#include "imx6qdl-tx6.dtsi"
45#include "imx6qdl-tx6-lcd.dtsi"
45 46
46/ { 47/ {
47 model = "Ka-Ro electronics TX6U-801x Module"; 48 model = "Ka-Ro electronics TX6U-801x Module";
48 compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; 49 compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl";
49
50 aliases {
51 display = &display;
52 };
53
54 backlight: backlight {
55 compatible = "pwm-backlight";
56 pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
57 power-supply = <&reg_3v3>;
58 /*
59 * a poor man's way to create a 1:1 relationship between
60 * the PWM value and the actual duty cycle
61 */
62 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
63 10 11 12 13 14 15 16 17 18 19
64 20 21 22 23 24 25 26 27 28 29
65 30 31 32 33 34 35 36 37 38 39
66 40 41 42 43 44 45 46 47 48 49
67 50 51 52 53 54 55 56 57 58 59
68 60 61 62 63 64 65 66 67 68 69
69 70 71 72 73 74 75 76 77 78 79
70 80 81 82 83 84 85 86 87 88 89
71 90 91 92 93 94 95 96 97 98 99
72 100>;
73 default-brightness-level = <50>;
74 };
75
76 display: display@di0 {
77 compatible = "fsl,imx-parallel-display";
78 interface-pix-fmt = "rgb24";
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_disp0_1>;
81 status = "okay";
82
83 port {
84 display0_in: endpoint {
85 remote-endpoint = <&ipu1_di0_disp0>;
86 };
87 };
88
89 display-timings {
90 VGA {
91 clock-frequency = <25200000>;
92 hactive = <640>;
93 vactive = <480>;
94 hback-porch = <48>;
95 hsync-len = <96>;
96 hfront-porch = <16>;
97 vback-porch = <31>;
98 vsync-len = <2>;
99 vfront-porch = <12>;
100 hsync-active = <0>;
101 vsync-active = <0>;
102 de-active = <1>;
103 pixelclk-active = <0>;
104 };
105
106 ETV570 {
107 clock-frequency = <25200000>;
108 hactive = <640>;
109 vactive = <480>;
110 hback-porch = <114>;
111 hsync-len = <30>;
112 hfront-porch = <16>;
113 vback-porch = <32>;
114 vsync-len = <3>;
115 vfront-porch = <10>;
116 hsync-active = <0>;
117 vsync-active = <0>;
118 de-active = <1>;
119 pixelclk-active = <0>;
120 };
121
122 ET0350 {
123 clock-frequency = <6413760>;
124 hactive = <320>;
125 vactive = <240>;
126 hback-porch = <34>;
127 hsync-len = <34>;
128 hfront-porch = <20>;
129 vback-porch = <15>;
130 vsync-len = <3>;
131 vfront-porch = <4>;
132 hsync-active = <0>;
133 vsync-active = <0>;
134 de-active = <1>;
135 pixelclk-active = <0>;
136 };
137
138 ET0430 {
139 clock-frequency = <9009000>;
140 hactive = <480>;
141 vactive = <272>;
142 hback-porch = <2>;
143 hsync-len = <41>;
144 hfront-porch = <2>;
145 vback-porch = <2>;
146 vsync-len = <10>;
147 vfront-porch = <2>;
148 hsync-active = <0>;
149 vsync-active = <0>;
150 de-active = <1>;
151 pixelclk-active = <1>;
152 };
153
154 ET0500 {
155 clock-frequency = <33264000>;
156 hactive = <800>;
157 vactive = <480>;
158 hback-porch = <88>;
159 hsync-len = <128>;
160 hfront-porch = <40>;
161 vback-porch = <33>;
162 vsync-len = <2>;
163 vfront-porch = <10>;
164 hsync-active = <0>;
165 vsync-active = <0>;
166 de-active = <1>;
167 pixelclk-active = <0>;
168 };
169
170 ET0700 { /* same as ET0500 */
171 clock-frequency = <33264000>;
172 hactive = <800>;
173 vactive = <480>;
174 hback-porch = <88>;
175 hsync-len = <128>;
176 hfront-porch = <40>;
177 vback-porch = <33>;
178 vsync-len = <2>;
179 vfront-porch = <10>;
180 hsync-active = <0>;
181 vsync-active = <0>;
182 de-active = <1>;
183 pixelclk-active = <0>;
184 };
185
186 ETQ570 {
187 clock-frequency = <6596040>;
188 hactive = <320>;
189 vactive = <240>;
190 hback-porch = <38>;
191 hsync-len = <30>;
192 hfront-porch = <30>;
193 vback-porch = <16>;
194 vsync-len = <3>;
195 vfront-porch = <4>;
196 hsync-active = <0>;
197 vsync-active = <0>;
198 de-active = <1>;
199 pixelclk-active = <0>;
200 };
201 };
202 };
203};
204
205&ipu1_di0_disp0 {
206 remote-endpoint = <&display0_in>;
207}; 50};
diff --git a/arch/arm/boot/dts/imx6dl-tx6u-8033-mb7.dts b/arch/arm/boot/dts/imx6dl-tx6u-8033-mb7.dts
new file mode 100644
index 000000000000..d34189fc52d9
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-tx6u-8033-mb7.dts
@@ -0,0 +1,48 @@
1/*
2 * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42/dts-v1/;
43#include "imx6dl-tx6u-8033.dts"
44#include "imx6qdl-tx6-mb7.dtsi"
45
46/ {
47 model = "Ka-Ro electronics TX6U-8033 Module on MB7 baseboard";
48};
diff --git a/arch/arm/boot/dts/imx6dl-tx6u-8033.dts b/arch/arm/boot/dts/imx6dl-tx6u-8033.dts
index 4d3204a56f46..7030b2654bbd 100644
--- a/arch/arm/boot/dts/imx6dl-tx6u-8033.dts
+++ b/arch/arm/boot/dts/imx6dl-tx6u-8033.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> 2 * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de>
3 * 3 *
4 * This file is dual-licensed: you can use it either under the terms 4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual 5 * of the GPL or the X11 license, at your option. Note that this dual
@@ -42,169 +42,11 @@
42/dts-v1/; 42/dts-v1/;
43#include "imx6dl.dtsi" 43#include "imx6dl.dtsi"
44#include "imx6qdl-tx6.dtsi" 44#include "imx6qdl-tx6.dtsi"
45#include "imx6qdl-tx6-lcd.dtsi"
45 46
46/ { 47/ {
47 model = "Ka-Ro electronics TX6U-8033 Module"; 48 model = "Ka-Ro electronics TX6U-8033 Module";
48 compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; 49 compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl";
49
50 aliases {
51 display = &display;
52 };
53
54 backlight: backlight {
55 compatible = "pwm-backlight";
56 pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
57 pinctrl-names = "default";
58 pinctrl-0 = <&pinctrl_lcd0_pwr>;
59 enable-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
60 power-supply = <&reg_lcd1_pwr>;
61 /*
62 * a poor man's way to create a 1:1 relationship between
63 * the PWM value and the actual duty cycle
64 */
65 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
66 10 11 12 13 14 15 16 17 18 19
67 20 21 22 23 24 25 26 27 28 29
68 30 31 32 33 34 35 36 37 38 39
69 40 41 42 43 44 45 46 47 48 49
70 50 51 52 53 54 55 56 57 58 59
71 60 61 62 63 64 65 66 67 68 69
72 70 71 72 73 74 75 76 77 78 79
73 80 81 82 83 84 85 86 87 88 89
74 90 91 92 93 94 95 96 97 98 99
75 100>;
76 default-brightness-level = <50>;
77 };
78
79 display: display@di0 {
80 compatible = "fsl,imx-parallel-display";
81 pinctrl-names = "default";
82 pinctrl-0 = <&pinctrl_disp0_2>;
83 interface-pix-fmt = "rgb24";
84 status = "okay";
85
86 port {
87 display0_in: endpoint {
88 remote-endpoint = <&ipu1_di0_disp0>;
89 };
90 };
91
92 display-timings {
93 native-mode = <&vga>;
94
95 vga: VGA {
96 clock-frequency = <25200000>;
97 hactive = <640>;
98 vactive = <480>;
99 hback-porch = <48>;
100 hsync-len = <96>;
101 hfront-porch = <16>;
102 vback-porch = <31>;
103 vsync-len = <2>;
104 vfront-porch = <12>;
105 hsync-active = <0>;
106 vsync-active = <0>;
107 de-active = <1>;
108 pixelclk-active = <0>;
109 };
110
111 ETV570 {
112 clock-frequency = <25200000>;
113 hactive = <640>;
114 vactive = <480>;
115 hback-porch = <114>;
116 hsync-len = <30>;
117 hfront-porch = <16>;
118 vback-porch = <32>;
119 vsync-len = <3>;
120 vfront-porch = <10>;
121 hsync-active = <0>;
122 vsync-active = <0>;
123 de-active = <1>;
124 pixelclk-active = <0>;
125 };
126
127 ET0350 {
128 clock-frequency = <6413760>;
129 hactive = <320>;
130 vactive = <240>;
131 hback-porch = <34>;
132 hsync-len = <34>;
133 hfront-porch = <20>;
134 vback-porch = <15>;
135 vsync-len = <3>;
136 vfront-porch = <4>;
137 hsync-active = <0>;
138 vsync-active = <0>;
139 de-active = <1>;
140 pixelclk-active = <0>;
141 };
142
143 ET0430 {
144 clock-frequency = <9009000>;
145 hactive = <480>;
146 vactive = <272>;
147 hback-porch = <2>;
148 hsync-len = <41>;
149 hfront-porch = <2>;
150 vback-porch = <2>;
151 vsync-len = <10>;
152 vfront-porch = <2>;
153 hsync-active = <0>;
154 vsync-active = <0>;
155 de-active = <1>;
156 pixelclk-active = <1>;
157 };
158
159 ET0500 {
160 clock-frequency = <33264000>;
161 hactive = <800>;
162 vactive = <480>;
163 hback-porch = <88>;
164 hsync-len = <128>;
165 hfront-porch = <40>;
166 vback-porch = <33>;
167 vsync-len = <2>;
168 vfront-porch = <10>;
169 hsync-active = <0>;
170 vsync-active = <0>;
171 de-active = <1>;
172 pixelclk-active = <0>;
173 };
174
175 ET0700 { /* same as ET0500 */
176 clock-frequency = <33264000>;
177 hactive = <800>;
178 vactive = <480>;
179 hback-porch = <88>;
180 hsync-len = <128>;
181 hfront-porch = <40>;
182 vback-porch = <33>;
183 vsync-len = <2>;
184 vfront-porch = <10>;
185 hsync-active = <0>;
186 vsync-active = <0>;
187 de-active = <1>;
188 pixelclk-active = <0>;
189 };
190
191 ETQ570 {
192 clock-frequency = <6596040>;
193 hactive = <320>;
194 vactive = <240>;
195 hback-porch = <38>;
196 hsync-len = <30>;
197 hfront-porch = <30>;
198 vback-porch = <16>;
199 vsync-len = <3>;
200 vfront-porch = <4>;
201 hsync-active = <0>;
202 vsync-active = <0>;
203 de-active = <1>;
204 pixelclk-active = <0>;
205 };
206 };
207 };
208}; 50};
209 51
210&ds1339 { 52&ds1339 {
@@ -215,14 +57,6 @@
215 status = "disabled"; 57 status = "disabled";
216}; 58};
217 59
218&ipu1_di0_disp0 {
219 remote-endpoint = <&display0_in>;
220};
221
222&reg_lcd0_pwr {
223 status = "disabled";
224};
225
226&usdhc4 { 60&usdhc4 {
227 pinctrl-names = "default"; 61 pinctrl-names = "default";
228 pinctrl-0 = <&pinctrl_usdhc4>; 62 pinctrl-0 = <&pinctrl_usdhc4>;
diff --git a/arch/arm/boot/dts/imx6dl-tx6u-80xx-mb7.dts b/arch/arm/boot/dts/imx6dl-tx6u-80xx-mb7.dts
new file mode 100644
index 000000000000..aef5fcc42904
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-tx6u-80xx-mb7.dts
@@ -0,0 +1,48 @@
1/*
2 * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42/dts-v1/;
43#include "imx6dl-tx6u-801x.dts"
44#include "imx6qdl-tx6-mb7.dtsi"
45
46/ {
47 model = "Ka-Ro electronics TX6U-8030/-8010/-8012 Module on MB7 baseboard";
48};
diff --git a/arch/arm/boot/dts/imx6dl-tx6u-811x.dts b/arch/arm/boot/dts/imx6dl-tx6u-811x.dts
index 94bf1c485740..5342f2f5a8a8 100644
--- a/arch/arm/boot/dts/imx6dl-tx6u-811x.dts
+++ b/arch/arm/boot/dts/imx6dl-tx6u-811x.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> 2 * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de>
3 * 3 *
4 * This file is dual-licensed: you can use it either under the terms 4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual 5 * of the GPL or the X11 license, at your option. Note that this dual
@@ -42,137 +42,9 @@
42/dts-v1/; 42/dts-v1/;
43#include "imx6dl.dtsi" 43#include "imx6dl.dtsi"
44#include "imx6qdl-tx6.dtsi" 44#include "imx6qdl-tx6.dtsi"
45#include "imx6qdl-tx6-lvds.dtsi"
45 46
46/ { 47/ {
47 model = "Ka-Ro electronics TX6U-811x Module"; 48 model = "Ka-Ro electronics TX6U-811x Module";
48 compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; 49 compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl";
49
50 aliases {
51 display = &lvds0;
52 lvds0 = &lvds0;
53 lvds1 = &lvds1;
54 };
55
56 backlight0: backlight0 {
57 compatible = "pwm-backlight";
58 pwms = <&pwm2 0 500000 0>;
59 power-supply = <&reg_lcd0_pwr>;
60 /*
61 * a poor man's way to create a 1:1 relationship between
62 * the PWM value and the actual duty cycle
63 */
64 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
65 10 11 12 13 14 15 16 17 18 19
66 20 21 22 23 24 25 26 27 28 29
67 30 31 32 33 34 35 36 37 38 39
68 40 41 42 43 44 45 46 47 48 49
69 50 51 52 53 54 55 56 57 58 59
70 60 61 62 63 64 65 66 67 68 69
71 70 71 72 73 74 75 76 77 78 79
72 80 81 82 83 84 85 86 87 88 89
73 90 91 92 93 94 95 96 97 98 99
74 100>;
75 default-brightness-level = <50>;
76 };
77
78 backlight1: backlight1 {
79 compatible = "pwm-backlight";
80 pwms = <&pwm1 0 500000 0>;
81 power-supply = <&reg_lcd1_pwr>;
82 /*
83 * a poor man's way to create a 1:1 relationship between
84 * the PWM value and the actual duty cycle
85 */
86 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
87 10 11 12 13 14 15 16 17 18 19
88 20 21 22 23 24 25 26 27 28 29
89 30 31 32 33 34 35 36 37 38 39
90 40 41 42 43 44 45 46 47 48 49
91 50 51 52 53 54 55 56 57 58 59
92 60 61 62 63 64 65 66 67 68 69
93 70 71 72 73 74 75 76 77 78 79
94 80 81 82 83 84 85 86 87 88 89
95 90 91 92 93 94 95 96 97 98 99
96 100>;
97 default-brightness-level = <50>;
98 };
99};
100
101&i2c3 {
102 polytouch2: eeti@4 {
103 compatible = "eeti,egalax_ts";
104 reg = <0x04>;
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_eeti>;
107 interrupt-parent = <&gpio3>;
108 interrupts = <22 0>;
109 wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
110 wakeup-source;
111 };
112};
113
114&kpp {
115 status = "disabled"; /* pad conflict with backlight1 PWM */
116};
117
118&ldb {
119 status = "okay";
120
121 lvds0: lvds-channel@0 {
122 fsl,data-mapping = "spwg";
123 fsl,data-width = <18>;
124 status = "okay";
125
126 display-timings {
127 native-mode = <&lvds_timing0>;
128 lvds_timing0: hsd100pxn1 {
129 clock-frequency = <65000000>;
130 hactive = <1024>;
131 vactive = <768>;
132 hback-porch = <220>;
133 hfront-porch = <40>;
134 vback-porch = <21>;
135 vfront-porch = <7>;
136 hsync-len = <60>;
137 vsync-len = <10>;
138 de-active = <1>;
139 pixelclk-active = <1>;
140 };
141 };
142 };
143
144 lvds1: lvds-channel@1 {
145 fsl,data-mapping = "spwg";
146 fsl,data-width = <18>;
147 status = "disabled";
148
149 display-timings {
150 native-mode = <&lvds_timing1>;
151 lvds_timing1: hsd100pxn1 {
152 clock-frequency = <65000000>;
153 hactive = <1024>;
154 vactive = <768>;
155 hback-porch = <220>;
156 hfront-porch = <40>;
157 vback-porch = <21>;
158 vfront-porch = <7>;
159 hsync-len = <60>;
160 vsync-len = <10>;
161 de-active = <1>;
162 pixelclk-active = <1>;
163 };
164 };
165 };
166};
167
168&pwm1 {
169 status = "okay";
170};
171
172&iomuxc {
173 pinctrl_eeti: eetigrp {
174 fsl,pins = <
175 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */
176 >;
177 };
178}; 50};
diff --git a/arch/arm/boot/dts/imx6dl-tx6u-81xx-mb7.dts b/arch/arm/boot/dts/imx6dl-tx6u-81xx-mb7.dts
index 839ab8619bbd..c4588fb0bf6f 100644
--- a/arch/arm/boot/dts/imx6dl-tx6u-81xx-mb7.dts
+++ b/arch/arm/boot/dts/imx6dl-tx6u-81xx-mb7.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2016 Lothar Waßmann <LW@KARO-electronics.de> 2 * Copyright 2016-2017 Lothar Waßmann <LW@KARO-electronics.de>
3 * 3 *
4 * This file is dual-licensed: you can use it either under the terms 4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual 5 * of the GPL or the X11 license, at your option. Note that this dual
@@ -40,216 +40,9 @@
40 */ 40 */
41 41
42/dts-v1/; 42/dts-v1/;
43#include "imx6dl.dtsi" 43#include "imx6dl-tx6u-811x.dts"
44#include "imx6qdl-tx6.dtsi" 44#include "imx6qdl-tx6-mb7.dtsi"
45 45
46/ { 46/ {
47 model = "Ka-Ro electronics TX6U-81xx Module on MB7 baseboard"; 47 model = "Ka-Ro electronics TX6U-8130/-8110 Module on MB7 baseboard";
48 compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl";
49
50 aliases {
51 display = &lvds0;
52 lvds0 = &lvds0;
53 lvds1 = &lvds1;
54 };
55
56 backlight0: backlight0 {
57 compatible = "pwm-backlight";
58 pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
59 power-supply = <&reg_lcd0_pwr>;
60 /*
61 * a poor man's way to create a 1:1 relationship between
62 * the PWM value and the actual duty cycle
63 */
64 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
65 10 11 12 13 14 15 16 17 18 19
66 20 21 22 23 24 25 26 27 28 29
67 30 31 32 33 34 35 36 37 38 39
68 40 41 42 43 44 45 46 47 48 49
69 50 51 52 53 54 55 56 57 58 59
70 60 61 62 63 64 65 66 67 68 69
71 70 71 72 73 74 75 76 77 78 79
72 80 81 82 83 84 85 86 87 88 89
73 90 91 92 93 94 95 96 97 98 99
74 100>;
75 default-brightness-level = <50>;
76 };
77
78 backlight1: backlight1 {
79 compatible = "pwm-backlight";
80 pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>;
81 power-supply = <&reg_lcd1_pwr>;
82 /*
83 * a poor man's way to create a 1:1 relationship between
84 * the PWM value and the actual duty cycle
85 */
86 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
87 10 11 12 13 14 15 16 17 18 19
88 20 21 22 23 24 25 26 27 28 29
89 30 31 32 33 34 35 36 37 38 39
90 40 41 42 43 44 45 46 47 48 49
91 50 51 52 53 54 55 56 57 58 59
92 60 61 62 63 64 65 66 67 68 69
93 70 71 72 73 74 75 76 77 78 79
94 80 81 82 83 84 85 86 87 88 89
95 90 91 92 93 94 95 96 97 98 99
96 100>;
97 default-brightness-level = <50>;
98 };
99};
100
101&can1 {
102 status = "disabled";
103};
104
105&can2 {
106 xceiver-supply = <&reg_3v3>;
107};
108
109&i2c3 {
110 polytouch1: eeti@4 {
111 compatible = "eeti,egalax_ts";
112 reg = <0x04>;
113 pinctrl-names = "default";
114 pinctrl-0 = <&pinctrl_eeti>;
115 interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_FALLING>;
116 wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
117 wakeup-source;
118 };
119};
120
121&kpp {
122 status = "disabled"; /* pads partially clash with backlight1 PWM */
123};
124
125&ldb {
126 status = "okay";
127
128 lvds0: lvds-channel@0 {
129 fsl,data-mapping = "spwg";
130 fsl,data-width = <18>;
131 status = "okay";
132
133 display-timings {
134 native-mode = <&lvds0_timing1>;
135
136 lvds0_timing0: hsd100pxn1 {
137 clock-frequency = <65000000>;
138 hactive = <1024>;
139 vactive = <768>;
140 hback-porch = <220>;
141 hfront-porch = <40>;
142 vback-porch = <21>;
143 vfront-porch = <7>;
144 hsync-len = <60>;
145 vsync-len = <10>;
146 hsync-active = <0>;
147 vsync-active = <0>;
148 de-active = <1>;
149 pixelclk-active = <1>;
150 };
151
152 lvds0_timing1: VGA {
153 clock-frequency = <25200000>;
154 hactive = <640>;
155 vactive = <480>;
156 hback-porch = <48>;
157 hfront-porch = <16>;
158 vback-porch = <31>;
159 vfront-porch = <12>;
160 hsync-len = <96>;
161 vsync-len = <2>;
162 hsync-active = <0>;
163 vsync-active = <0>;
164 de-active = <1>;
165 pixelclk-active = <0>;
166 };
167
168 lvds0_timing2: nl12880bc20 {
169 clock-frequency = <71000000>;
170 hactive = <1280>;
171 vactive = <800>;
172 hback-porch = <50>;
173 hfront-porch = <50>;
174 vback-porch = <5>;
175 vfront-porch = <5>;
176 hsync-len = <60>;
177 vsync-len = <13>;
178 hsync-active = <0>;
179 vsync-active = <0>;
180 de-active = <1>;
181 pixelclk-active = <1>;
182 };
183 };
184 };
185
186 lvds1: lvds-channel@1 {
187 fsl,data-mapping = "spwg";
188 fsl,data-width = <18>;
189 status = "okay";
190
191 display-timings {
192 native-mode = <&lvds1_timing2>;
193
194 lvds1_timing0: hsd100pxn1 {
195 clock-frequency = <65000000>;
196 hactive = <1024>;
197 vactive = <768>;
198 hback-porch = <220>;
199 hfront-porch = <40>;
200 vback-porch = <21>;
201 vfront-porch = <7>;
202 hsync-len = <60>;
203 vsync-len = <10>;
204 hsync-active = <0>;
205 vsync-active = <0>;
206 de-active = <1>;
207 pixelclk-active = <1>;
208 };
209
210 lvds1_timing1: VGA {
211 clock-frequency = <25200000>;
212 hactive = <640>;
213 vactive = <480>;
214 hback-porch = <48>;
215 hfront-porch = <16>;
216 vback-porch = <31>;
217 vfront-porch = <12>;
218 hsync-len = <96>;
219 vsync-len = <2>;
220 hsync-active = <0>;
221 vsync-active = <0>;
222 de-active = <1>;
223 pixelclk-active = <0>;
224 };
225
226 lvds1_timing2: nl12880bc20 {
227 clock-frequency = <71000000>;
228 hactive = <1280>;
229 vactive = <800>;
230 hback-porch = <50>;
231 hfront-porch = <50>;
232 vback-porch = <5>;
233 vfront-porch = <5>;
234 hsync-len = <60>;
235 vsync-len = <13>;
236 hsync-active = <0>;
237 vsync-active = <0>;
238 de-active = <1>;
239 pixelclk-active = <1>;
240 };
241 };
242 };
243};
244
245&pwm1 {
246 status = "okay";
247};
248
249&iomuxc {
250 pinctrl_eeti: eetigrp {
251 fsl,pins = <
252 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */
253 >;
254 };
255}; 48};
diff --git a/arch/arm/boot/dts/imx6dl-wandboard-revd1.dts b/arch/arm/boot/dts/imx6dl-wandboard-revd1.dts
new file mode 100644
index 000000000000..aa4d4faaaec4
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-wandboard-revd1.dts
@@ -0,0 +1,22 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11/dts-v1/;
12#include "imx6dl.dtsi"
13#include "imx6qdl-wandboard-revd1.dtsi"
14
15/ {
16 model = "Wandboard i.MX6 Dual Lite Board revD1";
17 compatible = "wand,imx6dl-wandboard", "fsl,imx6dl";
18
19 memory {
20 reg = <0x10000000 0x40000000>;
21 };
22};
diff --git a/arch/arm/boot/dts/imx6q-apalis-eval.dts b/arch/arm/boot/dts/imx6q-apalis-eval.dts
index 4bbfe3d61027..8b56656e53da 100644
--- a/arch/arm/boot/dts/imx6q-apalis-eval.dts
+++ b/arch/arm/boot/dts/imx6q-apalis-eval.dts
@@ -76,7 +76,7 @@
76 }; 76 };
77 }; 77 };
78 78
79 lcd_display: display@di0 { 79 lcd_display: disp0 {
80 compatible = "fsl,imx-parallel-display"; 80 compatible = "fsl,imx-parallel-display";
81 #address-cells = <1>; 81 #address-cells = <1>;
82 #size-cells = <0>; 82 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
index a35c7a54ad3b..27dc0fc686a9 100644
--- a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
+++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
@@ -77,7 +77,7 @@
77 }; 77 };
78 }; 78 };
79 79
80 lcd_display: display@di0 { 80 lcd_display: disp0 {
81 compatible = "fsl,imx-parallel-display"; 81 compatible = "fsl,imx-parallel-display";
82 #address-cells = <1>; 82 #address-cells = <1>;
83 #size-cells = <0>; 83 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora.dts b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
index 60d33e99de76..40b2c67fe7af 100644
--- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts
+++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
@@ -76,7 +76,7 @@
76 }; 76 };
77 }; 77 };
78 78
79 lcd_display: display@di0 { 79 lcd_display: disp0 {
80 compatible = "fsl,imx-parallel-display"; 80 compatible = "fsl,imx-parallel-display";
81 #address-cells = <1>; 81 #address-cells = <1>;
82 #size-cells = <0>; 82 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts
index fe6ab0aa34f9..bc7587c383f6 100644
--- a/arch/arm/boot/dts/imx6q-cm-fx6.dts
+++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts
@@ -77,8 +77,7 @@
77 regulator-name = "regulator-pcie-power-on-gpio"; 77 regulator-name = "regulator-pcie-power-on-gpio";
78 regulator-min-microvolt = <3300000>; 78 regulator-min-microvolt = <3300000>;
79 regulator-max-microvolt = <3300000>; 79 regulator-max-microvolt = <3300000>;
80 gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>; 80 gpio = <&gpio2 24 GPIO_ACTIVE_LOW>;
81 enable-active-high;
82 }; 81 };
83 82
84 reg_usb_h1_vbus: usb_h1_vbus { 83 reg_usb_h1_vbus: usb_h1_vbus {
@@ -362,7 +361,7 @@
362 pinctrl-names = "default"; 361 pinctrl-names = "default";
363 pinctrl-0 = <&pinctrl_pcie>; 362 pinctrl-0 = <&pinctrl_pcie>;
364 reset-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>; 363 reset-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>;
365 vdd-supply = <&reg_pcie_power_on_gpio>; 364 vpcie-supply = <&reg_pcie_power_on_gpio>;
366 status = "okay"; 365 status = "okay";
367}; 366};
368 367
diff --git a/arch/arm/boot/dts/imx6q-display5-tianma-tm070-1280x768.dts b/arch/arm/boot/dts/imx6q-display5-tianma-tm070-1280x768.dts
new file mode 100644
index 000000000000..16658b76fc4e
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-display5-tianma-tm070-1280x768.dts
@@ -0,0 +1,51 @@
1/*
2 * Copyright 2017
3 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without
12 * any warranty of any kind, whether express or implied.
13 *
14 * Or, alternatively,
15 *
16 * b) Permission is hereby granted, free of charge, to any person
17 * obtaining a copy of this software and associated documentation
18 * files (the "Software"), to deal in the Software without
19 * restriction, including without limitation the rights to use,
20 * copy, modify, merge, publish, distribute, sublicense, and/or
21 * sell copies of the Software, and to permit persons to whom the
22 * Software is furnished to do so, subject to the following
23 * conditions:
24 *
25 * The above copyright notice and this permission notice shall be
26 * included in all copies or substantial portions of the Software.
27 *
28 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
29 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
30 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
31 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
32 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
33 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
34 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
35 * OTHER DEALINGS IN THE SOFTWARE.
36 */
37
38/dts-v1/;
39
40#include "imx6q-display5.dtsi"
41
42&panel {
43 compatible = "tianma,tm070jdhg30";
44};
45
46&ldb {
47 lvds0: lvds-channel@0 {
48 fsl,data-mapping = "spwg";
49 fsl,data-width = <18>;
50 };
51};
diff --git a/arch/arm/boot/dts/imx6q-display5.dtsi b/arch/arm/boot/dts/imx6q-display5.dtsi
new file mode 100644
index 000000000000..4084de43d4d9
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-display5.dtsi
@@ -0,0 +1,596 @@
1/*
2 * Copyright 2017
3 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without
12 * any warranty of any kind, whether express or implied.
13 *
14 * Or, alternatively,
15 *
16 * b) Permission is hereby granted, free of charge, to any person
17 * obtaining a copy of this software and associated documentation
18 * files (the "Software"), to deal in the Software without
19 * restriction, including without limitation the rights to use,
20 * copy, modify, merge, publish, distribute, sublicense, and/or
21 * sell copies of the Software, and to permit persons to whom the
22 * Software is furnished to do so, subject to the following
23 * conditions:
24 *
25 * The above copyright notice and this permission notice shall be
26 * included in all copies or substantial portions of the Software.
27 *
28 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
29 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
30 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
31 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
32 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
33 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
34 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
35 * OTHER DEALINGS IN THE SOFTWARE.
36 */
37
38/dts-v1/;
39
40#include "imx6q.dtsi"
41
42#include <dt-bindings/gpio/gpio.h>
43#include <dt-bindings/pwm/pwm.h>
44#include <dt-bindings/sound/fsl-imx-audmux.h>
45
46/ {
47 model = "Liebherr (LWN) display5 i.MX6 Quad Board";
48 compatible = "lwn,display5", "fsl,imx6q";
49
50 memory {
51 reg = <0x10000000 0x40000000>;
52 };
53
54 backlight_lvds: backlight {
55 compatible = "pwm-backlight";
56 pinctrl-names = "default";
57 pinctrl-0 = <&pinctrl_backlight>;
58 pwms = <&pwm2 0 5000000 0>;
59 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
60 10 11 12 13 14 15 16 17 18 19
61 20 21 22 23 24 25 26 27 28 29
62 30 31 32 33 34 35 36 37 38 39
63 40 41 42 43 44 45 46 47 48 49
64 50 51 52 53 54 55 56 57 58 59
65 60 61 62 63 64 65 66 67 68 69
66 70 71 72 73 74 75 76 77 78 79
67 80 81 82 83 84 85 86 87 88 89
68 90 91 92 93 94 95 96 97 98 99
69 100 101 102 103 104 105 106 107 108 109
70 110 111 112 113 114 115 116 117 118 119
71 120 121 122 123 124 125 126 127 128 129
72 130 131 132 133 134 135 136 137 138 139
73 140 141 142 143 144 145 146 147 148 149
74 150 151 152 153 154 155 156 157 158 159
75 160 161 162 163 164 165 166 167 168 169
76 170 171 172 173 174 175 176 177 178 179
77 180 181 182 183 184 185 186 187 188 189
78 190 191 192 193 194 195 196 197 198 199
79 200 201 202 203 204 205 206 207 208 209
80 210 211 212 213 214 215 216 217 218 219
81 220 221 222 223 224 225 226 227 228 229
82 230 231 232 233 234 235 236 237 238 239
83 240 241 242 243 244 245 246 247 248 249
84 250 251 252 253 254 255>;
85 default-brightness-level = <250>;
86 enable-gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>;
87 };
88
89 reg_lvds: regulator-lvds {
90 compatible = "regulator-fixed";
91 regulator-name = "lvds_ppen";
92 regulator-min-microvolt = <3300000>;
93 regulator-max-microvolt = <3300000>;
94 regulator-boot-on;
95 regulator-always-on;
96 pinctrl-names = "default";
97 pinctrl-0 = <&pinctrl_reg_lvds>;
98 gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>;
99 enable-active-high;
100 };
101
102 reg_usbh1_vbus: usb-h1-vbus {
103 compatible = "regulator-fixed";
104 gpio = <&gpio3 31 GPIO_ACTIVE_LOW>;
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_usbh1_vbus>;
107 regulator-name = "usb_h1_vbus";
108 regulator-min-microvolt = <5000000>;
109 regulator-max-microvolt = <5000000>;
110 regulator-enable-ramp-delay = <300000>;
111 };
112
113 sound {
114 compatible = "simple-audio-card";
115 label = "tfa9879-mono";
116
117 simple-audio-card,dai-link {
118 /* DAC */
119 format = "i2s";
120 bitclock-master = <&dailink_master>;
121 frame-master = <&dailink_master>;
122
123 dailink_master: cpu {
124 sound-dai = <&ssi2>;
125 };
126 codec {
127 sound-dai = <&codec>;
128 };
129 };
130 };
131
132 panel: panel-lvds0 {
133 backlight = <&backlight_lvds>;
134 power-supply = <&reg_lvds>;
135
136 port {
137 panel_in_lvds0: endpoint {
138 remote-endpoint = <&lvds0_out>;
139 };
140 };
141 };
142};
143
144&audmux {
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_audmux>;
147 status = "okay";
148
149 ssi2 {
150 fsl,audmux-port = <1>;
151 fsl,port-config = <
152 (IMX_AUDMUX_V2_PTCR_SYN |
153 IMX_AUDMUX_V2_PTCR_TFSEL(5) |
154 IMX_AUDMUX_V2_PTCR_TCSEL(5) |
155 IMX_AUDMUX_V2_PTCR_TFSDIR |
156 IMX_AUDMUX_V2_PTCR_TCLKDIR)
157 IMX_AUDMUX_V2_PDCR_RXDSEL(5)
158 >;
159 };
160
161 aud6 {
162 fsl,audmux-port = <5>;
163 fsl,port-config = <
164 (IMX_AUDMUX_V2_PTCR_RFSEL(8) |
165 IMX_AUDMUX_V2_PTCR_RCSEL(8) |
166 IMX_AUDMUX_V2_PTCR_TFSEL(1) |
167 IMX_AUDMUX_V2_PTCR_TCSEL(1) |
168 IMX_AUDMUX_V2_PTCR_RFSDIR |
169 IMX_AUDMUX_V2_PTCR_RCLKDIR |
170 IMX_AUDMUX_V2_PTCR_TFSDIR |
171 IMX_AUDMUX_V2_PTCR_TCLKDIR)
172 IMX_AUDMUX_V2_PDCR_RXDSEL(1)
173 >;
174 };
175};
176
177&ecspi2 {
178 cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
179 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs &pinctrl_ecspi2_flwp>;
181 status = "okay";
182
183 s25fl256s: flash@0 {
184 #address-cells = <1>;
185 #size-cells = <1>;
186 compatible = "jedec,spi-nor";
187 spi-max-frequency = <40000000>;
188 reg = <0>;
189
190 partition@0 {
191 label = "SPL (spi)";
192 reg = <0x0 0x20000>;
193 read-only;
194 };
195 partition@1 {
196 label = "u-boot (spi)";
197 reg = <0x20000 0x100000>;
198 read-only;
199 };
200 partition@2 {
201 label = "uboot-env (spi)";
202 reg = <0x120000 0x10000>;
203 };
204 partition@3 {
205 label = "uboot-envr (spi)";
206 reg = <0x130000 0x10000>;
207 };
208 partition@4 {
209 label = "linux-recovery (spi)";
210 reg = <0x140000 0x800000>;
211 };
212 partition@5 {
213 label = "swupdate-fitImg (spi)";
214 reg = <0x940000 0x400000>;
215 };
216 partition@6 {
217 label = "swupdate-initramfs (spi)";
218 reg = <0xD40000 0x800000>;
219 };
220 };
221};
222
223&ecspi3 {
224 cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
225 pinctrl-names = "default";
226 pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs &pinctrl_ecspi3_flwp>;
227 status = "okay";
228};
229
230&fec {
231 pinctrl-names = "default";
232 pinctrl-0 = <&pinctrl_enet>;
233 phy-handle = <&ethernet_phy0>;
234 phy-mode = "rgmii-id";
235 status = "okay";
236
237 mdio {
238 #address-cells = <1>;
239 #size-cells = <0>;
240 ethernet_phy0: ethernet-phy@0 {
241 compatible = "marvell,88E1510";
242 device_type = "ethernet-phy";
243 /* Set LED0 control: */
244 /* On - Link, Blink - Activity, Off - No Link */
245 marvell,reg-init = <3 0x10 0 0x1011>;
246 max-speed = <100>;
247 reg = <0>;
248 };
249 };
250};
251
252&i2c1 {
253 clock-frequency = <400000>;
254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_i2c1>;
256 status = "okay";
257
258 codec: tfa9879@6C {
259 #sound-dai-cells = <0>;
260 compatible = "nxp,tfa9879";
261 reg = <0x6C>;
262 };
263};
264
265&i2c2 {
266 clock-frequency = <400000>;
267 pinctrl-names = "default";
268 pinctrl-0 = <&pinctrl_i2c2>;
269 status = "okay";
270};
271
272&i2c3 {
273 clock-frequency = <400000>;
274 pinctrl-names = "default";
275 pinctrl-0 = <&pinctrl_i2c3>;
276 status = "okay";
277
278 at24@50 {
279 compatible = "atmel,24c256";
280 pagesize = <64>;
281 reg = <0x50>;
282 };
283
284 pfuze100: pmic@8 {
285 compatible = "fsl,pfuze100";
286 reg = <0x08>;
287
288 regulators {
289 sw1a_reg: sw1ab {
290 regulator-min-microvolt = <300000>;
291 regulator-max-microvolt = <1875000>;
292 regulator-boot-on;
293 regulator-always-on;
294 regulator-ramp-delay = <6250>;
295 };
296
297 sw1c_reg: sw1c {
298 regulator-min-microvolt = <300000>;
299 regulator-max-microvolt = <1875000>;
300 regulator-boot-on;
301 regulator-always-on;
302 regulator-ramp-delay = <6250>;
303 };
304
305 sw2_reg: sw2 {
306 regulator-min-microvolt = <800000>;
307 regulator-max-microvolt = <3950000>;
308 regulator-boot-on;
309 regulator-always-on;
310 };
311
312 sw3a_reg: sw3a {
313 regulator-min-microvolt = <400000>;
314 regulator-max-microvolt = <1975000>;
315 regulator-boot-on;
316 regulator-always-on;
317 };
318
319 sw3b_reg: sw3b {
320 regulator-min-microvolt = <400000>;
321 regulator-max-microvolt = <1975000>;
322 regulator-boot-on;
323 regulator-always-on;
324 };
325
326 sw4_reg: sw4 {
327 regulator-min-microvolt = <800000>;
328 regulator-max-microvolt = <3300000>;
329 };
330
331 swbst_reg: swbst {
332 regulator-min-microvolt = <5000000>;
333 regulator-max-microvolt = <5150000>;
334 };
335
336 snvs_reg: vsnvs {
337 regulator-min-microvolt = <1000000>;
338 regulator-max-microvolt = <3000000>;
339 regulator-boot-on;
340 regulator-always-on;
341 };
342
343 vref_reg: vrefddr {
344 regulator-boot-on;
345 regulator-always-on;
346 };
347
348 vgen1_reg: vgen1 {
349 regulator-min-microvolt = <800000>;
350 regulator-max-microvolt = <1550000>;
351 };
352
353 vgen2_reg: vgen2 {
354 regulator-min-microvolt = <800000>;
355 regulator-max-microvolt = <1550000>;
356 };
357
358 vgen3_reg: vgen3 {
359 regulator-min-microvolt = <1800000>;
360 regulator-max-microvolt = <3300000>;
361 };
362
363 vgen4_reg: vgen4 {
364 regulator-min-microvolt = <1800000>;
365 regulator-max-microvolt = <3300000>;
366 regulator-always-on;
367 };
368
369 vgen5_reg: vgen5 {
370 regulator-min-microvolt = <1800000>;
371 regulator-max-microvolt = <3300000>;
372 regulator-always-on;
373 };
374
375 vgen6_reg: vgen6 {
376 regulator-min-microvolt = <1800000>;
377 regulator-max-microvolt = <3300000>;
378 regulator-always-on;
379 };
380 };
381 };
382};
383
384&ldb {
385 status = "okay";
386
387 lvds0: lvds-channel@0 {
388 status = "okay";
389
390 port@4 {
391 reg = <4>;
392
393 lvds0_out: endpoint {
394 remote-endpoint = <&panel_in_lvds0>;
395 };
396 };
397 };
398};
399
400&pwm2 {
401 #pwm-cells = <3>;
402 pinctrl-names = "default";
403 pinctrl-0 = <&pinctrl_pwm2>;
404 status = "okay";
405};
406
407&ssi2 {
408 status = "okay";
409};
410
411&uart4 {
412 pinctrl-names = "default";
413 pinctrl-0 = <&pinctrl_uart4>;
414 uart-has-rtscts;
415 status = "okay";
416};
417
418&uart5 {
419 pinctrl-names = "default";
420 pinctrl-0 = <&pinctrl_uart5>;
421 status = "okay";
422};
423
424&usbh1 {
425 vbus-supply = <&reg_usbh1_vbus>;
426 pinctrl-0 = <&pinctrl_usbh1>;
427 status = "okay";
428};
429
430&usdhc4 {
431 pinctrl-names = "default";
432 pinctrl-0 = <&pinctrl_usdhc4>;
433 bus-width = <8>;
434 non-removable;
435 status = "okay";
436};
437
438&iomuxc {
439 pinctrl_audmux: audmuxgrp {
440 fsl,pins = <
441 /* I2S OUTPUT AUD6*/
442 MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0
443 MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0
444 MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0
445 MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0
446 >;
447 };
448
449 pinctrl_backlight: dispgrp {
450 fsl,pins = <
451 /* BLEN_OUT */
452 MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b0
453 >;
454 };
455
456 pinctrl_ecspi2: ecspi2grp {
457 fsl,pins = <
458 MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1
459 MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1
460 MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1
461 >;
462 };
463
464 pinctrl_ecspi2_cs: ecspi2csgrp {
465 fsl,pins = <
466 MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1
467 >;
468 };
469
470 pinctrl_ecspi2_flwp: ecspi2flwpgrp {
471 fsl,pins = <
472 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0
473 >;
474 };
475
476 pinctrl_ecspi3: ecspi3grp {
477 fsl,pins = <
478 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
479 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
480 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
481 >;
482 };
483
484 pinctrl_ecspi3_cs: ecspi3csgrp {
485 fsl,pins = <
486 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b0
487 >;
488 };
489
490 pinctrl_ecspi3_flwp: ecspi3flwpgrp {
491 fsl,pins = <
492 MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0
493 >;
494 };
495
496 pinctrl_enet: enetgrp {
497 fsl,pins = <
498 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
499 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
500 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
501 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
502 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
503 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
504 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
505 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
506 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
507 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
508 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
509 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
510 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
511 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
512 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
513 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
514 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
515 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0
516 >;
517 };
518
519 pinctrl_i2c1: i2c1grp {
520 fsl,pins = <
521 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
522 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
523 >;
524 };
525
526 pinctrl_i2c2: i2c2grp {
527 fsl,pins = <
528 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
529 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
530 >;
531 };
532
533 pinctrl_i2c3: i2c3grp {
534 fsl,pins = <
535 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
536 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
537 >;
538 };
539
540 pinctrl_pwm2: pwm2grp {
541 fsl,pins = <
542 MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1
543 >;
544 };
545
546 pinctrl_reg_lvds: reqlvdsgrp {
547 fsl,pins = <
548 /* LVDS_PPEN_OUT */
549 MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0
550 >;
551 };
552
553 pinctrl_uart4: uart4grp {
554 fsl,pins = <
555 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
556 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
557 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
558 MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
559 >;
560 };
561
562 pinctrl_uart5: uart5grp {
563 fsl,pins = <
564 MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
565 MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
566 >;
567 };
568
569 pinctrl_usbh1: usbh1grp {
570 fsl,pins = <
571 MX6QDL_PAD_EIM_D30__USB_H1_OC 0x030b0
572 >;
573 };
574
575 pinctrl_usbh1_vbus: usbh1_vbus_grp {
576 fsl,pins = <
577 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0
578 >;
579 };
580
581 pinctrl_usdhc4: usdhc4grp {
582 fsl,pins = <
583 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
584 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
585 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
586 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
587 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
588 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
589 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
590 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
591 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
592 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
593 MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x17059
594 >;
595 };
596};
diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts
index 9573e5cb003d..29adaa7c72f8 100644
--- a/arch/arm/boot/dts/imx6q-gw5400-a.dts
+++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts
@@ -392,127 +392,124 @@
392}; 392};
393 393
394&iomuxc { 394&iomuxc {
395 imx6q-gw5400-a { 395 pinctrl_audmux: audmuxgrp {
396 396 fsl,pins = <
397 pinctrl_audmux: audmuxgrp { 397 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
398 fsl,pins = < 398 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
399 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 399 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
400 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 400 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
401 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 401 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
402 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 402 >;
403 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ 403 };
404 >;
405 };
406 404
407 pinctrl_ecspi1: ecspi1grp { 405 pinctrl_ecspi1: ecspi1grp {
408 fsl,pins = < 406 fsl,pins = <
409 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 407 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
410 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 408 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
411 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 409 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
412 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 /* SPINOR_CS0# */ 410 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 /* SPINOR_CS0# */
413 >; 411 >;
414 }; 412 };
415 413
416 pinctrl_enet: enetgrp { 414 pinctrl_enet: enetgrp {
417 fsl,pins = < 415 fsl,pins = <
418 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 416 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
419 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 417 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
420 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 418 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
421 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 419 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
422 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 420 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
423 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 421 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
424 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 422 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
425 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 423 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
426 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 424 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
427 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 425 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
428 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 426 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
429 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 427 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
430 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 428 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
431 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 429 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
432 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 430 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
433 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 431 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
434 >; 432 >;
435 }; 433 };
436 434
437 pinctrl_gpio_leds: gpioledsgrp { 435 pinctrl_gpio_leds: gpioledsgrp {
438 fsl,pins = < 436 fsl,pins = <
439 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 /* user1 led */ 437 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 /* user1 led */
440 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /* user2 led */ 438 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /* user2 led */
441 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 /* user3 led */ 439 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 /* user3 led */
442 >; 440 >;
443 }; 441 };
444 442
445 pinctrl_i2c1: i2c1grp { 443 pinctrl_i2c1: i2c1grp {
446 fsl,pins = < 444 fsl,pins = <
447 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 445 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
448 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 446 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
449 >; 447 >;
450 }; 448 };
451 449
452 pinctrl_i2c2: i2c2grp { 450 pinctrl_i2c2: i2c2grp {
453 fsl,pins = < 451 fsl,pins = <
454 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 452 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
455 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 453 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
456 >; 454 >;
457 }; 455 };
458 456
459 pinctrl_i2c3: i2c3grp { 457 pinctrl_i2c3: i2c3grp {
460 fsl,pins = < 458 fsl,pins = <
461 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 459 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
462 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 460 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
463 >; 461 >;
464 }; 462 };
465 463
466 pinctrl_pcie: pciegrp { 464 pinctrl_pcie: pciegrp {
467 fsl,pins = < 465 fsl,pins = <
468 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ 466 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
469 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ 467 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
470 >; 468 >;
471 }; 469 };
472 470
473 pinctrl_pps: ppsgrp { 471 pinctrl_pps: ppsgrp {
474 fsl,pins = < 472 fsl,pins = <
475 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 /* GPS_PPS */ 473 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 /* GPS_PPS */
476 >; 474 >;
477 }; 475 };
478 476
479 pinctrl_uart1: uart1grp { 477 pinctrl_uart1: uart1grp {
480 fsl,pins = < 478 fsl,pins = <
481 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 479 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
482 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 480 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
483 >; 481 >;
484 }; 482 };
485 483
486 pinctrl_uart2: uart2grp { 484 pinctrl_uart2: uart2grp {
487 fsl,pins = < 485 fsl,pins = <
488 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 486 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
489 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 487 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
490 >; 488 >;
491 }; 489 };
492 490
493 pinctrl_uart5: uart5grp { 491 pinctrl_uart5: uart5grp {
494 fsl,pins = < 492 fsl,pins = <
495 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 493 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
496 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 494 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
497 >; 495 >;
498 }; 496 };
499 497
500 pinctrl_usbotg: usbotggrp { 498 pinctrl_usbotg: usbotggrp {
501 fsl,pins = < 499 fsl,pins = <
502 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 500 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
503 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ 501 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
504 >; 502 >;
505 }; 503 };
506 504
507 pinctrl_usdhc3: usdhc3grp { 505 pinctrl_usdhc3: usdhc3grp {
508 fsl,pins = < 506 fsl,pins = <
509 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 507 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
510 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 508 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
511 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 509 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
512 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 510 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
513 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 511 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
514 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 512 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
515 >; 513 >;
516 };
517 }; 514 };
518}; 515};
diff --git a/arch/arm/boot/dts/imx6q-icore-rqs.dts b/arch/arm/boot/dts/imx6q-icore-rqs.dts
index 745bc2886a47..b81f48c6a8c6 100644
--- a/arch/arm/boot/dts/imx6q-icore-rqs.dts
+++ b/arch/arm/boot/dts/imx6q-icore-rqs.dts
@@ -47,30 +47,6 @@
47/ { 47/ {
48 model = "Engicam i.CoreM6 Quad/Dual RQS Starter Kit"; 48 model = "Engicam i.CoreM6 Quad/Dual RQS Starter Kit";
49 compatible = "engicam,imx6-icore-rqs", "fsl,imx6q"; 49 compatible = "engicam,imx6-icore-rqs", "fsl,imx6q";
50
51 sound {
52 compatible = "fsl,imx-audio-sgtl5000";
53 model = "imx-audio-sgtl5000";
54 ssi-controller = <&ssi1>;
55 audio-codec = <&codec>;
56 audio-routing =
57 "MIC_IN", "Mic Jack",
58 "Mic Jack", "Mic Bias",
59 "Headphone Jack", "HP_OUT";
60 mux-int-port = <1>;
61 mux-ext-port = <4>;
62 };
63};
64
65&i2c3 {
66 codec: sgtl5000@a {
67 compatible = "fsl,sgtl5000";
68 reg = <0x0a>;
69 clocks = <&clks IMX6QDL_CLK_CKO>;
70 VDDA-supply = <&reg_2p5v>;
71 VDDIO-supply = <&reg_3p3v>;
72 VDDD-supply = <&reg_1p8v>;
73 };
74}; 50};
75 51
76&sata { 52&sata {
diff --git a/arch/arm/boot/dts/imx6q-novena.dts b/arch/arm/boot/dts/imx6q-novena.dts
index c130894951ee..7d7dc59507cf 100644
--- a/arch/arm/boot/dts/imx6q-novena.dts
+++ b/arch/arm/boot/dts/imx6q-novena.dts
@@ -158,7 +158,6 @@
158 regulator-max-microvolt = <1500000>; 158 regulator-max-microvolt = <1500000>;
159 gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; 159 gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
160 enable-active-high; 160 enable-active-high;
161 regulator-always-on;
162 }; 161 };
163 162
164 reg_sata: regulator-sata { 163 reg_sata: regulator-sata {
@@ -447,6 +446,7 @@
447 pinctrl-names = "default"; 446 pinctrl-names = "default";
448 pinctrl-0 = <&pinctrl_pcie_novena>; 447 pinctrl-0 = <&pinctrl_pcie_novena>;
449 reset-gpio = <&gpio3 29 GPIO_ACTIVE_LOW>; 448 reset-gpio = <&gpio3 29 GPIO_ACTIVE_LOW>;
449 vpcie-supply = <&reg_pcie>;
450 status = "okay"; 450 status = "okay";
451}; 451};
452 452
diff --git a/arch/arm/boot/dts/imx6q-pistachio.dts b/arch/arm/boot/dts/imx6q-pistachio.dts
new file mode 100644
index 000000000000..1effb58f304c
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-pistachio.dts
@@ -0,0 +1,693 @@
1/*
2 * Copyright (C) 2017 NutsBoard.Org
3 *
4 * Author: Wig Cheng <onlywig@gmail.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45/dts-v1/;
46
47#include <dt-bindings/gpio/gpio.h>
48#include <dt-bindings/input/input.h>
49#include "imx6q.dtsi"
50
51/ {
52 model = "NutsBoard i.MX6 Quad Pistachio board";
53 compatible = "nutsboard,imx6q-pistachio", "fsl,imx6q";
54
55 chosen {
56 stdout-path = &uart4;
57 };
58
59 memory: memory {
60 reg = <0x10000000 0x80000000>;
61 };
62
63 reg_3p3v: regulator-3p3v {
64 compatible = "regulator-fixed";
65 regulator-name = "3P3V";
66 regulator-min-microvolt = <3300000>;
67 regulator-max-microvolt = <3300000>;
68 };
69
70 reg_1p8v: regulator-1p8v {
71 compatible = "regulator-fixed";
72 regulator-name = "1P8V";
73 regulator-min-microvolt = <1800000>;
74 regulator-max-microvolt = <1800000>;
75 };
76
77 wlan_en_reg: regulator-wlan_en {
78 compatible = "regulator-fixed";
79 regulator-name = "wlan-en-regulator";
80 regulator-min-microvolt = <1800000>;
81 regulator-max-microvolt = <1800000>;
82 gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>;
83 startup-delay-us = <70000>;
84 enable-active-high;
85 };
86
87 reg_usb_otg_vbus: regulator-usb_vbus {
88 compatible = "regulator-fixed";
89 regulator-name = "usb_otg_vbus";
90 regulator-min-microvolt = <5000000>;
91 regulator-max-microvolt = <5000000>;
92 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
93 enable-active-high;
94 vin-supply = <&swbst_reg>;
95 };
96
97 gpio-keys {
98 compatible = "gpio-keys";
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_gpio_keys>;
101
102 power {
103 label = "Power Button";
104 gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
105 gpio-key,wakeup;
106 linux,code = <KEY_POWER>;
107 };
108 };
109
110 sound {
111 compatible = "fsl,imx-sgtl5000",
112 "fsl,imx-audio-sgtl5000";
113 model = "audio-sgtl5000";
114 ssi-controller = <&ssi1>;
115 audio-codec = <&codec>;
116 audio-routing =
117 "MIC_IN", "Mic Jack",
118 "Mic Jack", "Mic Bias",
119 "Headphone Jack", "HP_OUT";
120 mux-int-port = <1>;
121 mux-ext-port = <3>;
122 };
123
124 backlight_lvds: backlight-lvds {
125 compatible = "pwm-backlight";
126 pwms = <&pwm1 0 50000>;
127 brightness-levels = <
128 0 /*1 2 3 4 5 6*/ 7 8 9
129 10 11 12 13 14 15 16 17 18 19
130 20 21 22 23 24 25 26 27 28 29
131 30 31 32 33 34 35 36 37 38 39
132 40 41 42 43 44 45 46 47 48 49
133 50 51 52 53 54 55 56 57 58 59
134 60 61 62 63 64 65 66 67 68 69
135 70 71 72 73 74 75 76 77 78 79
136 80 81 82 83 84 85 86 87 88 89
137 90 91 92 93 94 95 96 97 98 99
138 100
139 >;
140 default-brightness-level = <94>;
141 status = "okay";
142 };
143
144 panel {
145 compatible = "hannstar,hsd100pxn1";
146 backlight = <&backlight_lvds>;
147
148 port {
149 panel_in: endpoint {
150 remote-endpoint = <&lvds0_out>;
151 };
152 };
153 };
154};
155
156&audmux {
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_audmux>;
159 status = "okay";
160};
161
162&can2 {
163 pinctrl-names = "default";
164 pinctrl-0 = <&pinctrl_flexcan2>;
165 status = "okay";
166};
167
168&clks {
169 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
170 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
171 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
172 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
173};
174
175&fec {
176 pinctrl-names = "default";
177 pinctrl-0 = <&pinctrl_enet>;
178 phy-mode = "rgmii";
179 status = "okay";
180};
181
182&hdmi {
183 ddc-i2c-bus = <&i2c2>;
184 status = "okay";
185};
186
187&i2c1 {
188 clock-frequency = <100000>;
189 pinctrl-names = "default";
190 pinctrl-0 = <&pinctrl_i2c1>;
191 status = "okay";
192
193 codec: sgtl5000@a {
194 compatible = "fsl,sgtl5000";
195 pinctrl-names = "default";
196 pinctrl-0 = <&pinctrl_i2c1_sgtl5000>;
197 reg = <0x0a>;
198 clocks = <&clks IMX6QDL_CLK_CKO>;
199 VDDA-supply = <&reg_1p8v>;
200 VDDIO-supply = <&reg_1p8v>;
201 };
202};
203
204&i2c2 {
205 clock-frequency = <100000>;
206 pinctrl-names = "default";
207 pinctrl-0 = <&pinctrl_i2c2>;
208 status = "okay";
209
210 pmic: pfuze100@8 {
211 compatible = "fsl,pfuze100";
212 reg = <0x08>;
213
214 regulators {
215 sw1a_reg: sw1ab {
216 regulator-min-microvolt = <300000>;
217 regulator-max-microvolt = <1875000>;
218 regulator-boot-on;
219 regulator-always-on;
220 regulator-ramp-delay = <6250>;
221 };
222
223 sw1c_reg: sw1c {
224 regulator-min-microvolt = <300000>;
225 regulator-max-microvolt = <1875000>;
226 regulator-boot-on;
227 regulator-always-on;
228 regulator-ramp-delay = <6250>;
229 };
230
231 sw2_reg: sw2 {
232 regulator-min-microvolt = <800000>;
233 regulator-max-microvolt = <3300000>;
234 regulator-boot-on;
235 regulator-always-on;
236 regulator-ramp-delay = <6250>;
237 };
238
239 sw3a_reg: sw3a {
240 regulator-min-microvolt = <400000>;
241 regulator-max-microvolt = <1975000>;
242 regulator-boot-on;
243 regulator-always-on;
244 };
245
246 sw3b_reg: sw3b {
247 regulator-min-microvolt = <400000>;
248 regulator-max-microvolt = <1975000>;
249 regulator-boot-on;
250 regulator-always-on;
251 };
252
253 sw4_reg: sw4 {
254 regulator-min-microvolt = <800000>;
255 regulator-max-microvolt = <3300000>;
256 };
257
258 swbst_reg: swbst {
259 regulator-min-microvolt = <5000000>;
260 regulator-max-microvolt = <5150000>;
261 };
262
263 snvs_reg: vsnvs {
264 regulator-min-microvolt = <1000000>;
265 regulator-max-microvolt = <3000000>;
266 regulator-boot-on;
267 regulator-always-on;
268 };
269
270 vref_reg: vrefddr {
271 regulator-boot-on;
272 regulator-always-on;
273 };
274
275 vgen1_reg: vgen1 {
276 regulator-min-microvolt = <800000>;
277 regulator-max-microvolt = <1550000>;
278 };
279
280 vgen2_reg: vgen2 {
281 regulator-min-microvolt = <800000>;
282 regulator-max-microvolt = <1550000>;
283 };
284
285 vgen3_reg: vgen3 {
286 regulator-min-microvolt = <1800000>;
287 regulator-max-microvolt = <3300000>;
288 };
289
290 vgen4_reg: vgen4 {
291 regulator-min-microvolt = <1800000>;
292 regulator-max-microvolt = <3300000>;
293 regulator-always-on;
294 };
295
296 vgen5_reg: vgen5 {
297 regulator-min-microvolt = <1800000>;
298 regulator-max-microvolt = <3300000>;
299 regulator-always-on;
300 };
301 vgen6_reg: vgen6 {
302 regulator-min-microvolt = <1800000>;
303 regulator-max-microvolt = <3300000>;
304 regulator-always-on;
305 };
306 };
307 };
308
309 ar1021@4d {
310 compatible = "microchip,ar1021-i2c";
311 reg = <0x4d>;
312 interrupt-parent = <&gpio6>;
313 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
314 };
315};
316
317&i2c3 {
318 clock-frequency = <100000>;
319 pinctrl-names = "default";
320 pinctrl-0 = <&pinctrl_i2c3>;
321 status = "okay";
322};
323
324&iomuxc {
325 pinctrl-names = "default";
326
327 pinctrl_hog: hoggrp {
328 fsl,pins = <
329 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /*pcie power*/
330 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 /*LCD power*/
331 MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x1b0b0 /*backlight power*/
332 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1 /*SD3 CD pin*/
333 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /*codec power*/
334 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /*touch reset*/
335 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b01 /*touch irq*/
336 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0/*backlight pwr*/
337 MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0 /*gpio 5V_1*/
338 MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0 /*gpio 5V_2*/
339 MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 /*gpio 5V_3*/
340 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 /*gpio 5V_4*/
341 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 /*AUX_5V_EN*/
342 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0 /*AUX_5VB_EN*/
343 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0 /*AUX_3V3_EN*/
344 MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x1b0b0 /*I2C expander pwr*/
345 >;
346 };
347
348 pinctrl_audmux: audmuxgrp {
349 fsl,pins = <
350 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
351 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
352 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
353 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
354 >;
355 };
356
357 pinctrl_ecspi1: ecspi1grp {
358 fsl,pins = <
359 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
360 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
361 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
362 MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
363 >;
364 };
365
366 pinctrl_enet: enetgrp {
367 fsl,pins = <
368 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0
369 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
370 /* AR8035 reset */
371 MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x130b0
372 /* AR8035 interrupt */
373 MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b1
374 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
375 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
376 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
377 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
378 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
379 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
380 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
381 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1
382 /* AR8035 pin strapping: IO voltage: pull up */
383 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
384 /* AR8035 pin strapping: PHYADDR#0: pull down */
385 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030
386 /* AR8035 pin strapping: PHYADDR#1: pull down */
387 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
388 /* AR8035 pin strapping: MODE#1: pull up */
389 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
390 /* AR8035 pin strapping: MODE#3: pull up */
391 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
392 /* AR8035 pin strapping: MODE#0: pull down */
393 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
394 >;
395 };
396
397 pinctrl_flexcan2: flexcan2grp {
398 fsl,pins = <
399 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
400 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
401 >;
402 };
403
404 pinctrl_gpio_keys: gpio_keysgrp {
405 fsl,pins = <
406 MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0
407 >;
408 };
409
410 pinctrl_hdmi_cec: hdmicecgrp {
411 fsl,pins = <
412 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x108b0
413 >;
414 };
415
416 pinctrl_i2c1: i2c1grp {
417 fsl,pins = <
418 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
419 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
420 >;
421 };
422
423 pinctrl_i2c2: i2c2grp {
424 fsl,pins = <
425 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
426 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
427 >;
428 };
429
430 pinctrl_i2c3: i2c3grp {
431 fsl,pins = <
432 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
433 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
434 >;
435 };
436
437 pinctrl_i2c1_sgtl5000: i2c1-sgtl5000grp {
438 fsl,pins = <
439 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* sys_mclk */
440 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x130b0 /*headphone det*/
441 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x130b0 /*microphone det*/
442 >;
443 };
444
445 pinctrl_pwm1: pwm1grp {
446 fsl,pins = <
447 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
448 >;
449 };
450
451 pinctrl_uart1: uart1grp {
452 fsl,pins = <
453 MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
454 MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
455 MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
456 MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
457 MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
458 MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
459 MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
460 >;
461 };
462
463 pinctrl_uart2: uart2grp {
464 fsl,pins = <
465 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
466 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
467 MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x1b0b1
468 MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x1b0b1
469 >;
470 };
471
472 pinctrl_uart3: uart3grp {
473 fsl,pins = <
474 MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
475 MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
476 MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
477 MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
478 >;
479 };
480
481 pinctrl_uart4: uart4grp {
482 fsl,pins = <
483 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
484 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
485 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
486 MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
487 >;
488 };
489
490 pinctrl_uart5: uart5grp {
491 fsl,pins = <
492 MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
493 MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
494 MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1
495 MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x1b0b1
496 MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x15059 /*BT_EN*/
497 >;
498 };
499
500 pinctrl_usbotg: usbotggrp {
501 fsl,pins = <
502 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
503 >;
504 };
505
506 pinctrl_usdhc1: usdhc1grp {
507 fsl,pins = <
508 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
509 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
510 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
511 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
512 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
513 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
514 MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059
515 MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059
516 MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059
517 MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059
518 >;
519 };
520
521 pinctrl_usdhc2: usdhc2grp {
522 fsl,pins = <
523 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
524 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
525 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
526 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
527 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
528 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
529 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x15059 /*WL_EN_LDO*/
530 MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x15059 /*WL_EN*/
531 MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x15059 /*WL_IRQ*/
532 >;
533 };
534
535 pinctrl_usdhc3: usdhc3grp {
536 fsl,pins = <
537 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17071
538 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071
539 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17071
540 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17071
541 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17071
542 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17071
543 >;
544 };
545
546 pinctrl_wdog: wdoggrp {
547 fsl,pins = <
548 MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b00
549 >;
550 };
551};
552
553&ldb {
554 status = "okay";
555
556 lvds-channel@1 {
557 fsl,data-mapping = "spwg";
558 fsl,data-width = <18>;
559 status = "okay";
560
561 port@4 {
562 reg = <4>;
563
564 lvds0_out: endpoint {
565 remote-endpoint = <&panel_in>;
566 };
567 };
568 };
569};
570
571&pwm1 {
572 pinctrl-names = "default";
573 pinctrl-0 = <&pinctrl_pwm1>;
574 status = "okay";
575};
576
577&snvs_poweroff {
578 status = "okay";
579};
580
581&ssi1 {
582 status = "okay";
583};
584
585&uart1 {
586 pinctrl-names = "default";
587 pinctrl-0 = <&pinctrl_uart1>;
588 uart-has-rtscts;
589 fsl,dte-mode;
590 status = "okay";
591};
592
593&uart2 {
594 pinctrl-names = "default";
595 pinctrl-0 = <&pinctrl_uart2>;
596 uart-has-rtscts;
597 status = "okay";
598};
599
600&uart3 {
601 pinctrl-names = "default";
602 pinctrl-0 = <&pinctrl_uart3>;
603 uart-has-rtscts;
604 status = "okay";
605};
606
607&uart4 {
608 pinctrl-names = "default";
609 pinctrl-0 = <&pinctrl_uart4>;
610 uart-has-rtscts;
611 status = "okay";
612};
613
614&uart5 {
615 pinctrl-names = "default";
616 pinctrl-0 = <&pinctrl_uart5>;
617 fsl,uart-has-rtscts;
618 status = "okay";
619};
620
621&usbotg {
622 vbus-supply = <&reg_usb_otg_vbus>;
623 pinctrl-names = "default";
624 pinctrl-0 = <&pinctrl_usbotg>;
625 disable-over-current;
626 srp-disable;
627 hnp-disable;
628 adp-disable;
629 status = "okay";
630};
631
632&usbh1 {
633 status = "okay";
634};
635
636&usbphy1 {
637 fsl,tx-d-cal = <0x5>;
638};
639
640&usbphy2 {
641 fsl,tx-d-cal = <0x5>;
642};
643
644&usdhc1 {
645 pinctrl-names = "default";
646 pinctrl-0 = <&pinctrl_usdhc1>;
647 bus-width = <8>;
648 keep-power-in-suspend;
649 vmmc-supply = <&reg_3p3v>;
650 status = "okay";
651};
652
653&usdhc2 {
654 pinctrl-names = "default";
655 pinctrl-0 = <&pinctrl_usdhc2>;
656 bus-width = <4>;
657 vmmc-supply = <&wlan_en_reg>;
658 no-1-8-v;
659 keep-power-in-suspend;
660 non-removable;
661 cap-power-off-card;
662 status = "okay";
663
664 #address-cells = <1>;
665 #size-cells = <0>;
666 wlcore: wlcore@2 {
667 compatible = "ti,wl1835";
668 reg = <2>;
669 interrupt-parent = <&gpio5>;
670 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
671 ref-clock-frequency = <38400000>;
672 tcxo-clock-frequency = <26000000>;
673 };
674};
675
676&usdhc3 {
677 pinctrl-names = "default";
678 pinctrl-0 = <&pinctrl_usdhc3>;
679 bus-width = <4>;
680 cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
681 no-1-8-v;
682 keep-power-in-suspend;
683 wakeup-source;
684 status = "okay";
685};
686
687&sata {
688 status = "okay";
689};
690
691&wdog1 {
692 status = "okay";
693};
diff --git a/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts b/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts
index 71746edc2ee9..ac3050a835e5 100644
--- a/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts
+++ b/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> 2 * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de>
3 * 3 *
4 * This file is dual-licensed: you can use it either under the terms 4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual 5 * of the GPL or the X11 license, at your option. Note that this dual
@@ -42,70 +42,16 @@
42/dts-v1/; 42/dts-v1/;
43#include "imx6q.dtsi" 43#include "imx6q.dtsi"
44#include "imx6qdl-tx6.dtsi" 44#include "imx6qdl-tx6.dtsi"
45#include "imx6qdl-tx6-lcd.dtsi"
45 46
46/ { 47/ {
47 model = "Ka-Ro electronics TX6Q-1010 Module on CoMpact TFT"; 48 model = "Ka-Ro electronics TX6Q-1010 Module on CoMpact TFT";
48 compatible = "karo,imx6q-tx6q", "fsl,imx6q"; 49 compatible = "karo,imx6q-tx6q", "fsl,imx6q";
50};
49 51
50 aliases { 52&backlight {
51 display = &display; 53 pwms = <&pwm2 0 500000 0>;
52 }; 54 /delete-property/ turn-on-delay-ms;
53
54 backlight: backlight {
55 compatible = "pwm-backlight";
56 pwms = <&pwm2 0 500000 0>;
57 power-supply = <&reg_3v3>;
58 /*
59 * a poor man's way to create a 1:1 relationship between
60 * the PWM value and the actual duty cycle
61 */
62 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
63 10 11 12 13 14 15 16 17 18 19
64 20 21 22 23 24 25 26 27 28 29
65 30 31 32 33 34 35 36 37 38 39
66 40 41 42 43 44 45 46 47 48 49
67 50 51 52 53 54 55 56 57 58 59
68 60 61 62 63 64 65 66 67 68 69
69 70 71 72 73 74 75 76 77 78 79
70 80 81 82 83 84 85 86 87 88 89
71 90 91 92 93 94 95 96 97 98 99
72 100>;
73 default-brightness-level = <50>;
74 };
75
76 display: display@di0 {
77 compatible = "fsl,imx-parallel-display";
78 interface-pix-fmt = "rgb24";
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_disp0_1>;
81 status = "okay";
82
83 port {
84 display0_in: endpoint {
85 remote-endpoint = <&ipu1_di0_disp0>;
86 };
87 };
88
89 display-timings {
90 native-mode = <&ET070001DM6>;
91
92 ET070001DM6: CoMTFT { /* same as ET0700 but with inverted pixel clock */
93 clock-frequency = <33264000>;
94 hactive = <800>;
95 vactive = <480>;
96 hback-porch = <88>;
97 hsync-len = <128>;
98 hfront-porch = <40>;
99 vback-porch = <33>;
100 vsync-len = <2>;
101 vfront-porch = <10>;
102 hsync-active = <0>;
103 vsync-active = <0>;
104 de-active = <1>;
105 pixelclk-active = <1>;
106 };
107 };
108 };
109}; 55};
110 56
111&can1 { 57&can1 {
@@ -116,14 +62,14 @@
116 xceiver-supply = <&reg_3v3>; 62 xceiver-supply = <&reg_3v3>;
117}; 63};
118 64
119&ipu1_di0_disp0 {
120 remote-endpoint = <&display0_in>;
121};
122
123&kpp { 65&kpp {
124 status = "disabled"; 66 status = "disabled";
125}; 67};
126 68
69&lcd_panel {
70 compatible = "edt,etm0700g0edh6";
71};
72
127&reg_can_xcvr { 73&reg_can_xcvr {
128 status = "disabled"; 74 status = "disabled";
129}; 75};
diff --git a/arch/arm/boot/dts/imx6q-tx6q-1010.dts b/arch/arm/boot/dts/imx6q-tx6q-1010.dts
index f9cd21a41a79..4ee860b626ff 100644
--- a/arch/arm/boot/dts/imx6q-tx6q-1010.dts
+++ b/arch/arm/boot/dts/imx6q-tx6q-1010.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> 2 * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de>
3 * 3 *
4 * This file is dual-licensed: you can use it either under the terms 4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual 5 * of the GPL or the X11 license, at your option. Note that this dual
@@ -42,166 +42,13 @@
42/dts-v1/; 42/dts-v1/;
43#include "imx6q.dtsi" 43#include "imx6q.dtsi"
44#include "imx6qdl-tx6.dtsi" 44#include "imx6qdl-tx6.dtsi"
45#include "imx6qdl-tx6-lcd.dtsi"
45 46
46/ { 47/ {
47 model = "Ka-Ro electronics TX6Q-1010 Module"; 48 model = "Ka-Ro electronics TX6Q-1010/-1030 Module";
48 compatible = "karo,imx6q-tx6q", "fsl,imx6q"; 49 compatible = "karo,imx6q-tx6q", "fsl,imx6q";
49
50 aliases {
51 display = &display;
52 };
53
54 backlight: backlight {
55 compatible = "pwm-backlight";
56 pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
57 power-supply = <&reg_3v3>;
58 /*
59 * a poor man's way to create a 1:1 relationship between
60 * the PWM value and the actual duty cycle
61 */
62 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
63 10 11 12 13 14 15 16 17 18 19
64 20 21 22 23 24 25 26 27 28 29
65 30 31 32 33 34 35 36 37 38 39
66 40 41 42 43 44 45 46 47 48 49
67 50 51 52 53 54 55 56 57 58 59
68 60 61 62 63 64 65 66 67 68 69
69 70 71 72 73 74 75 76 77 78 79
70 80 81 82 83 84 85 86 87 88 89
71 90 91 92 93 94 95 96 97 98 99
72 100>;
73 default-brightness-level = <50>;
74 };
75
76 display: display@di0 {
77 compatible = "fsl,imx-parallel-display";
78 interface-pix-fmt = "rgb24";
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_disp0_1>;
81 status = "okay";
82
83 port {
84 display0_in: endpoint {
85 remote-endpoint = <&ipu1_di0_disp0>;
86 };
87 };
88
89 display-timings {
90 VGA {
91 clock-frequency = <25200000>;
92 hactive = <640>;
93 vactive = <480>;
94 hback-porch = <48>;
95 hsync-len = <96>;
96 hfront-porch = <16>;
97 vback-porch = <31>;
98 vsync-len = <2>;
99 vfront-porch = <12>;
100 hsync-active = <0>;
101 vsync-active = <0>;
102 de-active = <1>;
103 pixelclk-active = <0>;
104 };
105
106 ETV570 {
107 clock-frequency = <25200000>;
108 hactive = <640>;
109 vactive = <480>;
110 hback-porch = <114>;
111 hsync-len = <30>;
112 hfront-porch = <16>;
113 vback-porch = <32>;
114 vsync-len = <3>;
115 vfront-porch = <10>;
116 hsync-active = <0>;
117 vsync-active = <0>;
118 de-active = <1>;
119 pixelclk-active = <0>;
120 };
121
122 ET0350 {
123 clock-frequency = <6413760>;
124 hactive = <320>;
125 vactive = <240>;
126 hback-porch = <34>;
127 hsync-len = <34>;
128 hfront-porch = <20>;
129 vback-porch = <15>;
130 vsync-len = <3>;
131 vfront-porch = <4>;
132 hsync-active = <0>;
133 vsync-active = <0>;
134 de-active = <1>;
135 pixelclk-active = <0>;
136 };
137
138 ET0430 {
139 clock-frequency = <9009000>;
140 hactive = <480>;
141 vactive = <272>;
142 hback-porch = <2>;
143 hsync-len = <41>;
144 hfront-porch = <2>;
145 vback-porch = <2>;
146 vsync-len = <10>;
147 vfront-porch = <2>;
148 hsync-active = <0>;
149 vsync-active = <0>;
150 de-active = <1>;
151 pixelclk-active = <1>;
152 };
153
154 ET0500 {
155 clock-frequency = <33264000>;
156 hactive = <800>;
157 vactive = <480>;
158 hback-porch = <88>;
159 hsync-len = <128>;
160 hfront-porch = <40>;
161 vback-porch = <33>;
162 vsync-len = <2>;
163 vfront-porch = <10>;
164 hsync-active = <0>;
165 vsync-active = <0>;
166 de-active = <1>;
167 pixelclk-active = <0>;
168 };
169
170 ET0700 { /* same as ET0500 */
171 clock-frequency = <33264000>;
172 hactive = <800>;
173 vactive = <480>;
174 hback-porch = <88>;
175 hsync-len = <128>;
176 hfront-porch = <40>;
177 vback-porch = <33>;
178 vsync-len = <2>;
179 vfront-porch = <10>;
180 hsync-active = <0>;
181 vsync-active = <0>;
182 de-active = <1>;
183 pixelclk-active = <0>;
184 };
185
186 ETQ570 {
187 clock-frequency = <6596040>;
188 hactive = <320>;
189 vactive = <240>;
190 hback-porch = <38>;
191 hsync-len = <30>;
192 hfront-porch = <30>;
193 vback-porch = <16>;
194 vsync-len = <3>;
195 vfront-porch = <4>;
196 hsync-active = <0>;
197 vsync-active = <0>;
198 de-active = <1>;
199 pixelclk-active = <0>;
200 };
201 };
202 };
203}; 50};
204 51
205&ipu1_di0_disp0 { 52&ipu2 {
206 remote-endpoint = <&display0_in>; 53 status = "disabled";
207}; 54};
diff --git a/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts b/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts
index 959ff3fb7304..a773f252816c 100644
--- a/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts
+++ b/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> 2 * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de>
3 * 3 *
4 * This file is dual-licensed: you can use it either under the terms 4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual 5 * of the GPL or the X11 license, at your option. Note that this dual
@@ -42,70 +42,16 @@
42/dts-v1/; 42/dts-v1/;
43#include "imx6q.dtsi" 43#include "imx6q.dtsi"
44#include "imx6qdl-tx6.dtsi" 44#include "imx6qdl-tx6.dtsi"
45#include "imx6qdl-tx6-lcd.dtsi"
45 46
46/ { 47/ {
47 model = "Ka-Ro electronics TX6Q-1020 Module on CoMpact TFT"; 48 model = "Ka-Ro electronics TX6Q-1020 Module on CoMpact TFT";
48 compatible = "karo,imx6q-tx6q", "fsl,imx6q"; 49 compatible = "karo,imx6q-tx6q", "fsl,imx6q";
50};
49 51
50 aliases { 52&backlight {
51 display = &display; 53 pwms = <&pwm2 0 500000 0>;
52 }; 54 /delete-property/ turn-on-delay-ms;
53
54 backlight: backlight {
55 compatible = "pwm-backlight";
56 pwms = <&pwm2 0 500000 0>;
57 power-supply = <&reg_3v3>;
58 /*
59 * a poor man's way to create a 1:1 relationship between
60 * the PWM value and the actual duty cycle
61 */
62 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
63 10 11 12 13 14 15 16 17 18 19
64 20 21 22 23 24 25 26 27 28 29
65 30 31 32 33 34 35 36 37 38 39
66 40 41 42 43 44 45 46 47 48 49
67 50 51 52 53 54 55 56 57 58 59
68 60 61 62 63 64 65 66 67 68 69
69 70 71 72 73 74 75 76 77 78 79
70 80 81 82 83 84 85 86 87 88 89
71 90 91 92 93 94 95 96 97 98 99
72 100>;
73 default-brightness-level = <50>;
74 };
75
76 display: display@di0 {
77 compatible = "fsl,imx-parallel-display";
78 interface-pix-fmt = "rgb24";
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_disp0_1>;
81 status = "okay";
82
83 port {
84 display0_in: endpoint {
85 remote-endpoint = <&ipu1_di0_disp0>;
86 };
87 };
88
89 display-timings {
90 native-mode = <&ET070001DM6>;
91
92 ET070001DM6: CoMTFT { /* same as ET0700 but with inverted pixel clock */
93 clock-frequency = <33264000>;
94 hactive = <800>;
95 vactive = <480>;
96 hback-porch = <88>;
97 hsync-len = <128>;
98 hfront-porch = <40>;
99 vback-porch = <33>;
100 vsync-len = <2>;
101 vfront-porch = <10>;
102 hsync-active = <0>;
103 vsync-active = <0>;
104 de-active = <1>;
105 pixelclk-active = <1>;
106 };
107 };
108 };
109}; 55};
110 56
111&can1 { 57&can1 {
@@ -124,14 +70,14 @@
124 status = "disabled"; 70 status = "disabled";
125}; 71};
126 72
127&ipu1_di0_disp0 {
128 remote-endpoint = <&display0_in>;
129};
130
131&kpp { 73&kpp {
132 status = "disabled"; 74 status = "disabled";
133}; 75};
134 76
77&lcd_panel {
78 compatible = "edt,etm0700g0edh6";
79};
80
135&reg_can_xcvr { 81&reg_can_xcvr {
136 status = "disabled"; 82 status = "disabled";
137}; 83};
diff --git a/arch/arm/boot/dts/imx6q-tx6q-1020.dts b/arch/arm/boot/dts/imx6q-tx6q-1020.dts
index b49133d25d80..0a4daec8d3ad 100644
--- a/arch/arm/boot/dts/imx6q-tx6q-1020.dts
+++ b/arch/arm/boot/dts/imx6q-tx6q-1020.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> 2 * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de>
3 * 3 *
4 * This file is dual-licensed: you can use it either under the terms 4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual 5 * of the GPL or the X11 license, at your option. Note that this dual
@@ -42,164 +42,11 @@
42/dts-v1/; 42/dts-v1/;
43#include "imx6q.dtsi" 43#include "imx6q.dtsi"
44#include "imx6qdl-tx6.dtsi" 44#include "imx6qdl-tx6.dtsi"
45#include "imx6qdl-tx6-lcd.dtsi"
45 46
46/ { 47/ {
47 model = "Ka-Ro electronics TX6Q-1020 Module"; 48 model = "Ka-Ro electronics TX6Q-1020 Module";
48 compatible = "karo,imx6q-tx6q", "fsl,imx6q"; 49 compatible = "karo,imx6q-tx6q", "fsl,imx6q";
49
50 aliases {
51 display = &display;
52 };
53
54 backlight: backlight {
55 compatible = "pwm-backlight";
56 pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
57 power-supply = <&reg_3v3>;
58 /*
59 * a poor man's way to create a 1:1 relationship between
60 * the PWM value and the actual duty cycle
61 */
62 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
63 10 11 12 13 14 15 16 17 18 19
64 20 21 22 23 24 25 26 27 28 29
65 30 31 32 33 34 35 36 37 38 39
66 40 41 42 43 44 45 46 47 48 49
67 50 51 52 53 54 55 56 57 58 59
68 60 61 62 63 64 65 66 67 68 69
69 70 71 72 73 74 75 76 77 78 79
70 80 81 82 83 84 85 86 87 88 89
71 90 91 92 93 94 95 96 97 98 99
72 100>;
73 default-brightness-level = <50>;
74 };
75
76 display: display@di0 {
77 compatible = "fsl,imx-parallel-display";
78 interface-pix-fmt = "rgb24";
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_disp0_1>;
81 status = "okay";
82
83 port {
84 display0_in: endpoint {
85 remote-endpoint = <&ipu1_di0_disp0>;
86 };
87 };
88
89 display-timings {
90 VGA {
91 clock-frequency = <25200000>;
92 hactive = <640>;
93 vactive = <480>;
94 hback-porch = <48>;
95 hsync-len = <96>;
96 hfront-porch = <16>;
97 vback-porch = <31>;
98 vsync-len = <2>;
99 vfront-porch = <12>;
100 hsync-active = <0>;
101 vsync-active = <0>;
102 de-active = <1>;
103 pixelclk-active = <0>;
104 };
105
106 ETV570 {
107 clock-frequency = <25200000>;
108 hactive = <640>;
109 vactive = <480>;
110 hback-porch = <114>;
111 hsync-len = <30>;
112 hfront-porch = <16>;
113 vback-porch = <32>;
114 vsync-len = <3>;
115 vfront-porch = <10>;
116 hsync-active = <0>;
117 vsync-active = <0>;
118 de-active = <1>;
119 pixelclk-active = <0>;
120 };
121
122 ET0350 {
123 clock-frequency = <6413760>;
124 hactive = <320>;
125 vactive = <240>;
126 hback-porch = <34>;
127 hsync-len = <34>;
128 hfront-porch = <20>;
129 vback-porch = <15>;
130 vsync-len = <3>;
131 vfront-porch = <4>;
132 hsync-active = <0>;
133 vsync-active = <0>;
134 de-active = <1>;
135 pixelclk-active = <0>;
136 };
137
138 ET0430 {
139 clock-frequency = <9009000>;
140 hactive = <480>;
141 vactive = <272>;
142 hback-porch = <2>;
143 hsync-len = <41>;
144 hfront-porch = <2>;
145 vback-porch = <2>;
146 vsync-len = <10>;
147 vfront-porch = <2>;
148 hsync-active = <0>;
149 vsync-active = <0>;
150 de-active = <1>;
151 pixelclk-active = <1>;
152 };
153
154 ET0500 {
155 clock-frequency = <33264000>;
156 hactive = <800>;
157 vactive = <480>;
158 hback-porch = <88>;
159 hsync-len = <128>;
160 hfront-porch = <40>;
161 vback-porch = <33>;
162 vsync-len = <2>;
163 vfront-porch = <10>;
164 hsync-active = <0>;
165 vsync-active = <0>;
166 de-active = <1>;
167 pixelclk-active = <0>;
168 };
169
170 ET0700 { /* same as ET0500 */
171 clock-frequency = <33264000>;
172 hactive = <800>;
173 vactive = <480>;
174 hback-porch = <88>;
175 hsync-len = <128>;
176 hfront-porch = <40>;
177 vback-porch = <33>;
178 vsync-len = <2>;
179 vfront-porch = <10>;
180 hsync-active = <0>;
181 vsync-active = <0>;
182 de-active = <1>;
183 pixelclk-active = <0>;
184 };
185
186 ETQ570 {
187 clock-frequency = <6596040>;
188 hactive = <320>;
189 vactive = <240>;
190 hback-porch = <38>;
191 hsync-len = <30>;
192 hfront-porch = <30>;
193 vback-porch = <16>;
194 vsync-len = <3>;
195 vfront-porch = <4>;
196 hsync-active = <0>;
197 vsync-active = <0>;
198 de-active = <1>;
199 pixelclk-active = <0>;
200 };
201 };
202 };
203}; 50};
204 51
205&ds1339 { 52&ds1339 {
@@ -210,14 +57,15 @@
210 status = "disabled"; 57 status = "disabled";
211}; 58};
212 59
213&ipu1_di0_disp0 { 60&ipu2 {
214 remote-endpoint = <&display0_in>; 61 status = "disabled";
215}; 62};
216 63
217&usdhc4 { 64&usdhc4 {
218 pinctrl-names = "default"; 65 pinctrl-names = "default";
219 pinctrl-0 = <&pinctrl_usdhc4>; 66 pinctrl-0 = <&pinctrl_usdhc4>;
220 bus-width = <4>; 67 bus-width = <4>;
68 non-removable;
221 no-1-8-v; 69 no-1-8-v;
222 fsl,wp-controller; 70 fsl,wp-controller;
223 status = "okay"; 71 status = "okay";
diff --git a/arch/arm/boot/dts/imx6q-tx6q-1036-mb7.dts b/arch/arm/boot/dts/imx6q-tx6q-1036-mb7.dts
new file mode 100644
index 000000000000..9ffbb0fe7df8
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-tx6q-1036-mb7.dts
@@ -0,0 +1,48 @@
1/*
2 * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42/dts-v1/;
43#include "imx6q-tx6q-1036.dts"
44#include "imx6qdl-tx6-mb7.dtsi"
45
46/ {
47 model = "Ka-Ro electronics TX6Q-1036 Module on MB7 baseboard";
48};
diff --git a/arch/arm/boot/dts/imx6q-tx6q-1036.dts b/arch/arm/boot/dts/imx6q-tx6q-1036.dts
index 7c152e32758c..cb2fcb4896c6 100644
--- a/arch/arm/boot/dts/imx6q-tx6q-1036.dts
+++ b/arch/arm/boot/dts/imx6q-tx6q-1036.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> 2 * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de>
3 * 3 *
4 * This file is dual-licensed: you can use it either under the terms 4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual 5 * of the GPL or the X11 license, at your option. Note that this dual
@@ -42,169 +42,11 @@
42/dts-v1/; 42/dts-v1/;
43#include "imx6q.dtsi" 43#include "imx6q.dtsi"
44#include "imx6qdl-tx6.dtsi" 44#include "imx6qdl-tx6.dtsi"
45#include "imx6qdl-tx6-lcd.dtsi"
45 46
46/ { 47/ {
47 model = "Ka-Ro electronics TX6Q-1036 Module"; 48 model = "Ka-Ro electronics TX6Q-1036 Module";
48 compatible = "karo,imx6q-tx6q", "fsl,imx6q"; 49 compatible = "karo,imx6q-tx6q", "fsl,imx6q";
49
50 aliases {
51 display = &display;
52 };
53
54 backlight: backlight {
55 compatible = "pwm-backlight";
56 pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
57 pinctrl-names = "default";
58 pinctrl-0 = <&pinctrl_lcd0_pwr>;
59 enable-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
60 power-supply = <&reg_lcd1_pwr>;
61 /*
62 * a poor man's way to create a 1:1 relationship between
63 * the PWM value and the actual duty cycle
64 */
65 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
66 10 11 12 13 14 15 16 17 18 19
67 20 21 22 23 24 25 26 27 28 29
68 30 31 32 33 34 35 36 37 38 39
69 40 41 42 43 44 45 46 47 48 49
70 50 51 52 53 54 55 56 57 58 59
71 60 61 62 63 64 65 66 67 68 69
72 70 71 72 73 74 75 76 77 78 79
73 80 81 82 83 84 85 86 87 88 89
74 90 91 92 93 94 95 96 97 98 99
75 100>;
76 default-brightness-level = <50>;
77 };
78
79 display: display@di0 {
80 compatible = "fsl,imx-parallel-display";
81 pinctrl-names = "default";
82 pinctrl-0 = <&pinctrl_disp0_2>;
83 interface-pix-fmt = "rgb24";
84 status = "okay";
85
86 port {
87 display0_in: endpoint {
88 remote-endpoint = <&ipu1_di0_disp0>;
89 };
90 };
91
92 display-timings {
93 native-mode = <&vga>;
94
95 vga: VGA {
96 clock-frequency = <25200000>;
97 hactive = <640>;
98 vactive = <480>;
99 hback-porch = <48>;
100 hsync-len = <96>;
101 hfront-porch = <16>;
102 vback-porch = <31>;
103 vsync-len = <2>;
104 vfront-porch = <12>;
105 hsync-active = <0>;
106 vsync-active = <0>;
107 de-active = <1>;
108 pixelclk-active = <0>;
109 };
110
111 ETV570 {
112 clock-frequency = <25200000>;
113 hactive = <640>;
114 vactive = <480>;
115 hback-porch = <114>;
116 hsync-len = <30>;
117 hfront-porch = <16>;
118 vback-porch = <32>;
119 vsync-len = <3>;
120 vfront-porch = <10>;
121 hsync-active = <0>;
122 vsync-active = <0>;
123 de-active = <1>;
124 pixelclk-active = <0>;
125 };
126
127 ET0350 {
128 clock-frequency = <6413760>;
129 hactive = <320>;
130 vactive = <240>;
131 hback-porch = <34>;
132 hsync-len = <34>;
133 hfront-porch = <20>;
134 vback-porch = <15>;
135 vsync-len = <3>;
136 vfront-porch = <4>;
137 hsync-active = <0>;
138 vsync-active = <0>;
139 de-active = <1>;
140 pixelclk-active = <0>;
141 };
142
143 ET0430 {
144 clock-frequency = <9009000>;
145 hactive = <480>;
146 vactive = <272>;
147 hback-porch = <2>;
148 hsync-len = <41>;
149 hfront-porch = <2>;
150 vback-porch = <2>;
151 vsync-len = <10>;
152 vfront-porch = <2>;
153 hsync-active = <0>;
154 vsync-active = <0>;
155 de-active = <1>;
156 pixelclk-active = <1>;
157 };
158
159 ET0500 {
160 clock-frequency = <33264000>;
161 hactive = <800>;
162 vactive = <480>;
163 hback-porch = <88>;
164 hsync-len = <128>;
165 hfront-porch = <40>;
166 vback-porch = <33>;
167 vsync-len = <2>;
168 vfront-porch = <10>;
169 hsync-active = <0>;
170 vsync-active = <0>;
171 de-active = <1>;
172 pixelclk-active = <0>;
173 };
174
175 ET0700 { /* same as ET0500 */
176 clock-frequency = <33264000>;
177 hactive = <800>;
178 vactive = <480>;
179 hback-porch = <88>;
180 hsync-len = <128>;
181 hfront-porch = <40>;
182 vback-porch = <33>;
183 vsync-len = <2>;
184 vfront-porch = <10>;
185 hsync-active = <0>;
186 vsync-active = <0>;
187 de-active = <1>;
188 pixelclk-active = <0>;
189 };
190
191 ETQ570 {
192 clock-frequency = <6596040>;
193 hactive = <320>;
194 vactive = <240>;
195 hback-porch = <38>;
196 hsync-len = <30>;
197 hfront-porch = <30>;
198 vback-porch = <16>;
199 vsync-len = <3>;
200 vfront-porch = <4>;
201 hsync-active = <0>;
202 vsync-active = <0>;
203 de-active = <1>;
204 pixelclk-active = <0>;
205 };
206 };
207 };
208}; 50};
209 51
210&ds1339 { 52&ds1339 {
@@ -215,18 +57,10 @@
215 status = "disabled"; 57 status = "disabled";
216}; 58};
217 59
218&ipu1_di0_disp0 {
219 remote-endpoint = <&display0_in>;
220};
221
222&ipu2 { 60&ipu2 {
223 status = "disabled"; 61 status = "disabled";
224}; 62};
225 63
226&reg_lcd0_pwr {
227 status = "disabled";
228};
229
230&usdhc4 { 64&usdhc4 {
231 pinctrl-names = "default"; 65 pinctrl-names = "default";
232 pinctrl-0 = <&pinctrl_usdhc4>; 66 pinctrl-0 = <&pinctrl_usdhc4>;
diff --git a/arch/arm/boot/dts/imx6q-tx6q-10x0-mb7.dts b/arch/arm/boot/dts/imx6q-tx6q-10x0-mb7.dts
new file mode 100644
index 000000000000..d43a5d8f1749
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-tx6q-10x0-mb7.dts
@@ -0,0 +1,48 @@
1/*
2 * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42/dts-v1/;
43#include "imx6q-tx6q-1010.dts"
44#include "imx6qdl-tx6-mb7.dtsi"
45
46/ {
47 model = "Ka-Ro electronics TX6Q-1010/-1030 Module on MB7 baseboard";
48};
diff --git a/arch/arm/boot/dts/imx6q-tx6q-1110.dts b/arch/arm/boot/dts/imx6q-tx6q-1110.dts
index f4793dec5d9b..f7b0acb65352 100644
--- a/arch/arm/boot/dts/imx6q-tx6q-1110.dts
+++ b/arch/arm/boot/dts/imx6q-tx6q-1110.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> 2 * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de>
3 * 3 *
4 * This file is dual-licensed: you can use it either under the terms 4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual 5 * of the GPL or the X11 license, at your option. Note that this dual
@@ -42,141 +42,17 @@
42/dts-v1/; 42/dts-v1/;
43#include "imx6q.dtsi" 43#include "imx6q.dtsi"
44#include "imx6qdl-tx6.dtsi" 44#include "imx6qdl-tx6.dtsi"
45#include "imx6qdl-tx6-lvds.dtsi"
45 46
46/ { 47/ {
47 model = "Ka-Ro electronics TX6Q-1110 Module"; 48 model = "Ka-Ro electronics TX6Q-1110/-1130 Module";
48 compatible = "karo,imx6q-tx6q", "fsl,imx6q"; 49 compatible = "karo,imx6q-tx6q", "fsl,imx6q";
49
50 aliases {
51 display = &lvds0;
52 lvds0 = &lvds0;
53 lvds1 = &lvds1;
54 };
55
56 backlight0: backlight0 {
57 compatible = "pwm-backlight";
58 pwms = <&pwm2 0 500000 0>;
59 power-supply = <&reg_lcd0_pwr>;
60 /*
61 * a poor man's way to create a 1:1 relationship between
62 * the PWM value and the actual duty cycle
63 */
64 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
65 10 11 12 13 14 15 16 17 18 19
66 20 21 22 23 24 25 26 27 28 29
67 30 31 32 33 34 35 36 37 38 39
68 40 41 42 43 44 45 46 47 48 49
69 50 51 52 53 54 55 56 57 58 59
70 60 61 62 63 64 65 66 67 68 69
71 70 71 72 73 74 75 76 77 78 79
72 80 81 82 83 84 85 86 87 88 89
73 90 91 92 93 94 95 96 97 98 99
74 100>;
75 default-brightness-level = <50>;
76 };
77
78 backlight1: backlight1 {
79 compatible = "pwm-backlight";
80 pwms = <&pwm1 0 500000 0>;
81 power-supply = <&reg_lcd1_pwr>;
82 /*
83 * a poor man's way to create a 1:1 relationship between
84 * the PWM value and the actual duty cycle
85 */
86 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
87 10 11 12 13 14 15 16 17 18 19
88 20 21 22 23 24 25 26 27 28 29
89 30 31 32 33 34 35 36 37 38 39
90 40 41 42 43 44 45 46 47 48 49
91 50 51 52 53 54 55 56 57 58 59
92 60 61 62 63 64 65 66 67 68 69
93 70 71 72 73 74 75 76 77 78 79
94 80 81 82 83 84 85 86 87 88 89
95 90 91 92 93 94 95 96 97 98 99
96 100>;
97 default-brightness-level = <50>;
98 };
99};
100
101&i2c3 {
102 polytouch1: eeti@4 {
103 compatible = "eeti,egalax_ts";
104 reg = <0x04>;
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_eeti>;
107 interrupt-parent = <&gpio3>;
108 interrupts = <22 0>;
109 wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
110 wakeup-source;
111 };
112}; 50};
113 51
114&kpp { 52&ipu2 {
115 status = "disabled"; /* pad conflict with backlight1 PWM */ 53 status = "disabled";
116};
117
118&ldb {
119 status = "okay";
120
121 lvds0: lvds-channel@0 {
122 fsl,data-mapping = "spwg";
123 fsl,data-width = <18>;
124 status = "okay";
125
126 display-timings {
127 native-mode = <&lvds_timing0>;
128 lvds_timing0: hsd100pxn1 {
129 clock-frequency = <65000000>;
130 hactive = <1024>;
131 vactive = <768>;
132 hback-porch = <220>;
133 hfront-porch = <40>;
134 vback-porch = <21>;
135 vfront-porch = <7>;
136 hsync-len = <60>;
137 vsync-len = <10>;
138 de-active = <1>;
139 pixelclk-active = <1>;
140 };
141 };
142 };
143
144 lvds1: lvds-channel@1 {
145 fsl,data-mapping = "spwg";
146 fsl,data-width = <18>;
147 status = "disabled";
148
149 display-timings {
150 native-mode = <&lvds_timing1>;
151 lvds_timing1: hsd100pxn1 {
152 clock-frequency = <65000000>;
153 hactive = <1024>;
154 vactive = <768>;
155 hback-porch = <220>;
156 hfront-porch = <40>;
157 vback-porch = <21>;
158 vfront-porch = <7>;
159 hsync-len = <60>;
160 vsync-len = <10>;
161 de-active = <1>;
162 pixelclk-active = <1>;
163 };
164 };
165 };
166};
167
168&pwm1 {
169 status = "okay";
170}; 54};
171 55
172&sata { 56&sata {
173 status = "okay"; 57 status = "okay";
174}; 58};
175
176&iomuxc {
177 pinctrl_eeti: eetigrp {
178 fsl,pins = <
179 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */
180 >;
181 };
182};
diff --git a/arch/arm/boot/dts/imx6q-tx6q-11x0-mb7.dts b/arch/arm/boot/dts/imx6q-tx6q-11x0-mb7.dts
index 7022704e79dc..387edf2b3f96 100644
--- a/arch/arm/boot/dts/imx6q-tx6q-11x0-mb7.dts
+++ b/arch/arm/boot/dts/imx6q-tx6q-11x0-mb7.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2016 Lothar Waßmann <LW@KARO-electronics.de> 2 * Copyright 2016-2017 Lothar Waßmann <LW@KARO-electronics.de>
3 * 3 *
4 * This file is dual-licensed: you can use it either under the terms 4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual 5 * of the GPL or the X11 license, at your option. Note that this dual
@@ -40,225 +40,9 @@
40 */ 40 */
41 41
42/dts-v1/; 42/dts-v1/;
43#include "imx6q.dtsi" 43#include "imx6q-tx6q-1110.dts"
44#include "imx6qdl-tx6.dtsi" 44#include "imx6qdl-tx6-mb7.dtsi"
45 45
46/ { 46/ {
47 model = "Ka-Ro electronics TX6Q-1110/-1130 Module on MB7 baseboard"; 47 model = "Ka-Ro electronics TX6Q-1110/-1130 Module on MB7 baseboard";
48 compatible = "karo,imx6q-tx6q", "fsl,imx6q";
49
50 aliases {
51 display = &lvds0;
52 ipu1 = &ipu2;
53 lvds0 = &lvds0;
54 lvds1 = &lvds1;
55 };
56
57 backlight0: backlight0 {
58 compatible = "pwm-backlight";
59 pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
60 power-supply = <&reg_lcd0_pwr>;
61 /*
62 * a poor man's way to create a 1:1 relationship between
63 * the PWM value and the actual duty cycle
64 */
65 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
66 10 11 12 13 14 15 16 17 18 19
67 20 21 22 23 24 25 26 27 28 29
68 30 31 32 33 34 35 36 37 38 39
69 40 41 42 43 44 45 46 47 48 49
70 50 51 52 53 54 55 56 57 58 59
71 60 61 62 63 64 65 66 67 68 69
72 70 71 72 73 74 75 76 77 78 79
73 80 81 82 83 84 85 86 87 88 89
74 90 91 92 93 94 95 96 97 98 99
75 100>;
76 default-brightness-level = <50>;
77 };
78
79 backlight1: backlight1 {
80 compatible = "pwm-backlight";
81 pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>;
82 power-supply = <&reg_lcd1_pwr>;
83 /*
84 * a poor man's way to create a 1:1 relationship between
85 * the PWM value and the actual duty cycle
86 */
87 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
88 10 11 12 13 14 15 16 17 18 19
89 20 21 22 23 24 25 26 27 28 29
90 30 31 32 33 34 35 36 37 38 39
91 40 41 42 43 44 45 46 47 48 49
92 50 51 52 53 54 55 56 57 58 59
93 60 61 62 63 64 65 66 67 68 69
94 70 71 72 73 74 75 76 77 78 79
95 80 81 82 83 84 85 86 87 88 89
96 90 91 92 93 94 95 96 97 98 99
97 100>;
98 default-brightness-level = <50>;
99 };
100};
101
102&can1 {
103 status = "disabled";
104};
105
106&can2 {
107 xceiver-supply = <&reg_3v3>;
108};
109
110&i2c3 {
111 polytouch1: eeti@4 {
112 compatible = "eeti,egalax_ts";
113 reg = <0x04>;
114 pinctrl-names = "default";
115 pinctrl-0 = <&pinctrl_eeti>;
116 interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_FALLING>;
117 wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
118 wakeup-source;
119 };
120};
121
122&ipu2 {
123 status = "disabled";
124};
125
126&kpp {
127 status = "disabled"; /* pads partially clash with backlight1 PWM */
128};
129
130&ldb {
131 status = "okay";
132
133 lvds0: lvds-channel@0 {
134 fsl,data-mapping = "spwg";
135 fsl,data-width = <18>;
136 status = "okay";
137
138 display-timings {
139 native-mode = <&lvds0_timing1>;
140
141 lvds0_timing0: hsd100pxn1 {
142 clock-frequency = <65000000>;
143 hactive = <1024>;
144 vactive = <768>;
145 hback-porch = <220>;
146 hfront-porch = <40>;
147 vback-porch = <21>;
148 vfront-porch = <7>;
149 hsync-len = <60>;
150 vsync-len = <10>;
151 hsync-active = <0>;
152 vsync-active = <0>;
153 de-active = <1>;
154 pixelclk-active = <1>;
155 };
156
157 lvds0_timing1: VGA {
158 clock-frequency = <25200000>;
159 hactive = <640>;
160 vactive = <480>;
161 hback-porch = <48>;
162 hfront-porch = <16>;
163 vback-porch = <31>;
164 vfront-porch = <12>;
165 hsync-len = <96>;
166 vsync-len = <2>;
167 hsync-active = <0>;
168 vsync-active = <0>;
169 de-active = <1>;
170 pixelclk-active = <0>;
171 };
172
173 lvds0_timing2: nl12880bc20 {
174 clock-frequency = <71000000>;
175 hactive = <1280>;
176 vactive = <800>;
177 hback-porch = <50>;
178 hfront-porch = <50>;
179 vback-porch = <5>;
180 vfront-porch = <5>;
181 hsync-len = <60>;
182 vsync-len = <13>;
183 hsync-active = <0>;
184 vsync-active = <0>;
185 de-active = <1>;
186 pixelclk-active = <1>;
187 };
188 };
189 };
190
191 lvds1: lvds-channel@1 {
192 fsl,data-mapping = "spwg";
193 fsl,data-width = <18>;
194 status = "okay";
195
196 display-timings {
197 native-mode = <&lvds1_timing2>;
198
199 lvds1_timing0: hsd100pxn1 {
200 clock-frequency = <65000000>;
201 hactive = <1024>;
202 vactive = <768>;
203 hback-porch = <220>;
204 hfront-porch = <40>;
205 vback-porch = <21>;
206 vfront-porch = <7>;
207 hsync-len = <60>;
208 vsync-len = <10>;
209 hsync-active = <0>;
210 vsync-active = <0>;
211 de-active = <1>;
212 pixelclk-active = <1>;
213 };
214
215 lvds1_timing1: VGA {
216 clock-frequency = <25200000>;
217 hactive = <640>;
218 vactive = <480>;
219 hback-porch = <48>;
220 hfront-porch = <16>;
221 vback-porch = <31>;
222 vfront-porch = <12>;
223 hsync-len = <96>;
224 vsync-len = <2>;
225 hsync-active = <0>;
226 vsync-active = <0>;
227 de-active = <1>;
228 pixelclk-active = <0>;
229 };
230
231 lvds1_timing2: nl12880bc20 {
232 clock-frequency = <71000000>;
233 hactive = <1280>;
234 vactive = <800>;
235 hback-porch = <50>;
236 hfront-porch = <50>;
237 vback-porch = <5>;
238 vfront-porch = <5>;
239 hsync-len = <60>;
240 vsync-len = <13>;
241 hsync-active = <0>;
242 vsync-active = <0>;
243 de-active = <1>;
244 pixelclk-active = <1>;
245 };
246 };
247 };
248};
249
250&pwm1 {
251 status = "okay";
252};
253
254&sata {
255 status = "okay";
256};
257
258&iomuxc {
259 pinctrl_eeti: eetigrp {
260 fsl,pins = <
261 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */
262 >;
263 };
264}; 48};
diff --git a/arch/arm/boot/dts/imx6q-utilite-pro.dts b/arch/arm/boot/dts/imx6q-utilite-pro.dts
index 16d5be1aeb3c..f5d9c34b0d39 100644
--- a/arch/arm/boot/dts/imx6q-utilite-pro.dts
+++ b/arch/arm/boot/dts/imx6q-utilite-pro.dts
@@ -188,6 +188,8 @@
188/delete-node/&hdmi_mux_1; 188/delete-node/&hdmi_mux_1;
189 189
190&hdmi { 190&hdmi {
191 pinctrl-names = "default";
192 pinctrl-0 = <&pinctrl_hdmicec>;
191 ddc-i2c-bus = <&i2c2>; 193 ddc-i2c-bus = <&i2c2>;
192 status = "okay"; 194 status = "okay";
193}; 195};
@@ -211,6 +213,12 @@
211 >; 213 >;
212 }; 214 };
213 215
216 pinctrl_hdmicec: hdmicecgrp {
217 fsl,pins = <
218 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
219 >;
220 };
221
214 pinctrl_hpd: hpdgrp { 222 pinctrl_hpd: hpdgrp {
215 fsl,pins = < 223 fsl,pins = <
216 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 224 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
diff --git a/arch/arm/boot/dts/imx6q-wandboard-revd1.dts b/arch/arm/boot/dts/imx6q-wandboard-revd1.dts
new file mode 100644
index 000000000000..e87ddb168669
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-wandboard-revd1.dts
@@ -0,0 +1,26 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11/dts-v1/;
12#include "imx6q.dtsi"
13#include "imx6qdl-wandboard-revd1.dtsi"
14
15/ {
16 model = "Wandboard i.MX6 Quad Board revD1";
17 compatible = "wand,imx6q-wandboard", "fsl,imx6q";
18
19 memory {
20 reg = <0x10000000 0x80000000>;
21 };
22};
23
24&sata {
25 status = "okay";
26};
diff --git a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi b/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
index f80d8eabe43e..829a47938179 100644
--- a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
@@ -54,7 +54,7 @@
54 stdout-path = &uart4; 54 stdout-path = &uart4;
55 }; 55 };
56 56
57 display@di0 { 57 disp0 {
58 compatible = "fsl,imx-parallel-display"; 58 compatible = "fsl,imx-parallel-display";
59 interface-pix-fmt = "bgr666"; 59 interface-pix-fmt = "bgr666";
60 pinctrl-names = "default"; 60 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
index 885556260bd0..dea8fc43c692 100644
--- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
@@ -332,175 +332,173 @@
332}; 332};
333 333
334&iomuxc { 334&iomuxc {
335 imx6qdl-gw51xx { 335 pinctrl_adv7180: adv7180grp {
336 pinctrl_adv7180: adv7180grp { 336 fsl,pins = <
337 fsl,pins = < 337 MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0
338 MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0 338 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0
339 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0 339 >;
340 >; 340 };
341 };
342 341
343 pinctrl_enet: enetgrp { 342 pinctrl_enet: enetgrp {
344 fsl,pins = < 343 fsl,pins = <
345 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 344 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
346 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 345 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
347 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 346 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
348 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 347 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
349 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 348 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
350 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 349 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
351 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 350 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
352 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 351 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
353 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 352 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
354 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 353 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
355 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 354 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
356 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 355 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
357 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 356 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
358 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 357 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
359 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 358 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
360 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 359 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
361 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */ 360 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */
362 >; 361 >;
363 }; 362 };
364 363
365 pinctrl_gpio_leds: gpioledsgrp { 364 pinctrl_gpio_leds: gpioledsgrp {
366 fsl,pins = < 365 fsl,pins = <
367 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 366 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
368 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 367 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
369 >; 368 >;
370 }; 369 };
371 370
372 pinctrl_gpmi_nand: gpminandgrp { 371 pinctrl_gpmi_nand: gpminandgrp {
373 fsl,pins = < 372 fsl,pins = <
374 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 373 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
375 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 374 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
376 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 375 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
377 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 376 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
378 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 377 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
379 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 378 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
380 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 379 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
381 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 380 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
382 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 381 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
383 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 382 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
384 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 383 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
385 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 384 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
386 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 385 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
387 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 386 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
388 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 387 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
389 >; 388 >;
390 }; 389 };
391 390
392 pinctrl_i2c1: i2c1grp { 391 pinctrl_i2c1: i2c1grp {
393 fsl,pins = < 392 fsl,pins = <
394 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 393 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
395 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 394 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
396 >; 395 >;
397 }; 396 };
398 397
399 pinctrl_i2c2: i2c2grp { 398 pinctrl_i2c2: i2c2grp {
400 fsl,pins = < 399 fsl,pins = <
401 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 400 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
402 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 401 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
403 >; 402 >;
404 }; 403 };
405 404
406 pinctrl_i2c3: i2c3grp { 405 pinctrl_i2c3: i2c3grp {
407 fsl,pins = < 406 fsl,pins = <
408 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 407 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
409 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 408 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
410 >; 409 >;
411 }; 410 };
412 411
413 pinctrl_ipu1_csi0: ipu1csi0grp { 412 pinctrl_ipu1_csi0: ipu1csi0grp {
414 fsl,pins = < 413 fsl,pins = <
415 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 414 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
416 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 415 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
417 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 416 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
418 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 417 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
419 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 418 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
420 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 419 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
421 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 420 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
422 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 421 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
423 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 422 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
424 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 423 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
425 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 424 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
426 >; 425 >;
427 }; 426 };
428 427
429 pinctrl_pcie: pciegrp { 428 pinctrl_pcie: pciegrp {
430 fsl,pins = < 429 fsl,pins = <
431 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 430 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
432 >; 431 >;
433 }; 432 };
434 433
435 pinctrl_pmic: pmicgrp { 434 pinctrl_pmic: pmicgrp {
436 fsl,pins = < 435 fsl,pins = <
437 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ 436 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
438 >; 437 >;
439 }; 438 };
440 439
441 pinctrl_pps: ppsgrp { 440 pinctrl_pps: ppsgrp {
442 fsl,pins = < 441 fsl,pins = <
443 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 442 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
444 >; 443 >;
445 }; 444 };
446 445
447 pinctrl_pwm2: pwm2grp { 446 pinctrl_pwm2: pwm2grp {
448 fsl,pins = < 447 fsl,pins = <
449 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 448 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
450 >; 449 >;
451 }; 450 };
452 451
453 pinctrl_pwm3: pwm3grp { 452 pinctrl_pwm3: pwm3grp {
454 fsl,pins = < 453 fsl,pins = <
455 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 454 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
456 >; 455 >;
457 }; 456 };
458 457
459 pinctrl_pwm4: pwm4grp { 458 pinctrl_pwm4: pwm4grp {
460 fsl,pins = < 459 fsl,pins = <
461 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 460 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
462 >; 461 >;
463 }; 462 };
464 463
465 pinctrl_uart1: uart1grp { 464 pinctrl_uart1: uart1grp {
466 fsl,pins = < 465 fsl,pins = <
467 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 466 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
468 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 467 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
469 >; 468 >;
470 }; 469 };
471 470
472 pinctrl_uart2: uart2grp { 471 pinctrl_uart2: uart2grp {
473 fsl,pins = < 472 fsl,pins = <
474 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 473 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
475 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 474 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
476 >; 475 >;
477 }; 476 };
478 477
479 pinctrl_uart3: uart3grp { 478 pinctrl_uart3: uart3grp {
480 fsl,pins = < 479 fsl,pins = <
481 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 480 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
482 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 481 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
483 >; 482 >;
484 }; 483 };
485 484
486 pinctrl_uart5: uart5grp { 485 pinctrl_uart5: uart5grp {
487 fsl,pins = < 486 fsl,pins = <
488 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 487 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
489 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 488 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
490 >; 489 >;
491 }; 490 };
492 491
493 pinctrl_usbotg: usbotggrp { 492 pinctrl_usbotg: usbotggrp {
494 fsl,pins = < 493 fsl,pins = <
495 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 494 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
496 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ 495 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
497 >; 496 >;
498 }; 497 };
499 498
500 pinctrl_wdog: wdoggrp { 499 pinctrl_wdog: wdoggrp {
501 fsl,pins = < 500 fsl,pins = <
502 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 501 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
503 >; 502 >;
504 };
505 }; 503 };
506}; 504};
diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
index 07ff0cbf9e1f..363a44394dad 100644
--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
@@ -423,213 +423,211 @@
423}; 423};
424 424
425&iomuxc { 425&iomuxc {
426 imx6qdl-gw52xx { 426 pinctrl_audmux: audmuxgrp {
427 pinctrl_audmux: audmuxgrp { 427 fsl,pins = <
428 fsl,pins = < 428 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
429 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 429 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
430 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 430 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
431 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 431 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
432 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 432 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
433 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ 433 >;
434 >; 434 };
435 };
436 435
437 pinctrl_ecspi3: escpi3grp { 436 pinctrl_ecspi3: escpi3grp {
438 fsl,pins = < 437 fsl,pins = <
439 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 438 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
440 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 439 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
441 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 440 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
442 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1 441 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
443 >; 442 >;
444 }; 443 };
445 444
446 pinctrl_enet: enetgrp { 445 pinctrl_enet: enetgrp {
447 fsl,pins = < 446 fsl,pins = <
448 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 447 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
449 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 448 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
450 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 449 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
451 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 450 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
452 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 451 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
453 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 452 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
454 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 453 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
455 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 454 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
456 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 455 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
457 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 456 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
458 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 457 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
459 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 458 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
460 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 459 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
461 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 460 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
462 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 461 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
463 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 462 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
464 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */ 463 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */
465 >; 464 >;
466 }; 465 };
467 466
468 pinctrl_flexcan1: flexcan1grp { 467 pinctrl_flexcan1: flexcan1grp {
469 fsl,pins = < 468 fsl,pins = <
470 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 469 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
471 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 470 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
472 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */ 471 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */
473 >; 472 >;
474 }; 473 };
475 474
476 pinctrl_gpio_leds: gpioledsgrp { 475 pinctrl_gpio_leds: gpioledsgrp {
477 fsl,pins = < 476 fsl,pins = <
478 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 477 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
479 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 478 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
480 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 479 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
481 >; 480 >;
482 }; 481 };
483 482
484 pinctrl_gpmi_nand: gpminandgrp { 483 pinctrl_gpmi_nand: gpminandgrp {
485 fsl,pins = < 484 fsl,pins = <
486 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 485 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
487 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 486 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
488 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 487 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
489 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 488 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
490 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 489 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
491 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 490 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
492 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 491 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
493 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 492 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
494 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 493 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
495 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 494 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
496 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 495 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
497 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 496 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
498 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 497 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
499 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 498 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
500 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 499 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
501 >; 500 >;
502 }; 501 };
503 502
504 pinctrl_i2c1: i2c1grp { 503 pinctrl_i2c1: i2c1grp {
505 fsl,pins = < 504 fsl,pins = <
506 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 505 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
507 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 506 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
508 >; 507 >;
509 }; 508 };
510 509
511 pinctrl_i2c2: i2c2grp { 510 pinctrl_i2c2: i2c2grp {
512 fsl,pins = < 511 fsl,pins = <
513 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 512 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
514 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 513 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
515 >; 514 >;
516 }; 515 };
517 516
518 pinctrl_i2c3: i2c3grp { 517 pinctrl_i2c3: i2c3grp {
519 fsl,pins = < 518 fsl,pins = <
520 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 519 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
521 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 520 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
522 >; 521 >;
523 }; 522 };
524 523
525 pinctrl_pcie: pciegrp { 524 pinctrl_pcie: pciegrp {
526 fsl,pins = < 525 fsl,pins = <
527 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE_RST# */ 526 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE_RST# */
528 >; 527 >;
529 }; 528 };
530 529
531 pinctrl_pmic: pmicgrp { 530 pinctrl_pmic: pmicgrp {
532 fsl,pins = < 531 fsl,pins = <
533 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ 532 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
534 >; 533 >;
535 }; 534 };
536 535
537 pinctrl_pps: ppsgrp { 536 pinctrl_pps: ppsgrp {
538 fsl,pins = < 537 fsl,pins = <
539 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 538 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
540 >; 539 >;
541 }; 540 };
542 541
543 pinctrl_pwm2: pwm2grp { 542 pinctrl_pwm2: pwm2grp {
544 fsl,pins = < 543 fsl,pins = <
545 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 544 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
546 >; 545 >;
547 }; 546 };
548 547
549 pinctrl_pwm3: pwm3grp { 548 pinctrl_pwm3: pwm3grp {
550 fsl,pins = < 549 fsl,pins = <
551 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 550 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
552 >; 551 >;
553 }; 552 };
554 553
555 pinctrl_pwm4: pwm4grp { 554 pinctrl_pwm4: pwm4grp {
556 fsl,pins = < 555 fsl,pins = <
557 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 556 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
558 >; 557 >;
559 }; 558 };
560 559
561 pinctrl_uart1: uart1grp { 560 pinctrl_uart1: uart1grp {
562 fsl,pins = < 561 fsl,pins = <
563 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 562 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
564 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 563 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
565 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ 564 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
566 >; 565 >;
567 }; 566 };
568 567
569 pinctrl_uart2: uart2grp { 568 pinctrl_uart2: uart2grp {
570 fsl,pins = < 569 fsl,pins = <
571 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 570 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
572 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 571 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
573 >; 572 >;
574 }; 573 };
575 574
576 pinctrl_uart5: uart5grp { 575 pinctrl_uart5: uart5grp {
577 fsl,pins = < 576 fsl,pins = <
578 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 577 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
579 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 578 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
580 >; 579 >;
581 }; 580 };
582 581
583 pinctrl_usbotg: usbotggrp { 582 pinctrl_usbotg: usbotggrp {
584 fsl,pins = < 583 fsl,pins = <
585 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 584 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
586 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ 585 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
587 >; 586 >;
588 }; 587 };
589 588
590 pinctrl_usdhc3: usdhc3grp { 589 pinctrl_usdhc3: usdhc3grp {
591 fsl,pins = < 590 fsl,pins = <
592 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 591 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
593 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 592 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
594 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 593 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
595 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 594 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
596 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 595 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
597 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 596 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
598 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ 597 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
599 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 598 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
600 >; 599 >;
601 }; 600 };
602 601
603 pinctrl_usdhc3_100mhz: usdhc3grp100mhz { 602 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
604 fsl,pins = < 603 fsl,pins = <
605 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 604 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
606 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9 605 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9
607 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 606 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
608 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 607 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
609 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 608 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
610 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 609 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
611 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ 610 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
612 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 611 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
613 >; 612 >;
614 }; 613 };
615 614
616 pinctrl_usdhc3_200mhz: usdhc3grp200mhz { 615 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
617 fsl,pins = < 616 fsl,pins = <
618 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 617 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
619 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 618 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
620 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 619 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
621 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 620 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
622 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 621 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
623 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 622 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
624 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ 623 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
625 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 624 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
626 >; 625 >;
627 }; 626 };
628 627
629 pinctrl_wdog: wdoggrp { 628 pinctrl_wdog: wdoggrp {
630 fsl,pins = < 629 fsl,pins = <
631 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 630 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
632 >; 631 >;
633 };
634 }; 632 };
635}; 633};
diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
index 6f1be3f9dd2a..c75385c0cad0 100644
--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
@@ -415,205 +415,203 @@
415}; 415};
416 416
417&iomuxc { 417&iomuxc {
418 imx6qdl-gw53xx { 418 pinctrl_audmux: audmuxgrp {
419 pinctrl_audmux: audmuxgrp { 419 fsl,pins = <
420 fsl,pins = < 420 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
421 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 421 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
422 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 422 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
423 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 423 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
424 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 424 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
425 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ 425 >;
426 >; 426 };
427 };
428 427
429 pinctrl_enet: enetgrp { 428 pinctrl_enet: enetgrp {
430 fsl,pins = < 429 fsl,pins = <
431 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 430 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
432 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 431 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
433 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 432 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
434 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 433 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
435 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 434 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
436 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 435 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
437 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 436 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
438 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 437 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
439 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 438 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
440 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 439 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
441 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 440 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
442 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 441 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
443 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 442 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
444 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 443 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
445 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 444 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
446 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 445 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
447 >; 446 >;
448 }; 447 };
449 448
450 pinctrl_flexcan1: flexcan1grp { 449 pinctrl_flexcan1: flexcan1grp {
451 fsl,pins = < 450 fsl,pins = <
452 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 451 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
453 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 452 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
454 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ 453 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
455 >; 454 >;
456 }; 455 };
457 456
458 pinctrl_gpio_leds: gpioledsgrp { 457 pinctrl_gpio_leds: gpioledsgrp {
459 fsl,pins = < 458 fsl,pins = <
460 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 459 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
461 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 460 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
462 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 461 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
463 >; 462 >;
464 }; 463 };
465 464
466 pinctrl_gpmi_nand: gpminandgrp { 465 pinctrl_gpmi_nand: gpminandgrp {
467 fsl,pins = < 466 fsl,pins = <
468 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 467 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
469 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 468 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
470 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 469 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
471 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 470 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
472 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 471 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
473 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 472 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
474 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 473 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
475 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 474 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
476 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 475 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
477 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 476 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
478 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 477 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
479 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 478 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
480 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 479 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
481 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 480 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
482 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 481 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
483 >; 482 >;
484 }; 483 };
485 484
486 pinctrl_i2c1: i2c1grp { 485 pinctrl_i2c1: i2c1grp {
487 fsl,pins = < 486 fsl,pins = <
488 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 487 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
489 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 488 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
490 >; 489 >;
491 }; 490 };
492 491
493 pinctrl_i2c2: i2c2grp { 492 pinctrl_i2c2: i2c2grp {
494 fsl,pins = < 493 fsl,pins = <
495 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 494 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
496 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 495 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
497 >; 496 >;
498 }; 497 };
499 498
500 pinctrl_i2c3: i2c3grp { 499 pinctrl_i2c3: i2c3grp {
501 fsl,pins = < 500 fsl,pins = <
502 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 501 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
503 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 502 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
504 >; 503 >;
505 }; 504 };
506 505
507 pinctrl_pcie: pciegrp { 506 pinctrl_pcie: pciegrp {
508 fsl,pins = < 507 fsl,pins = <
509 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ 508 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
510 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ 509 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
511 >; 510 >;
512 }; 511 };
513 512
514 pinctrl_pmic: pmicgrp { 513 pinctrl_pmic: pmicgrp {
515 fsl,pins = < 514 fsl,pins = <
516 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ 515 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
517 >; 516 >;
518 }; 517 };
519 518
520 pinctrl_pps: ppsgrp { 519 pinctrl_pps: ppsgrp {
521 fsl,pins = < 520 fsl,pins = <
522 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 521 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
523 >; 522 >;
524 }; 523 };
525 524
526 pinctrl_pwm2: pwm2grp { 525 pinctrl_pwm2: pwm2grp {
527 fsl,pins = < 526 fsl,pins = <
528 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 527 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
529 >; 528 >;
530 }; 529 };
531 530
532 pinctrl_pwm3: pwm3grp { 531 pinctrl_pwm3: pwm3grp {
533 fsl,pins = < 532 fsl,pins = <
534 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 533 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
535 >; 534 >;
536 }; 535 };
537 536
538 pinctrl_pwm4: pwm4grp { 537 pinctrl_pwm4: pwm4grp {
539 fsl,pins = < 538 fsl,pins = <
540 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 539 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
541 >; 540 >;
542 }; 541 };
543 542
544 pinctrl_uart1: uart1grp { 543 pinctrl_uart1: uart1grp {
545 fsl,pins = < 544 fsl,pins = <
546 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 545 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
547 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 546 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
548 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ 547 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
549 >; 548 >;
550 }; 549 };
551 550
552 pinctrl_uart2: uart2grp { 551 pinctrl_uart2: uart2grp {
553 fsl,pins = < 552 fsl,pins = <
554 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 553 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
555 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 554 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
556 >; 555 >;
557 }; 556 };
558 557
559 pinctrl_uart5: uart5grp { 558 pinctrl_uart5: uart5grp {
560 fsl,pins = < 559 fsl,pins = <
561 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 560 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
562 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 561 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
563 >; 562 >;
564 }; 563 };
565 564
566 pinctrl_usbotg: usbotggrp { 565 pinctrl_usbotg: usbotggrp {
567 fsl,pins = < 566 fsl,pins = <
568 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 567 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
569 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ 568 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
570 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ 569 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */
571 >; 570 >;
572 }; 571 };
573 572
574 pinctrl_usdhc3: usdhc3grp { 573 pinctrl_usdhc3: usdhc3grp {
575 fsl,pins = < 574 fsl,pins = <
576 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 575 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
577 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 576 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
578 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 577 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
579 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 578 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
580 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 579 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
581 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 580 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
582 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ 581 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
583 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 582 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
584 >; 583 >;
585 }; 584 };
586 585
587 pinctrl_usdhc3_100mhz: usdhc3grp100mhz { 586 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
588 fsl,pins = < 587 fsl,pins = <
589 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 588 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
590 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 589 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
591 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 590 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
592 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 591 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
593 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 592 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
594 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 593 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
595 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ 594 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
596 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 595 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
597 >; 596 >;
598 }; 597 };
599 598
600 pinctrl_usdhc3_200mhz: usdhc3grp200mhz { 599 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
601 fsl,pins = < 600 fsl,pins = <
602 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 601 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
603 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 602 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
604 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 603 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
605 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 604 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
606 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 605 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
607 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 606 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
608 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ 607 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
609 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 608 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
610 >; 609 >;
611 }; 610 };
612 611
613 pinctrl_wdog: wdoggrp { 612 pinctrl_wdog: wdoggrp {
614 fsl,pins = < 613 fsl,pins = <
615 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 614 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
616 >; 615 >;
617 };
618 }; 616 };
619}; 617};
diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
index b27c9a1147bf..eab75f3dbaf3 100644
--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
@@ -468,221 +468,219 @@
468}; 468};
469 469
470&iomuxc { 470&iomuxc {
471 imx6qdl-gw54xx { 471 pinctrl_audmux: audmuxgrp {
472 pinctrl_audmux: audmuxgrp { 472 fsl,pins = <
473 fsl,pins = < 473 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
474 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 474 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
475 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 475 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
476 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 476 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
477 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 477 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
478 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ 478 >;
479 >; 479 };
480 };
481 480
482 pinctrl_enet: enetgrp { 481 pinctrl_enet: enetgrp {
483 fsl,pins = < 482 fsl,pins = <
484 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 483 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
485 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 484 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
486 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 485 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
487 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 486 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
488 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 487 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
489 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 488 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
490 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 489 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
491 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 490 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
492 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 491 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
493 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 492 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
494 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 493 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
495 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 494 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
496 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 495 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
497 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 496 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
498 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 497 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
499 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 498 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
500 >; 499 >;
501 }; 500 };
502 501
503 pinctrl_ecspi2: escpi2grp { 502 pinctrl_ecspi2: escpi2grp {
504 fsl,pins = < 503 fsl,pins = <
505 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 504 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
506 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 505 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
507 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 506 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
508 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 507 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1
509 >; 508 >;
510 }; 509 };
511 510
512 pinctrl_flexcan1: flexcan1grp { 511 pinctrl_flexcan1: flexcan1grp {
513 fsl,pins = < 512 fsl,pins = <
514 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 513 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
515 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 514 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
516 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ 515 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
517 >; 516 >;
518 }; 517 };
519 518
520 pinctrl_gpio_leds: gpioledsgrp { 519 pinctrl_gpio_leds: gpioledsgrp {
521 fsl,pins = < 520 fsl,pins = <
522 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 521 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
523 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 522 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
524 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 523 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
525 >; 524 >;
526 }; 525 };
527 526
528 pinctrl_gpmi_nand: gpminandgrp { 527 pinctrl_gpmi_nand: gpminandgrp {
529 fsl,pins = < 528 fsl,pins = <
530 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 529 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
531 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 530 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
532 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 531 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
533 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 532 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
534 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 533 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
535 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 534 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
536 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 535 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
537 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 536 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
538 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 537 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
539 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 538 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
540 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 539 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
541 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 540 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
542 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 541 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
543 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 542 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
544 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 543 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
545 >; 544 >;
546 }; 545 };
547 546
548 pinctrl_i2c1: i2c1grp { 547 pinctrl_i2c1: i2c1grp {
549 fsl,pins = < 548 fsl,pins = <
550 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 549 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
551 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 550 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
552 >; 551 >;
553 }; 552 };
554 553
555 pinctrl_i2c2: i2c2grp { 554 pinctrl_i2c2: i2c2grp {
556 fsl,pins = < 555 fsl,pins = <
557 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 556 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
558 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 557 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
559 >; 558 >;
560 }; 559 };
561 560
562 pinctrl_i2c3: i2c3grp { 561 pinctrl_i2c3: i2c3grp {
563 fsl,pins = < 562 fsl,pins = <
564 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 563 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
565 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 564 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
566 >; 565 >;
567 }; 566 };
568 567
569 pinctrl_pcie: pciegrp { 568 pinctrl_pcie: pciegrp {
570 fsl,pins = < 569 fsl,pins = <
571 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ 570 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
572 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ 571 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
573 >; 572 >;
574 }; 573 };
575 574
576 pinctrl_pps: ppsgrp { 575 pinctrl_pps: ppsgrp {
577 fsl,pins = < 576 fsl,pins = <
578 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 577 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
579 >; 578 >;
580 }; 579 };
581 580
582 pinctrl_pwm1: pwm1grp { 581 pinctrl_pwm1: pwm1grp {
583 fsl,pins = < 582 fsl,pins = <
584 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 583 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
585 >; 584 >;
586 }; 585 };
587 586
588 pinctrl_pwm2: pwm2grp { 587 pinctrl_pwm2: pwm2grp {
589 fsl,pins = < 588 fsl,pins = <
590 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 589 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
591 >; 590 >;
592 }; 591 };
593 592
594 pinctrl_pwm3: pwm3grp { 593 pinctrl_pwm3: pwm3grp {
595 fsl,pins = < 594 fsl,pins = <
596 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 595 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
597 >; 596 >;
598 }; 597 };
599 598
600 pinctrl_pwm4_backlight: pwm4grpbacklight { 599 pinctrl_pwm4_backlight: pwm4grpbacklight {
601 fsl,pins = < 600 fsl,pins = <
602 /* LVDS_PWM J6.5 */ 601 /* LVDS_PWM J6.5 */
603 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 602 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
604 >; 603 >;
605 }; 604 };
606 605
607 pinctrl_pwm4_dio: pwm4grpdio { 606 pinctrl_pwm4_dio: pwm4grpdio {
608 fsl,pins = < 607 fsl,pins = <
609 /* DIO3 J16.4 */ 608 /* DIO3 J16.4 */
610 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 609 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
611 >; 610 >;
612 }; 611 };
613 612
614 pinctrl_uart1: uart1grp { 613 pinctrl_uart1: uart1grp {
615 fsl,pins = < 614 fsl,pins = <
616 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 615 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
617 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 616 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
618 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ 617 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
619 >; 618 >;
620 }; 619 };
621 620
622 pinctrl_uart2: uart2grp { 621 pinctrl_uart2: uart2grp {
623 fsl,pins = < 622 fsl,pins = <
624 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 623 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
625 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 624 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
626 >; 625 >;
627 }; 626 };
628 627
629 pinctrl_uart5: uart5grp { 628 pinctrl_uart5: uart5grp {
630 fsl,pins = < 629 fsl,pins = <
631 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 630 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
632 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 631 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
633 >; 632 >;
634 }; 633 };
635 634
636 pinctrl_usbotg: usbotggrp { 635 pinctrl_usbotg: usbotggrp {
637 fsl,pins = < 636 fsl,pins = <
638 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 637 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
639 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ 638 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
640 >; 639 >;
641 }; 640 };
642 641
643 pinctrl_usdhc3: usdhc3grp { 642 pinctrl_usdhc3: usdhc3grp {
644 fsl,pins = < 643 fsl,pins = <
645 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 644 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
646 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 645 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
647 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 646 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
648 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 647 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
649 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 648 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
650 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 649 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
651 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ 650 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
652 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 651 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
653 >; 652 >;
654 }; 653 };
655 654
656 pinctrl_usdhc3_100mhz: usdhc3grp100mhz { 655 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
657 fsl,pins = < 656 fsl,pins = <
658 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 657 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
659 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 658 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
660 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 659 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
661 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 660 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
662 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 661 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
663 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 662 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
664 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ 663 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
665 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 664 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
666 >; 665 >;
667 }; 666 };
668 667
669 pinctrl_usdhc3_200mhz: usdhc3grp200mhz { 668 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
670 fsl,pins = < 669 fsl,pins = <
671 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 670 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
672 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 671 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
673 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 672 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
674 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 673 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
675 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 674 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
676 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 675 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
677 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ 676 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
678 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 677 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
679 >; 678 >;
680 }; 679 };
681 680
682 pinctrl_wdog: wdoggrp { 681 pinctrl_wdog: wdoggrp {
683 fsl,pins = < 682 fsl,pins = <
684 MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0 683 MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0
685 >; 684 >;
686 };
687 }; 685 };
688}; 686};
diff --git a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
index 405b40310ddf..30d4662d4480 100644
--- a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
@@ -320,110 +320,108 @@
320}; 320};
321 321
322&iomuxc { 322&iomuxc {
323 imx6qdl-gw51xx { 323 pinctrl_flexcan1: flexcan1grp {
324 pinctrl_flexcan1: flexcan1grp { 324 fsl,pins = <
325 fsl,pins = < 325 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
326 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 326 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
327 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 327 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */
328 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */ 328 >;
329 >; 329 };
330 };
331 330
332 pinctrl_gpio_leds: gpioledsgrp { 331 pinctrl_gpio_leds: gpioledsgrp {
333 fsl,pins = < 332 fsl,pins = <
334 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 333 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
335 >; 334 >;
336 }; 335 };
337 336
338 pinctrl_gpmi_nand: gpminandgrp { 337 pinctrl_gpmi_nand: gpminandgrp {
339 fsl,pins = < 338 fsl,pins = <
340 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 339 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
341 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 340 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
342 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 341 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
343 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 342 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
344 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 343 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
345 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 344 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
346 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 345 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
347 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 346 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
348 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 347 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
349 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 348 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
350 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 349 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
351 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 350 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
352 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 351 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
353 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 352 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
354 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 353 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
355 >; 354 >;
356 }; 355 };
357 356
358 pinctrl_i2c1: i2c1grp { 357 pinctrl_i2c1: i2c1grp {
359 fsl,pins = < 358 fsl,pins = <
360 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 359 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
361 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 360 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
362 >; 361 >;
363 }; 362 };
364 363
365 pinctrl_i2c2: i2c2grp { 364 pinctrl_i2c2: i2c2grp {
366 fsl,pins = < 365 fsl,pins = <
367 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 366 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
368 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 367 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
369 >; 368 >;
370 }; 369 };
371 370
372 pinctrl_i2c3: i2c3grp { 371 pinctrl_i2c3: i2c3grp {
373 fsl,pins = < 372 fsl,pins = <
374 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 373 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
375 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 374 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
376 >; 375 >;
377 }; 376 };
378 377
379 pinctrl_pcie: pciegrp { 378 pinctrl_pcie: pciegrp {
380 fsl,pins = < 379 fsl,pins = <
381 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */ 380 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */
382 >; 381 >;
383 }; 382 };
384 383
385 pinctrl_pmic: pmicgrp { 384 pinctrl_pmic: pmicgrp {
386 fsl,pins = < 385 fsl,pins = <
387 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ 386 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
388 >; 387 >;
389 }; 388 };
390 389
391 pinctrl_pwm2: pwm2grp { 390 pinctrl_pwm2: pwm2grp {
392 fsl,pins = < 391 fsl,pins = <
393 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 392 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
394 >; 393 >;
395 }; 394 };
396 395
397 pinctrl_pwm3: pwm3grp { 396 pinctrl_pwm3: pwm3grp {
398 fsl,pins = < 397 fsl,pins = <
399 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 398 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
400 >; 399 >;
401 }; 400 };
402 401
403 pinctrl_uart2: uart2grp { 402 pinctrl_uart2: uart2grp {
404 fsl,pins = < 403 fsl,pins = <
405 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 404 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
406 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 405 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
407 >; 406 >;
408 }; 407 };
409 408
410 pinctrl_uart3: uart3grp { 409 pinctrl_uart3: uart3grp {
411 fsl,pins = < 410 fsl,pins = <
412 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 411 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
413 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 412 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
414 >; 413 >;
415 }; 414 };
416 415
417 pinctrl_usbotg: usbotggrp { 416 pinctrl_usbotg: usbotggrp {
418 fsl,pins = < 417 fsl,pins = <
419 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 418 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
420 >; 419 >;
421 }; 420 };
422 421
423 pinctrl_wdog: wdoggrp { 422 pinctrl_wdog: wdoggrp {
424 fsl,pins = < 423 fsl,pins = <
425 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 424 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
426 >; 425 >;
427 };
428 }; 426 };
429}; 427};
diff --git a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
index 67613dd7cc92..c67c10605070 100644
--- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
@@ -270,105 +270,103 @@
270}; 270};
271 271
272&iomuxc { 272&iomuxc {
273 imx6qdl-gw552x { 273 pinctrl_gpio_leds: gpioledsgrp {
274 pinctrl_gpio_leds: gpioledsgrp { 274 fsl,pins = <
275 fsl,pins = < 275 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
276 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 276 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
277 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 277 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
278 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 278 >;
279 >; 279 };
280 };
281 280
282 pinctrl_gpmi_nand: gpminandgrp { 281 pinctrl_gpmi_nand: gpminandgrp {
283 fsl,pins = < 282 fsl,pins = <
284 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 283 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
285 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 284 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
286 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 285 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
287 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 286 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
288 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 287 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
289 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 288 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
290 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 289 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
291 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 290 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
292 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 291 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
293 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 292 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
294 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 293 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
295 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 294 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
296 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 295 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
297 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 296 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
298 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 297 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
299 >; 298 >;
300 }; 299 };
301 300
302 pinctrl_i2c1: i2c1grp { 301 pinctrl_i2c1: i2c1grp {
303 fsl,pins = < 302 fsl,pins = <
304 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 303 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
305 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 304 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
306 >; 305 >;
307 }; 306 };
308 307
309 pinctrl_i2c2: i2c2grp { 308 pinctrl_i2c2: i2c2grp {
310 fsl,pins = < 309 fsl,pins = <
311 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 310 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
312 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 311 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
313 >; 312 >;
314 }; 313 };
315 314
316 pinctrl_i2c3: i2c3grp { 315 pinctrl_i2c3: i2c3grp {
317 fsl,pins = < 316 fsl,pins = <
318 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 317 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
319 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 318 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
320 >; 319 >;
321 }; 320 };
322 321
323 pinctrl_pcie: pciegrp { 322 pinctrl_pcie: pciegrp {
324 fsl,pins = < 323 fsl,pins = <
325 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 324 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
326 >; 325 >;
327 }; 326 };
328 327
329 pinctrl_pmic: pmicgrp { 328 pinctrl_pmic: pmicgrp {
330 fsl,pins = < 329 fsl,pins = <
331 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ 330 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
332 >; 331 >;
333 }; 332 };
334 333
335 pinctrl_pwm2: pwm2grp { 334 pinctrl_pwm2: pwm2grp {
336 fsl,pins = < 335 fsl,pins = <
337 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 336 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
338 >; 337 >;
339 }; 338 };
340 339
341 pinctrl_pwm3: pwm3grp { 340 pinctrl_pwm3: pwm3grp {
342 fsl,pins = < 341 fsl,pins = <
343 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 342 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
344 >; 343 >;
345 }; 344 };
346 345
347 pinctrl_uart2: uart2grp { 346 pinctrl_uart2: uart2grp {
348 fsl,pins = < 347 fsl,pins = <
349 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 348 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
350 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 349 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
351 >; 350 >;
352 }; 351 };
353 352
354 pinctrl_uart3: uart3grp { 353 pinctrl_uart3: uart3grp {
355 fsl,pins = < 354 fsl,pins = <
356 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 355 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
357 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 356 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
358 >; 357 >;
359 }; 358 };
360 359
361 pinctrl_uart5: uart5grp { 360 pinctrl_uart5: uart5grp {
362 fsl,pins = < 361 fsl,pins = <
363 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 362 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
364 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 363 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
365 >; 364 >;
366 }; 365 };
367 366
368 pinctrl_wdog: wdoggrp { 367 pinctrl_wdog: wdoggrp {
369 fsl,pins = < 368 fsl,pins = <
370 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 369 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
371 >; 370 >;
372 };
373 }; 371 };
374}; 372};
diff --git a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
index 7ca291e9dbdb..b6220d62f6de 100644
--- a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
@@ -41,6 +41,7 @@
41 41
42#include <dt-bindings/gpio/gpio.h> 42#include <dt-bindings/gpio/gpio.h>
43#include <dt-bindings/clock/imx6qdl-clock.h> 43#include <dt-bindings/clock/imx6qdl-clock.h>
44#include <dt-bindings/sound/fsl-imx-audmux.h>
44 45
45/ { 46/ {
46 memory { 47 memory {
@@ -118,17 +119,77 @@
118 clocks = <&clks IMX6QDL_CLK_LVDS2_GATE>; 119 clocks = <&clks IMX6QDL_CLK_LVDS2_GATE>;
119 clock-names = "refclk"; 120 clock-names = "refclk";
120 }; 121 };
121};
122 122
123&clks { 123 sound {
124 assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>; 124 compatible = "simple-audio-card";
125 assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>; 125 simple-audio-card,name = "imx6qdl-icore-rqs-sgtl5000";
126 simple-audio-card,format = "i2s";
127 simple-audio-card,bitclock-master = <&dailink_master>;
128 simple-audio-card,frame-master = <&dailink_master>;
129 simple-audio-card,widgets =
130 "Microphone", "Mic Jack",
131 "Headphone", "Headphone Jack",
132 "Line", "Line In Jack",
133 "Speaker", "Line Out Jack",
134 "Speaker", "Ext Spk";
135 simple-audio-card,routing =
136 "MIC_IN", "Mic Jack",
137 "Mic Jack", "Mic Bias",
138 "Headphone Jack", "HP_OUT";
139
140 simple-audio-card,cpu {
141 sound-dai = <&ssi1>;
142 };
143
144 dailink_master: simple-audio-card,codec {
145 sound-dai = <&sgtl5000>;
146 };
147 };
126}; 148};
127 149
128&audmux { 150&audmux {
129 pinctrl-names = "default"; 151 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_audmux>; 152 pinctrl-0 = <&pinctrl_audmux>;
131 status = "okay"; 153 status = "okay";
154
155 audmux_ssi1 {
156 fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>;
157 fsl,port-config = <
158 (IMX_AUDMUX_V2_PTCR_TFSDIR |
159 IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) |
160 IMX_AUDMUX_V2_PTCR_TCLKDIR |
161 IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) |
162 IMX_AUDMUX_V2_PTCR_SYN)
163 IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4)
164 >;
165 };
166
167 audmux_aud4 {
168 fsl,audmux-port = <MX51_AUDMUX_PORT4>;
169 fsl,port-config = <
170 IMX_AUDMUX_V2_PTCR_SYN
171 IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0)
172 >;
173 };
174};
175
176&can1 {
177 pinctrl-names = "default";
178 pinctrl-0 = <&pinctrl_can1>;
179 xceiver-supply = <&reg_3p3v>;
180 status = "okay";
181};
182
183&can2 {
184 pinctrl-names = "default";
185 pinctrl-0 = <&pinctrl_can2>;
186 xceiver-supply = <&reg_3p3v>;
187 status = "okay";
188};
189
190&clks {
191 assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>;
192 assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>;
132}; 193};
133 194
134&fec { 195&fec {
@@ -174,6 +235,16 @@
174 pinctrl-names = "default"; 235 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_i2c3>; 236 pinctrl-0 = <&pinctrl_i2c3>;
176 status = "okay"; 237 status = "okay";
238
239 sgtl5000: codec@a {
240 #sound-dai-cells = <0>;
241 compatible = "fsl,sgtl5000";
242 reg = <0x0a>;
243 clocks = <&clks IMX6QDL_CLK_CKO>;
244 VDDA-supply = <&reg_2p5v>;
245 VDDIO-supply = <&reg_3p3v>;
246 VDDD-supply = <&reg_1p8v>;
247 };
177}; 248};
178 249
179&pcie { 250&pcie {
@@ -184,6 +255,7 @@
184}; 255};
185 256
186&ssi1 { 257&ssi1 {
258 fsl,mode = "i2s-slave";
187 status = "okay"; 259 status = "okay";
188}; 260};
189 261
@@ -270,6 +342,20 @@
270 >; 342 >;
271 }; 343 };
272 344
345 pinctrl_can1: can1grp {
346 fsl,pins = <
347 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020
348 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020
349 >;
350 };
351
352 pinctrl_can2: can2grp {
353 fsl,pins = <
354 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b020
355 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b020
356 >;
357 };
358
273 pinctrl_i2c1: i2c1grp { 359 pinctrl_i2c1: i2c1grp {
274 fsl,pins = < 360 fsl,pins = <
275 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 361 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
diff --git a/arch/arm/boot/dts/imx6qdl-icore.dtsi b/arch/arm/boot/dts/imx6qdl-icore.dtsi
index 56d0c5d21cd0..a1b469c142f1 100644
--- a/arch/arm/boot/dts/imx6qdl-icore.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-icore.dtsi
@@ -42,6 +42,7 @@
42 42
43#include <dt-bindings/gpio/gpio.h> 43#include <dt-bindings/gpio/gpio.h>
44#include <dt-bindings/input/input.h> 44#include <dt-bindings/input/input.h>
45#include <dt-bindings/sound/fsl-imx-audmux.h>
45 46
46/ { 47/ {
47 memory { 48 memory {
@@ -55,6 +56,25 @@
55 default-brightness-level = <7>; 56 default-brightness-level = <7>;
56 }; 57 };
57 58
59 reg_1p8v: regulator-1p8v {
60 compatible = "regulator-fixed";
61 regulator-name = "1P8V";
62 regulator-min-microvolt = <1800000>;
63 regulator-max-microvolt = <1800000>;
64 regulator-boot-on;
65 regulator-always-on;
66 };
67
68
69 reg_2p5v: regulator-3p3v {
70 compatible = "regulator-fixed";
71 regulator-name = "2P5V";
72 regulator-min-microvolt = <2500000>;
73 regulator-max-microvolt = <2500000>;
74 regulator-boot-on;
75 regulator-always-on;
76 };
77
58 reg_3p3v: regulator-3p3v { 78 reg_3p3v: regulator-3p3v {
59 compatible = "regulator-fixed"; 79 compatible = "regulator-fixed";
60 regulator-name = "3P3V"; 80 regulator-name = "3P3V";
@@ -87,6 +107,59 @@
87 #clock-cells = <0>; 107 #clock-cells = <0>;
88 clock-frequency = <25000000>; /* 25MHz for example */ 108 clock-frequency = <25000000>; /* 25MHz for example */
89 }; 109 };
110
111 sound {
112 compatible = "simple-audio-card";
113 simple-audio-card,name = "imx6qdl-icore-sgtl5000";
114 simple-audio-card,format = "i2s";
115 simple-audio-card,bitclock-master = <&dailink_master>;
116 simple-audio-card,frame-master = <&dailink_master>;
117 simple-audio-card,widgets =
118 "Microphone", "Mic Jack",
119 "Headphone", "Headphone Jack",
120 "Line", "Line In Jack",
121 "Speaker", "Line Out Jack",
122 "Speaker", "Ext Spk";
123 simple-audio-card,routing =
124 "MIC_IN", "Mic Jack",
125 "Mic Jack", "Mic Bias",
126 "Headphone Jack", "HP_OUT";
127
128 simple-audio-card,cpu {
129 sound-dai = <&ssi1>;
130 };
131
132 dailink_master: simple-audio-card,codec {
133 sound-dai = <&sgtl5000>;
134 };
135 };
136};
137
138&audmux {
139 pinctrl-names = "default";
140 pinctrl-0 = <&pinctrl_audmux>;
141 status = "okay";
142
143
144 audmux_ssi1 {
145 fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>;
146 fsl,port-config = <
147 (IMX_AUDMUX_V2_PTCR_TFSDIR |
148 IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) |
149 IMX_AUDMUX_V2_PTCR_TCLKDIR |
150 IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) |
151 IMX_AUDMUX_V2_PTCR_SYN)
152 IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4)
153 >;
154 };
155
156 audmux_aud4 {
157 fsl,audmux-port = <MX51_AUDMUX_PORT4>;
158 fsl,port-config = <
159 IMX_AUDMUX_V2_PTCR_SYN
160 IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0)
161 >;
162 };
90}; 163};
91 164
92&can1 { 165&can1 {
@@ -141,6 +214,16 @@
141 pinctrl-names = "default"; 214 pinctrl-names = "default";
142 pinctrl-0 = <&pinctrl_i2c3>; 215 pinctrl-0 = <&pinctrl_i2c3>;
143 status = "okay"; 216 status = "okay";
217
218 sgtl5000: codec@a {
219 #sound-dai-cells = <0>;
220 compatible = "fsl,sgtl5000";
221 reg = <0x0a>;
222 clocks = <&clks IMX6QDL_CLK_CKO>;
223 VDDA-supply = <&reg_2p5v>;
224 VDDIO-supply = <&reg_3p3v>;
225 VDDD-supply = <&reg_1p8v>;
226 };
144}; 227};
145 228
146&pwm3 { 229&pwm3 {
@@ -149,6 +232,11 @@
149 status = "okay"; 232 status = "okay";
150}; 233};
151 234
235&ssi1 {
236 fsl,mode = "i2s-slave";
237 status = "okay";
238};
239
152&uart4 { 240&uart4 {
153 pinctrl-names = "default"; 241 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_uart4>; 242 pinctrl-0 = <&pinctrl_uart4>;
@@ -178,6 +266,15 @@
178}; 266};
179 267
180&iomuxc { 268&iomuxc {
269 pinctrl_audmux: audmux {
270 fsl,pins = <
271 MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
272 MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0
273 MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
274 MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
275 >;
276 };
277
181 pinctrl_enet: enetgrp { 278 pinctrl_enet: enetgrp {
182 fsl,pins = < 279 fsl,pins = <
183 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 280 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
index d776fc63df91..3a77f0fedfce 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
@@ -256,7 +256,7 @@
256 status = "okay"; 256 status = "okay";
257 }; 257 };
258 258
259 lcd_display: display@di0 { 259 lcd_display: disp0 {
260 compatible = "fsl,imx-parallel-display"; 260 compatible = "fsl,imx-parallel-display";
261 #address-cells = <1>; 261 #address-cells = <1>;
262 #size-cells = <0>; 262 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
index c770f6c85ba2..40942d6b94b3 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
@@ -120,7 +120,7 @@
120 }; 120 };
121 }; 121 };
122 122
123 lcd_display: display@di0 { 123 lcd_display: disp0 {
124 compatible = "fsl,imx-parallel-display"; 124 compatible = "fsl,imx-parallel-display";
125 #address-cells = <1>; 125 #address-cells = <1>;
126 #size-cells = <0>; 126 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
index 735823787117..4bdf29169d2a 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
@@ -197,7 +197,7 @@
197 status = "okay"; 197 status = "okay";
198 }; 198 };
199 199
200 lcd_display: display@di0 { 200 lcd_display: disp0 {
201 compatible = "fsl,imx-parallel-display"; 201 compatible = "fsl,imx-parallel-display";
202 #address-cells = <1>; 202 #address-cells = <1>;
203 #size-cells = <0>; 203 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
index 356ac7666707..35de7adc997b 100644
--- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
@@ -221,7 +221,7 @@
221 status = "okay"; 221 status = "okay";
222 }; 222 };
223 223
224 lcd_display: display@di0 { 224 lcd_display: disp0 {
225 compatible = "fsl,imx-parallel-display"; 225 compatible = "fsl,imx-parallel-display";
226 #address-cells = <1>; 226 #address-cells = <1>;
227 #size-cells = <0>; 227 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index 517f34b5a061..0a50705b9c18 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -67,7 +67,6 @@
67 regulator-min-microvolt = <3300000>; 67 regulator-min-microvolt = <3300000>;
68 regulator-max-microvolt = <3300000>; 68 regulator-max-microvolt = <3300000>;
69 gpio = <&gpio3 19 0>; 69 gpio = <&gpio3 19 0>;
70 regulator-always-on;
71 enable-active-high; 70 enable-active-high;
72 }; 71 };
73 }; 72 };
@@ -214,6 +213,8 @@
214}; 213};
215 214
216&hdmi { 215&hdmi {
216 pinctrl-names = "default";
217 pinctrl-0 = <&pinctrl_hdmi_cec>;
217 ddc-i2c-bus = <&i2c2>; 218 ddc-i2c-bus = <&i2c2>;
218 status = "okay"; 219 status = "okay";
219}; 220};
@@ -486,6 +487,12 @@
486 >; 487 >;
487 }; 488 };
488 489
490 pinctrl_hdmi_cec: hdmicecgrp {
491 fsl,pins = <
492 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
493 >;
494 };
495
489 pinctrl_i2c1: i2c1grp { 496 pinctrl_i2c1: i2c1grp {
490 fsl,pins = < 497 fsl,pins = <
491 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 498 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
@@ -651,6 +658,7 @@
651 pinctrl-names = "default"; 658 pinctrl-names = "default";
652 pinctrl-0 = <&pinctrl_pcie>; 659 pinctrl-0 = <&pinctrl_pcie>;
653 reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; 660 reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
661 vpcie-supply = <&reg_pcie>;
654 status = "okay"; 662 status = "okay";
655}; 663};
656 664
diff --git a/arch/arm/boot/dts/imx6qdl-tx6-lcd.dtsi b/arch/arm/boot/dts/imx6qdl-tx6-lcd.dtsi
new file mode 100644
index 000000000000..5102fc47380b
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-tx6-lcd.dtsi
@@ -0,0 +1,252 @@
1/*
2 * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42/ {
43 aliases {
44 display = &display;
45 };
46
47 backlight: backlight {
48 compatible = "pwm-backlight";
49 pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
50 pinctrl-names = "default";
51 pinctrl-0 = <&pinctrl_lcd1_pwr>;
52 enable-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>;
53 power-supply = <&reg_3v3>;
54 turn-on-delay-ms = <35>;
55 /*
56 * a poor man's way to create a 1:1 relationship between
57 * the PWM value and the actual duty cycle
58 */
59 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
60 10 11 12 13 14 15 16 17 18 19
61 20 21 22 23 24 25 26 27 28 29
62 30 31 32 33 34 35 36 37 38 39
63 40 41 42 43 44 45 46 47 48 49
64 50 51 52 53 54 55 56 57 58 59
65 60 61 62 63 64 65 66 67 68 69
66 70 71 72 73 74 75 76 77 78 79
67 80 81 82 83 84 85 86 87 88 89
68 90 91 92 93 94 95 96 97 98 99
69 100>;
70 default-brightness-level = <50>;
71 };
72
73 lcd_panel: lcd-panel {
74 compatible = "edt,etm0700g0dh6";
75 pinctrl-names = "default";
76 pinctrl-0 = <&pinctrl_lcd0_pwr>;
77 enable-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
78 power-supply = <&reg_3v3>;
79 backlight = <&backlight>;
80 bus-format-override = "rgb24";
81
82 port {
83 lcd_panel_in: endpoint {
84 remote-endpoint = <&lcd_out>;
85 };
86 };
87 };
88
89 display: disp0 {
90 compatible = "fsl,imx-parallel-display";
91 #address-cells = <1>;
92 #size-cells = <0>;
93 pinctrl-names = "default";
94 pinctrl-0 = <&pinctrl_disp0_1>;
95 status = "okay";
96
97 port@0 {
98 reg = <0>;
99
100 lcd_in: endpoint {
101 remote-endpoint = <&ipu1_di0_disp0>;
102 };
103 };
104
105 port@1 {
106 reg = <1>;
107
108 lcd_out: endpoint {
109 remote-endpoint = <&lcd_panel_in>;
110 };
111 };
112
113 display-timings {
114 VGA {
115 clock-frequency = <25200000>;
116 hactive = <640>;
117 vactive = <480>;
118 hback-porch = <48>;
119 hsync-len = <96>;
120 hfront-porch = <16>;
121 vback-porch = <31>;
122 vsync-len = <2>;
123 vfront-porch = <12>;
124 hsync-active = <0>;
125 vsync-active = <0>;
126 de-active = <1>;
127 pixelclk-active = <0>;
128 };
129
130 ETV570 {
131 u-boot,panel-name = "edt,et057090dhu";
132 clock-frequency = <25200000>;
133 hactive = <640>;
134 vactive = <480>;
135 hback-porch = <114>;
136 hsync-len = <30>;
137 hfront-porch = <16>;
138 vback-porch = <32>;
139 vsync-len = <3>;
140 vfront-porch = <10>;
141 hsync-active = <0>;
142 vsync-active = <0>;
143 de-active = <1>;
144 pixelclk-active = <0>;
145 };
146
147 ET0350 {
148 u-boot,panel-name = "edt,et0350g0dh6";
149 clock-frequency = <6413760>;
150 hactive = <320>;
151 vactive = <240>;
152 hback-porch = <34>;
153 hsync-len = <34>;
154 hfront-porch = <20>;
155 vback-porch = <15>;
156 vsync-len = <3>;
157 vfront-porch = <4>;
158 hsync-active = <0>;
159 vsync-active = <0>;
160 de-active = <1>;
161 pixelclk-active = <0>;
162 };
163
164 ET0430 {
165 u-boot,panel-name = "edt,et0430g0dh6";
166 clock-frequency = <9009000>;
167 hactive = <480>;
168 vactive = <272>;
169 hback-porch = <2>;
170 hsync-len = <41>;
171 hfront-porch = <2>;
172 vback-porch = <2>;
173 vsync-len = <10>;
174 vfront-porch = <2>;
175 hsync-active = <0>;
176 vsync-active = <0>;
177 de-active = <1>;
178 pixelclk-active = <1>;
179 };
180
181 ET0500 {
182 clock-frequency = <33264000>;
183 hactive = <800>;
184 vactive = <480>;
185 hback-porch = <88>;
186 hsync-len = <128>;
187 hfront-porch = <40>;
188 vback-porch = <33>;
189 vsync-len = <2>;
190 vfront-porch = <10>;
191 hsync-active = <0>;
192 vsync-active = <0>;
193 de-active = <1>;
194 pixelclk-active = <0>;
195 };
196
197 ET0700 { /* same as ET0500 */
198 u-boot,panel-name = "edt,etm0700g0dh6";
199 clock-frequency = <33264000>;
200 hactive = <800>;
201 vactive = <480>;
202 hback-porch = <88>;
203 hsync-len = <128>;
204 hfront-porch = <40>;
205 vback-porch = <33>;
206 vsync-len = <2>;
207 vfront-porch = <10>;
208 hsync-active = <0>;
209 vsync-active = <0>;
210 de-active = <1>;
211 pixelclk-active = <0>;
212 };
213
214 ETQ570 {
215 clock-frequency = <6596040>;
216 hactive = <320>;
217 vactive = <240>;
218 hback-porch = <38>;
219 hsync-len = <30>;
220 hfront-porch = <30>;
221 vback-porch = <16>;
222 vsync-len = <3>;
223 vfront-porch = <4>;
224 hsync-active = <0>;
225 vsync-active = <0>;
226 de-active = <1>;
227 pixelclk-active = <0>;
228 };
229
230 CoMTFT { /* same as ET0700 but with inverted pixel clock */
231 u-boot,panel-name = "edt,etm0700g0edh6";
232 clock-frequency = <33264000>;
233 hactive = <800>;
234 vactive = <480>;
235 hback-porch = <88>;
236 hsync-len = <128>;
237 hfront-porch = <40>;
238 vback-porch = <33>;
239 vsync-len = <2>;
240 vfront-porch = <10>;
241 hsync-active = <0>;
242 vsync-active = <0>;
243 de-active = <1>;
244 pixelclk-active = <1>;
245 };
246 };
247 };
248};
249
250&ipu1_di0_disp0 {
251 remote-endpoint = <&lcd_in>;
252};
diff --git a/arch/arm/boot/dts/imx6qdl-tx6-lvds.dtsi b/arch/arm/boot/dts/imx6qdl-tx6-lvds.dtsi
new file mode 100644
index 000000000000..2ca2eb37e14f
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-tx6-lvds.dtsi
@@ -0,0 +1,286 @@
1/*
2 * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42/ {
43 aliases {
44 display = &lvds0;
45 lvds0 = &lvds0;
46 lvds1 = &lvds1;
47 };
48
49 backlight0: backlight0 {
50 compatible = "pwm-backlight";
51 pwms = <&pwm2 0 500000 0>;
52 power-supply = <&reg_lcd0_pwr>;
53 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
54 10 11 12 13 14 15 16 17 18 19
55 20 21 22 23 24 25 26 27 28 29
56 30 31 32 33 34 35 36 37 38 39
57 40 41 42 43 44 45 46 47 48 49
58 50 51 52 53 54 55 56 57 58 59
59 60 61 62 63 64 65 66 67 68 69
60 70 71 72 73 74 75 76 77 78 79
61 80 81 82 83 84 85 86 87 88 89
62 90 91 92 93 94 95 96 97 98 99
63 100>;
64 default-brightness-level = <50>;
65 };
66
67 backlight1: backlight1 {
68 compatible = "pwm-backlight";
69 pwms = <&pwm1 0 500000 0>;
70 power-supply = <&reg_lcd1_pwr>;
71 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
72 10 11 12 13 14 15 16 17 18 19
73 20 21 22 23 24 25 26 27 28 29
74 30 31 32 33 34 35 36 37 38 39
75 40 41 42 43 44 45 46 47 48 49
76 50 51 52 53 54 55 56 57 58 59
77 60 61 62 63 64 65 66 67 68 69
78 70 71 72 73 74 75 76 77 78 79
79 80 81 82 83 84 85 86 87 88 89
80 90 91 92 93 94 95 96 97 98 99
81 100>;
82 default-brightness-level = <50>;
83 };
84
85 lvds0_panel: lvds0-panel {
86 compatible = "nlt,nl12880bc20-spwg-24";
87 backlight = <&backlight0>;
88 power-supply = <&reg_3v3>;
89
90 port {
91 panel_in_lvds0: endpoint {
92 remote-endpoint = <&lvds0_out>;
93 };
94 };
95 };
96
97 lvds1_panel: lvds1-panel {
98 compatible = "nlt,nl12880bc20-spwg-24";
99 backlight = <&backlight1>;
100 power-supply = <&reg_3v3>;
101
102 port {
103 panel_in_lvds1: endpoint {
104 remote-endpoint = <&lvds1_out>;
105 };
106 };
107 };
108};
109
110&kpp {
111 status = "disabled"; /* pad conflict with backlight1 PWM */
112};
113
114&ldb {
115 status = "okay";
116
117 lvds0: lvds-channel@0 {
118 fsl,data-width = <18>;
119 status = "okay";
120
121 port@4 {
122 reg = <4>;
123
124 lvds0_out: endpoint {
125 remote-endpoint = <&panel_in_lvds0>;
126 };
127 };
128
129 display-timings {
130 hsd100pxn1 {
131 u-boot,panel-name = "hannstar,hsd100pxn1";
132 clock-frequency = <65000000>;
133 hactive = <1024>;
134 vactive = <768>;
135 hback-porch = <220>;
136 hfront-porch = <40>;
137 vback-porch = <21>;
138 vfront-porch = <7>;
139 hsync-len = <60>;
140 vsync-len = <10>;
141 de-active = <1>;
142 pixelclk-active = <1>;
143 };
144
145 VGA {
146 clock-frequency = <25200000>;
147 hactive = <640>;
148 vactive = <480>;
149 hback-porch = <48>;
150 hfront-porch = <16>;
151 vback-porch = <31>;
152 vfront-porch = <12>;
153 hsync-len = <96>;
154 vsync-len = <2>;
155 hsync-active = <0>;
156 vsync-active = <0>;
157 de-active = <1>;
158 pixelclk-active = <0>;
159 };
160
161 nl12880bc20 {
162 u-boot,panel-name = "nlt,nl12880bc20-spwg-24";
163 clock-frequency = <71000000>;
164 hactive = <1280>;
165 vactive = <800>;
166 hback-porch = <50>;
167 hfront-porch = <50>;
168 vback-porch = <5>;
169 vfront-porch = <5>;
170 hsync-len = <60>;
171 vsync-len = <13>;
172 hsync-active = <0>;
173 vsync-active = <0>;
174 de-active = <1>;
175 pixelclk-active = <1>;
176 };
177
178 ET0700 {
179 u-boot,panel-name = "edt,etm0700g0dh6";
180 clock-frequency = <33264000>;
181 hactive = <800>;
182 vactive = <480>;
183 hback-porch = <88>;
184 hsync-len = <128>;
185 hfront-porch = <40>;
186 vback-porch = <33>;
187 vsync-len = <2>;
188 vfront-porch = <10>;
189 hsync-active = <0>;
190 vsync-active = <0>;
191 de-active = <1>;
192 pixelclk-active = <0>;
193 };
194
195 ETV570 {
196 u-boot,panel-name = "edt,et057090dhu";
197 clock-frequency = <25200000>;
198 hactive = <640>;
199 vactive = <480>;
200 hback-porch = <114>;
201 hsync-len = <30>;
202 hfront-porch = <16>;
203 vback-porch = <32>;
204 vsync-len = <3>;
205 vfront-porch = <10>;
206 hsync-active = <0>;
207 vsync-active = <0>;
208 de-active = <1>;
209 pixelclk-active = <0>;
210 };
211 };
212 };
213
214 lvds1: lvds-channel@1 {
215 fsl,data-width = <18>;
216 status = "okay";
217
218 port@4 {
219 reg = <4>;
220
221 lvds1_out: endpoint {
222 remote-endpoint = <&panel_in_lvds1>;
223 };
224 };
225
226 display-timings {
227 hsd100pxn1 {
228 clock-frequency = <65000000>;
229 hactive = <1024>;
230 vactive = <768>;
231 hback-porch = <220>;
232 hfront-porch = <40>;
233 vback-porch = <21>;
234 vfront-porch = <7>;
235 hsync-len = <60>;
236 vsync-len = <10>;
237 de-active = <1>;
238 pixelclk-active = <1>;
239 };
240
241 VGA {
242 clock-frequency = <25200000>;
243 hactive = <640>;
244 vactive = <480>;
245 hback-porch = <48>;
246 hfront-porch = <16>;
247 vback-porch = <31>;
248 vfront-porch = <12>;
249 hsync-len = <96>;
250 vsync-len = <2>;
251 hsync-active = <0>;
252 vsync-active = <0>;
253 de-active = <1>;
254 pixelclk-active = <0>;
255 };
256
257 nl12880bc20 {
258 clock-frequency = <71000000>;
259 hactive = <1280>;
260 vactive = <800>;
261 hback-porch = <50>;
262 hfront-porch = <50>;
263 vback-porch = <5>;
264 vfront-porch = <5>;
265 hsync-len = <60>;
266 vsync-len = <13>;
267 hsync-active = <0>;
268 vsync-active = <0>;
269 de-active = <1>;
270 pixelclk-active = <1>;
271 };
272 };
273 };
274};
275
276&pwm1 {
277 status = "okay";
278};
279
280&reg_lcd0_pwr {
281 status = "okay";
282};
283
284&reg_lcd1_pwr {
285 status = "okay";
286};
diff --git a/arch/arm/boot/dts/imx6qdl-tx6-mb7.dtsi b/arch/arm/boot/dts/imx6qdl-tx6-mb7.dtsi
new file mode 100644
index 000000000000..4c4e2e1a931f
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-tx6-mb7.dtsi
@@ -0,0 +1,99 @@
1/*
2 * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42/ {
43 backlight0 {
44 pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>;
45 turn-on-delay-ms = <35>;
46 power-supply = <&reg_lcd1_pwr>;
47 };
48
49 backlight1 {
50 pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
51 turn-on-delay-ms = <35>;
52 power-supply = <&reg_lcd1_pwr>;
53 };
54
55 lcd-panel {
56 compatible = "edt,et057090dhu";
57 bus-format-override = "rgb24";
58 pixelclk-active = <0>;
59 };
60
61 lvds0-panel {
62 compatible = "edt,etml1010g0dka";
63 bus-format-override = "spwg-18";
64 pixelclk-active = <0>;
65 };
66
67 lvds1-panel {
68 compatible = "edt,etml1010g0dka";
69 bus-format-override = "spwg-18";
70 pixelclk-active = <0>;
71 };
72};
73
74&can1 {
75 status = "disabled";
76};
77
78&can2 {
79 xceiver-supply = <&reg_3v3>;
80};
81
82&ds1339 {
83 /*
84 * The backup voltage of the module internal RTC is not wired
85 * by default on the MB7, so disable that RTC chip.
86 */
87 status = "disabled";
88};
89
90&i2c3 {
91 rtc: mcp7940x@6f {
92 compatible = "microchip,mcp7940x";
93 reg = <0x6f>;
94 };
95};
96
97&reg_lcd0_pwr {
98 status = "disabled";
99};
diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/imx6qdl-tx6.dtsi
index 25fe6aef797b..6abb66cd7d4a 100644
--- a/arch/arm/boot/dts/imx6qdl-tx6.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-tx6.dtsi
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> 2 * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de>
3 * 3 *
4 * This file is dual-licensed: you can use it either under the terms 4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual 5 * of the GPL or the X11 license, at your option. Note that this dual
@@ -43,6 +43,7 @@
43#include <dt-bindings/input/input.h> 43#include <dt-bindings/input/input.h>
44#include <dt-bindings/interrupt-controller/irq.h> 44#include <dt-bindings/interrupt-controller/irq.h>
45#include <dt-bindings/pwm/pwm.h> 45#include <dt-bindings/pwm/pwm.h>
46#include <dt-bindings/sound/fsl-imx-audmux.h>
46 47
47/ { 48/ {
48 aliases { 49 aliases {
@@ -145,7 +146,7 @@
145 pinctrl-0 = <&pinctrl_lcd0_pwr>; 146 pinctrl-0 = <&pinctrl_lcd0_pwr>;
146 gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; 147 gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
147 enable-active-high; 148 enable-active-high;
148 regulator-boot-on; 149 status = "disabled";
149 }; 150 };
150 151
151 reg_lcd1_pwr: regulator-lcd1-pwr { 152 reg_lcd1_pwr: regulator-lcd1-pwr {
@@ -157,7 +158,7 @@
157 pinctrl-0 = <&pinctrl_lcd1_pwr>; 158 pinctrl-0 = <&pinctrl_lcd1_pwr>;
158 gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; 159 gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
159 enable-active-high; 160 enable-active-high;
160 regulator-boot-on; 161 status = "disabled";
161 }; 162 };
162 163
163 reg_usbh1_vbus: regulator-usbh1-vbus { 164 reg_usbh1_vbus: regulator-usbh1-vbus {
@@ -183,24 +184,56 @@
183 }; 184 };
184 185
185 sound { 186 sound {
186 compatible = "karo,imx6qdl-tx6qdl-sgtl5000", 187 compatible = "karo,imx6qdl-tx6-sgtl5000",
187 "fsl,imx-audio-sgtl5000"; 188 "simple-audio-card";
188 model = "sgtl5000-audio"; 189 simple-audio-card,name = "imx6qdl-tx6-sgtl5000-audio";
189 pinctrl-names = "default"; 190 pinctrl-names = "default";
190 pinctrl-0 = <&pinctrl_audmux>; 191 pinctrl-0 = <&pinctrl_audmux>;
191 ssi-controller = <&ssi1>; 192 simple-audio-card,format = "i2s";
192 audio-codec = <&sgtl5000>; 193 simple-audio-card,bitclock-master = <&codec_dai>;
193 audio-routing = 194 simple-audio-card,frame-master = <&codec_dai>;
195 simple-audio-card,widgets =
196 "Microphone", "Mic Jack",
197 "Line", "Line In",
198 "Line", "Line Out",
199 "Headphone", "Headphone Jack";
200 simple-audio-card,routing =
194 "MIC_IN", "Mic Jack", 201 "MIC_IN", "Mic Jack",
195 "Mic Jack", "Mic Bias", 202 "Mic Jack", "Mic Bias",
196 "Headphone Jack", "HP_OUT"; 203 "Headphone Jack", "HP_OUT";
197 mux-int-port = <1>; 204
198 mux-ext-port = <5>; 205 cpu_dai: simple-audio-card,cpu {
206 sound-dai = <&ssi1>;
207 };
208
209 codec_dai: simple-audio-card,codec {
210 sound-dai = <&sgtl5000>;
211 };
199 }; 212 };
200}; 213};
201 214
202&audmux { 215&audmux {
203 status = "okay"; 216 status = "okay";
217
218 ssi1 {
219 fsl,audmux-port = <0>;
220 fsl,port-config = <
221 (IMX_AUDMUX_V2_PTCR_SYN |
222 IMX_AUDMUX_V2_PTCR_TFSEL(4) |
223 IMX_AUDMUX_V2_PTCR_TCSEL(4) |
224 IMX_AUDMUX_V2_PTCR_TFSDIR |
225 IMX_AUDMUX_V2_PTCR_TCLKDIR)
226 IMX_AUDMUX_V2_PDCR_RXDSEL(4)
227 >;
228 };
229
230 pins5 {
231 fsl,audmux-port = <4>;
232 fsl,port-config = <
233 IMX_AUDMUX_V2_PTCR_SYN
234 IMX_AUDMUX_V2_PDCR_RXDSEL(0)
235 >;
236 };
204}; 237};
205 238
206&can1 { 239&can1 {
@@ -241,7 +274,7 @@
241 274
242&fec { 275&fec {
243 pinctrl-names = "default"; 276 pinctrl-names = "default";
244 pinctrl-0 = <&pinctrl_enet>; 277 pinctrl-0 = <&pinctrl_enet &pinctrl_enet_mdio &pinctrl_etnphy_rst>;
245 clocks = <&clks IMX6QDL_CLK_ENET>, 278 clocks = <&clks IMX6QDL_CLK_ENET>,
246 <&clks IMX6QDL_CLK_ENET>, 279 <&clks IMX6QDL_CLK_ENET>,
247 <&clks IMX6QDL_CLK_ENET_REF>, 280 <&clks IMX6QDL_CLK_ENET_REF>,
@@ -249,6 +282,7 @@
249 clock-names = "ipg", "ahb", "ptp", "enet_out"; 282 clock-names = "ipg", "ahb", "ptp", "enet_out";
250 phy-mode = "rmii"; 283 phy-mode = "rmii";
251 phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; 284 phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
285 phy-reset-post-delay = <10>;
252 phy-handle = <&etnphy>; 286 phy-handle = <&etnphy>;
253 phy-supply = <&reg_3v3_etn>; 287 phy-supply = <&reg_3v3_etn>;
254 status = "okay"; 288 status = "okay";
@@ -261,8 +295,9 @@
261 compatible = "ethernet-phy-ieee802.3-c22"; 295 compatible = "ethernet-phy-ieee802.3-c22";
262 reg = <0>; 296 reg = <0>;
263 pinctrl-names = "default"; 297 pinctrl-names = "default";
264 pinctrl-0 = <&pinctrl_enet_mdio>; 298 pinctrl-0 = <&pinctrl_etnphy_int>;
265 interrupts-extended = <&gpio7 1 IRQ_TYPE_EDGE_FALLING>; 299 interrupt-parent = <&gpio7>;
300 interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
266 }; 301 };
267 }; 302 };
268}; 303};
@@ -276,25 +311,34 @@
276}; 311};
277 312
278&i2c1 { 313&i2c1 {
279 pinctrl-names = "default"; 314 pinctrl-names = "default", "gpio";
280 pinctrl-0 = <&pinctrl_i2c1>; 315 pinctrl-0 = <&pinctrl_i2c1>;
316 pinctrl-1 = <&pinctrl_i2c1_gpio>;
317 scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
318 sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
281 clock-frequency = <400000>; 319 clock-frequency = <400000>;
282 status = "okay"; 320 status = "okay";
283 321
284 ds1339: rtc@68 { 322 ds1339: rtc@68 {
285 compatible = "dallas,ds1339"; 323 compatible = "dallas,ds1339";
286 reg = <0x68>; 324 reg = <0x68>;
325 trickle-resistor-ohms = <250>;
326 trickle-diode-disable;
287 }; 327 };
288}; 328};
289 329
290&i2c3 { 330&i2c3 {
291 pinctrl-names = "default"; 331 pinctrl-names = "default", "gpio";
292 pinctrl-0 = <&pinctrl_i2c3>; 332 pinctrl-0 = <&pinctrl_i2c3>;
333 pinctrl-1 = <&pinctrl_i2c3_gpio>;
334 scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
335 sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
293 clock-frequency = <400000>; 336 clock-frequency = <400000>;
294 status = "okay"; 337 status = "okay";
295 338
296 sgtl5000: sgtl5000@a { 339 sgtl5000: sgtl5000@a {
297 compatible = "fsl,sgtl5000"; 340 compatible = "fsl,sgtl5000";
341 #sound-dai-cells = <0>;
298 reg = <0x0a>; 342 reg = <0x0a>;
299 VDDA-supply = <&reg_2v5>; 343 VDDA-supply = <&reg_2v5>;
300 VDDIO-supply = <&reg_3v3>; 344 VDDIO-supply = <&reg_3v3>;
@@ -332,8 +376,6 @@
332 376
333 pinctrl_hog: hoggrp { 377 pinctrl_hog: hoggrp {
334 fsl,pins = < 378 fsl,pins = <
335 MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */
336 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT */
337 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* PWR BTN */ 379 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* PWR BTN */
338 >; 380 >;
339 }; 381 };
@@ -451,12 +493,24 @@
451 >; 493 >;
452 }; 494 };
453 495
496 pinctrl_etnphy_int: etnphy-intgrp {
497 fsl,pins = <
498 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT */
499 >;
500 };
501
454 pinctrl_etnphy_power: etnphy-pwrgrp { 502 pinctrl_etnphy_power: etnphy-pwrgrp {
455 fsl,pins = < 503 fsl,pins = <
456 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */ 504 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */
457 >; 505 >;
458 }; 506 };
459 507
508 pinctrl_etnphy_rst: etnphy-rstgrp {
509 fsl,pins = <
510 MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */
511 >;
512 };
513
460 pinctrl_flexcan1: flexcan1grp { 514 pinctrl_flexcan1: flexcan1grp {
461 fsl,pins = < 515 fsl,pins = <
462 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 516 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
@@ -504,6 +558,13 @@
504 >; 558 >;
505 }; 559 };
506 560
561 pinctrl_i2c1_gpio: i2c1-gpiogrp {
562 fsl,pins = <
563 MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1
564 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1
565 >;
566 };
567
507 pinctrl_i2c3: i2c3grp { 568 pinctrl_i2c3: i2c3grp {
508 fsl,pins = < 569 fsl,pins = <
509 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 570 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
@@ -511,6 +572,13 @@
511 >; 572 >;
512 }; 573 };
513 574
575 pinctrl_i2c3_gpio: i2c3-gpiogrp {
576 fsl,pins = <
577 MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1
578 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
579 >;
580 };
581
514 pinctrl_kpp: kppgrp { 582 pinctrl_kpp: kppgrp {
515 fsl,pins = < 583 fsl,pins = <
516 MX6QDL_PAD_GPIO_9__KEY_COL6 0x1b0b1 584 MX6QDL_PAD_GPIO_9__KEY_COL6 0x1b0b1
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi
new file mode 100644
index 000000000000..6d8d9ca96646
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi
@@ -0,0 +1,196 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#include "imx6qdl-wandboard.dtsi"
13
14/ {
15 reg_eth_phy: regulator-eth-phy {
16 compatible = "regulator-fixed";
17 regulator-name = "ETH_PHY";
18 regulator-min-microvolt = <3300000>;
19 regulator-max-microvolt = <3300000>;
20 gpio = <&gpio7 13 GPIO_ACTIVE_LOW>;
21 };
22};
23
24&i2c3 {
25 clock-frequency = <100000>;
26 pinctrl-names = "default";
27 pinctrl-0 = <&pinctrl_i2c3>;
28 status = "okay";
29
30 pmic: pfuze100@8 {
31 compatible = "fsl,pfuze100";
32 reg = <0x08>;
33
34 regulators {
35 sw1a_reg: sw1ab {
36 regulator-min-microvolt = <300000>;
37 regulator-max-microvolt = <1875000>;
38 regulator-boot-on;
39 regulator-always-on;
40 regulator-ramp-delay = <6250>;
41 };
42
43 sw1c_reg: sw1c {
44 regulator-min-microvolt = <300000>;
45 regulator-max-microvolt = <1875000>;
46 regulator-boot-on;
47 regulator-always-on;
48 regulator-ramp-delay = <6250>;
49 };
50
51 sw2_reg: sw2 {
52 regulator-min-microvolt = <800000>;
53 regulator-max-microvolt = <3300000>;
54 regulator-boot-on;
55 regulator-always-on;
56 regulator-ramp-delay = <6250>;
57 };
58
59 sw3a_reg: sw3a {
60 regulator-min-microvolt = <400000>;
61 regulator-max-microvolt = <1975000>;
62 regulator-boot-on;
63 regulator-always-on;
64 };
65
66 sw3b_reg: sw3b {
67 regulator-min-microvolt = <400000>;
68 regulator-max-microvolt = <1975000>;
69 regulator-boot-on;
70 regulator-always-on;
71 };
72
73 sw4_reg: sw4 {
74 regulator-min-microvolt = <800000>;
75 regulator-max-microvolt = <3300000>;
76 };
77
78 swbst_reg: swbst {
79 regulator-min-microvolt = <5000000>;
80 regulator-max-microvolt = <5150000>;
81 };
82
83 snvs_reg: vsnvs {
84 regulator-min-microvolt = <1000000>;
85 regulator-max-microvolt = <3000000>;
86 regulator-boot-on;
87 regulator-always-on;
88 };
89
90 vref_reg: vrefddr {
91 regulator-boot-on;
92 regulator-always-on;
93 };
94
95 vgen1_reg: vgen1 {
96 regulator-min-microvolt = <800000>;
97 regulator-max-microvolt = <1550000>;
98 };
99
100 vgen2_reg: vgen2 {
101 regulator-min-microvolt = <1500000>;
102 regulator-max-microvolt = <1500000>;
103 regulator-boot-on;
104 regulator-always-on;
105 };
106
107 vgen3_reg: vgen3 {
108 regulator-min-microvolt = <1800000>;
109 regulator-max-microvolt = <3300000>;
110 regulator-always-on;
111 };
112
113 vgen4_reg: vgen4 {
114 regulator-min-microvolt = <1800000>;
115 regulator-max-microvolt = <3300000>;
116 regulator-always-on;
117 };
118
119 vgen5_reg: vgen5 {
120 regulator-min-microvolt = <1800000>;
121 regulator-max-microvolt = <3300000>;
122 regulator-always-on;
123 };
124
125 vgen6_reg: vgen6 {
126 regulator-min-microvolt = <1800000>;
127 regulator-max-microvolt = <3300000>;
128 regulator-always-on;
129 };
130 };
131 };
132};
133
134&fec {
135 phy-supply = <&reg_eth_phy>;
136 status = "okay";
137};
138
139&iomuxc {
140 pinctrl-0 = <&pinctrl_hog>;
141
142 imx6qdl-wandboard {
143 pinctrl_hog: hoggrp {
144 fsl,pins = <
145 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
146 MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x80000000 /* USB Power Enable */
147 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* USDHC1 CD */
148 MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */
149 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1f0b1 /* RGMII PHY reset */
150 >;
151 };
152
153 pinctrl_enet: enetgrp {
154 fsl,pins = <
155 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
156 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
157 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
158 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
159 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
160 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
161 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
162 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
163 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
164 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
165 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
166 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
167 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
168 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
169 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
170 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
171 >;
172 };
173
174 pinctrl_i2c3: i2c3grp {
175 fsl,pins = <
176 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
177 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
178 >;
179 };
180
181 pinctrl_spdif: spdifgrp {
182 fsl,pins = <
183 MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0
184 >;
185 };
186 };
187};
188
189&usdhc2 {
190 pinctrl-names = "default";
191 pinctrl-0 = <&pinctrl_usdhc2>;
192 bus-width = <4>;
193 no-1-8-v;
194 non-removable;
195 status = "okay";
196};
diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
index cbd652e38fe8..7812fbac963c 100644
--- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
@@ -543,7 +543,7 @@
543 543
544 rmi4-f01@1 { 544 rmi4-f01@1 {
545 reg = <0x1>; 545 reg = <0x1>;
546 syna,nosleep-mode = <1>; 546 syna,nosleep-mode = <2>;
547 }; 547 };
548 548
549 rmi4-f11@11 { 549 rmi4-f11@11 {
@@ -728,6 +728,7 @@
728 728
729&usbh1 { 729&usbh1 {
730 vbus-supply = <&reg_5p0v_main>; 730 vbus-supply = <&reg_5p0v_main>;
731 disable-over-current;
731 status = "okay"; 732 status = "okay";
732}; 733};
733 734
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 222a7a4ef603..1ce4eabf0590 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -828,7 +828,7 @@
828 828
829 gpr: iomuxc-gpr@20e0000 { 829 gpr: iomuxc-gpr@20e0000 {
830 compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd"; 830 compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
831 reg = <0x020e0000 0x38>; 831 reg = <0x20e0000 0x38>;
832 832
833 mux: mux-controller { 833 mux: mux-controller {
834 compatible = "mmio-mux"; 834 compatible = "mmio-mux";
@@ -838,7 +838,7 @@
838 838
839 iomuxc: iomuxc@20e0000 { 839 iomuxc: iomuxc@20e0000 {
840 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc"; 840 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
841 reg = <0x020e0000 0x4000>; 841 reg = <0x20e0000 0x4000>;
842 }; 842 };
843 843
844 ldb: ldb { 844 ldb: ldb {
diff --git a/arch/arm/boot/dts/imx6qp-tx6qp-8037-mb7.dts b/arch/arm/boot/dts/imx6qp-tx6qp-8037-mb7.dts
new file mode 100644
index 000000000000..92b38e6699aa
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qp-tx6qp-8037-mb7.dts
@@ -0,0 +1,48 @@
1/*
2 * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42/dts-v1/;
43#include "imx6qp-tx6qp-8037.dts"
44#include "imx6qdl-tx6-mb7.dtsi"
45
46/ {
47 model = "Ka-Ro electronics TX6Q-8037 Module on MB7 baseboard";
48};
diff --git a/arch/arm/boot/dts/imx6qp-tx6qp-8037.dts b/arch/arm/boot/dts/imx6qp-tx6qp-8037.dts
new file mode 100644
index 000000000000..ffc0f2ee11d2
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qp-tx6qp-8037.dts
@@ -0,0 +1,86 @@
1/*
2 * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42/dts-v1/;
43#include "imx6qp.dtsi"
44#include "imx6qdl-tx6.dtsi"
45#include "imx6qdl-tx6-lcd.dtsi"
46
47/ {
48 model = "Ka-Ro electronics TX6QP-8037 Module";
49 compatible = "karo,imx6qp-tx6qp", "fsl,imx6qp";
50};
51
52&ds1339 {
53 status = "disabled";
54};
55
56&gpmi {
57 status = "disabled";
58};
59
60&ipu2 {
61 status = "disabled";
62};
63
64&usdhc4 {
65 pinctrl-names = "default";
66 pinctrl-0 = <&pinctrl_usdhc4>;
67 bus-width = <4>;
68 non-removable;
69 no-1-8-v;
70 fsl,wp-controller;
71 status = "okay";
72};
73
74&iomuxc {
75 pinctrl_usdhc4: usdhc4grp {
76 fsl,pins = <
77 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1
78 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1
79 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1
80 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1
81 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1
82 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1
83 MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1
84 >;
85 };
86};
diff --git a/arch/arm/boot/dts/imx6qp-tx6qp-8137-mb7.dts b/arch/arm/boot/dts/imx6qp-tx6qp-8137-mb7.dts
new file mode 100644
index 000000000000..07ad70718aec
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qp-tx6qp-8137-mb7.dts
@@ -0,0 +1,57 @@
1/*
2 * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42/dts-v1/;
43#include "imx6qp-tx6qp-8137.dts"
44#include "imx6qdl-tx6-mb7.dtsi"
45
46/ {
47 model = "Ka-Ro electronics TX6Q-8137 Module on MB7 baseboard";
48 compatible = "karo,imx6qp-tx6qp", "fsl,imx6qp";
49};
50
51&ipu2 {
52 status = "disabled";
53};
54
55&sata {
56 status = "okay";
57};
diff --git a/arch/arm/boot/dts/imx6qp-tx6qp-8137.dts b/arch/arm/boot/dts/imx6qp-tx6qp-8137.dts
new file mode 100644
index 000000000000..dd494d587014
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qp-tx6qp-8137.dts
@@ -0,0 +1,90 @@
1/*
2 * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42/dts-v1/;
43#include "imx6qp.dtsi"
44#include "imx6qdl-tx6.dtsi"
45#include "imx6qdl-tx6-lvds.dtsi"
46
47/ {
48 model = "Ka-Ro electronics TX6QP-8137 Module";
49 compatible = "karo,imx6qp-tx6qp", "fsl,imx6qp";
50};
51
52&ds1339 {
53 status = "disabled";
54};
55
56&gpmi {
57 status = "disabled";
58};
59
60&ipu2 {
61 status = "disabled";
62};
63
64&sata {
65 status = "okay";
66};
67
68&usdhc4 {
69 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_usdhc4>;
71 bus-width = <4>;
72 non-removable;
73 no-1-8-v;
74 fsl,wp-controller;
75 status = "okay";
76};
77
78&iomuxc {
79 pinctrl_usdhc4: usdhc4grp {
80 fsl,pins = <
81 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1
82 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1
83 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1
84 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1
85 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1
86 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1
87 MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1
88 >;
89 };
90};
diff --git a/arch/arm/boot/dts/imx6qp-wandboard-revd1.dts b/arch/arm/boot/dts/imx6qp-wandboard-revd1.dts
new file mode 100644
index 000000000000..f7badd82ce8a
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qp-wandboard-revd1.dts
@@ -0,0 +1,26 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11/dts-v1/;
12#include "imx6qp.dtsi"
13#include "imx6qdl-wandboard-revd1.dtsi"
14
15/ {
16 model = "Wandboard i.MX6 QuadPlus Board revD1";
17 compatible = "wand,imx6qp-wandboard", "fsl,imx6qp";
18
19 memory {
20 reg = <0x10000000 0x80000000>;
21 };
22};
23
24&sata {
25 status = "okay";
26};
diff --git a/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts b/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts
new file mode 100644
index 000000000000..4d8c6521845f
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts
@@ -0,0 +1,572 @@
1/*
2 * Copyright (C) 2016 Christoph Fritz <chf.fritz@googlemail.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/dts-v1/;
10
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/input/input.h>
13#include "imx6sx.dtsi"
14
15/ {
16 model = "Softing VIN|ING 2000";
17 compatible = "samtec,imx6sx-vining-2000", "fsl,imx6sx";
18
19 chosen {
20 stdout-path = &uart1;
21 };
22
23 memory {
24 reg = <0x80000000 0x40000000>;
25 };
26
27 reg_usb_otg1_vbus: regulator-usb_otg1_vbus {
28 compatible = "regulator-fixed";
29 regulator-name = "usb_otg1_vbus";
30 pinctrl-names = "default";
31 pinctrl-0 = <&pinctrl_usb_otg1>;
32 regulator-min-microvolt = <5000000>;
33 regulator-max-microvolt = <5000000>;
34 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
35 enable-active-high;
36 };
37
38 reg_peri_3v3: regulator-peri_3v3 {
39 compatible = "regulator-fixed";
40 regulator-name = "peri_3v3";
41 regulator-min-microvolt = <3300000>;
42 regulator-max-microvolt = <3300000>;
43 };
44
45 pwmleds {
46 compatible = "pwm-leds";
47
48 red {
49 label = "red";
50 max-brightness = <255>;
51 pwms = <&pwm6 0 50000>;
52 };
53
54 green {
55 label = "green";
56 max-brightness = <255>;
57 pwms = <&pwm2 0 50000>;
58 };
59
60 blue {
61 label = "blue";
62 max-brightness = <255>;
63 pwms = <&pwm1 0 50000>;
64 };
65 };
66};
67
68&adc1 {
69 vref-supply = <&reg_peri_3v3>;
70 status = "okay";
71};
72
73&cpu0 {
74 /*
75 * This board has a shared rail of reg_arm and reg_soc (supplied by
76 * sw1a_reg) which is modeled below, but still this module behaves
77 * unstable without higher voltages. Hence, set higher voltages here.
78 */
79 operating-points = <
80 /* kHz uV */
81 996000 1250000
82 792000 1175000
83 396000 1175000
84 198000 1175000
85 >;
86 fsl,soc-operating-points = <
87 /* ARM kHz SOC uV */
88 996000 1250000
89 792000 1175000
90 396000 1175000
91 198000 1175000
92 >;
93};
94
95&ecspi4 {
96 pinctrl-names = "default";
97 pinctrl-0 = <&pinctrl_ecspi4>;
98 cs-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>;
99 status = "okay";
100};
101
102&fec1 {
103 pinctrl-names = "default";
104 pinctrl-0 = <&pinctrl_enet1>;
105 phy-supply = <&reg_peri_3v3>;
106 phy-reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
107 phy-reset-duration = <5>;
108 phy-mode = "rmii";
109 phy-handle = <&ethphy0>;
110 status = "okay";
111
112 mdio {
113 #address-cells = <1>;
114 #size-cells = <0>;
115
116 ethphy0: ethernet0-phy@0 {
117 reg = <0>;
118 max-speed = <100>;
119 interrupt-parent = <&gpio2>;
120 interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
121 };
122 };
123};
124
125&fec2 {
126 pinctrl-names = "default";
127 pinctrl-0 = <&pinctrl_enet2>;
128 phy-supply = <&reg_peri_3v3>;
129 phy-reset-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
130 phy-reset-duration = <5>;
131 phy-mode = "rmii";
132 phy-handle = <&ethphy1>;
133 status = "okay";
134
135 mdio {
136 #address-cells = <1>;
137 #size-cells = <0>;
138
139 ethphy1: ethernet1-phy@0 {
140 reg = <0>;
141 max-speed = <100>;
142 interrupt-parent = <&gpio2>;
143 interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
144 };
145 };
146};
147
148&flexcan1 {
149 pinctrl-names = "default";
150 pinctrl-0 = <&pinctrl_flexcan1>;
151 status = "okay";
152};
153
154&flexcan2 {
155 pinctrl-names = "default";
156 pinctrl-0 = <&pinctrl_flexcan2>;
157 status = "okay";
158};
159
160&i2c1 {
161 clock-frequency = <100000>;
162 pinctrl-names = "default";
163 pinctrl-0 = <&pinctrl_i2c1>;
164 status = "okay";
165
166 proximity: sx9500@28 {
167 compatible = "semtech,sx9500";
168 reg = <0x28>;
169 pinctrl-names = "default";
170 pinctrl-0 = <&pinctrl_sx9500>;
171 interrupt-parent = <&gpio2>;
172 interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
173 reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
174 };
175
176 pmic: pfuze100@8 {
177 compatible = "fsl,pfuze200";
178 reg = <0x08>;
179
180 regulators {
181 sw1a_reg: sw1ab {
182 regulator-min-microvolt = <300000>;
183 regulator-max-microvolt = <1875000>;
184 regulator-boot-on;
185 regulator-always-on;
186 regulator-ramp-delay = <6250>;
187 };
188
189 sw2_reg: sw2 {
190 regulator-min-microvolt = <800000>;
191 regulator-max-microvolt = <3300000>;
192 regulator-boot-on;
193 regulator-always-on;
194 };
195
196 sw3a_reg: sw3a {
197 regulator-min-microvolt = <400000>;
198 regulator-max-microvolt = <1975000>;
199 regulator-boot-on;
200 regulator-always-on;
201 };
202
203 sw3b_reg: sw3b {
204 regulator-min-microvolt = <400000>;
205 regulator-max-microvolt = <1975000>;
206 regulator-boot-on;
207 regulator-always-on;
208 };
209
210 snvs_reg: vsnvs {
211 regulator-min-microvolt = <1000000>;
212 regulator-max-microvolt = <3000000>;
213 regulator-boot-on;
214 regulator-always-on;
215 };
216
217 vref_reg: vrefddr {
218 regulator-boot-on;
219 regulator-always-on;
220 };
221
222 vgen1_reg: vgen1 {
223 regulator-min-microvolt = <800000>;
224 regulator-max-microvolt = <1550000>;
225 regulator-always-on;
226 };
227
228 vgen2_reg: vgen2 {
229 regulator-min-microvolt = <800000>;
230 regulator-max-microvolt = <1550000>;
231 };
232
233 vgen3_reg: vgen3 {
234 regulator-min-microvolt = <1800000>;
235 regulator-max-microvolt = <3300000>;
236 regulator-always-on;
237 };
238
239 vgen4_reg: vgen4 {
240 regulator-min-microvolt = <1800000>;
241 regulator-max-microvolt = <3300000>;
242 regulator-always-on;
243 };
244
245 vgen5_reg: vgen5 {
246 regulator-min-microvolt = <1800000>;
247 regulator-max-microvolt = <3300000>;
248 regulator-always-on;
249 };
250
251 vgen6_reg: vgen6 {
252 regulator-min-microvolt = <1800000>;
253 regulator-max-microvolt = <3300000>;
254 regulator-always-on;
255 };
256 };
257 };
258};
259
260&i2c3 {
261 clock-frequency = <100000>;
262 pinctrl-names = "default";
263 pinctrl-0 = <&pinctrl_i2c3>;
264 status = "okay";
265};
266
267&iomuxc {
268 pinctrl-names = "default";
269 pinctrl-0 = <&pinctrl_gpios>;
270
271 pinctrl_ecspi4: ecspi4grp {
272 fsl,pins = <
273 MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x130b1
274 MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x130b1
275 MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x130b1
276 MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x30b0
277 >;
278 };
279
280 pinctrl_enet1: enet1grp {
281 fsl,pins = <
282 MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x30c1
283 MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x30c1
284 MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0f9
285 MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0f9
286 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x30c1
287 MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0f9
288 MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4000a038
289 /* LAN8720 PHY Reset */
290 MX6SX_PAD_RGMII1_TD3__GPIO5_IO_9 0x10b0
291 /* MDIO */
292 MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0f9
293 MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0f9
294 /* IRQ from PHY */
295 MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x10b0
296 >;
297 };
298
299 pinctrl_enet2: enet2grp {
300 fsl,pins = <
301 MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x1b0b0
302 MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x1b0b0
303 MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x1b0b0
304 MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x1b0b0
305 MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x1b0b0
306 MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x1b0b0
307 MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4000a038
308 /* LAN8720 PHY Reset */
309 MX6SX_PAD_RGMII2_TD3__GPIO5_IO_21 0x10b0
310 /* MDIO */
311 MX6SX_PAD_ENET1_COL__ENET2_MDC 0xa0f9
312 MX6SX_PAD_ENET1_CRS__ENET2_MDIO 0xa0f9
313 /* IRQ from PHY */
314 MX6SX_PAD_KEY_ROW4__GPIO2_IO_19 0x10b0
315 >;
316 };
317
318 pinctrl_flexcan1: flexcan1grp {
319 fsl,pins = <
320 MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0
321 MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0
322 >;
323 };
324
325 pinctrl_flexcan2: flexcan2grp {
326 fsl,pins = <
327 MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0
328 MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0
329 >;
330 };
331
332 pinctrl_gpios: gpiosgrp {
333 fsl,pins = <
334 /* reset external uC */
335 MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x10b0
336 /* IRQ from external uC */
337 MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x10b0
338 /* overcurrent detection */
339 MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8 0x10b0
340 >;
341 };
342
343 pinctrl_i2c1: i2c1grp {
344 fsl,pins = <
345 MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
346 MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
347 >;
348 };
349
350 pinctrl_i2c3: i2c3grp {
351 fsl,pins = <
352 MX6SX_PAD_NAND_ALE__I2C3_SDA 0x4001b8b1
353 MX6SX_PAD_NAND_CLE__I2C3_SCL 0x4001b8b1
354 >;
355 };
356
357 pinctrl_pwm1: pwm1grp-1 {
358 fsl,pins = <
359 /* blue LED */
360 MX6SX_PAD_RGMII2_RD3__PWM1_OUT 0x1b0b1
361 >;
362 };
363
364 pinctrl_pwm2: pwm2grp-1 {
365 fsl,pins = <
366 /* green LED */
367 MX6SX_PAD_RGMII2_RD2__PWM2_OUT 0x1b0b1
368 >;
369 };
370
371 pinctrl_pwm6: pwm6grp-1 {
372 fsl,pins = <
373 /* red LED */
374 MX6SX_PAD_RGMII2_TD2__PWM6_OUT 0x1b0b1
375 >;
376 };
377
378 pinctrl_sx9500: sx9500grp {
379 fsl,pins = <
380 /* Reset */
381 MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x838
382 /* IRQ */
383 MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x70e0
384 >;
385 };
386
387 pinctrl_uart1: uart1grp {
388 fsl,pins = <
389 MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
390 MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
391 >;
392 };
393
394 pinctrl_uart2: uart2grp {
395 fsl,pins = <
396 MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1
397 MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1
398 >;
399 };
400
401 pinctrl_usb_otg1: usbotg1grp {
402 fsl,pins = <
403 MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0
404 >;
405 };
406
407 pinctrl_usb_otg1_id: usbotg1idgrp {
408 fsl,pins = <
409 MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059
410 >;
411 };
412
413 pinctrl_usdhc2_50mhz: usdhc2grp-50mhz {
414 fsl,pins = <
415 MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059
416 MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059
417 MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
418 MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
419 MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
420 MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
421 MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x1b000
422 MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x10b0
423 >;
424 };
425
426 pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
427 fsl,pins = <
428 MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x100b9
429 MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x170b9
430 MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x170b9
431 MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x170b9
432 MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x170b9
433 MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x170b9
434 >;
435 };
436
437 pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
438 fsl,pins = <
439 MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x100f9
440 MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x170f9
441 MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x170f9
442 MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x170f9
443 MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x170f9
444 MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x170f9
445 >;
446 };
447
448 pinctrl_usdhc4_50mhz: usdhc4grp-50mhz {
449 fsl,pins = <
450 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
451 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
452 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
453 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
454 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
455 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
456 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059
457 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059
458 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059
459 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059
460 MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x17068
461 >;
462 };
463
464 pinctrl_usdhc4_100mhz: usdhc4-100mhz {
465 fsl,pins = <
466 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9
467 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9
468 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9
469 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9
470 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9
471 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9
472 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9
473 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9
474 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9
475 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9
476 >;
477 };
478
479 pinctrl_usdhc4_200mhz: usdhc4-200mhz {
480 fsl,pins = <
481 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9
482 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9
483 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9
484 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9
485 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9
486 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9
487 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9
488 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9
489 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9
490 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9
491 >;
492 };
493};
494
495&pwm1 {
496 pinctrl-names = "default";
497 pinctrl-0 = <&pinctrl_pwm1>;
498 status = "okay";
499};
500
501&pwm2 {
502 pinctrl-names = "default";
503 pinctrl-0 = <&pinctrl_pwm2>;
504 status = "okay";
505};
506
507&pwm6 {
508 pinctrl-names = "default";
509 pinctrl-0 = <&pinctrl_pwm6>;
510 status = "okay";
511};
512
513&reg_arm {
514 vin-supply = <&sw1a_reg>;
515};
516
517&reg_soc {
518 vin-supply = <&sw1a_reg>;
519};
520
521&snvs_poweroff {
522 status = "okay";
523};
524
525&uart1 {
526 pinctrl-names = "default";
527 pinctrl-0 = <&pinctrl_uart1>;
528 status = "okay";
529};
530
531&uart2 {
532 pinctrl-names = "default";
533 pinctrl-0 = <&pinctrl_uart2>;
534 status = "okay";
535};
536
537&usbotg1 {
538 vbus-supply = <&reg_usb_otg1_vbus>;
539 pinctrl-names = "default";
540 pinctrl-0 = <&pinctrl_usb_otg1_id>;
541 status = "okay";
542};
543
544&usbotg2 {
545 dr_mode = "host";
546 status = "okay";
547};
548
549&usdhc2 {
550 pinctrl-names = "default", "state_100mhz", "state_200mhz";
551 pinctrl-0 = <&pinctrl_usdhc2_50mhz>;
552 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
553 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
554 cd-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>;
555 keep-power-in-suspend;
556 status = "okay";
557};
558
559&usdhc4 {
560 /* hs200-mode is currently unsupported because Vccq is on 3.1V, but
561 * not on necessary 1.8V.
562 */
563 pinctrl-names = "default", "state_100mhz", "state_200mhz";
564 pinctrl-0 = <&pinctrl_usdhc4_50mhz>;
565 pinctrl-1 = <&pinctrl_usdhc4_100mhz>;
566 pinctrl-2 = <&pinctrl_usdhc4_200mhz>;
567 bus-width = <8>;
568 keep-power-in-suspend;
569 non-removable;
570 cap-mmc-hw-reset;
571 status = "okay";
572};
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 32d71245b2a6..5b03ba3beda9 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -675,7 +675,8 @@
675 compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon"; 675 compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
676 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 676 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
677 fsl,tempmon = <&anatop>; 677 fsl,tempmon = <&anatop>;
678 fsl,tempmon-data = <&ocotp>; 678 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
679 nvmem-cell-names = "calib", "temp_grade";
679 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>; 680 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
680 }; 681 };
681 682
@@ -994,9 +995,19 @@
994 }; 995 };
995 996
996 ocotp: ocotp@21bc000 { 997 ocotp: ocotp@21bc000 {
998 #address-cells = <1>;
999 #size-cells = <1>;
997 compatible = "fsl,imx6sx-ocotp", "syscon"; 1000 compatible = "fsl,imx6sx-ocotp", "syscon";
998 reg = <0x021bc000 0x4000>; 1001 reg = <0x021bc000 0x4000>;
999 clocks = <&clks IMX6SX_CLK_OCOTP>; 1002 clocks = <&clks IMX6SX_CLK_OCOTP>;
1003
1004 tempmon_calib: calib@38 {
1005 reg = <0x38 4>;
1006 };
1007
1008 tempmon_temp_grade: temp-grade@20 {
1009 reg = <0x20 4>;
1010 };
1000 }; 1011 };
1001 1012
1002 sai1: sai@21d4000 { 1013 sai1: sai@21d4000 {
diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dts b/arch/arm/boot/dts/imx6ul-14x14-evk.dts
index 9c23e017d86a..e5d3ef88be60 100644
--- a/arch/arm/boot/dts/imx6ul-14x14-evk.dts
+++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dts
@@ -147,6 +147,8 @@
147 147
148 148
149&lcdif { 149&lcdif {
150 assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>;
151 assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>;
150 pinctrl-names = "default"; 152 pinctrl-names = "default";
151 pinctrl-0 = <&pinctrl_lcdif_dat 153 pinctrl-0 = <&pinctrl_lcdif_dat
152 &pinctrl_lcdif_ctrl>; 154 &pinctrl_lcdif_ctrl>;
diff --git a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts
index 9a68fb0ed4ab..3bf26ebd4df9 100644
--- a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts
+++ b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts
@@ -175,7 +175,7 @@
175 reg = <1>; 175 reg = <1>;
176 max-speed = <100>; 176 max-speed = <100>;
177 interrupt-parent = <&gpio5>; 177 interrupt-parent = <&gpio5>;
178 interrupts = <6 IRQ_TYPE_LEVEL_LOW 0>; 178 interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
179 }; 179 };
180 }; 180 };
181}; 181};
diff --git a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi
index 7b844f4ef06a..65111f9843f4 100644
--- a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi
@@ -424,7 +424,7 @@
424 display = <&display>; 424 display = <&display>;
425 status = "okay"; 425 status = "okay";
426 426
427 display: display@di0 { 427 display: disp0 {
428 bits-per-pixel = <32>; 428 bits-per-pixel = <32>;
429 bus-width = <24>; 429 bus-width = <24>;
430 status = "okay"; 430 status = "okay";
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index 2057ee695a66..d5181f85ca9c 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -598,6 +598,15 @@
598 fsl,anatop = <&anatop>; 598 fsl,anatop = <&anatop>;
599 }; 599 };
600 600
601 tempmon: tempmon {
602 compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
603 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
604 fsl,tempmon = <&anatop>;
605 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
606 nvmem-cell-names = "calib", "temp_grade";
607 clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
608 };
609
601 snvs: snvs@20cc000 { 610 snvs: snvs@20cc000 {
602 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 611 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
603 reg = <0x020cc000 0x4000>; 612 reg = <0x020cc000 0x4000>;
@@ -861,9 +870,19 @@
861 }; 870 };
862 871
863 ocotp: ocotp-ctrl@21bc000 { 872 ocotp: ocotp-ctrl@21bc000 {
873 #address-cells = <1>;
874 #size-cells = <1>;
864 compatible = "fsl,imx6ul-ocotp", "syscon"; 875 compatible = "fsl,imx6ul-ocotp", "syscon";
865 reg = <0x021bc000 0x4000>; 876 reg = <0x021bc000 0x4000>;
866 clocks = <&clks IMX6UL_CLK_OCOTP>; 877 clocks = <&clks IMX6UL_CLK_OCOTP>;
878
879 tempmon_calib: calib@38 {
880 reg = <0x38 4>;
881 };
882
883 tempmon_temp_grade: temp-grade@20 {
884 reg = <0x20 4>;
885 };
867 }; 886 };
868 887
869 lcdif: lcdif@21c8000 { 888 lcdif: lcdif@21c8000 {
diff --git a/arch/arm/boot/dts/imx7d-pico.dts b/arch/arm/boot/dts/imx7d-pico.dts
index 52a3df62b879..508328b2a6bf 100644
--- a/arch/arm/boot/dts/imx7d-pico.dts
+++ b/arch/arm/boot/dts/imx7d-pico.dts
@@ -52,6 +52,17 @@
52 reg = <0x80000000 0x80000000>; 52 reg = <0x80000000 0x80000000>;
53 }; 53 };
54 54
55 reg_ap6212: regulator-ap6212 {
56 compatible = "regulator-fixed";
57 pinctrl-names = "default";
58 pinctrl-0 = <&pinctrl_reg_ap6212>;
59 regulator-name = "AP6212";
60 regulator-min-microvolt = <3300000>;
61 regulator-max-microvolt = <3300000>;
62 gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
63 enable-active-high;
64 };
65
55 reg_2p5v: regulator-2p5v { 66 reg_2p5v: regulator-2p5v {
56 compatible = "regulator-fixed"; 67 compatible = "regulator-fixed";
57 regulator-name = "2P5V"; 68 regulator-name = "2P5V";
@@ -271,6 +282,17 @@
271 status = "okay"; 282 status = "okay";
272}; 283};
273 284
285&usdhc2 { /* Wifi SDIO */
286 pinctrl-names = "default";
287 pinctrl-0 = <&pinctrl_usdhc2>;
288 no-1-8-v;
289 non-removable;
290 keep-power-in-suspend;
291 wakeup-source;
292 vmmc-supply = <&reg_ap6212>;
293 status = "okay";
294};
295
274&usdhc3 { 296&usdhc3 {
275 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 297 pinctrl-names = "default", "state_100mhz", "state_200mhz";
276 pinctrl-0 = <&pinctrl_usdhc3>; 298 pinctrl-0 = <&pinctrl_usdhc3>;
@@ -326,6 +348,12 @@
326 >; 348 >;
327 }; 349 };
328 350
351 pinctrl_reg_ap6212: regap6212grp {
352 fsl,pins = <
353 MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x59
354 >;
355 };
356
329 pinctrl_sai1: sai1grp { 357 pinctrl_sai1: sai1grp {
330 fsl,pins = < 358 fsl,pins = <
331 MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f 359 MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f
@@ -348,6 +376,17 @@
348 >; 376 >;
349 }; 377 };
350 378
379 pinctrl_usdhc2: usdhc2grp {
380 fsl,pins = <
381 MX7D_PAD_SD2_CMD__SD2_CMD 0x59
382 MX7D_PAD_SD2_CLK__SD2_CLK 0x19
383 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
384 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
385 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
386 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
387 >;
388 };
389
351 pinctrl_usdhc3: usdhc3grp { 390 pinctrl_usdhc3: usdhc3grp {
352 fsl,pins = < 391 fsl,pins = <
353 MX7D_PAD_SD3_CMD__SD3_CMD 0x59 392 MX7D_PAD_SD3_CMD__SD3_CMD 0x59
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-28 19:19:17 -0400