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authorStephane Viau <sviau@codeaurora.org>2015-06-19 16:04:46 -0400
committerRob Clark <robdclark@gmail.com>2015-08-15 18:27:12 -0400
commitda32855219f86f27cad1b12be2264ffb0b97b9fa (patch)
treea685f61df2e77d23d438ebbcc13ff4362b57fdc0
parentdcefc117cc192f215d04c4e7cbae6b76a9bafcf4 (diff)
drm/msm/hdmi: remove ->reset() from HDMI PHY
->reset() currently only accesses HDMI core registers, and yet it is located in hdmi_phy*. Since no PHY registers are being accessed during ->reset(), it would be better to bring that function in hdmi core module where HDMI core registers are usually being accessed. This will also help for msm8x94 for which no PHY registers accesses are done (->phy_init == NULL) but the HDMI PHY reset from HDMI core still needs to be done. Note: SW_RESET_PLL bit is not written in hdmi_phy_8x60_reset(); this write should not affect anything if the corresponding field is not writable. Signed-off-by: Stephane Viau <sviau@codeaurora.org> [fixed warning about unused 'phy' in hpd_enable() while merging] Signed-off-by: Rob Clark <robdclark@gmail.com>
-rw-r--r--drivers/gpu/drm/msm/hdmi/hdmi.h1
-rw-r--r--drivers/gpu/drm/msm/hdmi/hdmi_connector.c52
-rw-r--r--drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c52
-rw-r--r--drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c32
-rw-r--r--drivers/gpu/drm/msm/hdmi/hdmi_phy_8x74.c57
5 files changed, 50 insertions, 144 deletions
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h b/drivers/gpu/drm/msm/hdmi/hdmi.h
index 588f7a648555..d0e663192d01 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.h
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.h
@@ -139,7 +139,6 @@ static inline u32 hdmi_qfprom_read(struct hdmi *hdmi, u32 reg)
139 139
140struct hdmi_phy_funcs { 140struct hdmi_phy_funcs {
141 void (*destroy)(struct hdmi_phy *phy); 141 void (*destroy)(struct hdmi_phy *phy);
142 void (*reset)(struct hdmi_phy *phy);
143 void (*powerup)(struct hdmi_phy *phy, unsigned long int pixclock); 142 void (*powerup)(struct hdmi_phy *phy, unsigned long int pixclock);
144 void (*powerdown)(struct hdmi_phy *phy); 143 void (*powerdown)(struct hdmi_phy *phy);
145}; 144};
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_connector.c b/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
index 3f345e7c341a..d83fd2dcb776 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
@@ -28,6 +28,55 @@ struct hdmi_connector {
28}; 28};
29#define to_hdmi_connector(x) container_of(x, struct hdmi_connector, base) 29#define to_hdmi_connector(x) container_of(x, struct hdmi_connector, base)
30 30
31static void hdmi_phy_reset(struct hdmi *hdmi)
32{
33 unsigned int val;
34
35 val = hdmi_read(hdmi, REG_HDMI_PHY_CTRL);
36
37 if (val & HDMI_PHY_CTRL_SW_RESET_LOW) {
38 /* pull low */
39 hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
40 val & ~HDMI_PHY_CTRL_SW_RESET);
41 } else {
42 /* pull high */
43 hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
44 val | HDMI_PHY_CTRL_SW_RESET);
45 }
46
47 if (val & HDMI_PHY_CTRL_SW_RESET_PLL_LOW) {
48 /* pull low */
49 hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
50 val & ~HDMI_PHY_CTRL_SW_RESET_PLL);
51 } else {
52 /* pull high */
53 hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
54 val | HDMI_PHY_CTRL_SW_RESET_PLL);
55 }
56
57 msleep(100);
58
59 if (val & HDMI_PHY_CTRL_SW_RESET_LOW) {
60 /* pull high */
61 hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
62 val | HDMI_PHY_CTRL_SW_RESET);
63 } else {
64 /* pull low */
65 hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
66 val & ~HDMI_PHY_CTRL_SW_RESET);
67 }
68
69 if (val & HDMI_PHY_CTRL_SW_RESET_PLL_LOW) {
70 /* pull high */
71 hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
72 val | HDMI_PHY_CTRL_SW_RESET_PLL);
73 } else {
74 /* pull low */
75 hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
76 val & ~HDMI_PHY_CTRL_SW_RESET_PLL);
77 }
78}
79
31static int gpio_config(struct hdmi *hdmi, bool on) 80static int gpio_config(struct hdmi *hdmi, bool on)
32{ 81{
33 struct device *dev = &hdmi->pdev->dev; 82 struct device *dev = &hdmi->pdev->dev;
@@ -138,7 +187,6 @@ static int hpd_enable(struct hdmi_connector *hdmi_connector)
138 struct hdmi *hdmi = hdmi_connector->hdmi; 187 struct hdmi *hdmi = hdmi_connector->hdmi;
139 const struct hdmi_platform_config *config = hdmi->config; 188 const struct hdmi_platform_config *config = hdmi->config;
140 struct device *dev = &hdmi->pdev->dev; 189 struct device *dev = &hdmi->pdev->dev;
141 struct hdmi_phy *phy = hdmi->phy;
142 uint32_t hpd_ctrl; 190 uint32_t hpd_ctrl;
143 int i, ret; 191 int i, ret;
144 unsigned long flags; 192 unsigned long flags;
@@ -182,7 +230,7 @@ static int hpd_enable(struct hdmi_connector *hdmi_connector)
182 } 230 }
183 231
184 hdmi_set_mode(hdmi, false); 232 hdmi_set_mode(hdmi, false);
185 phy->funcs->reset(phy); 233 hdmi_phy_reset(hdmi);
186 hdmi_set_mode(hdmi, true); 234 hdmi_set_mode(hdmi, true);
187 235
188 hdmi_write(hdmi, REG_HDMI_USEC_REFTIMER, 0x0001001b); 236 hdmi_write(hdmi, REG_HDMI_USEC_REFTIMER, 0x0001001b);
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c
index 6997ec636c6d..3a01cb5051e2 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c
@@ -426,57 +426,6 @@ static void hdmi_phy_8960_destroy(struct hdmi_phy *phy)
426 kfree(phy_8960); 426 kfree(phy_8960);
427} 427}
428 428
429static void hdmi_phy_8960_reset(struct hdmi_phy *phy)
430{
431 struct hdmi_phy_8960 *phy_8960 = to_hdmi_phy_8960(phy);
432 struct hdmi *hdmi = phy_8960->hdmi;
433 unsigned int val;
434
435 val = hdmi_read(hdmi, REG_HDMI_PHY_CTRL);
436
437 if (val & HDMI_PHY_CTRL_SW_RESET_LOW) {
438 /* pull low */
439 hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
440 val & ~HDMI_PHY_CTRL_SW_RESET);
441 } else {
442 /* pull high */
443 hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
444 val | HDMI_PHY_CTRL_SW_RESET);
445 }
446
447 if (val & HDMI_PHY_CTRL_SW_RESET_PLL_LOW) {
448 /* pull low */
449 hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
450 val & ~HDMI_PHY_CTRL_SW_RESET_PLL);
451 } else {
452 /* pull high */
453 hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
454 val | HDMI_PHY_CTRL_SW_RESET_PLL);
455 }
456
457 msleep(100);
458
459 if (val & HDMI_PHY_CTRL_SW_RESET_LOW) {
460 /* pull high */
461 hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
462 val | HDMI_PHY_CTRL_SW_RESET);
463 } else {
464 /* pull low */
465 hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
466 val & ~HDMI_PHY_CTRL_SW_RESET);
467 }
468
469 if (val & HDMI_PHY_CTRL_SW_RESET_PLL_LOW) {
470 /* pull high */
471 hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
472 val | HDMI_PHY_CTRL_SW_RESET_PLL);
473 } else {
474 /* pull low */
475 hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
476 val & ~HDMI_PHY_CTRL_SW_RESET_PLL);
477 }
478}
479
480static void hdmi_phy_8960_powerup(struct hdmi_phy *phy, 429static void hdmi_phy_8960_powerup(struct hdmi_phy *phy,
481 unsigned long int pixclock) 430 unsigned long int pixclock)
482{ 431{
@@ -511,7 +460,6 @@ static void hdmi_phy_8960_powerdown(struct hdmi_phy *phy)
511 460
512static const struct hdmi_phy_funcs hdmi_phy_8960_funcs = { 461static const struct hdmi_phy_funcs hdmi_phy_8960_funcs = {
513 .destroy = hdmi_phy_8960_destroy, 462 .destroy = hdmi_phy_8960_destroy,
514 .reset = hdmi_phy_8960_reset,
515 .powerup = hdmi_phy_8960_powerup, 463 .powerup = hdmi_phy_8960_powerup,
516 .powerdown = hdmi_phy_8960_powerdown, 464 .powerdown = hdmi_phy_8960_powerdown,
517}; 465};
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c
index 391433c1af7c..cb01421ae1e4 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c
@@ -29,37 +29,6 @@ static void hdmi_phy_8x60_destroy(struct hdmi_phy *phy)
29 kfree(phy_8x60); 29 kfree(phy_8x60);
30} 30}
31 31
32static void hdmi_phy_8x60_reset(struct hdmi_phy *phy)
33{
34 struct hdmi_phy_8x60 *phy_8x60 = to_hdmi_phy_8x60(phy);
35 struct hdmi *hdmi = phy_8x60->hdmi;
36 unsigned int val;
37
38 val = hdmi_read(hdmi, REG_HDMI_PHY_CTRL);
39
40 if (val & HDMI_PHY_CTRL_SW_RESET_LOW) {
41 /* pull low */
42 hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
43 val & ~HDMI_PHY_CTRL_SW_RESET);
44 } else {
45 /* pull high */
46 hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
47 val | HDMI_PHY_CTRL_SW_RESET);
48 }
49
50 msleep(100);
51
52 if (val & HDMI_PHY_CTRL_SW_RESET_LOW) {
53 /* pull high */
54 hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
55 val | HDMI_PHY_CTRL_SW_RESET);
56 } else {
57 /* pull low */
58 hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
59 val & ~HDMI_PHY_CTRL_SW_RESET);
60 }
61}
62
63static void hdmi_phy_8x60_powerup(struct hdmi_phy *phy, 32static void hdmi_phy_8x60_powerup(struct hdmi_phy *phy,
64 unsigned long int pixclock) 33 unsigned long int pixclock)
65{ 34{
@@ -182,7 +151,6 @@ static void hdmi_phy_8x60_powerdown(struct hdmi_phy *phy)
182 151
183static const struct hdmi_phy_funcs hdmi_phy_8x60_funcs = { 152static const struct hdmi_phy_funcs hdmi_phy_8x60_funcs = {
184 .destroy = hdmi_phy_8x60_destroy, 153 .destroy = hdmi_phy_8x60_destroy,
185 .reset = hdmi_phy_8x60_reset,
186 .powerup = hdmi_phy_8x60_powerup, 154 .powerup = hdmi_phy_8x60_powerup,
187 .powerdown = hdmi_phy_8x60_powerdown, 155 .powerdown = hdmi_phy_8x60_powerdown,
188}; 156};
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8x74.c b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8x74.c
index 59fa6cdacb2a..56ab8917ee9a 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8x74.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8x74.c
@@ -19,7 +19,6 @@
19 19
20struct hdmi_phy_8x74 { 20struct hdmi_phy_8x74 {
21 struct hdmi_phy base; 21 struct hdmi_phy base;
22 struct hdmi *hdmi;
23 void __iomem *mmio; 22 void __iomem *mmio;
24}; 23};
25#define to_hdmi_phy_8x74(x) container_of(x, struct hdmi_phy_8x74, base) 24#define to_hdmi_phy_8x74(x) container_of(x, struct hdmi_phy_8x74, base)
@@ -41,59 +40,6 @@ static void hdmi_phy_8x74_destroy(struct hdmi_phy *phy)
41 kfree(phy_8x74); 40 kfree(phy_8x74);
42} 41}
43 42
44static void hdmi_phy_8x74_reset(struct hdmi_phy *phy)
45{
46 struct hdmi_phy_8x74 *phy_8x74 = to_hdmi_phy_8x74(phy);
47 struct hdmi *hdmi = phy_8x74->hdmi;
48 unsigned int val;
49
50 /* NOTE that HDMI_PHY_CTL is in core mmio, not phy mmio: */
51
52 val = hdmi_read(hdmi, REG_HDMI_PHY_CTRL);
53
54 if (val & HDMI_PHY_CTRL_SW_RESET_LOW) {
55 /* pull low */
56 hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
57 val & ~HDMI_PHY_CTRL_SW_RESET);
58 } else {
59 /* pull high */
60 hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
61 val | HDMI_PHY_CTRL_SW_RESET);
62 }
63
64 if (val & HDMI_PHY_CTRL_SW_RESET_PLL_LOW) {
65 /* pull low */
66 hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
67 val & ~HDMI_PHY_CTRL_SW_RESET_PLL);
68 } else {
69 /* pull high */
70 hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
71 val | HDMI_PHY_CTRL_SW_RESET_PLL);
72 }
73
74 msleep(100);
75
76 if (val & HDMI_PHY_CTRL_SW_RESET_LOW) {
77 /* pull high */
78 hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
79 val | HDMI_PHY_CTRL_SW_RESET);
80 } else {
81 /* pull low */
82 hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
83 val & ~HDMI_PHY_CTRL_SW_RESET);
84 }
85
86 if (val & HDMI_PHY_CTRL_SW_RESET_PLL_LOW) {
87 /* pull high */
88 hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
89 val | HDMI_PHY_CTRL_SW_RESET_PLL);
90 } else {
91 /* pull low */
92 hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
93 val & ~HDMI_PHY_CTRL_SW_RESET_PLL);
94 }
95}
96
97static void hdmi_phy_8x74_powerup(struct hdmi_phy *phy, 43static void hdmi_phy_8x74_powerup(struct hdmi_phy *phy,
98 unsigned long int pixclock) 44 unsigned long int pixclock)
99{ 45{
@@ -117,7 +63,6 @@ static void hdmi_phy_8x74_powerdown(struct hdmi_phy *phy)
117 63
118static const struct hdmi_phy_funcs hdmi_phy_8x74_funcs = { 64static const struct hdmi_phy_funcs hdmi_phy_8x74_funcs = {
119 .destroy = hdmi_phy_8x74_destroy, 65 .destroy = hdmi_phy_8x74_destroy,
120 .reset = hdmi_phy_8x74_reset,
121 .powerup = hdmi_phy_8x74_powerup, 66 .powerup = hdmi_phy_8x74_powerup,
122 .powerdown = hdmi_phy_8x74_powerdown, 67 .powerdown = hdmi_phy_8x74_powerdown,
123}; 68};
@@ -138,8 +83,6 @@ struct hdmi_phy *hdmi_phy_8x74_init(struct hdmi *hdmi)
138 83
139 phy->funcs = &hdmi_phy_8x74_funcs; 84 phy->funcs = &hdmi_phy_8x74_funcs;
140 85
141 phy_8x74->hdmi = hdmi;
142
143 /* for 8x74, the phy mmio is mapped separately: */ 86 /* for 8x74, the phy mmio is mapped separately: */
144 phy_8x74->mmio = msm_ioremap(hdmi->pdev, 87 phy_8x74->mmio = msm_ioremap(hdmi->pdev,
145 "phy_physical", "HDMI_8x74"); 88 "phy_physical", "HDMI_8x74");