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authorAndy Shevchenko <andriy.shevchenko@linux.intel.com>2015-01-22 10:59:34 -0500
committerMark Brown <broonie@kernel.org>2015-01-27 07:04:29 -0500
commitd9c14743a330315b6e2186cafc4812fe91a1fa8f (patch)
tree40622433c4f5fd1676e4ea4917e898f0afc34069
parentd58cf5ff6500522880683ce90d9caa79af385ed8 (diff)
spi: dw-mid: get a proper clock frequency for SPI2
The clock information is being kept in the custom register on Intel MID platforms. Each controller has its own dedicated custom register for that. Thus, to get a proper frequency we have to read value from the specific offset to the register block. This patch makes this happen. Fixes: d58cf5ff6500 (spi: dw-pci: describe Intel MID controllers better) Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r--drivers/spi/spi-dw-mid.c13
-rw-r--r--drivers/spi/spi-dw-pci.c6
2 files changed, 11 insertions, 8 deletions
diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-mid.c
index 47a8e65feafd..a0197fd4e95c 100644
--- a/drivers/spi/spi-dw-mid.c
+++ b/drivers/spi/spi-dw-mid.c
@@ -247,9 +247,9 @@ static struct dw_spi_dma_ops mid_dma_ops = {
247 247
248/* Some specific info for SPI0 controller on Intel MID */ 248/* Some specific info for SPI0 controller on Intel MID */
249 249
250/* HW info for MRST CLk Control Unit, one 32b reg */ 250/* HW info for MRST Clk Control Unit, 32b reg per controller */
251#define MRST_SPI_CLK_BASE 100000000 /* 100m */ 251#define MRST_SPI_CLK_BASE 100000000 /* 100m */
252#define MRST_CLK_SPI0_REG 0xff11d86c 252#define MRST_CLK_SPI_REG 0xff11d86c
253#define CLK_SPI_BDIV_OFFSET 0 253#define CLK_SPI_BDIV_OFFSET 0
254#define CLK_SPI_BDIV_MASK 0x00000007 254#define CLK_SPI_BDIV_MASK 0x00000007
255#define CLK_SPI_CDIV_OFFSET 9 255#define CLK_SPI_CDIV_OFFSET 9
@@ -261,13 +261,16 @@ int dw_spi_mid_init(struct dw_spi *dws)
261 void __iomem *clk_reg; 261 void __iomem *clk_reg;
262 u32 clk_cdiv; 262 u32 clk_cdiv;
263 263
264 clk_reg = ioremap_nocache(MRST_CLK_SPI0_REG, 16); 264 clk_reg = ioremap_nocache(MRST_CLK_SPI_REG, 16);
265 if (!clk_reg) 265 if (!clk_reg)
266 return -ENOMEM; 266 return -ENOMEM;
267 267
268 /* get SPI controller operating freq info */ 268 /* Get SPI controller operating freq info */
269 clk_cdiv = (readl(clk_reg) & CLK_SPI_CDIV_MASK) >> CLK_SPI_CDIV_OFFSET; 269 clk_cdiv = readl(clk_reg + dws->bus_num * sizeof(u32));
270 clk_cdiv &= CLK_SPI_CDIV_MASK;
271 clk_cdiv >>= CLK_SPI_CDIV_OFFSET;
270 dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1); 272 dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
273
271 iounmap(clk_reg); 274 iounmap(clk_reg);
272 275
273#ifdef CONFIG_SPI_DW_MID_DMA 276#ifdef CONFIG_SPI_DW_MID_DMA
diff --git a/drivers/spi/spi-dw-pci.c b/drivers/spi/spi-dw-pci.c
index 64f3efaf2472..5ba331047cbe 100644
--- a/drivers/spi/spi-dw-pci.c
+++ b/drivers/spi/spi-dw-pci.c
@@ -82,14 +82,14 @@ static int spi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
82 * clock rate, FIFO depth. 82 * clock rate, FIFO depth.
83 */ 83 */
84 if (desc) { 84 if (desc) {
85 dws->num_cs = desc->num_cs;
86 dws->bus_num = desc->bus_num;
87
85 if (desc->setup) { 88 if (desc->setup) {
86 ret = desc->setup(dws); 89 ret = desc->setup(dws);
87 if (ret) 90 if (ret)
88 return ret; 91 return ret;
89 } 92 }
90
91 dws->num_cs = desc->num_cs;
92 dws->bus_num = desc->bus_num;
93 } else { 93 } else {
94 return -ENODEV; 94 return -ENODEV;
95 } 95 }