diff options
author | Joao Pinto <Joao.Pinto@synopsys.com> | 2016-08-17 14:26:07 -0400 |
---|---|---|
committer | Bjorn Helgaas <bhelgaas@google.com> | 2016-08-17 15:43:41 -0400 |
commit | d8bbeb39fbf3ff06b6adae9d336f44bee4e3f3ec (patch) | |
tree | ced1d20fcf583996ac48bf4b1e92357d0d357738 | |
parent | c388de1c4f0e5da3e96b49efb0388e2a0d34e079 (diff) |
PCI: designware: Wait for iATU enable
Add a loop with timeout to make sure the iATU is really enabled before
subsequent config and I/O accesses.
[bhelgaas: split to separate patch, use dev_err() instead of dev_dbg()]
Signed-off-by: Joao Pinto <jpinto@synopsys.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-rw-r--r-- | drivers/pci/host/pcie-designware.c | 18 |
1 files changed, 15 insertions, 3 deletions
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index e99f56ecd61d..947fac37cf1b 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c | |||
@@ -31,7 +31,12 @@ | |||
31 | #define LINK_WAIT_USLEEP_MIN 90000 | 31 | #define LINK_WAIT_USLEEP_MIN 90000 |
32 | #define LINK_WAIT_USLEEP_MAX 100000 | 32 | #define LINK_WAIT_USLEEP_MAX 100000 |
33 | 33 | ||
34 | /* Synopsis specific PCIE configuration registers */ | 34 | /* Parameters for the waiting for iATU enabled routine */ |
35 | #define LINK_WAIT_MAX_IATU_RETRIES 5 | ||
36 | #define LINK_WAIT_IATU_MIN 9000 | ||
37 | #define LINK_WAIT_IATU_MAX 10000 | ||
38 | |||
39 | /* Synopsys-specific PCIe configuration registers */ | ||
35 | #define PCIE_PORT_LINK_CONTROL 0x710 | 40 | #define PCIE_PORT_LINK_CONTROL 0x710 |
36 | #define PORT_LINK_MODE_MASK (0x3f << 16) | 41 | #define PORT_LINK_MODE_MASK (0x3f << 16) |
37 | #define PORT_LINK_MODE_1_LANES (0x1 << 16) | 42 | #define PORT_LINK_MODE_1_LANES (0x1 << 16) |
@@ -157,7 +162,7 @@ static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, | |||
157 | static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index, | 162 | static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index, |
158 | int type, u64 cpu_addr, u64 pci_addr, u32 size) | 163 | int type, u64 cpu_addr, u64 pci_addr, u32 size) |
159 | { | 164 | { |
160 | u32 val; | 165 | u32 retries, val; |
161 | 166 | ||
162 | dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | index, | 167 | dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | index, |
163 | PCIE_ATU_VIEWPORT); | 168 | PCIE_ATU_VIEWPORT); |
@@ -174,7 +179,14 @@ static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index, | |||
174 | * Make sure ATU enable takes effect before any subsequent config | 179 | * Make sure ATU enable takes effect before any subsequent config |
175 | * and I/O accesses. | 180 | * and I/O accesses. |
176 | */ | 181 | */ |
177 | val = dw_pcie_readl_rc(pp, PCIE_ATU_CR2); | 182 | for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { |
183 | val = dw_pcie_readl_rc(pp, PCIE_ATU_CR2); | ||
184 | if (val == PCIE_ATU_ENABLE) | ||
185 | return; | ||
186 | |||
187 | usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX); | ||
188 | } | ||
189 | dev_err(pp->dev, "iATU is not being enabled\n"); | ||
178 | } | 190 | } |
179 | 191 | ||
180 | static struct irq_chip dw_msi_irq_chip = { | 192 | static struct irq_chip dw_msi_irq_chip = { |