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authorSekhar Nori <nsekhar@ti.com>2016-12-13 06:29:45 -0500
committerTony Lindgren <tony@atomide.com>2017-01-05 11:53:46 -0500
commitd888e9d7833715e1122ba7641469b80398cec7e4 (patch)
tree74d666f3d5044f80196205237bcfddbb9bee934b
parentca244a83ecc7f0a9242ee2116e622cb6d7ec2a90 (diff)
ARM: dts: dra7-evm: Remove pinmux configurations for erratum i869
Pinmuxing for DRA7x/AM57x family of processors need to be done in IO isolation as part of initial bootloader executed from SRAM. This is done as part of iodelay configuration sequence and is required due to the limitations introduced by erratum ID: i869[1] (IO Glitches can occur when changing IO settings) and elaborated in the Technical Reference Manual[2] 18.4.6.1.7 Isolation Requirements. Only peripheral that is permitted for dynamic pin mux configuration is MMC and DCAN. MMC is permitted to change to accommodate the requirements for varied speeds (which require IO-delay support in kernel as well). DCAN is a result of i893[1] (DCAN initialization sequence). DCAN pinmux is retained in this patch. MMC pinmux is missing from the dra7-evm.dts file and the board is relying on configuration done by bootloader. A subsequent patch will add MMC pinmux configuration. A side-effect of this patch is that NAND support is removed. NAND pins clash with VOUT3 on DRA7-EVM. U-Boot selects VOUT3 over NAND as per TI EVM application needs. [1] http://www.ti.com/lit/pdf/sprz429 [2] http://www.ti.com/lit/pdf/sprui30 Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat
-rw-r--r--arch/arm/boot/dts/dra7-evm.dts267
1 files changed, 6 insertions, 261 deletions
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 132f2be10889..80ebfd6a5c7b 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -151,204 +151,6 @@
151}; 151};
152 152
153&dra7_pmx_core { 153&dra7_pmx_core {
154 pinctrl-names = "default";
155 pinctrl-0 = <&vtt_pin>;
156
157 vtt_pin: pinmux_vtt_pin {
158 pinctrl-single,pins = <
159 DRA7XX_CORE_IOPAD(0x37b4, PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
160 >;
161 };
162
163 i2c1_pins: pinmux_i2c1_pins {
164 pinctrl-single,pins = <
165 DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT | MUX_MODE0) /* i2c1_sda */
166 DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT | MUX_MODE0) /* i2c1_scl */
167 >;
168 };
169
170 i2c2_pins: pinmux_i2c2_pins {
171 pinctrl-single,pins = <
172 DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE0) /* i2c2_sda */
173 DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE0) /* i2c2_scl */
174 >;
175 };
176
177 i2c3_pins: pinmux_i2c3_pins {
178 pinctrl-single,pins = <
179 DRA7XX_CORE_IOPAD(0x3688, PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
180 DRA7XX_CORE_IOPAD(0x368c, PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
181 >;
182 };
183
184 mcspi1_pins: pinmux_mcspi1_pins {
185 pinctrl-single,pins = <
186 DRA7XX_CORE_IOPAD(0x37a4, PIN_INPUT | MUX_MODE0) /* spi1_sclk */
187 DRA7XX_CORE_IOPAD(0x37a8, PIN_INPUT | MUX_MODE0) /* spi1_d1 */
188 DRA7XX_CORE_IOPAD(0x37ac, PIN_INPUT | MUX_MODE0) /* spi1_d0 */
189 DRA7XX_CORE_IOPAD(0x37b0, PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
190 DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
191 DRA7XX_CORE_IOPAD(0x37bc, PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
192 >;
193 };
194
195 mcspi2_pins: pinmux_mcspi2_pins {
196 pinctrl-single,pins = <
197 DRA7XX_CORE_IOPAD(0x37c0, PIN_INPUT | MUX_MODE0) /* spi2_sclk */
198 DRA7XX_CORE_IOPAD(0x37c4, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
199 DRA7XX_CORE_IOPAD(0x37c8, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
200 DRA7XX_CORE_IOPAD(0x37cc, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
201 >;
202 };
203
204 uart1_pins: pinmux_uart1_pins {
205 pinctrl-single,pins = <
206 DRA7XX_CORE_IOPAD(0x37e0, PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
207 DRA7XX_CORE_IOPAD(0x37e4, PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
208 DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
209 DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
210 >;
211 };
212
213 uart2_pins: pinmux_uart2_pins {
214 pinctrl-single,pins = <
215 DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT | MUX_MODE0) /* uart2_rxd */
216 DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT | MUX_MODE0) /* uart2_txd */
217 DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
218 DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
219 >;
220 };
221
222 uart3_pins: pinmux_uart3_pins {
223 pinctrl-single,pins = <
224 DRA7XX_CORE_IOPAD(0x3648, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
225 DRA7XX_CORE_IOPAD(0x364c, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
226 >;
227 };
228
229 usb1_pins: pinmux_usb1_pins {
230 pinctrl-single,pins = <
231 DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
232 >;
233 };
234
235 usb2_pins: pinmux_usb2_pins {
236 pinctrl-single,pins = <
237 DRA7XX_CORE_IOPAD(0x3684, PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
238 >;
239 };
240
241 nand_flash_x16: nand_flash_x16 {
242 /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
243 * So NAND flash requires following switch settings:
244 * SW5.1 (NAND_BOOTn) = ON (LOW)
245 * SW5.9 (GPMC_WPN) = OFF (HIGH)
246 */
247 pinctrl-single,pins = <
248 DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
249 DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
250 DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
251 DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
252 DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
253 DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
254 DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
255 DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
256 DRA7XX_CORE_IOPAD(0x3420, PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
257 DRA7XX_CORE_IOPAD(0x3424, PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
258 DRA7XX_CORE_IOPAD(0x3428, PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
259 DRA7XX_CORE_IOPAD(0x342c, PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
260 DRA7XX_CORE_IOPAD(0x3430, PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
261 DRA7XX_CORE_IOPAD(0x3434, PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
262 DRA7XX_CORE_IOPAD(0x3438, PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
263 DRA7XX_CORE_IOPAD(0x343c, PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
264 DRA7XX_CORE_IOPAD(0x34d8, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */
265 DRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
266 DRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */
267 DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
268 DRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
269 DRA7XX_CORE_IOPAD(0x34d0, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */
270 >;
271 };
272
273 cpsw_default: cpsw_default {
274 pinctrl-single,pins = <
275 /* Slave 1 */
276 DRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */
277 DRA7XX_CORE_IOPAD(0x3654, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */
278 DRA7XX_CORE_IOPAD(0x3658, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */
279 DRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */
280 DRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */
281 DRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */
282 DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */
283 DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */
284 DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */
285 DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */
286 DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */
287 DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */
288
289 /* Slave 2 */
290 DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
291 DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
292 DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
293 DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
294 DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
295 DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
296 DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
297 DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
298 DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
299 DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
300 DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
301 DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
302 >;
303
304 };
305
306 cpsw_sleep: cpsw_sleep {
307 pinctrl-single,pins = <
308 /* Slave 1 */
309 DRA7XX_CORE_IOPAD(0x3650, MUX_MODE15)
310 DRA7XX_CORE_IOPAD(0x3654, MUX_MODE15)
311 DRA7XX_CORE_IOPAD(0x3658, MUX_MODE15)
312 DRA7XX_CORE_IOPAD(0x365c, MUX_MODE15)
313 DRA7XX_CORE_IOPAD(0x3660, MUX_MODE15)
314 DRA7XX_CORE_IOPAD(0x3664, MUX_MODE15)
315 DRA7XX_CORE_IOPAD(0x3668, MUX_MODE15)
316 DRA7XX_CORE_IOPAD(0x366c, MUX_MODE15)
317 DRA7XX_CORE_IOPAD(0x3670, MUX_MODE15)
318 DRA7XX_CORE_IOPAD(0x3674, MUX_MODE15)
319 DRA7XX_CORE_IOPAD(0x3678, MUX_MODE15)
320 DRA7XX_CORE_IOPAD(0x367c, MUX_MODE15)
321
322 /* Slave 2 */
323 DRA7XX_CORE_IOPAD(0x3598, MUX_MODE15)
324 DRA7XX_CORE_IOPAD(0x359c, MUX_MODE15)
325 DRA7XX_CORE_IOPAD(0x35a0, MUX_MODE15)
326 DRA7XX_CORE_IOPAD(0x35a4, MUX_MODE15)
327 DRA7XX_CORE_IOPAD(0x35a8, MUX_MODE15)
328 DRA7XX_CORE_IOPAD(0x35ac, MUX_MODE15)
329 DRA7XX_CORE_IOPAD(0x35b0, MUX_MODE15)
330 DRA7XX_CORE_IOPAD(0x35b4, MUX_MODE15)
331 DRA7XX_CORE_IOPAD(0x35b8, MUX_MODE15)
332 DRA7XX_CORE_IOPAD(0x35bc, MUX_MODE15)
333 DRA7XX_CORE_IOPAD(0x35c0, MUX_MODE15)
334 DRA7XX_CORE_IOPAD(0x35c4, MUX_MODE15)
335 >;
336 };
337
338 davinci_mdio_default: davinci_mdio_default {
339 pinctrl-single,pins = <
340 DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
341 DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
342 >;
343 };
344
345 davinci_mdio_sleep: davinci_mdio_sleep {
346 pinctrl-single,pins = <
347 DRA7XX_CORE_IOPAD(0x363c, MUX_MODE15)
348 DRA7XX_CORE_IOPAD(0x3640, MUX_MODE15)
349 >;
350 };
351
352 dcan1_pins_default: dcan1_pins_default { 154 dcan1_pins_default: dcan1_pins_default {
353 pinctrl-single,pins = < 155 pinctrl-single,pins = <
354 DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ 156 DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
@@ -362,37 +164,10 @@
362 DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */ 164 DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
363 >; 165 >;
364 }; 166 };
365
366 atl_pins: pinmux_atl_pins {
367 pinctrl-single,pins = <
368 DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */
369 DRA7XX_CORE_IOPAD(0x369c, PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */
370 >;
371 };
372
373 mcasp3_pins: pinmux_mcasp3_pins {
374 pinctrl-single,pins = <
375 DRA7XX_CORE_IOPAD(0x3724, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */
376 DRA7XX_CORE_IOPAD(0x3728, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */
377 DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */
378 DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */
379 >;
380 };
381
382 mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins {
383 pinctrl-single,pins = <
384 DRA7XX_CORE_IOPAD(0x3724, MUX_MODE15)
385 DRA7XX_CORE_IOPAD(0x3728, MUX_MODE15)
386 DRA7XX_CORE_IOPAD(0x372c, MUX_MODE15)
387 DRA7XX_CORE_IOPAD(0x3730, MUX_MODE15)
388 >;
389 };
390}; 167};
391 168
392&i2c1 { 169&i2c1 {
393 status = "okay"; 170 status = "okay";
394 pinctrl-names = "default";
395 pinctrl-0 = <&i2c1_pins>;
396 clock-frequency = <400000>; 171 clock-frequency = <400000>;
397 172
398 tps659038: tps659038@58 { 173 tps659038: tps659038@58 {
@@ -581,8 +356,6 @@
581 356
582&i2c2 { 357&i2c2 {
583 status = "okay"; 358 status = "okay";
584 pinctrl-names = "default";
585 pinctrl-0 = <&i2c2_pins>;
586 clock-frequency = <400000>; 359 clock-frequency = <400000>;
587 360
588 pcf_hdmi: gpio@26 { 361 pcf_hdmi: gpio@26 {
@@ -602,41 +375,29 @@
602 375
603&i2c3 { 376&i2c3 {
604 status = "okay"; 377 status = "okay";
605 pinctrl-names = "default";
606 pinctrl-0 = <&i2c3_pins>;
607 clock-frequency = <400000>; 378 clock-frequency = <400000>;
608}; 379};
609 380
610&mcspi1 { 381&mcspi1 {
611 status = "okay"; 382 status = "okay";
612 pinctrl-names = "default";
613 pinctrl-0 = <&mcspi1_pins>;
614}; 383};
615 384
616&mcspi2 { 385&mcspi2 {
617 status = "okay"; 386 status = "okay";
618 pinctrl-names = "default";
619 pinctrl-0 = <&mcspi2_pins>;
620}; 387};
621 388
622&uart1 { 389&uart1 {
623 status = "okay"; 390 status = "okay";
624 pinctrl-names = "default";
625 pinctrl-0 = <&uart1_pins>;
626 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 391 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
627 <&dra7_pmx_core 0x3e0>; 392 <&dra7_pmx_core 0x3e0>;
628}; 393};
629 394
630&uart2 { 395&uart2 {
631 status = "okay"; 396 status = "okay";
632 pinctrl-names = "default";
633 pinctrl-0 = <&uart2_pins>;
634}; 397};
635 398
636&uart3 { 399&uart3 {
637 status = "okay"; 400 status = "okay";
638 pinctrl-names = "default";
639 pinctrl-0 = <&uart3_pins>;
640}; 401};
641 402
642&mmc1 { 403&mmc1 {
@@ -732,14 +493,10 @@
732 493
733&usb1 { 494&usb1 {
734 dr_mode = "peripheral"; 495 dr_mode = "peripheral";
735 pinctrl-names = "default";
736 pinctrl-0 = <&usb1_pins>;
737}; 496};
738 497
739&usb2 { 498&usb2 {
740 dr_mode = "host"; 499 dr_mode = "host";
741 pinctrl-names = "default";
742 pinctrl-0 = <&usb2_pins>;
743}; 500};
744 501
745&elm { 502&elm {
@@ -747,9 +504,12 @@
747}; 504};
748 505
749&gpmc { 506&gpmc {
750 status = "okay"; 507 /*
751 pinctrl-names = "default"; 508 * For the existing IOdelay configuration via U-Boot we don't
752 pinctrl-0 = <&nand_flash_x16>; 509 * support NAND on dra7-evm. Keep it disabled. Enabling it
510 * requires a different configuration by U-Boot.
511 */
512 status = "disabled";
753 ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ 513 ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
754 nand@0,0 { 514 nand@0,0 {
755 compatible = "ti,omap2-nand"; 515 compatible = "ti,omap2-nand";
@@ -845,9 +605,6 @@
845 605
846&mac { 606&mac {
847 status = "okay"; 607 status = "okay";
848 pinctrl-names = "default", "sleep";
849 pinctrl-0 = <&cpsw_default>;
850 pinctrl-1 = <&cpsw_sleep>;
851 dual_emac; 608 dual_emac;
852}; 609};
853 610
@@ -863,12 +620,6 @@
863 dual_emac_res_vlan = <2>; 620 dual_emac_res_vlan = <2>;
864}; 621};
865 622
866&davinci_mdio {
867 pinctrl-names = "default", "sleep";
868 pinctrl-0 = <&davinci_mdio_default>;
869 pinctrl-1 = <&davinci_mdio_sleep>;
870};
871
872&dcan1 { 623&dcan1 {
873 status = "ok"; 624 status = "ok";
874 pinctrl-names = "default", "sleep", "active"; 625 pinctrl-names = "default", "sleep", "active";
@@ -878,9 +629,6 @@
878}; 629};
879 630
880&atl { 631&atl {
881 pinctrl-names = "default";
882 pinctrl-0 = <&atl_pins>;
883
884 assigned-clocks = <&abe_dpll_sys_clk_mux>, 632 assigned-clocks = <&abe_dpll_sys_clk_mux>,
885 <&atl_gfclk_mux>, 633 <&atl_gfclk_mux>,
886 <&dpll_abe_ck>, 634 <&dpll_abe_ck>,
@@ -899,9 +647,6 @@
899 647
900&mcasp3 { 648&mcasp3 {
901 #sound-dai-cells = <0>; 649 #sound-dai-cells = <0>;
902 pinctrl-names = "default", "sleep";
903 pinctrl-0 = <&mcasp3_pins>;
904 pinctrl-1 = <&mcasp3_sleep_pins>;
905 650
906 assigned-clocks = <&mcasp3_ahclkx_mux>; 651 assigned-clocks = <&mcasp3_ahclkx_mux>;
907 assigned-clock-parents = <&atl_clkin2_ck>; 652 assigned-clock-parents = <&atl_clkin2_ck>;
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-21 20:04:46 -0400