diff options
author | Chen-Yu Tsai <wens@csie.org> | 2017-05-31 03:58:23 -0400 |
---|---|---|
committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2017-05-31 15:57:30 -0400 |
commit | d85da227c3ae43d9ca513d60f244213cb4e55485 (patch) | |
tree | e79a871a9911bf02179fdd86ea6f65549b7f6344 | |
parent | c4be8c68e6900b1811bc64f74cb13d5032a389ce (diff) |
clk: sunxi-ng: a64: Export PLL_PERIPH0 clock for the PRCM
The PRCM takes PLL_PERIPH0 as one of its parents for the AR100 clock.
As such we need to be able to describe this relationship in the device
tree.
Export the PLL_PERIPH0 clock so we can reference it in the PRCM node.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-rw-r--r-- | drivers/clk/sunxi-ng/ccu-sun50i-a64.h | 4 | ||||
-rw-r--r-- | include/dt-bindings/clock/sun50i-a64-ccu.h | 2 |
2 files changed, 5 insertions, 1 deletions
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.h b/drivers/clk/sunxi-ng/ccu-sun50i-a64.h index 9b3cd24b78d2..061b6fbb4f95 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.h +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.h | |||
@@ -31,7 +31,9 @@ | |||
31 | #define CLK_PLL_VIDEO0_2X 8 | 31 | #define CLK_PLL_VIDEO0_2X 8 |
32 | #define CLK_PLL_VE 9 | 32 | #define CLK_PLL_VE 9 |
33 | #define CLK_PLL_DDR0 10 | 33 | #define CLK_PLL_DDR0 10 |
34 | #define CLK_PLL_PERIPH0 11 | 34 | |
35 | /* PLL_PERIPH0 exported for PRCM */ | ||
36 | |||
35 | #define CLK_PLL_PERIPH0_2X 12 | 37 | #define CLK_PLL_PERIPH0_2X 12 |
36 | #define CLK_PLL_PERIPH1 13 | 38 | #define CLK_PLL_PERIPH1 13 |
37 | #define CLK_PLL_PERIPH1_2X 14 | 39 | #define CLK_PLL_PERIPH1_2X 14 |
diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h index 370c0a0473fc..d66432c6e675 100644 --- a/include/dt-bindings/clock/sun50i-a64-ccu.h +++ b/include/dt-bindings/clock/sun50i-a64-ccu.h | |||
@@ -43,6 +43,8 @@ | |||
43 | #ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_ | 43 | #ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_ |
44 | #define _DT_BINDINGS_CLK_SUN50I_A64_H_ | 44 | #define _DT_BINDINGS_CLK_SUN50I_A64_H_ |
45 | 45 | ||
46 | #define CLK_PLL_PERIPH0 11 | ||
47 | |||
46 | #define CLK_BUS_MIPI_DSI 28 | 48 | #define CLK_BUS_MIPI_DSI 28 |
47 | #define CLK_BUS_CE 29 | 49 | #define CLK_BUS_CE 29 |
48 | #define CLK_BUS_DMA 30 | 50 | #define CLK_BUS_DMA 30 |