dmaengine: owl: Add Slave and Cyclic mode support for Actions Semi Owl S900 SoC

Add Slave and Cyclic mode support for Actions Semi Owl S900 SoC. The slave
mode supports bus width of 4 bytes common for all peripherals and 1 byte
specific for UART.

The cyclic mode supports only block mode transfer.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>

1 files changed, 272 insertions, 7 deletions

diff --git a/drivers/dma/owl-dma.c b/drivers/dma/owl-dma.c
index 7812a6338acd..1d26db4c9229 100644
--- a/drivers/dma/owl-dma.c
+++ b/drivers/dma/owl-dma.c
@@ -21,6 +21,7 @@
 #include <linux/mm.h>
 #include <linux/module.h>
 #include <linux/of_device.h>
+#include <linux/of_dma.h>
 #include <linux/slab.h>
 #include "virt-dma.h"
 
@@ -165,6 +166,7 @@ struct owl_dma_lli {
 struct owl_dma_txd {
         struct virt_dma_desc    vd;
         struct list_head        lli_list;
+        bool                    cyclic;
 };
 
 /**
@@ -191,6 +193,8 @@ struct owl_dma_vchan {
         struct virt_dma_chan    vc;
         struct owl_dma_pchan    *pchan;
         struct owl_dma_txd      *txd;
+        struct dma_slave_config cfg;
+        u8                      drq;
 };
 
 /**
@@ -336,9 +340,11 @@ static struct owl_dma_lli *owl_dma_alloc_lli(struct owl_dma *od)
 
 static struct owl_dma_lli *owl_dma_add_lli(struct owl_dma_txd *txd,
                                            struct owl_dma_lli *prev,
-                                           struct owl_dma_lli *next)
+                                           struct owl_dma_lli *next,
+                                           bool is_cyclic)
 {
-        list_add_tail(&next->node, &txd->lli_list);
+        if (!is_cyclic)
+                list_add_tail(&next->node, &txd->lli_list);
 
         if (prev) {
                 prev->hw.next_lli = next->phys;
@@ -351,7 +357,9 @@ static struct owl_dma_lli *owl_dma_add_lli(struct owl_dma_txd *txd,
 static inline int owl_dma_cfg_lli(struct owl_dma_vchan *vchan,
                                   struct owl_dma_lli *lli,
                                   dma_addr_t src, dma_addr_t dst,
-                                  u32 len, enum dma_transfer_direction dir)
+                                  u32 len, enum dma_transfer_direction dir,
+                                  struct dma_slave_config *sconfig,
+                                  bool is_cyclic)
 {
         struct owl_dma_lli_hw *hw = &lli->hw;
         u32 mode;
@@ -365,6 +373,32 @@ static inline int owl_dma_cfg_lli(struct owl_dma_vchan *vchan,
                         OWL_DMA_MODE_DAM_INC;
 
                 break;
+        case DMA_MEM_TO_DEV:
+                mode |= OWL_DMA_MODE_TS(vchan->drq)
+                        | OWL_DMA_MODE_ST_DCU | OWL_DMA_MODE_DT_DEV
+                        | OWL_DMA_MODE_SAM_INC | OWL_DMA_MODE_DAM_CONST;
+
+                /*
+                 * Hardware only supports 32bit and 8bit buswidth. Since the
+                 * default is 32bit, select 8bit only when requested.
+                 */
+                if (sconfig->dst_addr_width == DMA_SLAVE_BUSWIDTH_1_BYTE)
+                        mode |= OWL_DMA_MODE_NDDBW_8BIT;
+
+                break;
+        case DMA_DEV_TO_MEM:
+                 mode |= OWL_DMA_MODE_TS(vchan->drq)
+                        | OWL_DMA_MODE_ST_DEV | OWL_DMA_MODE_DT_DCU
+                        | OWL_DMA_MODE_SAM_CONST | OWL_DMA_MODE_DAM_INC;
+
+                /*
+                 * Hardware only supports 32bit and 8bit buswidth. Since the
+                 * default is 32bit, select 8bit only when requested.
+                 */
+                if (sconfig->src_addr_width == DMA_SLAVE_BUSWIDTH_1_BYTE)
+                        mode |= OWL_DMA_MODE_NDDBW_8BIT;
+
+                break;
         default:
                 return -EINVAL;
         }
@@ -381,7 +415,10 @@ static inline int owl_dma_cfg_lli(struct owl_dma_vchan *vchan,
                                  OWL_DMA_LLC_SAV_LOAD_NEXT |
                                  OWL_DMA_LLC_DAV_LOAD_NEXT);
 
-        hw->ctrlb = llc_hw_ctrlb(OWL_DMA_INTCTL_SUPER_BLOCK);
+        if (is_cyclic)
+                hw->ctrlb = llc_hw_ctrlb(OWL_DMA_INTCTL_BLOCK);
+        else
+                hw->ctrlb = llc_hw_ctrlb(OWL_DMA_INTCTL_SUPER_BLOCK);
 
         return 0;
 }
@@ -443,6 +480,16 @@ static void owl_dma_terminate_pchan(struct owl_dma *od,
         spin_unlock_irqrestore(&od->lock, flags);
 }
 
+static void owl_dma_pause_pchan(struct owl_dma_pchan *pchan)
+{
+        pchan_writel(pchan, 1, OWL_DMAX_PAUSE);
+}
+
+static void owl_dma_resume_pchan(struct owl_dma_pchan *pchan)
+{
+        pchan_writel(pchan, 0, OWL_DMAX_PAUSE);
+}
+
 static int owl_dma_start_next_txd(struct owl_dma_vchan *vchan)
 {
         struct owl_dma *od = to_owl_dma(vchan->vc.chan.device);
@@ -464,7 +511,10 @@ static int owl_dma_start_next_txd(struct owl_dma_vchan *vchan)
         lli = list_first_entry(&txd->lli_list,
                                struct owl_dma_lli, node);
 
-        int_ctl = OWL_DMA_INTCTL_SUPER_BLOCK;
+        if (txd->cyclic)
+                int_ctl = OWL_DMA_INTCTL_BLOCK;
+        else
+                int_ctl = OWL_DMA_INTCTL_SUPER_BLOCK;
 
         pchan_writel(pchan, OWL_DMAX_MODE, OWL_DMA_MODE_LME);
         pchan_writel(pchan, OWL_DMAX_LINKLIST_CTL,
@@ -627,6 +677,54 @@ static int owl_dma_terminate_all(struct dma_chan *chan)
         return 0;
 }
 
+static int owl_dma_config(struct dma_chan *chan,
+                          struct dma_slave_config *config)
+{
+        struct owl_dma_vchan *vchan = to_owl_vchan(chan);
+
+        /* Reject definitely invalid configurations */
+        if (config->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
+            config->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
+                return -EINVAL;
+
+        memcpy(&vchan->cfg, config, sizeof(struct dma_slave_config));
+
+        return 0;
+}
+
+static int owl_dma_pause(struct dma_chan *chan)
+{
+        struct owl_dma_vchan *vchan = to_owl_vchan(chan);
+        unsigned long flags;
+
+        spin_lock_irqsave(&vchan->vc.lock, flags);
+
+        owl_dma_pause_pchan(vchan->pchan);
+
+        spin_unlock_irqrestore(&vchan->vc.lock, flags);
+
+        return 0;
+}
+
+static int owl_dma_resume(struct dma_chan *chan)
+{
+        struct owl_dma_vchan *vchan = to_owl_vchan(chan);
+        unsigned long flags;
+
+        if (!vchan->pchan && !vchan->txd)
+                return 0;
+
+        dev_dbg(chan2dev(chan), "vchan %p: resume\n", &vchan->vc);
+
+        spin_lock_irqsave(&vchan->vc.lock, flags);
+
+        owl_dma_resume_pchan(vchan->pchan);
+
+        spin_unlock_irqrestore(&vchan->vc.lock, flags);
+
+        return 0;
+}
+
 static u32 owl_dma_getbytes_chan(struct owl_dma_vchan *vchan)
 {
         struct owl_dma_pchan *pchan;
@@ -754,13 +852,14 @@ static struct dma_async_tx_descriptor
                 bytes = min_t(size_t, (len - offset), OWL_DMA_FRAME_MAX_LENGTH);
 
                 ret = owl_dma_cfg_lli(vchan, lli, src + offset, dst + offset,
-                                      bytes, DMA_MEM_TO_MEM);
+                                      bytes, DMA_MEM_TO_MEM,
+                                      &vchan->cfg, txd->cyclic);
                 if (ret) {