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authorLinus Torvalds <torvalds@linux-foundation.org>2014-04-01 16:10:49 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2014-04-01 16:10:49 -0400
commitd64b3932531cbc0c9d6bdb744446934435e9d6af (patch)
tree32220446dde284e82f26616b852fa51fd8d0111d
parent4dedde7c7a18f55180574f934dbc1be84ca0400b (diff)
parent43f23a0660fa0fdc74c7b1bfc5a209883dbf8153 (diff)
Merge tag 'pinctrl-v3.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control bulk changes from Linus Walleij: "Pin control bulk changes for the v3.15 series, no new core functionality this time, just incremental driver updates: - A large refactoring of the MVEBU (Marvell) driver. - A large refactoring of the Tegra (nVidia) driver. - GPIO interrupt including soft edges support in the STi driver. - Misc updates to PFC (Renesas), AT91, ADI2 (Blackfin), pinctrl-single, sirf (CSR), msm (Qualcomm), Exynos (Samsung), sunxi (AllWinner), i.MX (Freescale), Baytrail" * tag 'pinctrl-v3.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (72 commits) pinctrl: tegra: add some missing Tegra114 entries pinctrl: tegra: fix some mistakes in Tegra124 pinctrl: msm: fix up out-of-order merge conflict pinctrl: st: Fix error check for of_irq_to_resource usage pinctrl: tegra: consistency cleanup pinctrl: tegra: dynamically calculate function list of groups pinctrl: tegra: init Tegra20/30 at module_init time pinctrl: st: Use ARRAY_SIZE instead of raw value for number of delays pinctrl: st: add pinctrl support for the STiH407 SoC pinctrl: st: Enhance the controller to manage unavailable registers pinctrl: msm: Simplify msm_config_reg() and callers pinctrl: msm: Remove impossible WARN_ON()s pinctrl: msm: Replace lookup tables with math pinctrl: msm: Drop OF_IRQ dependency pinctrl: msm: Drop unused includes pinctrl: msm: Check for ngpios > MAX_NR_GPIO pinctrl: msm: Silence recursive lockdep warning pinctrl: mvebu: silence WARN to dev_warn pinctrl: msm: drop wake_irqs bitmap pinctrl-baytrail: add function mux checking in gpio pin request ...
Diffstat
-rw-r--r--Documentation/devicetree/bindings/arm/marvell,dove.txt22
-rw-r--r--Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt1
-rw-r--r--Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt82
-rw-r--r--Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt80
-rw-r--r--Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt1
-rw-r--r--Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt1
-rw-r--r--Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt1
-rw-r--r--Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt2
-rw-r--r--Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt7
-rw-r--r--Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt73
-rw-r--r--Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt14
-rw-r--r--Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt1
-rw-r--r--arch/arm/boot/dts/r8a7791.dtsi2
-rw-r--r--arch/blackfin/include/asm/irq.h9
-rw-r--r--drivers/pinctrl/Kconfig2
-rw-r--r--drivers/pinctrl/devicetree.c4
-rw-r--r--drivers/pinctrl/mvebu/Kconfig9
-rw-r--r--drivers/pinctrl/mvebu/Makefile2
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-armada-370.c20
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-armada-375.c459
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-armada-38x.c462
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-armada-xp.c24
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-dove.c404
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-kirkwood.c25
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-mvebu.c122
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-mvebu.h55
-rw-r--r--drivers/pinctrl/pinctrl-adi2-bf54x.c138
-rw-r--r--drivers/pinctrl/pinctrl-adi2-bf60x.c128
-rw-r--r--drivers/pinctrl/pinctrl-adi2.c31
-rw-r--r--drivers/pinctrl/pinctrl-adi2.h8
-rw-r--r--drivers/pinctrl/pinctrl-at91.c39
-rw-r--r--drivers/pinctrl/pinctrl-baytrail.c42
-rw-r--r--drivers/pinctrl/pinctrl-exynos.c82
-rw-r--r--drivers/pinctrl/pinctrl-imx.c2
-rw-r--r--drivers/pinctrl/pinctrl-msm.c113
-rw-r--r--drivers/pinctrl/pinctrl-msm.h5
-rw-r--r--drivers/pinctrl/pinctrl-msm8x74.c14
-rw-r--r--drivers/pinctrl/pinctrl-nomadik.c19
-rw-r--r--drivers/pinctrl/pinctrl-samsung.c2
-rw-r--r--drivers/pinctrl/pinctrl-samsung.h1
-rw-r--r--drivers/pinctrl/pinctrl-single.c3
-rw-r--r--drivers/pinctrl/pinctrl-st.c462
-rw-r--r--drivers/pinctrl/pinctrl-sunxi-pins.h12
-rw-r--r--drivers/pinctrl/pinctrl-tegra.c38
-rw-r--r--drivers/pinctrl/pinctrl-tegra.h4
-rw-r--r--drivers/pinctrl/pinctrl-tegra114.c1100
-rw-r--r--drivers/pinctrl/pinctrl-tegra124.c1243
-rw-r--r--drivers/pinctrl/pinctrl-tegra20.c640
-rw-r--r--drivers/pinctrl/pinctrl-tegra30.c1287
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7790.c171
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7791.c596
-rw-r--r--drivers/pinctrl/sirf/pinctrl-atlas6.c46
-rw-r--r--drivers/pinctrl/sirf/pinctrl-prima2.c3
-rw-r--r--drivers/pinctrl/sirf/pinctrl-sirf.c3
54 files changed, 3439 insertions, 4677 deletions
diff --git a/Documentation/devicetree/bindings/arm/marvell,dove.txt b/Documentation/devicetree/bindings/arm/marvell,dove.txt
new file mode 100644
index 000000000000..aaaf64c56e44
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/marvell,dove.txt
@@ -0,0 +1,22 @@
1Marvell Dove Platforms Device Tree Bindings
2-----------------------------------------------
3
4Boards with a Marvell Dove SoC shall have the following properties:
5
6Required root node property:
7- compatible: must contain "marvell,dove";
8
9* Global Configuration registers
10
11Global Configuration registers of Dove SoC are shared by a syscon node.
12
13Required properties:
14- compatible: must contain "marvell,dove-global-config" and "syscon".
15- reg: base address and size of the Global Configuration registers.
16
17Example:
18
19gconf: global-config@e802c {
20 compatible = "marvell,dove-global-config", "syscon";
21 reg = <0xe802c 0x14>;
22};
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
index 01ef408e205f..adda2a8d1d52 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
@@ -5,6 +5,7 @@ part and usage.
5 5
6Required properties: 6Required properties:
7- compatible: "marvell,88f6710-pinctrl" 7- compatible: "marvell,88f6710-pinctrl"
8- reg: register specifier of MPP registers
8 9
9Available mpp pins/groups and functions: 10Available mpp pins/groups and functions:
10Note: brackets (x) are not part of the mpp name for marvell,function and given 11Note: brackets (x) are not part of the mpp name for marvell,function and given
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt
new file mode 100644
index 000000000000..7de0cda4a379
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt
@@ -0,0 +1,82 @@
1* Marvell Armada 375 SoC pinctrl driver for mpp
2
3Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
4part and usage.
5
6Required properties:
7- compatible: "marvell,88f6720-pinctrl"
8- reg: register specifier of MPP registers
9
10Available mpp pins/groups and functions:
11Note: brackets (x) are not part of the mpp name for marvell,function and given
12only for more detailed description in this document.
13
14name pins functions
15================================================================================
16mpp0 0 gpio, dev(ad2), spi0(cs1), spi1(cs1)
17mpp1 1 gpio, dev(ad3), spi0(mosi), spi1(mosi)
18mpp2 2 gpio, dev(ad4), ptp(eventreq), led(c0), audio(sdi)
19mpp3 3 gpio, dev(ad5), ptp(triggen), led(p3), audio(mclk)
20mpp4 4 gpio, dev(ad6), spi0(miso), spi1(miso)
21mpp5 5 gpio, dev(ad7), spi0(cs2), spi1(cs2)
22mpp6 6 gpio, dev(ad0), led(p1), audio(rclk)
23mpp7 7 gpio, dev(ad1), ptp(clk), led(p2), audio(extclk)
24mpp8 8 gpio, dev (bootcs), spi0(cs0), spi1(cs0)
25mpp9 9 gpio, nf(wen), spi0(sck), spi1(sck)
26mpp10 10 gpio, nf(ren), dram(vttctrl), led(c1)
27mpp11 11 gpio, dev(a0), led(c2), audio(sdo)
28mpp12 12 gpio, dev(a1), audio(bclk)
29mpp13 13 gpio, dev(readyn), pcie0(rstoutn), pcie1(rstoutn)
30mpp14 14 gpio, i2c0(sda), uart1(txd)
31mpp15 15 gpio, i2c0(sck), uart1(rxd)
32mpp16 16 gpio, uart0(txd)
33mpp17 17 gpio, uart0(rxd)
34mpp18 18 gpio, tdm(intn)
35mpp19 19 gpio, tdm(rstn)
36mpp20 20 gpio, tdm(pclk)
37mpp21 21 gpio, tdm(fsync)
38mpp22 22 gpio, tdm(drx)
39mpp23 23 gpio, tdm(dtx)
40mpp24 24 gpio, led(p0), ge1(rxd0), sd(cmd), uart0(rts)
41mpp25 25 gpio, led(p2), ge1(rxd1), sd(d0), uart0(cts)
42mpp26 26 gpio, pcie0(clkreq), ge1(rxd2), sd(d2), uart1(rts)
43mpp27 27 gpio, pcie1(clkreq), ge1(rxd3), sd(d1), uart1(cts)
44mpp28 28 gpio, led(p3), ge1(txctl), sd(clk)
45mpp29 29 gpio, pcie1(clkreq), ge1(rxclk), sd(d3)
46mpp30 30 gpio, ge1(txd0), spi1(cs0)
47mpp31 31 gpio, ge1(txd1), spi1(mosi)
48mpp32 32 gpio, ge1(txd2), spi1(sck), ptp(triggen)
49mpp33 33 gpio, ge1(txd3), spi1(miso)
50mpp34 34 gpio, ge1(txclkout), spi1(sck)
51mpp35 35 gpio, ge1(rxctl), spi1(cs1), spi0(cs2)
52mpp36 36 gpio, pcie0(clkreq)
53mpp37 37 gpio, pcie0(clkreq), tdm(intn), ge(mdc)
54mpp38 38 gpio, pcie1(clkreq), ge(mdio)
55mpp39 39 gpio, ref(clkout)
56mpp40 40 gpio, uart1(txd)
57mpp41 41 gpio, uart1(rxd)
58mpp42 42 gpio, spi1(cs2), led(c0)
59mpp43 43 gpio, sata0(prsnt), dram(vttctrl)
60mpp44 44 gpio, sata0(prsnt)
61mpp45 45 gpio, spi0(cs2), pcie0(rstoutn)
62mpp46 46 gpio, led(p0), ge0(txd0), ge1(txd0)
63mpp47 47 gpio, led(p1), ge0(txd1), ge1(txd1)
64mpp48 48 gpio, led(p2), ge0(txd2), ge1(txd2)
65mpp49 49 gpio, led(p3), ge0(txd3), ge1(txd3)
66mpp50 50 gpio, led(c0), ge0(rxd0), ge1(rxd0)
67mpp51 51 gpio, led(c1), ge0(rxd1), ge1(rxd1)
68mpp52 52 gpio, led(c2), ge0(rxd2), ge1(rxd2)
69mpp53 53 gpio, pcie1(rstoutn), ge0(rxd3), ge1(rxd3)
70mpp54 54 gpio, pcie0(rstoutn), ge0(rxctl), ge1(rxctl)
71mpp55 55 gpio, ge0(rxclk), ge1(rxclk)
72mpp56 56 gpio, ge0(txclkout), ge1(txclkout)
73mpp57 57 gpio, ge0(txctl), ge1(txctl)
74mpp58 58 gpio, led(c0)
75mpp59 59 gpio, led(c1)
76mpp60 60 gpio, uart1(txd), led(c2)
77mpp61 61 gpio, i2c1(sda), uart1(rxd), spi1(cs2), led(p0)
78mpp62 62 gpio, i2c1(sck), led(p1)
79mpp63 63 gpio, ptp(triggen), led(p2)
80mpp64 64 gpio, dram(vttctrl), led(p3)
81mpp65 65 gpio, sata1(prsnt)
82mpp66 66 gpio, ptp(eventreq), spi1(cs3)
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt
new file mode 100644
index 000000000000..b17c96849fc9
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt
@@ -0,0 +1,80 @@
1* Marvell Armada 380/385 SoC pinctrl driver for mpp
2
3Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
4part and usage.
5
6Required properties:
7- compatible: "marvell,88f6810-pinctrl", "marvell,88f6820-pinctrl" or
8 "marvell,88f6828-pinctrl" depending on the specific variant of the
9 SoC being used.
10- reg: register specifier of MPP registers
11
12Available mpp pins/groups and functions:
13Note: brackets (x) are not part of the mpp name for marvell,function and given
14only for more detailed description in this document.
15
16name pins functions
17================================================================================
18mpp0 0 gpio, ua0(rxd)
19mpp1 1 gpio, ua0(txd)
20mpp2 2 gpio, i2c0(sck)
21mpp3 3 gpio, i2c0(sda)
22mpp4 4 gpio, ge(mdc), ua1(txd), ua0(rts)
23mpp5 5 gpio, ge(mdio), ua1(rxd), ua0(cts)
24mpp6 6 gpio, ge0(txclkout), ge0(crs), dev(cs3)
25mpp7 7 gpio, ge0(txd0), dev(ad9)
26mpp8 8 gpio, ge0(txd1), dev(ad10)
27mpp9 9 gpio, ge0(txd2), dev(ad11)
28mpp10 10 gpio, ge0(txd3), dev(ad12)
29mpp11 11 gpio, ge0(txctl), dev(ad13)
30mpp12 12 gpio, ge0(rxd0), pcie0(rstout), pcie1(rstout) [1], spi0(cs1), dev(ad14)
31mpp13 13 gpio, ge0(rxd1), pcie0(clkreq), pcie1(clkreq) [1], spi0(cs2), dev(ad15)
32mpp14 14 gpio, ge0(rxd2), ptp(clk), m(vtt_ctrl), spi0(cs3), dev(wen1)
33mpp15 15 gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi), pcie1(rstout) [1]
34mpp16 16 gpio, ge0(rxctl), ge(mdio slave), m(decc_err), spi0(miso), pcie0(clkreq)
35mpp17 17 gpio, ge0(rxclk), ptp(clk), ua1(rxd), spi0(sck), sata1(prsnt)
36mpp18 18 gpio, ge0(rxerr), ptp(trig_gen), ua1(txd), spi0(cs0), pcie1(rstout) [1]
37mpp19 19 gpio, ge0(col), ptp(event_req), pcie0(clkreq), sata1(prsnt), ua0(cts)
38mpp20 20 gpio, ge0(txclk), ptp(clk), pcie1(rstout) [1], sata0(prsnt), ua0(rts)
39mpp21 21 gpio, spi0(cs1), ge1(rxd0), sata0(prsnt), sd0(cmd), dev(bootcs)
40mpp22 22 gpio, spi0(mosi), dev(ad0)
41mpp23 23 gpio, spi0(sck), dev(ad2)
42mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(ready)
43mpp25 25 gpio, spi0(cs0), ua0(rts), ua1(txd), sd0(d5), dev(cs0)
44mpp26 26 gpio, spi0(cs2), i2c1(sck), sd0(d6), dev(cs1)
45mpp27 27 gpio, spi0(cs3), ge1(txclkout), i2c1(sda), sd0(d7), dev(cs2)
46mpp28 28 gpio, ge1(txd0), sd0(clk), dev(ad5)
47mpp29 29 gpio, ge1(txd1), dev(ale0)
48mpp30 30 gpio, ge1(txd2), dev(oen)
49mpp31 31 gpio, ge1(txd3), dev(ale1)
50mpp32 32 gpio, ge1(txctl), dev(wen0)
51mpp33 33 gpio, m(decc_err), dev(ad3)
52mpp34 34 gpio, dev(ad1)
53mpp35 35 gpio, ref(clk_out1), dev(a1)
54mpp36 36 gpio, ptp(trig_gen), dev(a0)
55mpp37 37 gpio, ptp(clk), ge1(rxclk), sd0(d3), dev(ad8)
56mpp38 38 gpio, ptp(event_req), ge1(rxd1), ref(clk_out0), sd0(d0), dev(ad4)
57mpp39 39 gpio, i2c1(sck), ge1(rxd2), ua0(cts), sd0(d1), dev(a2)
58mpp40 40 gpio, i2c1(sda), ge1(rxd3), ua0(rts), sd0(d2), dev(ad6)
59mpp41 41 gpio, ua1(rxd), ge1(rxctl), ua0(cts), spi1(cs3), dev(burst/last)
60mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7)
61mpp43 43 gpio, pcie0(clkreq), m(vtt_ctrl), m(decc_err), pcie0(rstout), dev(clkout)
62mpp44 44 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [3], pcie0(rstout)
63mpp45 45 gpio, ref(clk_out0), pcie0(rstout), pcie1(rstout) [1], pcie2(rstout), pcie3(rstout)
64mpp46 46 gpio, ref(clk_out1), pcie0(rstout), pcie1(rstout) [1], pcie2(rstout), pcie3(rstout)
65mpp47 47 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], spi1(cs2), sata3(prsnt) [2]
66mpp48 48 gpio, sata0(prsnt), m(vtt_ctrl), tdm2c(pclk), audio(mclk), sd0(d4)
67mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm2c(fsync), audio(lrclk), sd0(d5)
68mpp50 50 gpio, pcie0(rstout), pcie1(rstout) [1], tdm2c(drx), audio(extclk), sd0(cmd)
69mpp51 51 gpio, tdm2c(dtx), audio(sdo), m(decc_err)
70mpp52 52 gpio, pcie0(rstout), pcie1(rstout) [1], tdm2c(intn), audio(sdi), sd0(d6)
71mpp53 53 gpio, sata1(prsnt), sata0(prsnt), tdm2c(rstn), audio(bclk), sd0(d7)
72mpp54 54 gpio, sata0(prsnt), sata1(prsnt), pcie0(rstout), pcie1(rstout) [1], sd0(d3)
73mpp55 55 gpio, ua1(cts), ge(mdio), pcie1(clkreq) [1], spi1(cs1), sd0(d0)
74mpp56 56 gpio, ua1(rts), ge(mdc), m(decc_err), spi1(mosi)
75mpp57 57 gpio, spi1(sck), sd0(clk)
76mpp58 58 gpio, pcie1(clkreq) [1], i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1)
77mpp59 59 gpio, pcie0(rstout), i2c1(sda), pcie1(rstout) [1], spi1(cs0), sd0(d2)
78
79[1]: only available on 88F6820 and 88F6828
80[2]: only available on 88F6828
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
index bfa0a2e5e0cb..373dbccd7ab0 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
@@ -6,6 +6,7 @@ part and usage.
6Required properties: 6Required properties:
7- compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl", 7- compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",
8 "marvell,mv78460-pinctrl" 8 "marvell,mv78460-pinctrl"
9- reg: register specifier of MPP registers
9 10
10This driver supports all Armada XP variants, i.e. mv78230, mv78260, and mv78460. 11This driver supports all Armada XP variants, i.e. mv78230, mv78260, and mv78460.
11 12
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
index 50ec3512a292..cf52477cc7ee 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
@@ -6,6 +6,7 @@ part and usage.
6Required properties: 6Required properties:
7- compatible: "marvell,dove-pinctrl" 7- compatible: "marvell,dove-pinctrl"
8- clocks: (optional) phandle of pdma clock 8- clocks: (optional) phandle of pdma clock
9- reg: register specifiers of MPP, MPP4, and PMU MPP registers
9 10
10Available mpp pins/groups and functions: 11Available mpp pins/groups and functions:
11Note: brackets (x) are not part of the mpp name for marvell,function and given 12Note: brackets (x) are not part of the mpp name for marvell,function and given
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
index 95daf6335c37..730444a9a4de 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
@@ -8,6 +8,7 @@ Required properties:
8 "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl", 8 "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
9 "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl" 9 "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl"
10 "marvell,98dx4122-pinctrl" 10 "marvell,98dx4122-pinctrl"
11- reg: register specifier of MPP registers
11 12
12This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x. 13This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x.
13It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs. 14It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
index 0a26c3aa4e6d..0c09f4eb2af0 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
@@ -37,7 +37,7 @@ uart1: serial@12100 {
37 37
38pinctrl: pinctrl@d0200 { 38pinctrl: pinctrl@d0200 {
39 compatible = "marvell,dove-pinctrl"; 39 compatible = "marvell,dove-pinctrl";
40 reg = <0xd0200 0x20>; 40 reg = <0xd0200 0x14>, <0xd0440 0x04>, <0xd802c 0x08>;
41 41
42 pmx_uart1_sw: pmx-uart1-sw { 42 pmx_uart1_sw: pmx-uart1-sw {
43 marvell,pins = "mpp_uart1"; 43 marvell,pins = "mpp_uart1";
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
index bc0dfdfdb148..66dcaa9efd74 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
@@ -63,6 +63,13 @@ Optional properties:
63 /* input, enable bits, disable bits, mask */ 63 /* input, enable bits, disable bits, mask */
64 pinctrl-single,input-schmitt-enable = <0x30 0x40 0 0x70>; 64 pinctrl-single,input-schmitt-enable = <0x30 0x40 0 0x70>;
65 65
66- pinctrl-single,low-power-mode : array of value that are used to configure
67 low power mode of this pin. For some silicons, the low power mode will
68 control the output of the pin when the pad including the pin enter low
69 power mode.
70 /* low power mode value, mask */
71 pinctrl-single,low-power-mode = <0x288 0x388>;
72
66- pinctrl-single,gpio-range : list of value that are used to configure a GPIO 73- pinctrl-single,gpio-range : list of value that are used to configure a GPIO
67 range. They're value of subnode phandle, pin base in pinctrl device, pin 74 range. They're value of subnode phandle, pin base in pinctrl device, pin
68 number in this range, GPIO function value of this GPIO range. 75 number in this range, GPIO function value of this GPIO range.
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt
index 05bf82a07dfd..4bd5be0e5e7d 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt
@@ -11,18 +11,68 @@ Pull Up (PU) are driven by the related PIO block.
11ST pinctrl driver controls PIO multiplexing block and also interacts with 11ST pinctrl driver controls PIO multiplexing block and also interacts with
12gpio driver to configure a pin. 12gpio driver to configure a pin.
13 13
14Required properties: (PIO multiplexing block) 14GPIO bank can have one of the two possible types of interrupt-wirings.
15
16First type is via irqmux, single interrupt is used by multiple gpio banks. This
17reduces number of overall interrupts numbers required. All these banks belong to
18a single pincontroller.
19 _________
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
23 | |----> [gpio-bank (... )]
24 |_________|----> [gpio-bank (n + 7)]
25
26Second type has a dedicated interrupt per gpio bank.
27
28 [irqN]----> [gpio-bank (n)]
29
30
31Pin controller node:
32Required properties:
15- compatible : should be "st,<SOC>-<pio-block>-pinctrl" 33- compatible : should be "st,<SOC>-<pio-block>-pinctrl"
16 like st,stih415-sbc-pinctrl, st,stih415-front-pinctrl and so on. 34 like st,stih415-sbc-pinctrl, st,stih415-front-pinctrl and so on.
17- gpio-controller : Indicates this device is a GPIO controller 35- st,syscfg : Should be a phandle of the syscfg node.
18- #gpio-cells : Should be one. The first cell is the pin number.
19- st,retime-pin-mask : Should be mask to specify which pins can be retimed. 36- st,retime-pin-mask : Should be mask to specify which pins can be retimed.
20 If the property is not present, it is assumed that all the pins in the 37 If the property is not present, it is assumed that all the pins in the
21 bank are capable of retiming. Retiming is mainly used to improve the 38 bank are capable of retiming. Retiming is mainly used to improve the
22 IO timing margins of external synchronous interfaces. 39 IO timing margins of external synchronous interfaces.
23- st,bank-name : Should be a name string for this bank as 40- ranges : defines mapping between pin controller node (parent) to gpio-bank
24 specified in datasheet. 41 node (children).
25- st,syscfg : Should be a phandle of the syscfg node. 42
43Optional properties:
44- interrupts : Interrupt number of the irqmux. If the interrupt is shared
45 with other gpio banks via irqmux.
46 a irqline and gpio banks.
47- reg : irqmux memory resource. If irqmux is present.
48- reg-names : irqmux resource should be named as "irqmux".
49
50GPIO controller/bank node.
51Required properties:
52- gpio-controller : Indicates this device is a GPIO controller
53- #gpio-cells : Should be one. The first cell is the pin number.
54- st,bank-name : Should be a name string for this bank as specified in
55 datasheet.
56
57Optional properties:
58- interrupts : Interrupt number for this gpio bank. If there is a dedicated
59 interrupt wired up for this gpio bank.
60
61- interrupt-controller : Indicates this device is a interrupt controller. GPIO
62 bank can be an interrupt controller iff one of the interrupt type either via
63irqmux or a dedicated interrupt per bank is specified.
64
65- #interrupt-cells: the value of this property should be 2.
66 - First Cell: represents the external gpio interrupt number local to the
67 gpio interrupt space of the controller.
68 - Second Cell: flags to identify the type of the interrupt
69 - 1 = rising edge triggered
70 - 2 = falling edge triggered
71 - 3 = rising and falling edge triggered
72 - 4 = high level triggered
73 - 8 = low level triggered
74for related macros look in:
75include/dt-bindings/interrupt-controller/irq.h
26 76
27Example: 77Example:
28 pin-controller-sbc { 78 pin-controller-sbc {
@@ -30,10 +80,17 @@ Example:
30 #size-cells = <1>; 80 #size-cells = <1>;
31 compatible = "st,stih415-sbc-pinctrl"; 81 compatible = "st,stih415-sbc-pinctrl";
32 st,syscfg = <&syscfg_sbc>; 82 st,syscfg = <&syscfg_sbc>;
83 reg = <0xfe61f080 0x4>;
84 reg-names = "irqmux";
85 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
86 interrupts-names = "irqmux";
33 ranges = <0 0xfe610000 0x5000>; 87 ranges = <0 0xfe610000 0x5000>;
88
34 PIO0: gpio@fe610000 { 89 PIO0: gpio@fe610000 {
35 gpio-controller; 90 gpio-controller;
36 #gpio-cells = <1>; 91 #gpio-cells = <1>;
92 interrupt-controller;
93 #interrupt-cells = <2>;
37 reg = <0 0x100>; 94 reg = <0 0x100>;
38 st,bank-name = "PIO0"; 95 st,bank-name = "PIO0";
39 }; 96 };
@@ -105,6 +162,10 @@ pin-controller {
105 162
106sdhci0:sdhci@fe810000{ 163sdhci0:sdhci@fe810000{
107 ... 164 ...
165 interrupt-parent = <&PIO3>;
166 #interrupt-cells = <2>;
167 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; /* Interrupt line via PIO3-3 */
168 interrupts-names = "card-detect";
108 pinctrl-names = "default"; 169 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_mmc>; 170 pinctrl-0 = <&pinctrl_mmc>;
110}; 171};
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt
index 4c352be5dd61..9fb89e3f61ea 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt
@@ -1,7 +1,7 @@
1Qualcomm MSM8974 TLMM block 1Qualcomm MSM8974 TLMM block
2 2
3Required properties: 3Required properties:
4- compatible: "qcom,msm8x74-pinctrl" 4- compatible: "qcom,msm8974-pinctrl"
5- reg: Should be the base address and length of the TLMM block. 5- reg: Should be the base address and length of the TLMM block.
6- interrupts: Should be the parent IRQ of the TLMM block. 6- interrupts: Should be the parent IRQ of the TLMM block.
7- interrupt-controller: Marks the device node as an interrupt controller. 7- interrupt-controller: Marks the device node as an interrupt controller.
@@ -42,14 +42,14 @@ Non-empty subnodes must specify the 'pins' property.
42Note that not all properties are valid for all pins. 42Note that not all properties are valid for all pins.
43 43
44 44
45Valid values for qcom,pins are: 45Valid values for pins are:
46 gpio0-gpio145 46 gpio0-gpio145
47 Supports mux, bias and drive-strength 47 Supports mux, bias and drive-strength
48 48
49 sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data 49 sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data
50 Supports bias and drive-strength 50 Supports bias and drive-strength
51 51
52Valid values for qcom,function are: 52Valid values for function are:
53 blsp_i2c2, blsp_i2c6, blsp_i2c11, blsp_spi1, blsp_uart2, blsp_uart8, slimbus 53 blsp_i2c2, blsp_i2c6, blsp_i2c11, blsp_spi1, blsp_uart2, blsp_uart8, slimbus
54 54
55 (Note that this is not yet the complete list of functions) 55 (Note that this is not yet the complete list of functions)
@@ -73,18 +73,18 @@ Example:
73 73
74 uart2_default: uart2_default { 74 uart2_default: uart2_default {
75 mux { 75 mux {
76 qcom,pins = "gpio4", "gpio5"; 76 pins = "gpio4", "gpio5";
77 qcom,function = "blsp_uart2"; 77 function = "blsp_uart2";
78 }; 78 };
79 79
80 tx { 80 tx {
81 qcom,pins = "gpio4"; 81 pins = "gpio4";
82 drive-strength = <4>; 82 drive-strength = <4>;
83 bias-disable; 83 bias-disable;
84 }; 84 };
85 85
86 rx { 86 rx {
87 qcom,pins = "gpio5"; 87 pins = "gpio5";
88 drive-strength = <2>; 88 drive-strength = <2>;
89 bias-pull-up; 89 bias-pull-up;
90 }; 90 };
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index 257677de3e6b..2b32783ba821 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -16,6 +16,7 @@ Required Properties:
16 - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller. 16 - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
17 - "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller. 17 - "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller.
18 - "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller. 18 - "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller.
19 - "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller.
19 - "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller. 20 - "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller.
20 21
21- reg: Base address of the pin controller hardware module and length of 22- reg: Base address of the pin controller hardware module and length of
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 19c65509a22d..3b075dd19b51 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -429,7 +429,7 @@
429 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2 429 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
430 >; 430 >;
431 clock-output-names = 431 clock-output-names =
432 "scifa2", "scifa1", "scifa0", "misof2", "scifb0", 432 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
433 "scifb1", "msiof1", "scifb2"; 433 "scifb1", "msiof1", "scifb2";
434 }; 434 };
435 mstp3_clks: mstp3_clks@e615013c { 435 mstp3_clks: mstp3_clks@e615013c {
diff --git a/arch/blackfin/include/asm/irq.h b/arch/blackfin/include/asm/irq.h
index 2fd04f10cc26..89de539ed010 100644
--- a/arch/blackfin/include/asm/irq.h
+++ b/arch/blackfin/include/asm/irq.h
@@ -20,15 +20,6 @@
20/* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h> */ 20/* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h> */
21#include <mach/irq.h> 21#include <mach/irq.h>
22 22
23/*
24 * pm save bfin pint registers
25 */
26struct adi_pm_pint_save {
27 u32 assign;
28 u32 edge_set;
29 u32 invert_set;
30};
31
32#if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE) 23#if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE)
33# define NOP_PAD_ANOMALY_05000244 "nop; nop;" 24# define NOP_PAD_ANOMALY_05000244 "nop; nop;"
34#else 25#else
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 1e4e69384baa..06cee0189f3e 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -224,7 +224,7 @@ config PINCTRL_MSM
224 224
225config PINCTRL_MSM8X74 225config PINCTRL_MSM8X74
226 tristate "Qualcomm 8x74 pin controller driver" 226 tristate "Qualcomm 8x74 pin controller driver"
227 depends on GPIOLIB && OF && OF_IRQ 227 depends on GPIOLIB && OF
228 select PINCTRL_MSM 228 select PINCTRL_MSM
229 help 229 help
230 This is the pinctrl, pinmux, pinconf and gpiolib driver for the 230 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
diff --git a/drivers/pinctrl/devicetree.c b/drivers/pinctrl/devicetree.c
index 340fb4e6c600..eda13de2e7c0 100644
--- a/drivers/pinctrl/devicetree.c
+++ b/drivers/pinctrl/devicetree.c
@@ -186,7 +186,9 @@ int pinctrl_dt_to_map(struct pinctrl *p)
186 186
187 /* CONFIG_OF enabled, p->dev not instantiated from DT */ 187 /* CONFIG_OF enabled, p->dev not instantiated from DT */
188 if (!np) { 188 if (!np) {
189 dev_dbg(p->dev, "no of_node; not parsing pinctrl DT\n"); 189 if (of_have_populated_dt())
190 dev_dbg(p->dev,
191 "no of_node; not parsing pinctrl DT\n");
190 return 0; 192 return 0;
191 } 193 }
192 194
diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig
index 366fa541ee91..cc298fade93a 100644
--- a/drivers/pinctrl/mvebu/Kconfig
+++ b/drivers/pinctrl/mvebu/Kconfig
@@ -8,6 +8,7 @@ config PINCTRL_MVEBU
8config PINCTRL_DOVE 8config PINCTRL_DOVE
9 bool 9 bool
10 select PINCTRL_MVEBU 10 select PINCTRL_MVEBU
11 select MFD_SYSCON
11 12
12config PINCTRL_KIRKWOOD 13config PINCTRL_KIRKWOOD
13 bool 14 bool
@@ -17,6 +18,14 @@ config PINCTRL_ARMADA_370
17 bool 18 bool
18 select PINCTRL_MVEBU 19 select PINCTRL_MVEBU
19 20
21config PINCTRL_ARMADA_375
22 bool
23 select PINCTRL_MVEBU
24
25config PINCTRL_ARMADA_38X
26 bool
27 select PINCTRL_MVEBU
28
20config PINCTRL_ARMADA_XP 29config PINCTRL_ARMADA_XP
21 bool 30 bool
22 select PINCTRL_MVEBU 31 select PINCTRL_MVEBU
diff --git a/drivers/pinctrl/mvebu/Makefile b/drivers/pinctrl/mvebu/Makefile
index 37c253297af0..bc1b9f14f539 100644
--- a/drivers/pinctrl/mvebu/Makefile
+++ b/drivers/pinctrl/mvebu/Makefile
@@ -2,4 +2,6 @@ obj-$(CONFIG_PINCTRL_MVEBU) += pinctrl-mvebu.o
2obj-$(CONFIG_PINCTRL_DOVE) += pinctrl-dove.o 2obj-$(CONFIG_PINCTRL_DOVE) += pinctrl-dove.o
3obj-$(CONFIG_PINCTRL_KIRKWOOD) += pinctrl-kirkwood.o 3obj-$(CONFIG_PINCTRL_KIRKWOOD) += pinctrl-kirkwood.o
4obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o 4obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o
5obj-$(CONFIG_PINCTRL_ARMADA_375) += pinctrl-armada-375.o
6obj-$(CONFIG_PINCTRL_ARMADA_38X) += pinctrl-armada-38x.o
5obj-$(CONFIG_PINCTRL_ARMADA_XP) += pinctrl-armada-xp.o 7obj-$(CONFIG_PINCTRL_ARMADA_XP) += pinctrl-armada-xp.o
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-370.c b/drivers/pinctrl/mvebu/pinctrl-armada-370.c
index ae1f760cbdd2..670e5b01c678 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-370.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-370.c
@@ -23,6 +23,18 @@
23 23
24#include "pinctrl-mvebu.h" 24#include "pinctrl-mvebu.h"
25 25
26static void __iomem *mpp_base;
27
28static int armada_370_mpp_ctrl_get(unsigned pid, unsigned long *config)
29{
30 return default_mpp_ctrl_get(mpp_base, pid, config);
31}
32
33static int armada_370_mpp_ctrl_set(unsigned pid, unsigned long config)
34{
35 return default_mpp_ctrl_set(mpp_base, pid, config);
36}
37
26static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = { 38static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = {
27 MPP_MODE(0, 39 MPP_MODE(0,
28 MPP_FUNCTION(0x0, "gpio", NULL), 40 MPP_FUNCTION(0x0, "gpio", NULL),
@@ -373,7 +385,7 @@ static struct of_device_id armada_370_pinctrl_of_match[] = {
373}; 385};
374 386
375static struct mvebu_mpp_ctrl mv88f6710_mpp_controls[] = { 387static struct mvebu_mpp_ctrl mv88f6710_mpp_controls[] = {
376 MPP_REG_CTRL(0, 65), 388 MPP_FUNC_CTRL(0, 65, NULL, armada_370_mpp_ctrl),
377}; 389};
378 390
379static struct pinctrl_gpio_range mv88f6710_mpp_gpio_ranges[] = { 391static struct pinctrl_gpio_range mv88f6710_mpp_gpio_ranges[] = {
@@ -385,6 +397,12 @@ static struct pinctrl_gpio_range mv88f6710_mpp_gpio_ranges[] = {
385static int armada_370_pinctrl_probe(struct platform_device *pdev) 397static int armada_370_pinctrl_probe(struct platform_device *pdev)
386{ 398{
387 struct mvebu_pinctrl_soc_info *soc = &armada_370_pinctrl_info; 399 struct mvebu_pinctrl_soc_info *soc = &armada_370_pinctrl_info;
400 struct resource *res;
401
402 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
403 mpp_base = devm_ioremap_resource(&pdev->dev, res);
404 if (IS_ERR(mpp_base))
405 return PTR_ERR(mpp_base);
388 406
389 soc->variant = 0; /* no variants for Armada 370 */ 407 soc->variant = 0; /* no variants for Armada 370 */
390 soc->controls = mv88f6710_mpp_controls; 408 soc->controls = mv88f6710_mpp_controls;
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-375.c b/drivers/pinctrl/mvebu/pinctrl-armada-375.c
new file mode 100644
index 000000000000..db078fe7ace6
--- /dev/null
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-375.c
@@ -0,0 +1,459 @@
1/*
2 * Marvell Armada 375 pinctrl driver based on mvebu pinctrl core
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/err.h>
15#include <linux/init.h>
16#include <linux/io.h>
17#include <linux/module.h>
18#include <linux/platform_device.h>
19#include <linux/clk.h>
20#include <linux/of.h>
21#include <linux/of_device.h>
22#include <linux/pinctrl/pinctrl.h>
23
24#include "pinctrl-mvebu.h"
25
26static void __iomem *mpp_base;
27
28static int armada_375_mpp_ctrl_get(unsigned pid, unsigned long *config)
29{
30 return default_mpp_ctrl_get(mpp_base, pid, config);
31}
32
33static int armada_375_mpp_ctrl_set(unsigned pid, unsigned long config)
34{
35 return default_mpp_ctrl_set(mpp_base, pid, config);
36}
37
38static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = {
39 MPP_MODE(0,
40 MPP_FUNCTION(0x0, "gpio", NULL),
41 MPP_FUNCTION(0x1, "dev", "ad2"),
42 MPP_FUNCTION(0x2, "spi0", "cs1"),
43 MPP_FUNCTION(0x3, "spi1", "cs1"),
44 MPP_FUNCTION(0x5, "nand", "io2")),
45 MPP_MODE(1,
46 MPP_FUNCTION(0x0, "gpio", NULL),
47 MPP_FUNCTION(0x1, "dev", "ad3"),
48 MPP_FUNCTION(0x2, "spi0", "mosi"),
49 MPP_FUNCTION(0x3, "spi1", "mosi"),
50 MPP_FUNCTION(0x5, "nand", "io3")),
51 MPP_MODE(2,
52 MPP_FUNCTION(0x0, "gpio", NULL),
53 MPP_FUNCTION(0x1, "dev", "ad4"),
54 MPP_FUNCTION(0x2, "ptp", "eventreq"),
55 MPP_FUNCTION(0x3, "led", "c0"),
56 MPP_FUNCTION(0x4, "audio", "sdi"),
57 MPP_FUNCTION(0x5, "nand", "io4"),
58 MPP_FUNCTION(0x6, "spi1", "mosi")),
59 MPP_MODE(3,
60 MPP_FUNCTION(0x0, "gpio", NULL),
61 MPP_FUNCTION(0x1, "dev", "ad5"),
62 MPP_FUNCTION(0x2, "ptp", "triggen"),
63 MPP_FUNCTION(0x3, "led", "p3"),
64 MPP_FUNCTION(0x4, "audio", "mclk"),
65 MPP_FUNCTION(0x5, "nand", "io5"),
66 MPP_FUNCTION(0x6, "spi1", "miso")),
67 MPP_MODE(4,
68 MPP_FUNCTION(0x0, "gpio", NULL),
69 MPP_FUNCTION(0x1, "dev", "ad6"),
70 MPP_FUNCTION(0x2, "spi0", "miso"),
71 MPP_FUNCTION(0x3, "spi1", "miso"),
72 MPP_FUNCTION(0x5, "nand", "io6")),
73 MPP_MODE(5,
74 MPP_FUNCTION(0x0, "gpio", NULL),
75 MPP_FUNCTION(0x1, "dev", "ad7"),
76 MPP_FUNCTION(0x2, "spi0", "cs2"),
77 MPP_FUNCTION(0x3, "spi1", "cs2"),
78 MPP_FUNCTION(0x5, "nand", "io7"),
79 MPP_FUNCTION(0x6, "spi1", "miso")),
80 MPP_MODE(6,
81 MPP_FUNCTION(0x0, "gpio", NULL),
82 MPP_FUNCTION(0x1, "dev", "ad0"),
83 MPP_FUNCTION(0x3, "led", "p1"),
84 MPP_FUNCTION(0x4, "audio", "rclk"),
85 MPP_FUNCTION(0x5, "nand", "io0")),
86 MPP_MODE(7,
87 MPP_FUNCTION(0x0, "gpio", NULL),
88 MPP_FUNCTION(0x1, "dev", "ad1"),
89 MPP_FUNCTION(0x2, "ptp", "clk"),
90 MPP_FUNCTION(0x3, "led", "p2"),
91 MPP_FUNCTION(0x4, "audio", "extclk"),
92 MPP_FUNCTION(0x5, "nand", "io1")),
93 MPP_MODE(8,
94 MPP_FUNCTION(0x0, "gpio", NULL),
95 MPP_FUNCTION(0x1, "dev ", "bootcs"),
96 MPP_FUNCTION(0x2, "spi0", "cs0"),
97 MPP_FUNCTION(0x3, "spi1", "cs0"),
98 MPP_FUNCTION(0x5, "nand", "ce")),
99 MPP_MODE(9,
100 MPP_FUNCTION(0x0, "gpio", NULL),
101 MPP_FUNCTION(0x1, "nf", "wen"),
102 MPP_FUNCTION(0x2, "spi0", "sck"),
103 MPP_FUNCTION(0x3, "spi1", "sck"),
104 MPP_FUNCTION(0x5, "nand", "we")),
105 MPP_MODE(10,
106 MPP_FUNCTION(0x0, "gpio", NULL),
107 MPP_FUNCTION(0x1, "nf", "ren"),
108 MPP_FUNCTION(0x2, "dram", "vttctrl"),
109 MPP_FUNCTION(0x3, "led", "c1"),
110 MPP_FUNCTION(0x5, "nand", "re"),
111 MPP_FUNCTION(0x6, "spi1", "sck")),
112 MPP_MODE(11,
113 MPP_FUNCTION(0x0, "gpio", NULL),
114 MPP_FUNCTION(0x1, "dev", "a0"),
115 MPP_FUNCTION(0x3, "led", "c2"),
116 MPP_FUNCTION(0x4, "audio", "sdo"),
117 MPP_FUNCTION(0x5, "nand", "cle")),
118 MPP_MODE(12,
119 MPP_FUNCTION(0x0, "gpio", NULL),
120 MPP_FUNCTION(0x1, "dev", "a1"),
121 MPP_FUNCTION(0x4, "audio", "bclk"),
122 MPP_FUNCTION(0x5, "nand", "ale")),
123 MPP_MODE(13,
124 MPP_FUNCTION(0x0, "gpio", NULL),
125 MPP_FUNCTION(0x1, "dev", "readyn"),
126 MPP_FUNCTION(0x2, "pcie0", "rstoutn"),
127 MPP_FUNCTION(0x3, "pcie1", "rstoutn"),
128 MPP_FUNCTION(0x5, "nand", "rb"),
129 MPP_FUNCTION(0x6, "spi1", "mosi")),
130 MPP_MODE(14,
131 MPP_FUNCTION(0x0, "gpio", NULL),
132 MPP_FUNCTION(0x2, "i2c0", "sda"),
133 MPP_FUNCTION(0x3, "uart1", "txd")),
134 MPP_MODE(15,
135 MPP_FUNCTION(0x0, "gpio", NULL),
136 MPP_FUNCTION(0x2, "i2c0", "sck"),
137 MPP_FUNCTION(0x3, "uart1", "rxd")),
138 MPP_MODE(16,
139 MPP_FUNCTION(0x0, "gpio", NULL),
140 MPP_FUNCTION(0x2, "uart0", "txd")),
141 MPP_MODE(17,
142 MPP_FUNCTION(0x0, "gpio", NULL),
143 MPP_FUNCTION(0x2, "uart0", "rxd")),
144 MPP_MODE(18,
145 MPP_FUNCTION(0x0, "gpio", NULL),
146 MPP_FUNCTION(0x2, "tdm", "intn")),
147 MPP_MODE(19,
148 MPP_FUNCTION(0x0, "gpio", NULL),
149 MPP_FUNCTION(0x2, "tdm", "rstn")),
150 MPP_MODE(20,
151 MPP_FUNCTION(0x0, "gpio", NULL),
152 MPP_FUNCTION(0x2, "tdm", "pclk")),
153 MPP_MODE(21,
154 MPP_FUNCTION(0x0, "gpio", NULL),
155 MPP_FUNCTION(0x2, "tdm", "fsync")),
156 MPP_MODE(22,
157 MPP_FUNCTION(0x0, "gpio", NULL),
158 MPP_FUNCTION(0x2, "tdm", "drx")),
159 MPP_MODE(23,
160 MPP_FUNCTION(0x0, "gpio", NULL),
161 MPP_FUNCTION(0x2, "tdm", "dtx")),
162 MPP_MODE(24,
163 MPP_FUNCTION(0x0, "gpio", NULL),
164 MPP_FUNCTION(0x1, "led", "p0"),
165 MPP_FUNCTION(0x2, "ge1", "rxd0"),
166 MPP_FUNCTION(0x3, "sd", "cmd"),
167 MPP_FUNCTION(0x4, "uart0", "rts"),
168 MPP_FUNCTION(0x5, "spi0", "cs0"),
169 MPP_FUNCTION(0x6, "dev", "cs1")),
170 MPP_MODE(25,
171 MPP_FUNCTION(0x0, "gpio", NULL),
172 MPP_FUNCTION(0x1, "led", "p2"),
173 MPP_FUNCTION(0x2, "ge1", "rxd1"),
174 MPP_FUNCTION(0x3, "sd", "d0"),
175 MPP_FUNCTION(0x4, "uart0", "cts"),
176 MPP_FUNCTION(0x5, "spi0", "mosi"),
177 MPP_FUNCTION(0x6, "dev", "cs2")),
178 MPP_MODE(26,
179 MPP_FUNCTION(0x0, "gpio", NULL),
180 MPP_FUNCTION(0x1, "pcie0", "clkreq"),
181 MPP_FUNCTION(0x2, "ge1", "rxd2"),
182 MPP_FUNCTION(0x3, "sd", "d2"),
183 MPP_FUNCTION(0x4, "uart1", "rts"),
184 MPP_FUNCTION(0x5, "spi0", "cs1"),
185 MPP_FUNCTION(0x6, "led", "c1")),
186 MPP_MODE(27,
187 MPP_FUNCTION(0x0, "gpio", NULL),
188 MPP_FUNCTION(0x1, "pcie1", "clkreq"),
189 MPP_FUNCTION(0x2, "ge1", "rxd3"),
190 MPP_FUNCTION(0x3, "sd", "d1"),
191 MPP_FUNCTION(0x4, "uart1", "cts"),
192 MPP_FUNCTION(0x5, "spi0", "miso"),
193 MPP_FUNCTION(0x6, "led", "c2")),
194 MPP_MODE(28,
195 MPP_FUNCTION(0x0, "gpio", NULL),
196 MPP_FUNCTION(0x1, "led", "p3"),
197 MPP_FUNCTION(0x2, "ge1", "txctl"),
198 MPP_FUNCTION(0x3, "sd", "clk"),
199 MPP_FUNCTION(0x5, "dram", "vttctrl")),
200 MPP_MODE(29,
201 MPP_FUNCTION(0x0, "gpio", NULL),
202 MPP_FUNCTION(0x1, "pcie1", "clkreq"),
203 MPP_FUNCTION(0x2, "ge1", "rxclk"),
204 MPP_FUNCTION(0x3, "sd", "d3"),
205 MPP_FUNCTION(0x5, "spi0", "sck"),
206 MPP_FUNCTION(0x6, "pcie0", "rstoutn")),
207 MPP_MODE(30,
208 MPP_FUNCTION(0x0, "gpio", NULL),
209 MPP_FUNCTION(0x2, "ge1", "txd0"),
210 MPP_FUNCTION(0x3, "spi1", "cs0"),
211 MPP_FUNCTION(0x5, "led", "p3"),
212 MPP_FUNCTION(0x6, "ptp", "eventreq")),
213 MPP_MODE(31,
214 MPP_FUNCTION(0x0, "gpio", NULL),
215 MPP_FUNCTION(0x2, "ge1", "txd1"),
216 MPP_FUNCTION(0x3, "spi1", "mosi"),
217 MPP_FUNCTION(0x5, "led", "p0")),
218 MPP_MODE(32,
219 MPP_FUNCTION(0x0, "gpio", NULL),
220 MPP_FUNCTION(0x2, "ge1", "txd2"),
221 MPP_FUNCTION(0x3, "spi1", "sck"),
222 MPP_FUNCTION(0x4, "ptp", "triggen"),
223 MPP_FUNCTION(0x5, "led", "c0")),
224 MPP_MODE(33,
225 MPP_FUNCTION(0x0, "gpio", NULL),
226 MPP_FUNCTION(0x2, "ge1", "txd3"),
227 MPP_FUNCTION(0x3, "spi1", "miso"),
228 MPP_FUNCTION(0x5, "led", "p2")),
229 MPP_MODE(34,
230 MPP_FUNCTION(0x0, "gpio", NULL),
231 MPP_FUNCTION(0x2, "ge1", "txclkout"),
232 MPP_FUNCTION(0x3, "spi1", "sck"),
233 MPP_FUNCTION(0x5, "led", "c1")),
234 MPP_MODE(35,
235 MPP_FUNCTION(0x0, "gpio", NULL),
236 MPP_FUNCTION(0x2, "ge1", "rxctl"),
237 MPP_FUNCTION(0x3, "spi1", "cs1"),
238 MPP_FUNCTION(0x4, "spi0", "cs2"),
239 MPP_FUNCTION(0x5, "led", "p1")),
240 MPP_MODE(36,
241 MPP_FUNCTION(0x0, "gpio", NULL),
242 MPP_FUNCTION(0x1, "pcie0", "clkreq"),
243 MPP_FUNCTION(0x5, "led", "c2")),
244 MPP_MODE(37,
245 MPP_FUNCTION(0x0, "gpio", NULL),
246 MPP_FUNCTION(0x1, "pcie0", "clkreq"),
247 MPP_FUNCTION(0x2, "tdm", "intn"),
248 MPP_FUNCTION(0x4, "ge", "mdc")),
249 MPP_MODE(38,
250 MPP_FUNCTION(0x0, "gpio", NULL),
251 MPP_FUNCTION(0x1, "pcie1", "clkreq"),
252 MPP_FUNCTION(0x4, "ge", "mdio")),
253 MPP_MODE(39,
254 MPP_FUNCTION(0x0, "gpio", NULL),
255 MPP_FUNCTION(0x4, "ref", "clkout"),
256 MPP_FUNCTION(0x5, "led", "p3")),
257 MPP_MODE(40,
258 MPP_FUNCTION(0x0, "gpio", NULL),
259 MPP_FUNCTION(0x4, "uart1", "txd"),
260 MPP_FUNCTION(0x5, "led", "p0")),
261 MPP_MODE(41,
262 MPP_FUNCTION(0x0, "gpio", NULL),
263 MPP_FUNCTION(0x4, "uart1", "rxd"),
264 MPP_FUNCTION(0x5, "led", "p1")),
265 MPP_MODE(42,
266 MPP_FUNCTION(0x0, "gpio", NULL),
267 MPP_FUNCTION(0x3, "spi1", "cs2"),
268 MPP_FUNCTION(0x4, "led", "c0"),
269 MPP_FUNCTION(0x6, "ptp", "clk")),
270 MPP_MODE(43,
271 MPP_FUNCTION(0x0, "gpio", NULL),
272 MPP_FUNCTION(0x2, "sata0", "prsnt"),
273 MPP_FUNCTION(0x4, "dram", "vttctrl"),
274 MPP_FUNCTION(0x5, "led", "c1")),
275 MPP_MODE(44,
276 MPP_FUNCTION(0x0, "gpio", NULL),
277 MPP_FUNCTION(0x4, "sata0", "prsnt")),
278 MPP_MODE(45,
279 MPP_FUNCTION(0x0, "gpio", NULL),
280 MPP_FUNCTION(0x2, "spi0", "cs2"),
281 MPP_FUNCTION(0x4, "pcie0", "rstoutn"),
282 MPP_FUNCTION(0x5, "led", "c2"),
283 MPP_FUNCTION(0x6, "spi1", "cs2")),
284 MPP_MODE(46,
285 MPP_FUNCTION(0x0, "gpio", NULL),
286 MPP_FUNCTION(0x1, "led", "p0"),
287 MPP_FUNCTION(0x2, "ge0", "txd0"),
288 MPP_FUNCTION(0x3, "ge1", "txd0"),
289 MPP_FUNCTION(0x6, "dev", "wen1")),
290 MPP_MODE(47,
291 MPP_FUNCTION(0x0, "gpio", NULL),
292 MPP_FUNCTION(0x1, "led", "p1"),
293 MPP_FUNCTION(0x2, "ge0", "txd1"),
294 MPP_FUNCTION(0x3, "ge1", "txd1"),
295 MPP_FUNCTION(0x5, "ptp", "triggen"),
296 MPP_FUNCTION(0x6, "dev", "ale0")),
297 MPP_MODE(48,
298 MPP_FUNCTION(0x0, "gpio", NULL),
299 MPP_FUNCTION(0x1, "led", "p2"),
300 MPP_FUNCTION(0x2, "ge0", "txd2"),
301 MPP_FUNCTION(0x3, "ge1", "txd2"),
302 MPP_FUNCTION(0x6, "dev", "ale1")),
303 MPP_MODE(49,
304 MPP_FUNCTION(0x0, "gpio", NULL),
305 MPP_FUNCTION(0x1, "led", "p3"),
306 MPP_FUNCTION(0x2, "ge0", "txd3"),
307 MPP_FUNCTION(0x3, "ge1", "txd3"),
308 MPP_FUNCTION(0x6, "dev", "a2")),
309 MPP_MODE(50,
310 MPP_FUNCTION(0x0, "gpio", NULL),
311 MPP_FUNCTION(0x1, "led", "c0"),
312 MPP_FUNCTION(0x2, "ge0", "rxd0"),
313 MPP_FUNCTION(0x3, "ge1", "rxd0"),
314 MPP_FUNCTION(0x5, "ptp", "eventreq"),
315 MPP_FUNCTION(0x6, "dev", "ad12")),
316 MPP_MODE(51,
317 MPP_FUNCTION(0x0, "gpio", NULL),
318 MPP_FUNCTION(0x1, "led", "c1"),
319 MPP_FUNCTION(0x2, "ge0", "rxd1"),
320 MPP_FUNCTION(0x3, "ge1", "rxd1"),
321 MPP_FUNCTION(0x6, "dev", "ad8")),
322 MPP_MODE(52,
323 MPP_FUNCTION(0x0, "gpio", NULL),
324 MPP_FUNCTION(0x1, "led", "c2"),
325 MPP_FUNCTION(0x2, "ge0", "rxd2"),
326 MPP_FUNCTION(0x3, "ge1", "rxd2"),
327 MPP_FUNCTION(0x5, "i2c0", "sda"),
328 MPP_FUNCTION(0x6, "dev", "ad9")),
329 MPP_MODE(53,
330 MPP_FUNCTION(0x0, "gpio", NULL),
331 MPP_FUNCTION(0x1, "pcie1", "rstoutn"),
332 MPP_FUNCTION(0x2, "ge0", "rxd3"),
333 MPP_FUNCTION(0x3, "ge1", "rxd3"),
334 MPP_FUNCTION(0x5, "i2c0", "sck"),
335 MPP_FUNCTION(0x6, "dev", "ad10")),
336 MPP_MODE(54,
337 MPP_FUNCTION(0x0, "gpio", NULL),
338 MPP_FUNCTION(0x1, "pcie0", "rstoutn"),
339 MPP_FUNCTION(0x2, "ge0", "rxctl"),
340 MPP_FUNCTION(0x3, "ge1", "rxctl"),
341 MPP_FUNCTION(0x6, "dev", "ad11")),
342 MPP_MODE(55,
343 MPP_FUNCTION(0x0, "gpio", NULL),
344 MPP_FUNCTION(0x2, "ge0", "rxclk"),
345 MPP_FUNCTION(0x3, "ge1", "rxclk"),
346 MPP_FUNCTION(0x6, "dev", "cs0")),
347 MPP_MODE(56,
348 MPP_FUNCTION(0x0, "gpio", NULL),
349 MPP_FUNCTION(0x2, "ge0", "txclkout"),
350 MPP_FUNCTION(0x3, "ge1", "txclkout"),
351 MPP_FUNCTION(0x6, "dev", "oe")),
352 MPP_MODE(57,
353 MPP_FUNCTION(0x0, "gpio", NULL),
354 MPP_FUNCTION(0x2, "ge0", "txctl"),
355 MPP_FUNCTION(0x3, "ge1", "txctl"),
356 MPP_FUNCTION(0x6, "dev", "wen0")),
357 MPP_MODE(58,
358 MPP_FUNCTION(0x0, "gpio", NULL),
359 MPP_FUNCTION(0x4, "led", "c0")),
360 MPP_MODE(59,
361 MPP_FUNCTION(0x0, "gpio", NULL),
362 MPP_FUNCTION(0x4, "led", "c1")),
363 MPP_MODE(60,
364 MPP_FUNCTION(0x0, "gpio", NULL),
365 MPP_FUNCTION(0x2, "uart1", "txd"),
366 MPP_FUNCTION(0x4, "led", "c2"),
367 MPP_FUNCTION(0x6, "dev", "ad13")),
368 MPP_MODE(61,
369 MPP_FUNCTION(0x0, "gpio", NULL),
370 MPP_FUNCTION(0x1, "i2c1", "sda"),
371 MPP_FUNCTION(0x2, "uart1", "rxd"),
372 MPP_FUNCTION(0x3, "spi1", "cs2"),
373 MPP_FUNCTION(0x4, "led", "p0"),
374 MPP_FUNCTION(0x6, "dev", "ad14")),
375 MPP_MODE(62,
376 MPP_FUNCTION(0x0, "gpio", NULL),
377 MPP_FUNCTION(0x1, "i2c1", "sck"),
378 MPP_FUNCTION(0x4, "led", "p1"),
379 MPP_FUNCTION(0x6, "dev", "ad15")),
380 MPP_MODE(63,
381 MPP_FUNCTION(0x0, "gpio", NULL),
382 MPP_FUNCTION(0x2, "ptp", "triggen"),
383 MPP_FUNCTION(0x4, "led", "p2"),
384 MPP_FUNCTION(0x6, "dev", "burst")),
385 MPP_MODE(64,
386 MPP_FUNCTION(0x0, "gpio", NULL),
387 MPP_FUNCTION(0x2, "dram", "vttctrl"),
388 MPP_FUNCTION(0x4, "led", "p3")),
389 MPP_MODE(65,
390 MPP_FUNCTION(0x0, "gpio", NULL),
391 MPP_FUNCTION(0x1, "sata1", "prsnt")),
392 MPP_MODE(66,
393 MPP_FUNCTION(0x0, "gpio", NULL),
394 MPP_FUNCTION(0x2, "ptp", "eventreq"),
395 MPP_FUNCTION(0x4, "spi1", "cs3"),
396 MPP_FUNCTION(0x5, "pcie0", "rstoutn"),
397 MPP_FUNCTION(0x6, "dev", "cs3")),
398};
399
400static struct mvebu_pinctrl_soc_info armada_375_pinctrl_info;
401
402static struct of_device_id armada_375_pinctrl_of_match[] = {
403 { .compatible = "marvell,mv88f6720-pinctrl" },
404 { },
405};
406
407static struct mvebu_mpp_ctrl mv88f6720_mpp_controls[] = {
408 MPP_FUNC_CTRL(0, 69, NULL, armada_375_mpp_ctrl),
409};
410
411static struct pinctrl_gpio_range mv88f6720_mpp_gpio_ranges[] = {
412 MPP_GPIO_RANGE(0, 0, 0, 32),
413 MPP_GPIO_RANGE(1, 32, 32, 32),
414 MPP_GPIO_RANGE(2, 64, 64, 3),
415};
416
417static int armada_375_pinctrl_probe(struct platform_device *pdev)
418{
419 struct mvebu_pinctrl_soc_info *soc = &armada_375_pinctrl_info;
420 struct resource *res;
421
422 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
423 mpp_base = devm_ioremap_resource(&pdev->dev, res);
424 if (IS_ERR(mpp_base))
425 return PTR_ERR(mpp_base);
426
427 soc->variant = 0; /* no variants for Armada 375 */
428 soc->controls = mv88f6720_mpp_controls;
429 soc->ncontrols = ARRAY_SIZE(mv88f6720_mpp_controls);
430 soc->modes = mv88f6720_mpp_modes;
431 soc->nmodes = ARRAY_SIZE(mv88f6720_mpp_modes);
432 soc->gpioranges = mv88f6720_mpp_gpio_ranges;
433 soc->ngpioranges = ARRAY_SIZE(mv88f6720_mpp_gpio_ranges);
434
435 pdev->dev.platform_data = soc;
436
437 return mvebu_pinctrl_probe(pdev);
438}
439
440static int armada_375_pinctrl_remove(struct platform_device *pdev)
441{
442 return mvebu_pinctrl_remove(pdev);
443}
444
445static struct platform_driver armada_375_pinctrl_driver = {
446 .driver = {
447 .name = "armada-375-pinctrl",
448 .owner = THIS_MODULE,
449 .of_match_table = of_match_ptr(armada_375_pinctrl_of_match),
450 },
451 .probe = armada_375_pinctrl_probe,
452 .remove = armada_375_pinctrl_remove,
453};
454
455module_platform_driver(armada_375_pinctrl_driver);
456
457MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
458MODULE_DESCRIPTION("Marvell Armada 375 pinctrl driver");
459MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c
new file mode 100644
index 000000000000..1049f82fb62f
--- /dev/null
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c
@@ -0,0 +1,462 @@
1/*
2 * Marvell Armada 380/385 pinctrl driver based on mvebu pinctrl core
3 *
4 * Copyright (C) 2013 Marvell
5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/err.h>
15#include <linux/init.h>
16#include <linux/io.h>
17#include <linux/module.h>
18#include <linux/platform_device.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/pinctrl/pinctrl.h>
22
23#include "pinctrl-mvebu.h"
24
25static void __iomem *mpp_base;
26
27static int armada_38x_mpp_ctrl_get(unsigned pid, unsigned long *config)
28{
29 return default_mpp_ctrl_get(mpp_base, pid, config);
30}
31
32static int armada_38x_mpp_ctrl_set(unsigned pid, unsigned long config)
33{
34 return default_mpp_ctrl_set(mpp_base, pid, config);
35}
36
37enum {
38 V_88F6810 = BIT(0),
39 V_88F6820 = BIT(1),
40 V_88F6828 = BIT(2),
41 V_88F6810_PLUS = (V_88F6810 | V_88F6820 | V_88F6828),
42 V_88F6820_PLUS = (V_88F6820 | V_88F6828),
43};
44
45static struct mvebu_mpp_mode armada_38x_mpp_modes[] = {
46 MPP_MODE(0,
47 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
48 MPP_VAR_FUNCTION(1, "ua0", "rxd", V_88F6810_PLUS)),
49 MPP_MODE(1,
50 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
51 MPP_VAR_FUNCTION(1, "ua0", "txd", V_88F6810_PLUS)),
52 MPP_MODE(2,
53 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
54 MPP_VAR_FUNCTION(1, "i2c0", "sck", V_88F6810_PLUS)),
55 MPP_MODE(3,
56 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
57 MPP_VAR_FUNCTION(1, "i2c0", "sda", V_88F6810_PLUS)),
58 MPP_MODE(4,
59 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
60 MPP_VAR_FUNCTION(1, "ge", "mdc", V_88F6810_PLUS),
61 MPP_VAR_FUNCTION(2, "ua1", "txd", V_88F6810_PLUS),
62 MPP_VAR_FUNCTION(3, "ua0", "rts", V_88F6810_PLUS)),
63 MPP_MODE(5,
64 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
65 MPP_VAR_FUNCTION(1, "ge", "mdio", V_88F6810_PLUS),
66 MPP_VAR_FUNCTION(2, "ua1", "rxd", V_88F6810_PLUS),
67 MPP_VAR_FUNCTION(3, "ua0", "cts", V_88F6810_PLUS)),
68 MPP_MODE(6,
69 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
70 MPP_VAR_FUNCTION(1, "ge0", "txclkout", V_88F6810_PLUS),
71 MPP_VAR_FUNCTION(2, "ge0", "crs", V_88F6810_PLUS),
72 MPP_VAR_FUNCTION(5, "dev", "cs3", V_88F6810_PLUS)),
73 MPP_MODE(7,
74 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
75 MPP_VAR_FUNCTION(1, "ge0", "txd0", V_88F6810_PLUS),
76 MPP_VAR_FUNCTION(5, "dev", "ad9", V_88F6810_PLUS)),
77 MPP_MODE(8,
78 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
79 MPP_VAR_FUNCTION(1, "ge0", "txd1", V_88F6810_PLUS),
80 MPP_VAR_FUNCTION(5, "dev", "ad10", V_88F6810_PLUS)),
81 MPP_MODE(9,
82 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
83 MPP_VAR_FUNCTION(1, "ge0", "txd2", V_88F6810_PLUS),
84 MPP_VAR_FUNCTION(5, "dev", "ad11", V_88F6810_PLUS)),
85 MPP_MODE(10,
86 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
87 MPP_VAR_FUNCTION(1, "ge0", "txd3", V_88F6810_PLUS),
88 MPP_VAR_FUNCTION(5, "dev", "ad12", V_88F6810_PLUS)),
89 MPP_MODE(11,
90 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
91 MPP_VAR_FUNCTION(1, "ge0", "txctl", V_88F6810_PLUS),
92 MPP_VAR_FUNCTION(5, "dev", "ad13", V_88F6810_PLUS)),
93 MPP_MODE(12,
94 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
95 MPP_VAR_FUNCTION(1, "ge0", "rxd0", V_88F6810_PLUS),
96 MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS),
97 MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS),
98 MPP_VAR_FUNCTION(4, "spi0", "cs1", V_88F6810_PLUS),
99 MPP_VAR_FUNCTION(5, "dev", "ad14", V_88F6810_PLUS)),
100 MPP_MODE(13,
101 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
102 MPP_VAR_FUNCTION(1, "ge0", "rxd1", V_88F6810_PLUS),
103 MPP_VAR_FUNCTION(2, "pcie0", "clkreq", V_88F6810_PLUS),
104 MPP_VAR_FUNCTION(3, "pcie1", "clkreq", V_88F6820_PLUS),
105 MPP_VAR_FUNCTION(4, "spi0", "cs2", V_88F6810_PLUS),
106 MPP_VAR_FUNCTION(5, "dev", "ad15", V_88F6810_PLUS)),
107 MPP_MODE(14,
108 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
109 MPP_VAR_FUNCTION(1, "ge0", "rxd2", V_88F6810_PLUS),
110 MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS),
111 MPP_VAR_FUNCTION(3, "m", "vtt_ctrl", V_88F6810_PLUS),
112 MPP_VAR_FUNCTION(4, "spi0", "cs3", V_88F6810_PLUS),
113 MPP_VAR_FUNCTION(5, "dev", "wen1", V_88F6810_PLUS)),
114 MPP_MODE(15,
115 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
116 MPP_VAR_FUNCTION(1, "ge0", "rxd3", V_88F6810_PLUS),
117 MPP_VAR_FUNCTION(2, "ge", "mdc slave", V_88F6810_PLUS),
118 MPP_VAR_FUNCTION(3, "pcie0", "rstout", V_88F6810_PLUS),
119 MPP_VAR_FUNCTION(4, "spi0", "mosi", V_88F6810_PLUS),
120 MPP_VAR_FUNCTION(5, "pcie1", "rstout", V_88F6820_PLUS)),
121 MPP_MODE(16,
122 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
123 MPP_VAR_FUNCTION(1, "ge0", "rxctl", V_88F6810_PLUS),
124 MPP_VAR_FUNCTION(2, "ge", "mdio slave", V_88F6810_PLUS),
125 MPP_VAR_FUNCTION(3, "m", "decc_err", V_88F6810_PLUS),
126 MPP_VAR_FUNCTION(4, "spi0", "miso", V_88F6810_PLUS),
127 MPP_VAR_FUNCTION(5, "pcie0", "clkreq", V_88F6810_PLUS)),
128 MPP_MODE(17,
129 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
130 MPP_VAR_FUNCTION(1, "ge0", "rxclk", V_88F6810_PLUS),
131 MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS),
132 MPP_VAR_FUNCTION(3, "ua1", "rxd", V_88F6810_PLUS),
133 MPP_VAR_FUNCTION(4, "spi0", "sck", V_88F6810_PLUS),
134 MPP_VAR_FUNCTION(5, "sata1", "prsnt", V_88F6810_PLUS)),
135 MPP_MODE(18,
136 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
137 MPP_VAR_FUNCTION(1, "ge0", "rxerr", V_88F6810_PLUS),
138 MPP_VAR_FUNCTION(2, "ptp", "trig_gen", V_88F6810_PLUS),
139 MPP_VAR_FUNCTION(3, "ua1", "txd", V_88F6810_PLUS),
140 MPP_VAR_FUNCTION(4, "spi0", "cs0", V_88F6810_PLUS),
141 MPP_VAR_FUNCTION(5, "pcie1", "rstout", V_88F6820_PLUS)),
142 MPP_MODE(19,
143 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
144 MPP_VAR_FUNCTION(1, "ge0", "col", V_88F6810_PLUS),
145 MPP_VAR_FUNCTION(2, "ptp", "event_req", V_88F6810_PLUS),
146 MPP_VAR_FUNCTION(3, "pcie0", "clkreq", V_88F6810_PLUS),
147 MPP_VAR_FUNCTION(4, "sata1", "prsnt", V_88F6810_PLUS),
148 MPP_VAR_FUNCTION(5, "ua0", "cts", V_88F6810_PLUS)),
149 MPP_MODE(20,
150 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
151 MPP_VAR_FUNCTION(1, "ge0", "txclk", V_88F6810_PLUS),
152 MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS),
153 MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS),
154 MPP_VAR_FUNCTION(4, "sata0", "prsnt", V_88F6810_PLUS),
155 MPP_VAR_FUNCTION(5, "ua0", "rts", V_88F6810_PLUS)),
156 MPP_MODE(21,
157 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
158 MPP_VAR_FUNCTION(1, "spi0", "cs1", V_88F6810_PLUS),
159 MPP_VAR_FUNCTION(2, "ge1", "rxd0", V_88F6810_PLUS),
160 MPP_VAR_FUNCTION(3, "sata0", "prsnt", V_88F6810_PLUS),
161 MPP_VAR_FUNCTION(4, "sd0", "cmd", V_88F6810_PLUS),
162 MPP_VAR_FUNCTION(5, "dev", "bootcs", V_88F6810_PLUS)),
163 MPP_MODE(22,
164 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
165 MPP_VAR_FUNCTION(1, "spi0", "mosi", V_88F6810_PLUS),
166 MPP_VAR_FUNCTION(5, "dev", "ad0", V_88F6810_PLUS)),
167 MPP_MODE(23,
168 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
169 MPP_VAR_FUNCTION(1, "spi0", "sck", V_88F6810_PLUS),
170 MPP_VAR_FUNCTION(5, "dev", "ad2", V_88F6810_PLUS)),
171 MPP_MODE(24,
172 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
173 MPP_VAR_FUNCTION(1, "spi0", "miso", V_88F6810_PLUS),
174 MPP_VAR_FUNCTION(2, "ua0", "cts", V_88F6810_PLUS),
175 MPP_VAR_FUNCTION(3, "ua1", "rxd", V_88F6810_PLUS),
176 MPP_VAR_FUNCTION(4, "sd0", "d4", V_88F6810_PLUS),
177 MPP_VAR_FUNCTION(5, "dev", "ready", V_88F6810_PLUS)),
178 MPP_MODE(25,
179 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
180 MPP_VAR_FUNCTION(1, "spi0", "cs0", V_88F6810_PLUS),
181 MPP_VAR_FUNCTION(2, "ua0", "rts", V_88F6810_PLUS),
182 MPP_VAR_FUNCTION(3, "ua1", "txd", V_88F6810_PLUS),
183 MPP_VAR_FUNCTION(4, "sd0", "d5", V_88F6810_PLUS),
184 MPP_VAR_FUNCTION(5, "dev", "cs0", V_88F6810_PLUS)),
185 MPP_MODE(26,
186 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
187 MPP_VAR_FUNCTION(1, "spi0", "cs2", V_88F6810_PLUS),
188 MPP_VAR_FUNCTION(3, "i2c1", "sck", V_88F6810_PLUS),
189 MPP_VAR_FUNCTION(4, "sd0", "d6", V_88F6810_PLUS),
190 MPP_VAR_FUNCTION(5, "dev", "cs1", V_88F6810_PLUS)),
191 MPP_MODE(27,
192 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
193 MPP_VAR_FUNCTION(1, "spi0", "cs3", V_88F6810_PLUS),
194 MPP_VAR_FUNCTION(2, "ge1", "txclkout", V_88F6810_PLUS),
195 MPP_VAR_FUNCTION(3, "i2c1", "sda", V_88F6810_PLUS),
196 MPP_VAR_FUNCTION(4, "sd0", "d7", V_88F6810_PLUS),
197 MPP_VAR_FUNCTION(5, "dev", "cs2", V_88F6810_PLUS)),
198 MPP_MODE(28,
199 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
200 MPP_VAR_FUNCTION(2, "ge1", "txd0", V_88F6810_PLUS),
201 MPP_VAR_FUNCTION(4, "sd0", "clk", V_88F6810_PLUS),
202 MPP_VAR_FUNCTION(5, "dev", "ad5", V_88F6810_PLUS)),
203 MPP_MODE(29,
204 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
205 MPP_VAR_FUNCTION(2, "ge1", "txd1", V_88F6810_PLUS),
206 MPP_VAR_FUNCTION(5, "dev", "ale0", V_88F6810_PLUS)),
207 MPP_MODE(30,
208 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
209 MPP_VAR_FUNCTION(2, "ge1", "txd2", V_88F6810_PLUS),
210 MPP_VAR_FUNCTION(5, "dev", "oen", V_88F6810_PLUS)),
211 MPP_MODE(31,
212 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
213 MPP_VAR_FUNCTION(2, "ge1", "txd3", V_88F6810_PLUS),
214 MPP_VAR_FUNCTION(5, "dev", "ale1", V_88F6810_PLUS)),
215 MPP_MODE(32,
216 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
217 MPP_VAR_FUNCTION(2, "ge1", "txctl", V_88F6810_PLUS),
218 MPP_VAR_FUNCTION(5, "dev", "wen0", V_88F6810_PLUS)),
219 MPP_MODE(33,
220 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
221 MPP_VAR_FUNCTION(1, "m", "decc_err", V_88F6810_PLUS),
222 MPP_VAR_FUNCTION(5, "dev", "ad3", V_88F6810_PLUS)),
223 MPP_MODE(34,
224 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
225 MPP_VAR_FUNCTION(5, "dev", "ad1", V_88F6810_PLUS)),
226 MPP_MODE(35,
227 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
228 MPP_VAR_FUNCTION(1, "ref", "clk_out1", V_88F6810_PLUS),
229 MPP_VAR_FUNCTION(5, "dev", "a1", V_88F6810_PLUS)),
230 MPP_MODE(36,
231 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
232 MPP_VAR_FUNCTION(1, "ptp", "trig_gen", V_88F6810_PLUS),
233 MPP_VAR_FUNCTION(5, "dev", "a0", V_88F6810_PLUS)),
234 MPP_MODE(37,
235 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
236 MPP_VAR_FUNCTION(1, "ptp", "clk", V_88F6810_PLUS),
237 MPP_VAR_FUNCTION(2, "ge1", "rxclk", V_88F6810_PLUS),
238 MPP_VAR_FUNCTION(4, "sd0", "d3", V_88F6810_PLUS),
239 MPP_VAR_FUNCTION(5, "dev", "ad8", V_88F6810_PLUS)),
240 MPP_MODE(38,
241 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
242 MPP_VAR_FUNCTION(1, "ptp", "event_req", V_88F6810_PLUS),
243 MPP_VAR_FUNCTION(2, "ge1", "rxd1", V_88F6810_PLUS),
244 MPP_VAR_FUNCTION(3, "ref", "clk_out0", V_88F6810_PLUS),
245 MPP_VAR_FUNCTION(4, "sd0", "d0", V_88F6810_PLUS),
246 MPP_VAR_FUNCTION(5, "dev", "ad4", V_88F6810_PLUS)),
247 MPP_MODE(39,
248 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
249 MPP_VAR_FUNCTION(1, "i2c1", "sck", V_88F6810_PLUS),
250 MPP_VAR_FUNCTION(2, "ge1", "rxd2", V_88F6810_PLUS),
251 MPP_VAR_FUNCTION(3, "ua0", "cts", V_88F6810_PLUS),
252 MPP_VAR_FUNCTION(4, "sd0", "d1", V_88F6810_PLUS),
253 MPP_VAR_FUNCTION(5, "dev", "a2", V_88F6810_PLUS)),
254 MPP_MODE(40,
255 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
256 MPP_VAR_FUNCTION(1, "i2c1", "sda", V_88F6810_PLUS),
257 MPP_VAR_FUNCTION(2, "ge1", "rxd3", V_88F6810_PLUS),
258 MPP_VAR_FUNCTION(3, "ua0", "rts", V_88F6810_PLUS),
259 MPP_VAR_FUNCTION(4, "sd0", "d2", V_88F6810_PLUS),
260 MPP_VAR_FUNCTION(5, "dev", "ad6", V_88F6810_PLUS)),
261 MPP_MODE(41,
262 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
263 MPP_VAR_FUNCTION(1, "ua1", "rxd", V_88F6810_PLUS),
264 MPP_VAR_FUNCTION(2, "ge1", "rxctl", V_88F6810_PLUS),
265 MPP_VAR_FUNCTION(3, "ua0", "cts", V_88F6810_PLUS),
266 MPP_VAR_FUNCTION(4, "spi1", "cs3", V_88F6810_PLUS),
267 MPP_VAR_FUNCTION(5, "dev", "burst/last", V_88F6810_PLUS)),
268 MPP_MODE(42,
269 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
270 MPP_VAR_FUNCTION(1, "ua1", "txd", V_88F6810_PLUS),
271 MPP_VAR_FUNCTION(3, "ua0", "rts", V_88F6810_PLUS),
272 MPP_VAR_FUNCTION(5, "dev", "ad7", V_88F6810_PLUS)),
273 MPP_MODE(43,
274 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
275 MPP_VAR_FUNCTION(1, "pcie0", "clkreq", V_88F6810_PLUS),
276 MPP_VAR_FUNCTION(2, "m", "vtt_ctrl", V_88F6810_PLUS),
277 MPP_VAR_FUNCTION(3, "m", "decc_err", V_88F6810_PLUS),
278 MPP_VAR_FUNCTION(4, "pcie0", "rstout", V_88F6810_PLUS),
279 MPP_VAR_FUNCTION(5, "dev", "clkout", V_88F6810_PLUS)),
280 MPP_MODE(44,
281 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
282 MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS),
283 MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6810_PLUS),
284 MPP_VAR_FUNCTION(3, "sata2", "prsnt", V_88F6828),
285 MPP_VAR_FUNCTION(4, "sata3", "prsnt", V_88F6828),
286 MPP_VAR_FUNCTION(5, "pcie0", "rstout", V_88F6810_PLUS)),
287 MPP_MODE(45,
288 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
289 MPP_VAR_FUNCTION(1, "ref", "clk_out0", V_88F6810_PLUS),
290 MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS),
291 MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS),
292 MPP_VAR_FUNCTION(4, "pcie2", "rstout", V_88F6810_PLUS),
293 MPP_VAR_FUNCTION(5, "pcie3", "rstout", V_88F6810_PLUS)),
294 MPP_MODE(46,
295 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
296 MPP_VAR_FUNCTION(1, "ref", "clk_out1", V_88F6810_PLUS),
297 MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS),
298 MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS),
299 MPP_VAR_FUNCTION(4, "pcie2", "rstout", V_88F6810_PLUS),
300 MPP_VAR_FUNCTION(5, "pcie3", "rstout", V_88F6810_PLUS)),
301 MPP_MODE(47,
302 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
303 MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS),
304 MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6810_PLUS),
305 MPP_VAR_FUNCTION(3, "sata2", "prsnt", V_88F6828),
306 MPP_VAR_FUNCTION(4, "spi1", "cs2", V_88F6810_PLUS),
307 MPP_VAR_FUNCTION(5, "sata3", "prsnt", V_88F6828)),
308 MPP_MODE(48,
309 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
310 MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS),
311 MPP_VAR_FUNCTION(2, "m", "vtt_ctrl", V_88F6810_PLUS),
312 MPP_VAR_FUNCTION(3, "tdm2c", "pclk", V_88F6810_PLUS),
313 MPP_VAR_FUNCTION(4, "audio", "mclk", V_88F6810_PLUS),
314 MPP_VAR_FUNCTION(5, "sd0", "d4", V_88F6810_PLUS)),
315 MPP_MODE(49,
316 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
317 MPP_VAR_FUNCTION(1, "sata2", "prsnt", V_88F6828),
318 MPP_VAR_FUNCTION(2, "sata3", "prsnt", V_88F6828),
319 MPP_VAR_FUNCTION(3, "tdm2c", "fsync", V_88F6810_PLUS),
320 MPP_VAR_FUNCTION(4, "audio", "lrclk", V_88F6810_PLUS),
321 MPP_VAR_FUNCTION(5, "sd0", "d5", V_88F6810_PLUS)),
322 MPP_MODE(50,
323 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
324 MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6810_PLUS),
325 MPP_VAR_FUNCTION(2, "pcie1", "rstout", V_88F6820_PLUS),
326 MPP_VAR_FUNCTION(3, "tdm2c", "drx", V_88F6810_PLUS),
327 MPP_VAR_FUNCTION(4, "audio", "extclk", V_88F6810_PLUS),
328 MPP_VAR_FUNCTION(5, "sd0", "cmd", V_88F6810_PLUS)),
329 MPP_MODE(51,
330 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
331 MPP_VAR_FUNCTION(3, "tdm2c", "dtx", V_88F6810_PLUS),
332 MPP_VAR_FUNCTION(4, "audio", "sdo", V_88F6810_PLUS),
333 MPP_VAR_FUNCTION(5, "m", "decc_err", V_88F6810_PLUS)),
334 MPP_MODE(52,
335 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
336 MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6810_PLUS),
337 MPP_VAR_FUNCTION(2, "pcie1", "rstout", V_88F6820_PLUS),
338 MPP_VAR_FUNCTION(3, "tdm2c", "intn", V_88F6810_PLUS),
339 MPP_VAR_FUNCTION(4, "audio", "sdi", V_88F6810_PLUS),
340 MPP_VAR_FUNCTION(5, "sd0", "d6", V_88F6810_PLUS)),
341 MPP_MODE(53,
342 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
343 MPP_VAR_FUNCTION(1, "sata1", "prsnt", V_88F6810_PLUS),
344 MPP_VAR_FUNCTION(2, "sata0", "prsnt", V_88F6810_PLUS),
345 MPP_VAR_FUNCTION(3, "tdm2c", "rstn", V_88F6810_PLUS),
346 MPP_VAR_FUNCTION(4, "audio", "bclk", V_88F6810_PLUS),
347 MPP_VAR_FUNCTION(5, "sd0", "d7", V_88F6810_PLUS)),
348 MPP_MODE(54,
349 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
350 MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS),
351 MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6810_PLUS),
352 MPP_VAR_FUNCTION(3, "pcie0", "rstout", V_88F6810_PLUS),
353 MPP_VAR_FUNCTION(4, "pcie1", "rstout", V_88F6820_PLUS),
354 MPP_VAR_FUNCTION(5, "sd0", "d3", V_88F6810_PLUS)),
355 MPP_MODE(55,
356 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
357 MPP_VAR_FUNCTION(1, "ua1", "cts", V_88F6810_PLUS),
358 MPP_VAR_FUNCTION(2, "ge", "mdio", V_88F6810_PLUS),
359 MPP_VAR_FUNCTION(3, "pcie1", "clkreq", V_88F6820_PLUS),
360 MPP_VAR_FUNCTION(4, "spi1", "cs1", V_88F6810_PLUS),
361 MPP_VAR_FUNCTION(5, "sd0", "d0", V_88F6810_PLUS)),
362 MPP_MODE(56,
363 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
364 MPP_VAR_FUNCTION(1, "ua1", "rts", V_88F6810_PLUS),
365 MPP_VAR_FUNCTION(2, "ge", "mdc", V_88F6810_PLUS),
366 MPP_VAR_FUNCTION(3, "m", "decc_err", V_88F6810_PLUS),
367 MPP_VAR_FUNCTION(4, "spi1", "mosi", V_88F6810_PLUS)),
368 MPP_MODE(57,
369 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
370 MPP_VAR_FUNCTION(4, "spi1", "sck", V_88F6810_PLUS),
371 MPP_VAR_FUNCTION(5, "sd0", "clk", V_88F6810_PLUS)),
372 MPP_MODE(58,
373 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
374 MPP_VAR_FUNCTION(1, "pcie1", "clkreq", V_88F6820_PLUS),
375 MPP_VAR_FUNCTION(2, "i2c1", "sck", V_88F6810_PLUS),
376 MPP_VAR_FUNCTION(3, "pcie2", "clkreq", V_88F6810_PLUS),
377 MPP_VAR_FUNCTION(4, "spi1", "miso", V_88F6810_PLUS),
378 MPP_VAR_FUNCTION(5, "sd0", "d1", V_88F6810_PLUS)),
379 MPP_MODE(59,
380 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
381 MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6810_PLUS),
382 MPP_VAR_FUNCTION(2, "i2c1", "sda", V_88F6810_PLUS),
383 MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS),
384 MPP_VAR_FUNCTION(4, "spi1", "cs0", V_88F6810_PLUS),
385 MPP_VAR_FUNCTION(5, "sd0", "d2", V_88F6810_PLUS)),
386};
387
388static struct mvebu_pinctrl_soc_info armada_38x_pinctrl_info;
389
390static struct of_device_id armada_38x_pinctrl_of_match[] = {
391 {
392 .compatible = "marvell,mv88f6810-pinctrl",
393 .data = (void *) V_88F6810,
394 },
395 {
396 .compatible = "marvell,mv88f6820-pinctrl",
397 .data = (void *) V_88F6820,
398 },
399 {
400 .compatible = "marvell,mv88f6828-pinctrl",
401 .data = (void *) V_88F6828,
402 },
403 { },
404};
405
406static struct mvebu_mpp_ctrl armada_38x_mpp_controls[] = {
407 MPP_FUNC_CTRL(0, 59, NULL, armada_38x_mpp_ctrl),
408};
409
410static struct pinctrl_gpio_range armada_38x_mpp_gpio_ranges[] = {
411 MPP_GPIO_RANGE(0, 0, 0, 32),
412 MPP_GPIO_RANGE(1, 32, 32, 27),
413};
414
415static int armada_38x_pinctrl_probe(struct platform_device *pdev)
416{
417 struct mvebu_pinctrl_soc_info *soc = &armada_38x_pinctrl_info;
418 const struct of_device_id *match =
419 of_match_device(armada_38x_pinctrl_of_match, &pdev->dev);
420 struct resource *res;
421
422 if (!match)
423 return -ENODEV;
424
425 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
426 mpp_base = devm_ioremap_resource(&pdev->dev, res);
427 if (IS_ERR(mpp_base))
428 return PTR_ERR(mpp_base);
429
430 soc->variant = (unsigned) match->data & 0xff;
431 soc->controls = armada_38x_mpp_controls;
432 soc->ncontrols = ARRAY_SIZE(armada_38x_mpp_controls);
433 soc->gpioranges = armada_38x_mpp_gpio_ranges;
434 soc->ngpioranges = ARRAY_SIZE(armada_38x_mpp_gpio_ranges);
435 soc->modes = armada_38x_mpp_modes;
436 soc->nmodes = armada_38x_mpp_controls[0].npins;
437
438 pdev->dev.platform_data = soc;
439
440 return mvebu_pinctrl_probe(pdev);
441}
442
443static int armada_38x_pinctrl_remove(struct platform_device *pdev)
444{
445 return mvebu_pinctrl_remove(pdev);
446}
447
448static struct platform_driver armada_38x_pinctrl_driver = {
449 .driver = {
450 .name = "armada-38x-pinctrl",
451 .owner = THIS_MODULE,
452 .of_match_table = of_match_ptr(armada_38x_pinctrl_of_match),
453 },
454 .probe = armada_38x_pinctrl_probe,
455 .remove = armada_38x_pinctrl_remove,
456};
457
458module_platform_driver(armada_38x_pinctrl_driver);
459
460MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
461MODULE_DESCRIPTION("Marvell Armada 38x pinctrl driver");
462MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
index 843a51f9d129..de311129f7a0 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
@@ -33,6 +33,18 @@
33 33
34#include "pinctrl-mvebu.h" 34#include "pinctrl-mvebu.h"
35 35
36static void __iomem *mpp_base;
37
38static int armada_xp_mpp_ctrl_get(unsigned pid, unsigned long *config)
39{
40 return default_mpp_ctrl_get(mpp_base, pid, config);
41}
42
43static int armada_xp_mpp_ctrl_set(unsigned pid, unsigned long config)
44{
45 return default_mpp_ctrl_set(mpp_base, pid, config);
46}
47
36enum armada_xp_variant { 48enum armada_xp_variant {
37 V_MV78230 = BIT(0), 49 V_MV78230 = BIT(0),
38 V_MV78260 = BIT(1), 50 V_MV78260 = BIT(1),
@@ -366,7 +378,7 @@ static struct of_device_id armada_xp_pinctrl_of_match[] = {
366}; 378};
367 379
368static struct mvebu_mpp_ctrl mv78230_mpp_controls[] = { 380static struct mvebu_mpp_ctrl mv78230_mpp_controls[] = {
369 MPP_REG_CTRL(0, 48), 381 MPP_FUNC_CTRL(0, 48, NULL, armada_xp_mpp_ctrl),
370}; 382};
371 383
372static struct pinctrl_gpio_range mv78230_mpp_gpio_ranges[] = { 384static struct pinctrl_gpio_range mv78230_mpp_gpio_ranges[] = {
@@ -375,7 +387,7 @@ static struct pinctrl_gpio_range mv78230_mpp_gpio_ranges[] = {
375}; 387};
376 388
377static struct mvebu_mpp_ctrl mv78260_mpp_controls[] = { 389static struct mvebu_mpp_ctrl mv78260_mpp_controls[] = {
378 MPP_REG_CTRL(0, 66), 390 MPP_FUNC_CTRL(0, 66, NULL, armada_xp_mpp_ctrl),
379}; 391};
380 392
381static struct pinctrl_gpio_range mv78260_mpp_gpio_ranges[] = { 393static struct pinctrl_gpio_range mv78260_mpp_gpio_ranges[] = {
@@ -385,7 +397,7 @@ static struct pinctrl_gpio_range mv78260_mpp_gpio_ranges[] = {
385}; 397};
386 398
387static struct mvebu_mpp_ctrl mv78460_mpp_controls[] = { 399static struct mvebu_mpp_ctrl mv78460_mpp_controls[] = {
388 MPP_REG_CTRL(0, 66), 400 MPP_FUNC_CTRL(0, 66, NULL, armada_xp_mpp_ctrl),
389}; 401};
390 402
391static struct pinctrl_gpio_range mv78460_mpp_gpio_ranges[] = { 403static struct pinctrl_gpio_range mv78460_mpp_gpio_ranges[] = {
@@ -399,10 +411,16 @@ static int armada_xp_pinctrl_probe(struct platform_device *pdev)
399 struct mvebu_pinctrl_soc_info *soc = &armada_xp_pinctrl_info; 411 struct mvebu_pinctrl_soc_info *soc = &armada_xp_pinctrl_info;
400 const struct of_device_id *match = 412 const struct of_device_id *match =
401 of_match_device(armada_xp_pinctrl_of_match, &pdev->dev); 413 of_match_device(armada_xp_pinctrl_of_match, &pdev->dev);
414 struct resource *res;
402 415
403 if (!match) 416 if (!match)
404 return -ENODEV; 417 return -ENODEV;
405 418
419 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
420 mpp_base = devm_ioremap_resource(&pdev->dev, res);
421 if (IS_ERR(mpp_base))
422 return PTR_ERR(mpp_base);
423
406 soc->variant = (unsigned) match->data & 0xff; 424 soc->variant = (unsigned) match->data & 0xff;
407 425
408 switch (soc->variant) { 426 switch (soc->variant) {
diff --git a/drivers/pinctrl/mvebu/pinctrl-dove.c b/drivers/pinctrl/mvebu/pinctrl-dove.c
index 47268393af34..3b022178a566 100644
--- a/drivers/pinctrl/mvebu/pinctrl-dove.c
+++ b/drivers/pinctrl/mvebu/pinctrl-dove.c
@@ -18,107 +18,122 @@
18#include <linux/clk.h> 18#include <linux/clk.h>
19#include <linux/of.h> 19#include <linux/of.h>
20#include <linux/of_device.h> 20#include <linux/of_device.h>
21#include <linux/mfd/syscon.h>
21#include <linux/pinctrl/pinctrl.h> 22#include <linux/pinctrl/pinctrl.h>
23#include <linux/regmap.h>
22 24
23#include "pinctrl-mvebu.h" 25#include "pinctrl-mvebu.h"
24 26
25#define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfde00000) 27/* Internal registers can be configured at any 1 MiB aligned address */
26#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0200) 28#define INT_REGS_MASK ~(SZ_1M - 1)
27#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10) 29#define MPP4_REGS_OFFS 0xd0440
28#define DOVE_AU0_AC97_SEL BIT(16) 30#define PMU_REGS_OFFS 0xd802c
29#define DOVE_PMU_SIGNAL_SELECT_0 (DOVE_SB_REGS_VIRT_BASE + 0xd802C) 31#define GC_REGS_OFFS 0xe802c
30#define DOVE_PMU_SIGNAL_SELECT_1 (DOVE_SB_REGS_VIRT_BASE + 0xd8030) 32
31#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C) 33/* MPP Base registers */
32#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C) 34#define PMU_MPP_GENERAL_CTRL 0x10
33#define DOVE_TWSI_ENABLE_OPTION1 BIT(7) 35#define AU0_AC97_SEL BIT(16)
34#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE + 0xe8030) 36
35#define DOVE_TWSI_ENABLE_OPTION2 BIT(20) 37/* MPP Control 4 register */
36#define DOVE_TWSI_ENABLE_OPTION3 BIT(21) 38#define SPI_GPIO_SEL BIT(5)
37#define DOVE_TWSI_OPTION3_GPIO BIT(22) 39#define UART1_GPIO_SEL BIT(4)
38#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE + 0xe8034) 40#define AU1_GPIO_SEL BIT(3)
39#define DOVE_SSP_ON_AU1 BIT(0) 41#define CAM_GPIO_SEL BIT(2)
40#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe803c) 42#define SD1_GPIO_SEL BIT(1)
41#define DOVE_AU1_SPDIFO_GPIO_EN BIT(1) 43#define SD0_GPIO_SEL BIT(0)
42#define DOVE_NAND_GPIO_EN BIT(0) 44
43#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0400) 45/* PMU Signal Select registers */
44#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40) 46#define PMU_SIGNAL_SELECT_0 0x00
45#define DOVE_SPI_GPIO_SEL BIT(5) 47#define PMU_SIGNAL_SELECT_1 0x04
46#define DOVE_UART1_GPIO_SEL BIT(4) 48
47#define DOVE_AU1_GPIO_SEL BIT(3) 49/* Global Config regmap registers */
48#define DOVE_CAM_GPIO_SEL BIT(2) 50#define GLOBAL_CONFIG_1 0x00
49#define DOVE_SD1_GPIO_SEL BIT(1) 51#define TWSI_ENABLE_OPTION1 BIT(7)
50#define DOVE_SD0_GPIO_SEL BIT(0) 52#define GLOBAL_CONFIG_2 0x04
51 53#define TWSI_ENABLE_OPTION2 BIT(20)
52#define MPPS_PER_REG 8 54#define TWSI_ENABLE_OPTION3 BIT(21)
53#define MPP_BITS 4 55#define TWSI_OPTION3_GPIO BIT(22)
54#define MPP_MASK 0xf 56#define SSP_CTRL_STATUS_1 0x08
57#define SSP_ON_AU1 BIT(0)
58#define MPP_GENERAL_CONFIG 0x10
59#define AU1_SPDIFO_GPIO_EN BIT(1)
60#define NAND_GPIO_EN BIT(0)
55 61
56#define CONFIG_PMU BIT(4) 62#define CONFIG_PMU BIT(4)
57 63
58static int dove_pmu_mpp_ctrl_get(struct mvebu_mpp_ctrl *ctrl, 64static void __iomem *mpp_base;
59 unsigned long *config) 65static void __iomem *mpp4_base;
66static void __iomem *pmu_base;
67static struct regmap *gconfmap;
68
69static int dove_mpp_ctrl_get(unsigned pid, unsigned long *config)
70{
71 return default_mpp_ctrl_get(mpp_base, pid, config);
72}
73
74static int dove_mpp_ctrl_set(unsigned pid, unsigned long config)
60{ 75{
61 unsigned off = (ctrl->pid / MPPS_PER_REG) * MPP_BITS; 76 return default_mpp_ctrl_set(mpp_base, pid, config);
62 unsigned shift = (ctrl->pid % MPPS_PER_REG) * MPP_BITS; 77}
63 unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL); 78
79static int dove_pmu_mpp_ctrl_get(unsigned pid, unsigned long *config)
80{
81 unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
82 unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
83 unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL);
64 unsigned long func; 84 unsigned long func;
65 85
66 if (pmu & (1 << ctrl->pid)) { 86 if ((pmu & BIT(pid)) == 0)
67 func = readl(DOVE_PMU_SIGNAL_SELECT_0 + off); 87 return default_mpp_ctrl_get(mpp_base, pid, config);
68 *config = (func >> shift) & MPP_MASK; 88
69 *config |= CONFIG_PMU; 89 func = readl(pmu_base + PMU_SIGNAL_SELECT_0 + off);
70 } else { 90 *config = (func >> shift) & MVEBU_MPP_MASK;
71 func = readl(DOVE_MPP_VIRT_BASE + off); 91 *config |= CONFIG_PMU;
72 *config = (func >> shift) & MPP_MASK; 92
73 }
74 return 0; 93 return 0;
75} 94}
76 95
77static int dove_pmu_mpp_ctrl_set(struct mvebu_mpp_ctrl *ctrl, 96static int dove_pmu_mpp_ctrl_set(unsigned pid, unsigned long config)
78 unsigned long config)
79{ 97{
80 unsigned off = (ctrl->pid / MPPS_PER_REG) * MPP_BITS; 98 unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
81 unsigned shift = (ctrl->pid % MPPS_PER_REG) * MPP_BITS; 99 unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
82 unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL); 100 unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL);
83 unsigned long func; 101 unsigned long func;
84 102
85 if (config & CONFIG_PMU) { 103 if ((config & CONFIG_PMU) == 0) {
86 writel(pmu | (1 << ctrl->pid), DOVE_PMU_MPP_GENERAL_CTRL); 104 writel(pmu & ~BIT(pid), mpp_base + PMU_MPP_GENERAL_CTRL);
87 func = readl(DOVE_PMU_SIGNAL_SELECT_0 + off); 105 return default_mpp_ctrl_set(mpp_base, pid, config);
88 func &= ~(MPP_MASK << shift);
89 func |= (config & MPP_MASK) << shift;
90 writel(func, DOVE_PMU_SIGNAL_SELECT_0 + off);
91 } else {
92 writel(pmu & ~(1 << ctrl->pid), DOVE_PMU_MPP_GENERAL_CTRL);
93 func = readl(DOVE_MPP_VIRT_BASE + off);
94 func &= ~(MPP_MASK << shift);
95 func |= (config & MPP_MASK) << shift;
96 writel(func, DOVE_MPP_VIRT_BASE + off);
97 } 106 }
107
108 writel(pmu | BIT(pid), mpp_base + PMU_MPP_GENERAL_CTRL);
109 func = readl(pmu_base + PMU_SIGNAL_SELECT_0 + off);
110 func &= ~(MVEBU_MPP_MASK << shift);
111 func |= (config & MVEBU_MPP_MASK) << shift;
112 writel(func, pmu_base + PMU_SIGNAL_SELECT_0 + off);
113
98 return 0; 114 return 0;
99} 115}
100 116
101static int dove_mpp4_ctrl_get(struct mvebu_mpp_ctrl *ctrl, 117static int dove_mpp4_ctrl_get(unsigned pid, unsigned long *config)
102 unsigned long *config)
103{ 118{
104 unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); 119 unsigned long mpp4 = readl(mpp4_base);
105 unsigned long mask; 120 unsigned long mask;
106 121
107 switch (ctrl->pid) { 122 switch (pid) {
108 case 24: /* mpp_camera */ 123 case 24: /* mpp_camera */
109 mask = DOVE_CAM_GPIO_SEL; 124 mask = CAM_GPIO_SEL;
110 break; 125 break;
111 case 40: /* mpp_sdio0 */ 126 case 40: /* mpp_sdio0 */
112 mask = DOVE_SD0_GPIO_SEL; 127 mask = SD0_GPIO_SEL;
113 break; 128 break;
114 case 46: /* mpp_sdio1 */ 129 case 46: /* mpp_sdio1 */
115 mask = DOVE_SD1_GPIO_SEL; 130 mask = SD1_GPIO_SEL;
116 break; 131 break;
117 case 58: /* mpp_spi0 */ 132 case 58: /* mpp_spi0 */
118 mask = DOVE_SPI_GPIO_SEL; 133 mask = SPI_GPIO_SEL;
119 break; 134 break;
120 case 62: /* mpp_uart1 */ 135 case 62: /* mpp_uart1 */
121 mask = DOVE_UART1_GPIO_SEL; 136 mask = UART1_GPIO_SEL;
122 break; 137 break;
123 default: 138 default:
124 return -EINVAL; 139 return -EINVAL;
@@ -129,27 +144,26 @@ static int dove_mpp4_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
129 return 0; 144 return 0;
130} 145}
131 146
132static int dove_mpp4_ctrl_set(struct mvebu_mpp_ctrl *ctrl, 147static int dove_mpp4_ctrl_set(unsigned pid, unsigned long config)
133 unsigned long config)
134{ 148{
135 unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); 149 unsigned long mpp4 = readl(mpp4_base);
136 unsigned long mask; 150 unsigned long mask;
137 151
138 switch (ctrl->pid) { 152 switch (pid) {
139 case 24: /* mpp_camera */ 153 case 24: /* mpp_camera */
140 mask = DOVE_CAM_GPIO_SEL; 154 mask = CAM_GPIO_SEL;
141 break; 155 break;
142 case 40: /* mpp_sdio0 */ 156 case 40: /* mpp_sdio0 */
143 mask = DOVE_SD0_GPIO_SEL; 157 mask = SD0_GPIO_SEL;
144 break; 158 break;
145 case 46: /* mpp_sdio1 */ 159 case 46: /* mpp_sdio1 */
146 mask = DOVE_SD1_GPIO_SEL; 160 mask = SD1_GPIO_SEL;
147 break; 161 break;
148 case 58: /* mpp_spi0 */ 162 case 58: /* mpp_spi0 */
149 mask = DOVE_SPI_GPIO_SEL; 163 mask = SPI_GPIO_SEL;
150 break; 164 break;
151 case 62: /* mpp_uart1 */ 165 case 62: /* mpp_uart1 */
152 mask = DOVE_UART1_GPIO_SEL; 166 mask = UART1_GPIO_SEL;
153 break; 167 break;
154 default: 168 default:
155 return -EINVAL; 169 return -EINVAL;
@@ -159,74 +173,69 @@ static int dove_mpp4_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
159 if (config) 173 if (config)
160 mpp4 |= mask; 174 mpp4 |= mask;
161 175
162 writel(mpp4, DOVE_MPP_CTRL4_VIRT_BASE); 176 writel(mpp4, mpp4_base);
163 177
164 return 0; 178 return 0;
165} 179}
166 180
167static int dove_nand_ctrl_get(struct mvebu_mpp_ctrl *ctrl, 181static int dove_nand_ctrl_get(unsigned pid, unsigned long *config)
168 unsigned long *config)
169{ 182{
170 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); 183 unsigned int gmpp;
171 184
172 *config = ((gmpp & DOVE_NAND_GPIO_EN) != 0); 185 regmap_read(gconfmap, MPP_GENERAL_CONFIG, &gmpp);
186 *config = ((gmpp & NAND_GPIO_EN) != 0);
173 187
174 return 0; 188 return 0;
175} 189}
176 190
177static int dove_nand_ctrl_set(struct mvebu_mpp_ctrl *ctrl, 191static int dove_nand_ctrl_set(unsigned pid, unsigned long config)
178 unsigned long config)
179{ 192{
180 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); 193 regmap_update_bits(gconfmap, MPP_GENERAL_CONFIG,
181 194 NAND_GPIO_EN,
182 gmpp &= ~DOVE_NAND_GPIO_EN; 195 (config) ? NAND_GPIO_EN : 0);
183 if (config)
184 gmpp |= DOVE_NAND_GPIO_EN;
185
186 writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE);
187
188 return 0; 196 return 0;
189} 197}
190 198
191static int dove_audio0_ctrl_get(struct mvebu_mpp_ctrl *ctrl, 199static int dove_audio0_ctrl_get(unsigned pid, unsigned long *config)
192 unsigned long *config)
193{ 200{
194 unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL); 201 unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL);
195 202
196 *config = ((pmu & DOVE_AU0_AC97_SEL) != 0); 203 *config = ((pmu & AU0_AC97_SEL) != 0);
197 204
198 return 0; 205 return 0;
199} 206}
200 207
201static int dove_audio0_ctrl_set(struct mvebu_mpp_ctrl *ctrl, 208static int dove_audio0_ctrl_set(unsigned pid, unsigned long config)
202 unsigned long config)
203{ 209{
204 unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL); 210 unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL);
205 211
206 pmu &= ~DOVE_AU0_AC97_SEL; 212 pmu &= ~AU0_AC97_SEL;
207 if (config) 213 if (config)
208 pmu |= DOVE_AU0_AC97_SEL; 214 pmu |= AU0_AC97_SEL;
209 writel(pmu, DOVE_PMU_MPP_GENERAL_CTRL); 215 writel(pmu, mpp_base + PMU_MPP_GENERAL_CTRL);
210 216
211 return 0; 217 return 0;
212} 218}
213 219
214static int dove_audio1_ctrl_get(struct mvebu_mpp_ctrl *ctrl, 220static int dove_audio1_ctrl_get(unsigned pid, unsigned long *config)
215 unsigned long *config)
216{ 221{
217 unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); 222 unsigned int mpp4 = readl(mpp4_base);
218 unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1); 223 unsigned int sspc1;
219 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); 224 unsigned int gmpp;
220 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); 225 unsigned int gcfg2;
226
227 regmap_read(gconfmap, SSP_CTRL_STATUS_1, &sspc1);
228 regmap_read(gconfmap, MPP_GENERAL_CONFIG, &gmpp);
229 regmap_read(gconfmap, GLOBAL_CONFIG_2, &gcfg2);
221 230
222 *config = 0; 231 *config = 0;
223 if (mpp4 & DOVE_AU1_GPIO_SEL) 232 if (mpp4 & AU1_GPIO_SEL)
224 *config |= BIT(3); 233 *config |= BIT(3);
225 if (sspc1 & DOVE_SSP_ON_AU1) 234 if (sspc1 & SSP_ON_AU1)
226 *config |= BIT(2); 235 *config |= BIT(2);
227 if (gmpp & DOVE_AU1_SPDIFO_GPIO_EN) 236 if (gmpp & AU1_SPDIFO_GPIO_EN)
228 *config |= BIT(1); 237 *config |= BIT(1);
229 if (gcfg2 & DOVE_TWSI_OPTION3_GPIO) 238 if (gcfg2 & TWSI_OPTION3_GPIO)
230 *config |= BIT(0); 239 *config |= BIT(0);
231 240
232 /* SSP/TWSI only if I2S1 not set*/ 241 /* SSP/TWSI only if I2S1 not set*/
@@ -238,35 +247,24 @@ static int dove_audio1_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
238 return 0; 247 return 0;
239} 248}
240 249
241static int dove_audio1_ctrl_set(struct mvebu_mpp_ctrl *ctrl, 250static int dove_audio1_ctrl_set(unsigned pid, unsigned long config)
242 unsigned long config)
243{ 251{
244 unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); 252 unsigned int mpp4 = readl(mpp4_base);
245 unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1);
246 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
247 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
248 253
249 /* 254 mpp4 &= ~AU1_GPIO_SEL;
250 * clear all audio1 related bits before configure
251 */
252 gcfg2 &= ~DOVE_TWSI_OPTION3_GPIO;
253 gmpp &= ~DOVE_AU1_SPDIFO_GPIO_EN;
254 sspc1 &= ~DOVE_SSP_ON_AU1;
255 mpp4 &= ~DOVE_AU1_GPIO_SEL;
256
257 if (config & BIT(0))
258 gcfg2 |= DOVE_TWSI_OPTION3_GPIO;
259 if (config & BIT(1))
260 gmpp |= DOVE_AU1_SPDIFO_GPIO_EN;
261 if (config & BIT(2))
262 sspc1 |= DOVE_SSP_ON_AU1;
263 if (config & BIT(3)) 255 if (config & BIT(3))
264 mpp4 |= DOVE_AU1_GPIO_SEL; 256 mpp4 |= AU1_GPIO_SEL;
265 257 writel(mpp4, mpp4_base);
266 writel(mpp4, DOVE_MPP_CTRL4_VIRT_BASE); 258
267 writel(sspc1, DOVE_SSP_CTRL_STATUS_1); 259 regmap_update_bits(gconfmap, SSP_CTRL_STATUS_1,
268 writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE); 260 SSP_ON_AU1,
269 writel(gcfg2, DOVE_GLOBAL_CONFIG_2); 261 (config & BIT(2)) ? SSP_ON_AU1 : 0);
262 regmap_update_bits(gconfmap, MPP_GENERAL_CONFIG,
263 AU1_SPDIFO_GPIO_EN,
264 (config & BIT(1)) ? AU1_SPDIFO_GPIO_EN : 0);
265 regmap_update_bits(gconfmap, GLOBAL_CONFIG_2,
266 TWSI_OPTION3_GPIO,
267 (config & BIT(0)) ? TWSI_OPTION3_GPIO : 0);
270 268
271 return 0; 269 return 0;
272} 270}
@@ -276,11 +274,11 @@ static int dove_audio1_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
276 * break other functions. If you require all mpps as gpio 274 * break other functions. If you require all mpps as gpio
277 * enforce gpio setting by pinctrl mapping. 275 * enforce gpio setting by pinctrl mapping.
278 */ 276 */
279static int dove_audio1_ctrl_gpio_req(struct mvebu_mpp_ctrl *ctrl, u8 pid) 277static int dove_audio1_ctrl_gpio_req(unsigned pid)
280{ 278{
281 unsigned long config; 279 unsigned long config;
282 280
283 dove_audio1_ctrl_get(ctrl, &config); 281 dove_audio1_ctrl_get(pid, &config);
284 282
285 switch (config) { 283 switch (config) {
286 case 0x02: /* i2s1 : gpio[56:57] */ 284 case 0x02: /* i2s1 : gpio[56:57] */
@@ -303,76 +301,62 @@ static int dove_audio1_ctrl_gpio_req(struct mvebu_mpp_ctrl *ctrl, u8 pid)
303} 301}
304 302
305/* mpp[52:57] has gpio pins capable of in and out */ 303/* mpp[52:57] has gpio pins capable of in and out */
306static int dove_audio1_ctrl_gpio_dir(struct mvebu_mpp_ctrl *ctrl, u8 pid, 304static int dove_audio1_ctrl_gpio_dir(unsigned pid, bool input)
307 bool input)
308{ 305{
309 if (pid < 52 || pid > 57) 306 if (pid < 52 || pid > 57)
310 return -ENOTSUPP; 307 return -ENOTSUPP;
311 return 0; 308 return 0;
312} 309}
313 310
314static int dove_twsi_ctrl_get(struct mvebu_mpp_ctrl *ctrl, 311static int dove_twsi_ctrl_get(unsigned pid, unsigned long *config)
315 unsigned long *config)
316{ 312{
317 unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1); 313 unsigned int gcfg1;
318 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); 314 unsigned int gcfg2;
315
316 regmap_read(gconfmap, GLOBAL_CONFIG_1, &gcfg1);
317 regmap_read(gconfmap, GLOBAL_CONFIG_2, &gcfg2);
319 318
320 *config = 0; 319 *config = 0;
321 if (gcfg1 & DOVE_TWSI_ENABLE_OPTION1) 320 if (gcfg1 & TWSI_ENABLE_OPTION1)
322 *config = 1; 321 *config = 1;
323 else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION2) 322 else if (gcfg2 & TWSI_ENABLE_OPTION2)
324 *config = 2; 323 *config = 2;
325 else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION3) 324 else if (gcfg2 & TWSI_ENABLE_OPTION3)
326 *config = 3; 325 *config = 3;
327 326
328 return 0; 327 return 0;
329} 328}
330 329
331static int dove_twsi_ctrl_set(struct mvebu_mpp_ctrl *ctrl, 330static int dove_twsi_ctrl_set(unsigned pid, unsigned long config)
332 unsigned long config)
333{ 331{
334 unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1); 332 unsigned int gcfg1 = 0;
335 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); 333 unsigned int gcfg2 = 0;
336
337 gcfg1 &= ~DOVE_TWSI_ENABLE_OPTION1;
338 gcfg2 &= ~(DOVE_TWSI_ENABLE_OPTION2 | DOVE_TWSI_ENABLE_OPTION3);
339 334
340 switch (config) { 335 switch (config) {
341 case 1: 336 case 1:
342 gcfg1 |= DOVE_TWSI_ENABLE_OPTION1; 337 gcfg1 = TWSI_ENABLE_OPTION1;
343 break; 338 break;
344 case 2: 339 case 2:
345 gcfg2 |= DOVE_TWSI_ENABLE_OPTION2; 340 gcfg2 = TWSI_ENABLE_OPTION2;
346 break; 341 break;
347 case 3: 342 case 3:
348 gcfg2 |= DOVE_TWSI_ENABLE_OPTION3; 343 gcfg2 = TWSI_ENABLE_OPTION3;
349 break; 344 break;
350 } 345 }
351 346
352 writel(gcfg1, DOVE_GLOBAL_CONFIG_1); 347 regmap_update_bits(gconfmap, GLOBAL_CONFIG_1,
353 writel(gcfg2, DOVE_GLOBAL_CONFIG_2); 348 TWSI_ENABLE_OPTION1,
349 gcfg1);
350 regmap_update_bits(gconfmap, GLOBAL_CONFIG_2,
351 TWSI_ENABLE_OPTION2 | TWSI_ENABLE_OPTION3,
352 gcfg2);
354 353
355 return 0; 354 return 0;
356} 355}
357 356
358static struct mvebu_mpp_ctrl dove_mpp_controls[] = { 357static struct mvebu_mpp_ctrl dove_mpp_controls[] = {
359 MPP_FUNC_CTRL(0, 0, "mpp0", dove_pmu_mpp_ctrl), 358 MPP_FUNC_CTRL(0, 15, NULL, dove_pmu_mpp_ctrl),
360 MPP_FUNC_CTRL(1, 1, "mpp1", dove_pmu_mpp_ctrl), 359 MPP_FUNC_CTRL(16, 23, NULL, dove_mpp_ctrl),
361 MPP_FUNC_CTRL(2, 2, "mpp2", dove_pmu_mpp_ctrl),
362 MPP_FUNC_CTRL(3, 3, "mpp3", dove_pmu_mpp_ctrl),
363 MPP_FUNC_CTRL(4, 4, "mpp4", dove_pmu_mpp_ctrl),
364 MPP_FUNC_CTRL(5, 5, "mpp5", dove_pmu_mpp_ctrl),
365 MPP_FUNC_CTRL(6, 6, "mpp6", dove_pmu_mpp_ctrl),
366 MPP_FUNC_CTRL(7, 7, "mpp7", dove_pmu_mpp_ctrl),
367 MPP_FUNC_CTRL(8, 8, "mpp8", dove_pmu_mpp_ctrl),
368 MPP_FUNC_CTRL(9, 9, "mpp9", dove_pmu_mpp_ctrl),
369 MPP_FUNC_CTRL(10, 10, "mpp10", dove_pmu_mpp_ctrl),
370 MPP_FUNC_CTRL(11, 11, "mpp11", dove_pmu_mpp_ctrl),
371 MPP_FUNC_CTRL(12, 12, "mpp12", dove_pmu_mpp_ctrl),
372 MPP_FUNC_CTRL(13, 13, "mpp13", dove_pmu_mpp_ctrl),
373 MPP_FUNC_CTRL(14, 14, "mpp14", dove_pmu_mpp_ctrl),
374 MPP_FUNC_CTRL(15, 15, "mpp15", dove_pmu_mpp_ctrl),
375 MPP_REG_CTRL(16, 23),
376 MPP_FUNC_CTRL(24, 39, "mpp_camera", dove_mpp4_ctrl), 360 MPP_FUNC_CTRL(24, 39, "mpp_camera", dove_mpp4_ctrl),
377 MPP_FUNC_CTRL(40, 45, "mpp_sdio0", dove_mpp4_ctrl), 361 MPP_FUNC_CTRL(40, 45, "mpp_sdio0", dove_mpp4_ctrl),
378 MPP_FUNC_CTRL(46, 51, "mpp_sdio1", dove_mpp4_ctrl), 362 MPP_FUNC_CTRL(46, 51, "mpp_sdio1", dove_mpp4_ctrl),
@@ -772,8 +756,17 @@ static struct of_device_id dove_pinctrl_of_match[] = {
772 { } 756 { }
773}; 757};
774 758
759static struct regmap_config gc_regmap_config = {
760 .reg_bits = 32,
761 .val_bits = 32,
762 .reg_stride = 4,
763 .max_register = 5,
764};
765
775static int dove_pinctrl_probe(struct platform_device *pdev) 766static int dove_pinctrl_probe(struct platform_device *pdev)
776{ 767{
768 struct resource *res, *mpp_res;
769 struct resource fb_res;
777 const struct of_device_id *match = 770 const struct of_device_id *match =
778 of_match_device(dove_pinctrl_of_match, &pdev->dev); 771 of_match_device(dove_pinctrl_of_match, &pdev->dev);
779 pdev->dev.platform_data = (void *)match->data; 772 pdev->dev.platform_data = (void *)match->data;
@@ -789,6 +782,59 @@ static int dove_pinctrl_probe(struct platform_device *pdev)
789 } 782 }
790 clk_prepare_enable(clk); 783 clk_prepare_enable(clk);
791 784
785 mpp_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
786 mpp_base = devm_ioremap_resource(&pdev->dev, mpp_res);
787 if (IS_ERR(mpp_base))
788 return PTR_ERR(mpp_base);
789
790 /* prepare fallback resource */
791 memcpy(&fb_res, mpp_res, sizeof(struct resource));
792 fb_res.start = 0;
793
794 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
795 if (!res) {
796 dev_warn(&pdev->dev, "falling back to hardcoded MPP4 resource\n");
797 adjust_resource(&fb_res,
798 (mpp_res->start & INT_REGS_MASK) + MPP4_REGS_OFFS, 0x4);
799 res = &fb_res;
800 }
801
802 mpp4_base = devm_ioremap_resource(&pdev->dev, res);
803 if (IS_ERR(mpp4_base))
804 return PTR_ERR(mpp4_base);
805
806 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
807 if (!res) {
808 dev_warn(&pdev->dev, "falling back to hardcoded PMU resource\n");
809 adjust_resource(&fb_res,
810 (mpp_res->start & INT_REGS_MASK) + PMU_REGS_OFFS, 0x8);
811 res = &fb_res;
812 }
813
814 pmu_base = devm_ioremap_resource(&pdev->dev, res);
815 if (IS_ERR(pmu_base))
816 return PTR_ERR(pmu_base);
817
818 gconfmap = syscon_regmap_lookup_by_compatible("marvell,dove-global-config");
819 if (IS_ERR(gconfmap)) {
820 void __iomem *gc_base;
821
822 dev_warn(&pdev->dev, "falling back to hardcoded global registers\n");
823 adjust_resource(&fb_res,
824 (mpp_res->start & INT_REGS_MASK) + GC_REGS_OFFS, 0x14);
825 gc_base = devm_ioremap_resource(&pdev->dev, &fb_res);
826 if (IS_ERR(gc_base))
827 return PTR_ERR(gc_base);
828 gconfmap = devm_regmap_init_mmio(&pdev->dev,
829 gc_base, &gc_regmap_config);
830 if (IS_ERR(gconfmap))
831 return PTR_ERR(gconfmap);
832 }
833
834 /* Warn on any missing DT resource */
835 if (fb_res.start)
836 dev_warn(&pdev->dev, FW_BUG "Missing pinctrl regs in DTB. Please update your firmware.\n");
837
792 return mvebu_pinctrl_probe(pdev); 838 return mvebu_pinctrl_probe(pdev);
793} 839}
794 840
diff --git a/drivers/pinctrl/mvebu/pinctrl-kirkwood.c b/drivers/pinctrl/mvebu/pinctrl-kirkwood.c
index 6b504b5935a5..0d0211a1a0b0 100644
--- a/drivers/pinctrl/mvebu/pinctrl-kirkwood.c
+++ b/drivers/pinctrl/mvebu/pinctrl-kirkwood.c
@@ -21,6 +21,18 @@
21 21
22#include "pinctrl-mvebu.h" 22#include "pinctrl-mvebu.h"
23 23
24static void __iomem *mpp_base;
25
26static int kirkwood_mpp_ctrl_get(unsigned pid, unsigned long *config)
27{
28 return default_mpp_ctrl_get(mpp_base, pid, config);
29}
30
31static int kirkwood_mpp_ctrl_set(unsigned pid, unsigned long config)
32{
33 return default_mpp_ctrl_set(mpp_base, pid, config);
34}
35
24#define V(f6180, f6190, f6192, f6281, f6282, dx4122) \ 36#define V(f6180, f6190, f6192, f6281, f6282, dx4122) \
25 ((f6180 << 0) | (f6190 << 1) | (f6192 << 2) | \ 37 ((f6180 << 0) | (f6190 << 1) | (f6192 << 2) | \
26 (f6281 << 3) | (f6282 << 4) | (dx4122 << 5)) 38 (f6281 << 3) | (f6282 << 4) | (dx4122 << 5))
@@ -359,7 +371,7 @@ static struct mvebu_mpp_mode mv88f6xxx_mpp_modes[] = {
359}; 371};
360 372
361static struct mvebu_mpp_ctrl mv88f6180_mpp_controls[] = { 373static struct mvebu_mpp_ctrl mv88f6180_mpp_controls[] = {
362 MPP_REG_CTRL(0, 29), 374 MPP_FUNC_CTRL(0, 29, NULL, kirkwood_mpp_ctrl),
363}; 375};
364 376
365static struct pinctrl_gpio_range mv88f6180_gpio_ranges[] = { 377static struct pinctrl_gpio_range mv88f6180_gpio_ranges[] = {
@@ -367,7 +379,7 @@ static struct pinctrl_gpio_range mv88f6180_gpio_ranges[] = {
367}; 379};
368 380
369static struct mvebu_mpp_ctrl mv88f619x_mpp_controls[] = { 381static struct mvebu_mpp_ctrl mv88f619x_mpp_controls[] = {
370 MPP_REG_CTRL(0, 35), 382 MPP_FUNC_CTRL(0, 35, NULL, kirkwood_mpp_ctrl),
371}; 383};
372 384
373static struct pinctrl_gpio_range mv88f619x_gpio_ranges[] = { 385static struct pinctrl_gpio_range mv88f619x_gpio_ranges[] = {
@@ -376,7 +388,7 @@ static struct pinctrl_gpio_range mv88f619x_gpio_ranges[] = {
376}; 388};
377 389
378static struct mvebu_mpp_ctrl mv88f628x_mpp_controls[] = { 390static struct mvebu_mpp_ctrl mv88f628x_mpp_controls[] = {
379 MPP_REG_CTRL(0, 49), 391 MPP_FUNC_CTRL(0, 49, NULL, kirkwood_mpp_ctrl),
380}; 392};
381 393
382static struct pinctrl_gpio_range mv88f628x_gpio_ranges[] = { 394static struct pinctrl_gpio_range mv88f628x_gpio_ranges[] = {
@@ -456,9 +468,16 @@ static struct of_device_id kirkwood_pinctrl_of_match[] = {
456 468
457static int kirkwood_pinctrl_probe(struct platform_device *pdev) 469static int kirkwood_pinctrl_probe(struct platform_device *pdev)
458{ 470{
471 struct resource *res;
459 const struct of_device_id *match = 472 const struct of_device_id *match =
460 of_match_device(kirkwood_pinctrl_of_match, &pdev->dev); 473 of_match_device(kirkwood_pinctrl_of_match, &pdev->dev);
461 pdev->dev.platform_data = (void *)match->data; 474 pdev->dev.platform_data = (void *)match->data;
475
476 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
477 mpp_base = devm_ioremap_resource(&pdev->dev, res);
478 if (IS_ERR(mpp_base))
479 return PTR_ERR(mpp_base);
480
462 return mvebu_pinctrl_probe(pdev); 481 return mvebu_pinctrl_probe(pdev);
463} 482}
464 483
diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.c b/drivers/pinctrl/mvebu/pinctrl-mvebu.c
index 0fd1ad31fbf9..9908374f8f92 100644
--- a/drivers/pinctrl/mvebu/pinctrl-mvebu.c
+++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.c
@@ -50,7 +50,6 @@ struct mvebu_pinctrl {
50 struct device *dev; 50 struct device *dev;
51 struct pinctrl_dev *pctldev; 51 struct pinctrl_dev *pctldev;
52 struct pinctrl_desc desc; 52 struct pinctrl_desc desc;
53 void __iomem *base;
54 struct mvebu_pinctrl_group *groups; 53 struct mvebu_pinctrl_group *groups;
55 unsigned num_groups; 54 unsigned num_groups;
56 struct mvebu_pinctrl_function *functions; 55 struct mvebu_pinctrl_function *functions;
@@ -138,43 +137,6 @@ static struct mvebu_pinctrl_function *mvebu_pinctrl_find_function_by_name(
138 return NULL; 137 return NULL;
139} 138}
140 139
141/*
142 * Common mpp pin configuration registers on MVEBU are
143 * registers of eight 4-bit values for each mpp setting.
144 * Register offset and bit mask are calculated accordingly below.
145 */
146static int mvebu_common_mpp_get(struct mvebu_pinctrl *pctl,
147 struct mvebu_pinctrl_group *grp,
148 unsigned long *config)
149{
150 unsigned pin = grp->gid;
151 unsigned off = (pin / MPPS_PER_REG) * MPP_BITS;
152 unsigned shift = (pin % MPPS_PER_REG) * MPP_BITS;
153
154 *config = readl(pctl->base + off);
155 *config >>= shift;
156 *config &= MPP_MASK;
157
158 return 0;
159}
160
161static int mvebu_common_mpp_set(struct mvebu_pinctrl *pctl,
162 struct mvebu_pinctrl_group *grp,
163 unsigned long config)
164{
165 unsigned pin = grp->gid;
166 unsigned off = (pin / MPPS_PER_REG) * MPP_BITS;
167 unsigned shift = (pin % MPPS_PER_REG) * MPP_BITS;
168 unsigned long reg;
169
170 reg = readl(pctl->base + off);
171 reg &= ~(MPP_MASK << shift);
172 reg |= (config << shift);
173 writel(reg, pctl->base + off);
174
175 return 0;
176}
177
178static int mvebu_pinconf_group_get(struct pinctrl_dev *pctldev, 140static int mvebu_pinconf_group_get(struct pinctrl_dev *pctldev,
179 unsigned gid, unsigned long *config) 141 unsigned gid, unsigned long *config)
180{ 142{
@@ -184,10 +146,7 @@ static int mvebu_pinconf_group_get(struct pinctrl_dev *pctldev,
184 if (!grp->ctrl) 146 if (!grp->ctrl)
185 return -EINVAL; 147 return -EINVAL;
186 148
187 if (grp->ctrl->mpp_get) 149 return grp->ctrl->mpp_get(grp->pins[0], config);
188 return grp->ctrl->mpp_get(grp->ctrl, config);
189
190 return mvebu_common_mpp_get(pctl, grp, config);
191} 150}
192 151
193static int mvebu_pinconf_group_set(struct pinctrl_dev *pctldev, 152static int mvebu_pinconf_group_set(struct pinctrl_dev *pctldev,
@@ -202,11 +161,7 @@ static int mvebu_pinconf_group_set(struct pinctrl_dev *pctldev,
202 return -EINVAL; 161 return -EINVAL;
203 162
204 for (i = 0; i < num_configs; i++) { 163 for (i = 0; i < num_configs; i++) {
205 if (grp->ctrl->mpp_set) 164 ret = grp->ctrl->mpp_set(grp->pins[0], configs[i]);
206 ret = grp->ctrl->mpp_set(grp->ctrl, configs[i]);
207 else
208 ret = mvebu_common_mpp_set(pctl, grp, configs[i]);
209
210 if (ret) 165 if (ret)
211 return ret; 166 return ret;
212 } /* for each config */ 167 } /* for each config */
@@ -347,7 +302,7 @@ static int mvebu_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
347 return -EINVAL; 302 return -EINVAL;
348 303
349 if (grp->ctrl->mpp_gpio_req) 304 if (grp->ctrl->mpp_gpio_req)
350 return grp->ctrl->mpp_gpio_req(grp->ctrl, offset); 305 return grp->ctrl->mpp_gpio_req(offset);
351 306
352 setting = mvebu_pinctrl_find_gpio_setting(pctl, grp); 307 setting = mvebu_pinctrl_find_gpio_setting(pctl, grp);
353 if (!setting) 308 if (!setting)
@@ -370,7 +325,7 @@ static int mvebu_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
370 return -EINVAL; 325 return -EINVAL;
371 326
372 if (grp->ctrl->mpp_gpio_dir) 327 if (grp->ctrl->mpp_gpio_dir)
373 return grp->ctrl->mpp_gpio_dir(grp->ctrl, offset, input); 328 return grp->ctrl->mpp_gpio_dir(offset, input);
374 329
375 setting = mvebu_pinctrl_find_gpio_setting(pctl, grp); 330 setting = mvebu_pinctrl_find_gpio_setting(pctl, grp);
376 if (!setting) 331 if (!setting)
@@ -593,11 +548,12 @@ static int mvebu_pinctrl_build_functions(struct platform_device *pdev,
593int mvebu_pinctrl_probe(struct platform_device *pdev) 548int mvebu_pinctrl_probe(struct platform_device *pdev)
594{ 549{
595 struct mvebu_pinctrl_soc_info *soc = dev_get_platdata(&pdev->dev); 550 struct mvebu_pinctrl_soc_info *soc = dev_get_platdata(&pdev->dev);
596 struct resource *res;
597 struct mvebu_pinctrl *pctl; 551 struct mvebu_pinctrl *pctl;
598 void __iomem *base;
599 struct pinctrl_pin_desc *pdesc; 552 struct pinctrl_pin_desc *pdesc;
600 unsigned gid, n, k; 553 unsigned gid, n, k;
554 unsigned size, noname = 0;
555 char *noname_buf;
556 void *p;
601 int ret; 557 int ret;
602 558
603 if (!soc || !soc->controls || !soc->modes) { 559 if (!soc || !soc->controls || !soc->modes) {
@@ -605,11 +561,6 @@ int mvebu_pinctrl_probe(struct platform_device *pdev)
605 return -EINVAL; 561 return -EINVAL;
606 } 562 }
607 563
608 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
609 base = devm_ioremap_resource(&pdev->dev, res);
610 if (IS_ERR(base))
611 return PTR_ERR(base);
612
613 pctl = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pinctrl), 564 pctl = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pinctrl),
614 GFP_KERNEL); 565 GFP_KERNEL);
615 if (!pctl) { 566 if (!pctl) {
@@ -623,7 +574,6 @@ int mvebu_pinctrl_probe(struct platform_device *pdev)
623 pctl->desc.pmxops = &mvebu_pinmux_ops; 574 pctl->desc.pmxops = &mvebu_pinmux_ops;
624 pctl->desc.confops = &mvebu_pinconf_ops; 575 pctl->desc.confops = &mvebu_pinconf_ops;
625 pctl->variant = soc->variant; 576 pctl->variant = soc->variant;
626 pctl->base = base;
627 pctl->dev = &pdev->dev; 577 pctl->dev = &pdev->dev;
628 platform_set_drvdata(pdev, pctl); 578 platform_set_drvdata(pdev, pctl);
629 579
@@ -633,33 +583,23 @@ int mvebu_pinctrl_probe(struct platform_device *pdev)
633 pctl->desc.npins = 0; 583 pctl->desc.npins = 0;
634 for (n = 0; n < soc->ncontrols; n++) { 584 for (n = 0; n < soc->ncontrols; n++) {
635 struct mvebu_mpp_ctrl *ctrl = &soc->controls[n]; 585 struct mvebu_mpp_ctrl *ctrl = &soc->controls[n];
636 char *names;
637 586
638 pctl->desc.npins += ctrl->npins; 587 pctl->desc.npins += ctrl->npins;
639 /* initial control pins */ 588 /* initialize control's pins[] array */
640 for (k = 0; k < ctrl->npins; k++) 589 for (k = 0; k < ctrl->npins; k++)
641 ctrl->pins[k] = ctrl->pid + k; 590 ctrl->pins[k] = ctrl->pid + k;
642 591
643 /* special soc specific control */ 592 /*
644 if (ctrl->mpp_get || ctrl->mpp_set) { 593 * We allow to pass controls with NULL name that we treat
645 if (!ctrl->name || !ctrl->mpp_get || !ctrl->mpp_set) { 594 * as a range of one-pin groups with generic mvebu register
646 dev_err(&pdev->dev, "wrong soc control info\n"); 595 * controls.
647 return -EINVAL; 596 */
648 } 597 if (!ctrl->name) {
598 pctl->num_groups += ctrl->npins;
599 noname += ctrl->npins;
600 } else {
649 pctl->num_groups += 1; 601 pctl->num_groups += 1;
650 continue;
651 } 602 }
652
653 /* generic mvebu register control */
654 names = devm_kzalloc(&pdev->dev, ctrl->npins * 8, GFP_KERNEL);
655 if (!names) {
656 dev_err(&pdev->dev, "failed to alloc mpp names\n");
657 return -ENOMEM;
658 }
659 for (k = 0; k < ctrl->npins; k++)
660 sprintf(names + 8*k, "mpp%d", ctrl->pid+k);
661 ctrl->name = names;
662 pctl->num_groups += ctrl->npins;
663 } 603 }
664 604
665 pdesc = devm_kzalloc(&pdev->dev, pctl->desc.npins * 605 pdesc = devm_kzalloc(&pdev->dev, pctl->desc.npins *
@@ -673,12 +613,17 @@ int mvebu_pinctrl_probe(struct platform_device *pdev)
673 pdesc[n].number = n; 613 pdesc[n].number = n;
674 pctl->desc.pins = pdesc; 614 pctl->desc.pins = pdesc;
675 615
676 pctl->groups = devm_kzalloc(&pdev->dev, pctl->num_groups * 616 /*
677 sizeof(struct mvebu_pinctrl_group), GFP_KERNEL); 617 * allocate groups and name buffers for unnamed groups.
678 if (!pctl->groups) { 618 */
679 dev_err(&pdev->dev, "failed to alloc pinctrl groups\n"); 619 size = pctl->num_groups * sizeof(*pctl->groups) + noname * 8;
620 p = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
621 if (!p) {
622 dev_err(&pdev->dev, "failed to alloc group data\n");
680 return -ENOMEM; 623 return -ENOMEM;
681 } 624 }
625 pctl->groups = p;
626 noname_buf = p + pctl->num_groups * sizeof(*pctl->groups);
682 627
683 /* assign mpp controls to groups */ 628 /* assign mpp controls to groups */
684 gid = 0; 629 gid = 0;
@@ -690,17 +635,26 @@ int mvebu_pinctrl_probe(struct platform_device *pdev)
690 pctl->groups[gid].pins = ctrl->pins; 635 pctl->groups[gid].pins = ctrl->pins;
691 pctl->groups[gid].npins = ctrl->npins; 636 pctl->groups[gid].npins = ctrl->npins;
692 637
693 /* generic mvebu register control maps to a number of groups */ 638 /*
694 if (!ctrl->mpp_get && !ctrl->mpp_set) { 639 * We treat unnamed controls as a range of one-pin groups
640 * with generic mvebu register controls. Use one group for
641 * each in this range and assign a default group name.
642 */
643 if (!ctrl->name) {
644 pctl->groups[gid].name = noname_buf;
695 pctl->groups[gid].npins = 1; 645 pctl->groups[gid].npins = 1;
646 sprintf(noname_buf, "mpp%d", ctrl->pid+0);
647 noname_buf += 8;
696 648
697 for (k = 1; k < ctrl->npins; k++) { 649 for (k = 1; k < ctrl->npins; k++) {
698 gid++; 650 gid++;
699 pctl->groups[gid].gid = gid; 651 pctl->groups[gid].gid = gid;
700 pctl->groups[gid].ctrl = ctrl; 652 pctl->groups[gid].ctrl = ctrl;
701 pctl->groups[gid].name = &ctrl->name[8*k]; 653 pctl->groups[gid].name = noname_buf;
702 pctl->groups[gid].pins = &ctrl->pins[k]; 654 pctl->groups[gid].pins = &ctrl->pins[k];
703 pctl->groups[gid].npins = 1; 655 pctl->groups[gid].npins = 1;
656 sprintf(noname_buf, "mpp%d", ctrl->pid+k);
657 noname_buf += 8;
704 } 658 }
705 } 659 }
706 gid++; 660 gid++;
diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.h b/drivers/pinctrl/mvebu/pinctrl-mvebu.h
index 90bd3beee860..65a98e6f7265 100644
--- a/drivers/pinctrl/mvebu/pinctrl-mvebu.h
+++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.h
@@ -28,20 +28,19 @@
28 * between two or more different settings, e.g. assign mpp pin 13 to 28 * between two or more different settings, e.g. assign mpp pin 13 to
29 * uart1 or sata. 29 * uart1 or sata.
30 * 30 *
31 * If optional mpp_get/_set functions are set these are used to get/set 31 * The mpp_get/_set functions are mandatory and are used to get/set a
32 * a specific mode. Otherwise it is assumed that the mpp control is based 32 * specific mode. The optional mpp_gpio_req/_dir functions can be used
33 * on 4-bit groups in subsequent registers. The optional mpp_gpio_req/_dir 33 * to allow pin settings with varying gpio pins.
34 * functions can be used to allow pin settings with varying gpio pins.
35 */ 34 */
36struct mvebu_mpp_ctrl { 35struct mvebu_mpp_ctrl {
37 const char *name; 36 const char *name;
38 u8 pid; 37 u8 pid;
39 u8 npins; 38 u8 npins;
40 unsigned *pins; 39 unsigned *pins;
41 int (*mpp_get)(struct mvebu_mpp_ctrl *ctrl, unsigned long *config); 40 int (*mpp_get)(unsigned pid, unsigned long *config);
42 int (*mpp_set)(struct mvebu_mpp_ctrl *ctrl, unsigned long config); 41 int (*mpp_set)(unsigned pid, unsigned long config);
43 int (*mpp_gpio_req)(struct mvebu_mpp_ctrl *ctrl, u8 pid); 42 int (*mpp_gpio_req)(unsigned pid);
44 int (*mpp_gpio_dir)(struct mvebu_mpp_ctrl *ctrl, u8 pid, bool input); 43 int (*mpp_gpio_dir)(unsigned pid, bool input);
45}; 44};
46 45
47/** 46/**
@@ -114,18 +113,6 @@ struct mvebu_pinctrl_soc_info {
114 int ngpioranges; 113 int ngpioranges;
115}; 114};
116 115
117#define MPP_REG_CTRL(_idl, _idh) \
118 { \
119 .name = NULL, \
120 .pid = _idl, \
121 .npins = _idh - _idl + 1, \
122 .pins = (unsigned[_idh - _idl + 1]) { }, \
123 .mpp_get = NULL, \
124 .mpp_set = NULL, \
125 .mpp_gpio_req = NULL, \
126 .mpp_gpio_dir = NULL, \
127 }
128
129#define MPP_FUNC_CTRL(_idl, _idh, _name, _func) \ 116#define MPP_FUNC_CTRL(_idl, _idh, _name, _func) \
130 { \ 117 { \
131 .name = _name, \ 118 .name = _name, \
@@ -186,6 +173,34 @@ struct mvebu_pinctrl_soc_info {
186 .npins = _npins, \ 173 .npins = _npins, \
187 } 174 }
188 175
176#define MVEBU_MPPS_PER_REG 8
177#define MVEBU_MPP_BITS 4
178#define MVEBU_MPP_MASK 0xf
179
180static inline int default_mpp_ctrl_get(void __iomem *base, unsigned int pid,
181 unsigned long *config)
182{
183 unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
184 unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
185
186 *config = (readl(base + off) >> shift) & MVEBU_MPP_MASK;
187
188 return 0;
189}
190
191static inline int default_mpp_ctrl_set(void __iomem *base, unsigned int pid,
192 unsigned long config)
193{
194 unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
195 unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
196 unsigned long reg;
197
198 reg = readl(base + off) & ~(MVEBU_MPP_MASK << shift);
199 writel(reg | (config << shift), base + off);
200
201 return 0;
202}
203
189int mvebu_pinctrl_probe(struct platform_device *pdev); 204int mvebu_pinctrl_probe(struct platform_device *pdev);
190int mvebu_pinctrl_remove(struct platform_device *pdev); 205int mvebu_pinctrl_remove(struct platform_device *pdev);
191 206
diff --git a/drivers/pinctrl/pinctrl-adi2-bf54x.c b/drivers/pinctrl/pinctrl-adi2-bf54x.c
index ea9d9ab9cda1..008a29e92e56 100644
--- a/drivers/pinctrl/pinctrl-adi2-bf54x.c
+++ b/drivers/pinctrl/pinctrl-adi2-bf54x.c
@@ -309,39 +309,6 @@ static const unsigned keys_8x8_pins[] = {
309 GPIO_PE4, GPIO_PE5, GPIO_PE6, GPIO_PE7, 309 GPIO_PE4, GPIO_PE5, GPIO_PE6, GPIO_PE7,
310}; 310};
311 311
312static const struct adi_pin_group adi_pin_groups[] = {
313 ADI_PIN_GROUP("uart0grp", uart0_pins),
314 ADI_PIN_GROUP("uart1grp", uart1_pins),
315 ADI_PIN_GROUP("uart1ctsrtsgrp", uart1_ctsrts_pins),
316 ADI_PIN_GROUP("uart2grp", uart2_pins),
317 ADI_PIN_GROUP("uart3grp", uart3_pins),
318 ADI_PIN_GROUP("uart3ctsrtsgrp", uart3_ctsrts_pins),
319 ADI_PIN_GROUP("rsi0grp", rsi0_pins),
320 ADI_PIN_GROUP("spi0grp", spi0_pins),
321 ADI_PIN_GROUP("spi1grp", spi1_pins),
322 ADI_PIN_GROUP("twi0grp", twi0_pins),
323 ADI_PIN_GROUP("twi1grp", twi1_pins),
324 ADI_PIN_GROUP("rotarygrp", rotary_pins),
325 ADI_PIN_GROUP("can0grp", can0_pins),
326 ADI_PIN_GROUP("can1grp", can1_pins),
327 ADI_PIN_GROUP("smc0grp", smc0_pins),
328 ADI_PIN_GROUP("sport0grp", sport0_pins),
329 ADI_PIN_GROUP("sport1grp", sport1_pins),
330 ADI_PIN_GROUP("sport2grp", sport2_pins),
331 ADI_PIN_GROUP("sport3grp", sport3_pins),
332 ADI_PIN_GROUP("ppi0_8bgrp", ppi0_8b_pins),
333 ADI_PIN_GROUP("ppi0_16bgrp", ppi0_16b_pins),
334 ADI_PIN_GROUP("ppi0_24bgrp", ppi0_24b_pins),
335 ADI_PIN_GROUP("ppi1_8bgrp", ppi1_8b_pins),
336 ADI_PIN_GROUP("ppi1_16bgrp", ppi1_16b_pins),
337 ADI_PIN_GROUP("ppi2_8bgrp", ppi2_8b_pins),
338 ADI_PIN_GROUP("atapigrp", atapi_pins),
339 ADI_PIN_GROUP("atapialtergrp", atapi_alter_pins),
340 ADI_PIN_GROUP("nfc0grp", nfc0_pins),
341 ADI_PIN_GROUP("keys_4x4grp", keys_4x4_pins),
342 ADI_PIN_GROUP("keys_8x8grp", keys_8x8_pins),
343};
344
345static const unsigned short uart0_mux[] = { 312static const unsigned short uart0_mux[] = {
346 P_UART0_TX, P_UART0_RX, 313 P_UART0_TX, P_UART0_RX,
347 0 314 0
@@ -513,6 +480,39 @@ static const unsigned short keys_8x8_mux[] = {
513 0 480 0
514}; 481};
515 482
483static const struct adi_pin_group adi_pin_groups[] = {
484 ADI_PIN_GROUP("uart0grp", uart0_pins, uart0_mux),
485 ADI_PIN_GROUP("uart1grp", uart1_pins, uart1_mux),
486 ADI_PIN_GROUP("uart1ctsrtsgrp", uart1_ctsrts_pins, uart1_ctsrts_mux),
487 ADI_PIN_GROUP("uart2grp", uart2_pins, uart2_mux),
488 ADI_PIN_GROUP("uart3grp", uart3_pins, uart3_mux),
489 ADI_PIN_GROUP("uart3ctsrtsgrp", uart3_ctsrts_pins, uart3_ctsrts_mux),
490 ADI_PIN_GROUP("rsi0grp", rsi0_pins, rsi0_mux),
491 ADI_PIN_GROUP("spi0grp", spi0_pins, spi0_mux),
492 ADI_PIN_GROUP("spi1grp", spi1_pins, spi1_mux),
493 ADI_PIN_GROUP("twi0grp", twi0_pins, twi0_mux),
494 ADI_PIN_GROUP("twi1grp", twi1_pins, twi1_mux),
495 ADI_PIN_GROUP("rotarygrp", rotary_pins, rotary_mux),
496 ADI_PIN_GROUP("can0grp", can0_pins, can0_mux),
497 ADI_PIN_GROUP("can1grp", can1_pins, can1_mux),
498 ADI_PIN_GROUP("smc0grp", smc0_pins, smc0_mux),
499 ADI_PIN_GROUP("sport0grp", sport0_pins, sport0_mux),
500 ADI_PIN_GROUP("sport1grp", sport1_pins, sport1_mux),
501 ADI_PIN_GROUP("sport2grp", sport2_pins, sport2_mux),
502 ADI_PIN_GROUP("sport3grp", sport3_pins, sport3_mux),
503 ADI_PIN_GROUP("ppi0_8bgrp", ppi0_8b_pins, ppi0_8b_mux),
504 ADI_PIN_GROUP("ppi0_16bgrp", ppi0_16b_pins, ppi0_16b_mux),
505 ADI_PIN_GROUP("ppi0_24bgrp", ppi0_24b_pins, ppi0_24b_mux),
506 ADI_PIN_GROUP("ppi1_8bgrp", ppi1_8b_pins, ppi1_8b_mux),
507 ADI_PIN_GROUP("ppi1_16bgrp", ppi1_16b_pins, ppi1_16b_mux),
508 ADI_PIN_GROUP("ppi2_8bgrp", ppi2_8b_pins, ppi2_8b_mux),
509 ADI_PIN_GROUP("atapigrp", atapi_pins, atapi_mux),
510 ADI_PIN_GROUP("atapialtergrp", atapi_alter_pins, atapi_alter_mux),
511 ADI_PIN_GROUP("nfc0grp", nfc0_pins, nfc0_mux),
512 ADI_PIN_GROUP("keys_4x4grp", keys_4x4_pins, keys_4x4_mux),
513 ADI_PIN_GROUP("keys_8x8grp", keys_8x8_pins, keys_8x8_mux),
514};
515
516static const char * const uart0grp[] = { "uart0grp" }; 516static const char * const uart0grp[] = { "uart0grp" };
517static const char * const uart1grp[] = { "uart1grp" }; 517static const char * const uart1grp[] = { "uart1grp" };
518static const char * const uart1ctsrtsgrp[] = { "uart1ctsrtsgrp" }; 518static const char * const uart1ctsrtsgrp[] = { "uart1ctsrtsgrp" };
@@ -532,49 +532,45 @@ static const char * const sport0grp[] = { "sport0grp" };
532static const char * const sport1grp[] = { "sport1grp" }; 532static const char * const sport1grp[] = { "sport1grp" };
533static const char * const sport2grp[] = { "sport2grp" }; 533static const char * const sport2grp[] = { "sport2grp" };
534static const char * const sport3grp[] = { "sport3grp" }; 534static const char * const sport3grp[] = { "sport3grp" };
535static const char * const ppi0_8bgrp[] = { "ppi0_8bgrp" }; 535static const char * const ppi0grp[] = { "ppi0_8bgrp",
536static const char * const ppi0_16bgrp[] = { "ppi0_16bgrp" }; 536 "ppi0_16bgrp",
537static const char * const ppi0_24bgrp[] = { "ppi0_24bgrp" }; 537 "ppi0_24bgrp" };
538static const char * const ppi1_8bgrp[] = { "ppi1_8bgrp" }; 538static const char * const ppi1grp[] = { "ppi1_8bgrp",
539static const char * const ppi1_16bgrp[] = { "ppi1_16bgrp" }; 539 "ppi1_16bgrp" };
540static const char * const ppi2_8bgrp[] = { "ppi2_8bgrp" }; 540static const char * const ppi2grp[] = { "ppi2_8bgrp" };
541static const char * const atapigrp[] = { "atapigrp" }; 541static const char * const atapigrp[] = { "atapigrp" };
542static const char * const atapialtergrp[] = { "atapialtergrp" }; 542static const char * const atapialtergrp[] = { "atapialtergrp" };
543static const char * const nfc0grp[] = { "nfc0grp" }; 543static const char * const nfc0grp[] = { "nfc0grp" };
544static const char * const keys_4x4grp[] = { "keys_4x4grp" }; 544static const char * const keysgrp[] = { "keys_4x4grp",
545static const char * const keys_8x8grp[] = { "keys_8x8grp" }; 545 "keys_8x8grp" };
546 546
547static const struct adi_pmx_func adi_pmx_functions[] = { 547static const struct adi_pmx_func adi_pmx_functions[] = {
548 ADI_PMX_FUNCTION("uart0", uart0grp, uart0_mux), 548 ADI_PMX_FUNCTION("uart0", uart0grp),
549 ADI_PMX_FUNCTION("uart1", uart1grp, uart1_mux), 549 ADI_PMX_FUNCTION("uart1", uart1grp),
550 ADI_PMX_FUNCTION("uart1_ctsrts", uart1ctsrtsgrp, uart1_ctsrts_mux), 550 ADI_PMX_FUNCTION("uart1_ctsrts", uart1ctsrtsgrp),
551 ADI_PMX_FUNCTION("uart2", uart2grp, uart2_mux), 551 ADI_PMX_FUNCTION("uart2", uart2grp),
552 ADI_PMX_FUNCTION("uart3", uart3grp, uart3_mux), 552 ADI_PMX_FUNCTION("uart3", uart3grp),
553 ADI_PMX_FUNCTION("uart3_ctsrts", uart3ctsrtsgrp, uart3_ctsrts_mux), 553 ADI_PMX_FUNCTION("uart3_ctsrts", uart3ctsrtsgrp),
554 ADI_PMX_FUNCTION("rsi0", rsi0grp, rsi0_mux), 554 ADI_PMX_FUNCTION("rsi0", rsi0grp),
555 ADI_PMX_FUNCTION("spi0", spi0grp, spi0_mux), 555 ADI_PMX_FUNCTION("spi0", spi0grp),
556 ADI_PMX_FUNCTION("spi1", spi1grp, spi1_mux), 556 ADI_PMX_FUNCTION("spi1", spi1grp),
557 ADI_PMX_FUNCTION("twi0", twi0grp, twi0_mux), 557 ADI_PMX_FUNCTION("twi0", twi0grp),
558 ADI_PMX_FUNCTION("twi1", twi1grp, twi1_mux), 558 ADI_PMX_FUNCTION("twi1", twi1grp),
559 ADI_PMX_FUNCTION("rotary", rotarygrp, rotary_mux), 559 ADI_PMX_FUNCTION("rotary", rotarygrp),
560 ADI_PMX_FUNCTION("can0", can0grp, can0_mux), 560 ADI_PMX_FUNCTION("can0", can0grp),
561 ADI_PMX_FUNCTION("can1", can1grp, can1_mux), 561 ADI_PMX_FUNCTION("can1", can1grp),
562 ADI_PMX_FUNCTION("smc0", smc0grp, smc0_mux), 562 ADI_PMX_FUNCTION("smc0", smc0grp),
563 ADI_PMX_FUNCTION("sport0", sport0grp, sport0_mux), 563 ADI_PMX_FUNCTION("sport0", sport0grp),
564 ADI_PMX_FUNCTION("sport1", sport1grp, sport1_mux), 564 ADI_PMX_FUNCTION("sport1", sport1grp),
565 ADI_PMX_FUNCTION("sport2", sport2grp, sport2_mux), 565 ADI_PMX_FUNCTION("sport2", sport2grp),
566 ADI_PMX_FUNCTION("sport3", sport3grp, sport3_mux), 566 ADI_PMX_FUNCTION("sport3", sport3grp),
567 ADI_PMX_FUNCTION("ppi0_8b", ppi0_8bgrp, ppi0_8b_mux), 567 ADI_PMX_FUNCTION("ppi0", ppi0grp),
568 ADI_PMX_FUNCTION("ppi0_16b", ppi0_16bgrp, ppi0_16b_mux), 568 ADI_PMX_FUNCTION("ppi1", ppi1grp),
569 ADI_PMX_FUNCTION("ppi0_24b", ppi0_24bgrp, ppi0_24b_mux), 569 ADI_PMX_FUNCTION("ppi2", ppi2grp),
570 ADI_PMX_FUNCTION("ppi1_8b", ppi1_8bgrp, ppi1_8b_mux), 570 ADI_PMX_FUNCTION("atapi", atapigrp),
571 ADI_PMX_FUNCTION("ppi1_16b", ppi1_16bgrp, ppi1_16b_mux), 571 ADI_PMX_FUNCTION("atapi_alter", atapialtergrp),
572 ADI_PMX_FUNCTION("ppi2_8b", ppi2_8bgrp, ppi2_8b_mux), 572 ADI_PMX_FUNCTION("nfc0", nfc0grp),
573 ADI_PMX_FUNCTION("atapi", atapigrp, atapi_mux), 573 ADI_PMX_FUNCTION("keys", keysgrp),
574 ADI_PMX_FUNCTION("atapi_alter", atapialtergrp, atapi_alter_mux),
575 ADI_PMX_FUNCTION("nfc0", nfc0grp, nfc0_mux),
576 ADI_PMX_FUNCTION("keys_4x4", keys_4x4grp, keys_4x4_mux),
577 ADI_PMX_FUNCTION("keys_8x8", keys_8x8grp, keys_8x8_mux),
578}; 574};
579 575
580static const struct adi_pinctrl_soc_data adi_bf54x_soc = { 576static const struct adi_pinctrl_soc_data adi_bf54x_soc = {
diff --git a/drivers/pinctrl/pinctrl-adi2-bf60x.c b/drivers/pinctrl/pinctrl-adi2-bf60x.c
index bf57aea2826c..4cb59fe9be70 100644
--- a/drivers/pinctrl/pinctrl-adi2-bf60x.c
+++ b/drivers/pinctrl/pinctrl-adi2-bf60x.c
@@ -259,37 +259,6 @@ static const unsigned lp3_pins[] = {
259 GPIO_PF12, GPIO_PF13, GPIO_PF14, GPIO_PF15, 259 GPIO_PF12, GPIO_PF13, GPIO_PF14, GPIO_PF15,
260}; 260};
261 261
262static const struct adi_pin_group adi_pin_groups[] = {
263 ADI_PIN_GROUP("uart0grp", uart0_pins),
264 ADI_PIN_GROUP("uart0ctsrtsgrp", uart0_ctsrts_pins),
265 ADI_PIN_GROUP("uart1grp", uart1_pins),
266 ADI_PIN_GROUP("uart1ctsrtsgrp", uart1_ctsrts_pins),
267 ADI_PIN_GROUP("rsi0grp", rsi0_pins),
268 ADI_PIN_GROUP("eth0grp", eth0_pins),
269 ADI_PIN_GROUP("eth1grp", eth1_pins),
270 ADI_PIN_GROUP("spi0grp", spi0_pins),
271 ADI_PIN_GROUP("spi1grp", spi1_pins),
272 ADI_PIN_GROUP("twi0grp", twi0_pins),
273 ADI_PIN_GROUP("twi1grp", twi1_pins),
274 ADI_PIN_GROUP("rotarygrp", rotary_pins),
275 ADI_PIN_GROUP("can0grp", can0_pins),
276 ADI_PIN_GROUP("smc0grp", smc0_pins),
277 ADI_PIN_GROUP("sport0grp", sport0_pins),
278 ADI_PIN_GROUP("sport1grp", sport1_pins),
279 ADI_PIN_GROUP("sport2grp", sport2_pins),
280 ADI_PIN_GROUP("ppi0_8bgrp", ppi0_8b_pins),
281 ADI_PIN_GROUP("ppi0_16bgrp", ppi0_16b_pins),
282 ADI_PIN_GROUP("ppi0_24bgrp", ppi0_24b_pins),
283 ADI_PIN_GROUP("ppi1_8bgrp", ppi1_8b_pins),
284 ADI_PIN_GROUP("ppi1_16bgrp", ppi1_16b_pins),
285 ADI_PIN_GROUP("ppi2_8bgrp", ppi2_8b_pins),
286 ADI_PIN_GROUP("ppi2_16bgrp", ppi2_16b_pins),
287 ADI_PIN_GROUP("lp0grp", lp0_pins),
288 ADI_PIN_GROUP("lp1grp", lp1_pins),
289 ADI_PIN_GROUP("lp2grp", lp2_pins),
290 ADI_PIN_GROUP("lp3grp", lp3_pins),
291};
292
293static const unsigned short uart0_mux[] = { 262static const unsigned short uart0_mux[] = {
294 P_UART0_TX, P_UART0_RX, 263 P_UART0_TX, P_UART0_RX,
295 0 264 0
@@ -446,6 +415,37 @@ static const unsigned short lp3_mux[] = {
446 0 415 0
447}; 416};
448 417
418static const struct adi_pin_group adi_pin_groups[] = {
419 ADI_PIN_GROUP("uart0grp", uart0_pins, uart0_mux),
420 ADI_PIN_GROUP("uart0ctsrtsgrp", uart0_ctsrts_pins, uart0_ctsrts_mux),
421 ADI_PIN_GROUP("uart1grp", uart1_pins, uart1_mux),
422 ADI_PIN_GROUP("uart1ctsrtsgrp", uart1_ctsrts_pins, uart1_ctsrts_mux),
423 ADI_PIN_GROUP("rsi0grp", rsi0_pins, rsi0_mux),
424 ADI_PIN_GROUP("eth0grp", eth0_pins, eth0_mux),
425 ADI_PIN_GROUP("eth1grp", eth1_pins, eth1_mux),
426 ADI_PIN_GROUP("spi0grp", spi0_pins, spi0_mux),
427 ADI_PIN_GROUP("spi1grp", spi1_pins, spi1_mux),
428 ADI_PIN_GROUP("twi0grp", twi0_pins, twi0_mux),
429 ADI_PIN_GROUP("twi1grp", twi1_pins, twi1_mux),
430 ADI_PIN_GROUP("rotarygrp", rotary_pins, rotary_mux),
431 ADI_PIN_GROUP("can0grp", can0_pins, can0_mux),
432 ADI_PIN_GROUP("smc0grp", smc0_pins, smc0_mux),
433 ADI_PIN_GROUP("sport0grp", sport0_pins, sport0_mux),
434 ADI_PIN_GROUP("sport1grp", sport1_pins, sport1_mux),
435 ADI_PIN_GROUP("sport2grp", sport2_pins, sport2_mux),
436 ADI_PIN_GROUP("ppi0_8bgrp", ppi0_8b_pins, ppi0_8b_mux),
437 ADI_PIN_GROUP("ppi0_16bgrp", ppi0_16b_pins, ppi0_16b_mux),
438 ADI_PIN_GROUP("ppi0_24bgrp", ppi0_24b_pins, ppi0_24b_mux),
439 ADI_PIN_GROUP("ppi1_8bgrp", ppi1_8b_pins, ppi1_8b_mux),
440 ADI_PIN_GROUP("ppi1_16bgrp", ppi1_16b_pins, ppi1_16b_mux),
441 ADI_PIN_GROUP("ppi2_8bgrp", ppi2_8b_pins, ppi2_8b_mux),
442 ADI_PIN_GROUP("ppi2_16bgrp", ppi2_16b_pins, ppi2_16b_mux),
443 ADI_PIN_GROUP("lp0grp", lp0_pins, lp0_mux),
444 ADI_PIN_GROUP("lp1grp", lp1_pins, lp1_mux),
445 ADI_PIN_GROUP("lp2grp", lp2_pins, lp2_mux),
446 ADI_PIN_GROUP("lp3grp", lp3_pins, lp3_mux),
447};
448
449static const char * const uart0grp[] = { "uart0grp" }; 449static const char * const uart0grp[] = { "uart0grp" };
450static const char * const uart0ctsrtsgrp[] = { "uart0ctsrtsgrp" }; 450static const char * const uart0ctsrtsgrp[] = { "uart0ctsrtsgrp" };
451static const char * const uart1grp[] = { "uart1grp" }; 451static const char * const uart1grp[] = { "uart1grp" };
@@ -463,47 +463,43 @@ static const char * const smc0grp[] = { "smc0grp" };
463static const char * const sport0grp[] = { "sport0grp" }; 463static const char * const sport0grp[] = { "sport0grp" };
464static const char * const sport1grp[] = { "sport1grp" }; 464static const char * const sport1grp[] = { "sport1grp" };
465static const char * const sport2grp[] = { "sport2grp" }; 465static const char * const sport2grp[] = { "sport2grp" };
466static const char * const ppi0_8bgrp[] = { "ppi0_8bgrp" }; 466static const char * const ppi0grp[] = { "ppi0_8bgrp",
467static const char * const ppi0_16bgrp[] = { "ppi0_16bgrp" }; 467 "ppi0_16bgrp",
468static const char * const ppi0_24bgrp[] = { "ppi0_24bgrp" }; 468 "ppi0_24bgrp" };
469static const char * const ppi1_8bgrp[] = { "ppi1_8bgrp" }; 469static const char * const ppi1grp[] = { "ppi1_8bgrp",
470static const char * const ppi1_16bgrp[] = { "ppi1_16bgrp" }; 470 "ppi1_16bgrp" };
471static const char * const ppi2_8bgrp[] = { "ppi2_8bgrp" }; 471static const char * const ppi2grp[] = { "ppi2_8bgrp",
472static const char * const ppi2_16bgrp[] = { "ppi2_16bgrp" }; 472 "ppi2_16bgrp" };
473static const char * const lp0grp[] = { "lp0grp" }; 473static const char * const lp0grp[] = { "lp0grp" };
474static const char * const lp1grp[] = { "lp1grp" }; 474static const char * const lp1grp[] = { "lp1grp" };
475static const char * const lp2grp[] = { "lp2grp" }; 475static const char * const lp2grp[] = { "lp2grp" };
476static const char * const lp3grp[] = { "lp3grp" }; 476static const char * const lp3grp[] = { "lp3grp" };
477 477
478static const struct adi_pmx_func adi_pmx_functions[] = { 478static const struct adi_pmx_func adi_pmx_functions[] = {
479 ADI_PMX_FUNCTION("uart0", uart0grp, uart0_mux), 479 ADI_PMX_FUNCTION("uart0", uart0grp),
480 ADI_PMX_FUNCTION("uart0_ctsrts", uart0ctsrtsgrp, uart0_ctsrts_mux), 480 ADI_PMX_FUNCTION("uart0_ctsrts", uart0ctsrtsgrp),
481 ADI_PMX_FUNCTION("uart1", uart1grp, uart1_mux), 481 ADI_PMX_FUNCTION("uart1", uart1grp),
482 ADI_PMX_FUNCTION("uart1_ctsrts", uart1ctsrtsgrp, uart1_ctsrts_mux), 482 ADI_PMX_FUNCTION("uart1_ctsrts", uart1ctsrtsgrp),
483 ADI_PMX_FUNCTION("rsi0", rsi0grp, rsi0_mux), 483 ADI_PMX_FUNCTION("rsi0", rsi0grp),
484 ADI_PMX_FUNCTION("eth0", eth0grp, eth0_mux), 484 ADI_PMX_FUNCTION("eth0", eth0grp),
485 ADI_PMX_FUNCTION("eth1", eth1grp, eth1_mux), 485 ADI_PMX_FUNCTION("eth1", eth1grp),
486 ADI_PMX_FUNCTION("spi0", spi0grp, spi0_mux), 486 ADI_PMX_FUNCTION("spi0", spi0grp),
487 ADI_PMX_FUNCTION("spi1", spi1grp, spi1_mux), 487 ADI_PMX_FUNCTION("spi1", spi1grp),
488 ADI_PMX_FUNCTION("twi0", twi0grp, twi0_mux), 488 ADI_PMX_FUNCTION("twi0", twi0grp),
489 ADI_PMX_FUNCTION("twi1", twi1grp, twi1_mux), 489 ADI_PMX_FUNCTION("twi1", twi1grp),
490 ADI_PMX_FUNCTION("rotary", rotarygrp, rotary_mux), 490 ADI_PMX_FUNCTION("rotary", rotarygrp),
491 ADI_PMX_FUNCTION("can0", can0grp, can0_mux), 491 ADI_PMX_FUNCTION("can0", can0grp),
492 ADI_PMX_FUNCTION("smc0", smc0grp, smc0_mux), 492 ADI_PMX_FUNCTION("smc0", smc0grp),
493 ADI_PMX_FUNCTION("sport0", sport0grp, sport0_mux), 493 ADI_PMX_FUNCTION("sport0", sport0grp),
494 ADI_PMX_FUNCTION("sport1", sport1grp, sport1_mux), 494 ADI_PMX_FUNCTION("sport1", sport1grp),
495 ADI_PMX_FUNCTION("sport2", sport2grp, sport2_mux), 495 ADI_PMX_FUNCTION("sport2", sport2grp),
496 ADI_PMX_FUNCTION("ppi0_8b", ppi0_8bgrp, ppi0_8b_mux), 496 ADI_PMX_FUNCTION("ppi0", ppi0grp),
497 ADI_PMX_FUNCTION("ppi0_16b", ppi0_16bgrp, ppi0_16b_mux), 497 ADI_PMX_FUNCTION("ppi1", ppi1grp),
498 ADI_PMX_FUNCTION("ppi0_24b", ppi0_24bgrp, ppi0_24b_mux), 498 ADI_PMX_FUNCTION("ppi2", ppi2grp),
499 ADI_PMX_FUNCTION("ppi1_8b", ppi1_8bgrp, ppi1_8b_mux), 499 ADI_PMX_FUNCTION("lp0", lp0grp),
500 ADI_PMX_FUNCTION("ppi1_16b", ppi1_16bgrp, ppi1_16b_mux), 500 ADI_PMX_FUNCTION("lp1", lp1grp),
501 ADI_PMX_FUNCTION("ppi2_8b", ppi2_8bgrp, ppi2_8b_mux), 501 ADI_PMX_FUNCTION("lp2", lp2grp),
502 ADI_PMX_FUNCTION("ppi2_16b", ppi2_16bgrp, ppi2_16b_mux), 502 ADI_PMX_FUNCTION("lp3", lp3grp),
503 ADI_PMX_FUNCTION("lp0", lp0grp, lp0_mux),
504 ADI_PMX_FUNCTION("lp1", lp1grp, lp1_mux),
505 ADI_PMX_FUNCTION("lp2", lp2grp, lp2_mux),
506 ADI_PMX_FUNCTION("lp3", lp3grp, lp3_mux),
507}; 503};
508 504
509static const struct adi_pinctrl_soc_data adi_bf60x_soc = { 505static const struct adi_pinctrl_soc_data adi_bf60x_soc = {
diff --git a/drivers/pinctrl/pinctrl-adi2.c b/drivers/pinctrl/pinctrl-adi2.c
index 7a39562c3e42..200ea1e72d40 100644
--- a/drivers/pinctrl/pinctrl-adi2.c
+++ b/drivers/pinctrl/pinctrl-adi2.c
@@ -89,6 +89,19 @@ struct gpio_port_saved {
89 u32 mux; 89 u32 mux;
90}; 90};
91 91
92/*
93 * struct gpio_pint_saved - PINT registers saved in PM operations
94 *
95 * @assign: ASSIGN register
96 * @edge_set: EDGE_SET register
97 * @invert_set: INVERT_SET register
98 */
99struct gpio_pint_saved {
100 u32 assign;
101 u32 edge_set;
102 u32 invert_set;
103};
104
92/** 105/**
93 * struct gpio_pint - Pin interrupt controller device. Multiple ADI GPIO 106 * struct gpio_pint - Pin interrupt controller device. Multiple ADI GPIO
94 * banks can be mapped into one Pin interrupt controller. 107 * banks can be mapped into one Pin interrupt controller.
@@ -114,7 +127,7 @@ struct gpio_pint {
114 int irq; 127 int irq;
115 struct irq_domain *domain[2]; 128 struct irq_domain *domain[2];
116 struct gpio_pint_regs *regs; 129 struct gpio_pint_regs *regs;
117 struct adi_pm_pint_save saved_data; 130 struct gpio_pint_saved saved_data;
118 int map_count; 131 int map_count;
119 spinlock_t lock; 132 spinlock_t lock;
120 133
@@ -160,7 +173,7 @@ struct adi_pinctrl {
160struct gpio_port { 173struct gpio_port {
161 struct list_head node; 174 struct list_head node;
162 void __iomem *base; 175 void __iomem *base;
163 unsigned int irq_base; 176 int irq_base;
164 unsigned int width; 177 unsigned int width;
165 struct gpio_port_t *regs; 178 struct gpio_port_t *regs;
166 struct gpio_port_saved saved_data; 179 struct gpio_port_saved saved_data;
@@ -605,8 +618,8 @@ static struct pinctrl_ops adi_pctrl_ops = {
605 .get_group_pins = adi_get_group_pins, 618 .get_group_pins = adi_get_group_pins,
606}; 619};
607 620
608static int adi_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector, 621static int adi_pinmux_enable(struct pinctrl_dev *pctldev, unsigned func_id,
609 unsigned group) 622 unsigned group_id)
610{ 623{
611 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev); 624 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
612 struct gpio_port *port; 625 struct gpio_port *port;
@@ -614,7 +627,7 @@ static int adi_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector,
614 unsigned long flags; 627 unsigned long flags;
615 unsigned short *mux, pin; 628 unsigned short *mux, pin;
616 629
617 mux = (unsigned short *)pinctrl->soc->functions[selector].mux; 630 mux = (unsigned short *)pinctrl->soc->groups[group_id].mux;
618 631
619 while (*mux) { 632 while (*mux) {
620 pin = P_IDENT(*mux); 633 pin = P_IDENT(*mux);
@@ -628,7 +641,7 @@ static int adi_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector,
628 spin_lock_irqsave(&port->lock, flags); 641 spin_lock_irqsave(&port->lock, flags);
629 642
630 portmux_setup(port, pin_to_offset(range, pin), 643 portmux_setup(port, pin_to_offset(range, pin),
631 P_FUNCT2MUX(*mux)); 644 P_FUNCT2MUX(*mux));
632 port_setup(port, pin_to_offset(range, pin), false); 645 port_setup(port, pin_to_offset(range, pin), false);
633 mux++; 646 mux++;
634 647
@@ -638,8 +651,8 @@ static int adi_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector,
638 return 0; 651 return 0;
639} 652}
640 653
641static void adi_pinmux_disable(struct pinctrl_dev *pctldev, unsigned selector, 654static void adi_pinmux_disable(struct pinctrl_dev *pctldev, unsigned func_id,
642 unsigned group) 655 unsigned group_id)
643{ 656{
644 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev); 657 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
645 struct gpio_port *port; 658 struct gpio_port *port;
@@ -647,7 +660,7 @@ static void adi_pinmux_disable(struct pinctrl_dev *pctldev, unsigned selector,
647 unsigned long flags; 660 unsigned long flags;
648 unsigned short *mux, pin; 661 unsigned short *mux, pin;
649 662
650 mux = (unsigned short *)pinctrl->soc->functions[selector].mux; 663 mux = (unsigned short *)pinctrl->soc->groups[group_id].mux;
651 664
652 while (*mux) { 665 while (*mux) {
653 pin = P_IDENT(*mux); 666 pin = P_IDENT(*mux);
diff --git a/drivers/pinctrl/pinctrl-adi2.h b/drivers/pinctrl/pinctrl-adi2.h
index 1f06f8df1fa3..3ca29738213f 100644
--- a/drivers/pinctrl/pinctrl-adi2.h
+++ b/drivers/pinctrl/pinctrl-adi2.h
@@ -21,13 +21,15 @@ struct adi_pin_group {
21 const char *name; 21 const char *name;
22 const unsigned *pins; 22 const unsigned *pins;
23 const unsigned num; 23 const unsigned num;
24 const unsigned short *mux;
24}; 25};
25 26
26#define ADI_PIN_GROUP(n, p) \ 27#define ADI_PIN_GROUP(n, p, m) \
27 { \ 28 { \
28 .name = n, \ 29 .name = n, \
29 .pins = p, \ 30 .pins = p, \
30 .num = ARRAY_SIZE(p), \ 31 .num = ARRAY_SIZE(p), \
32 .mux = m, \
31 } 33 }
32 34
33 /** 35 /**
@@ -41,15 +43,13 @@ struct adi_pmx_func {
41 const char *name; 43 const char *name;
42 const char * const *groups; 44 const char * const *groups;
43 const unsigned num_groups; 45 const unsigned num_groups;
44 const unsigned short *mux;
45}; 46};
46 47
47#define ADI_PMX_FUNCTION(n, g, m) \ 48#define ADI_PMX_FUNCTION(n, g) \
48 { \ 49 { \
49 .name = n, \ 50 .name = n, \
50 .groups = g, \ 51 .groups = g, \
51 .num_groups = ARRAY_SIZE(g), \ 52 .num_groups = ARRAY_SIZE(g), \
52 .mux = m, \
53 } 53 }
54 54
55/** 55/**
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index d990e33d8aa7..5d24aaec5dbc 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -1137,6 +1137,17 @@ static void at91_gpio_free(struct gpio_chip *chip, unsigned offset)
1137 pinctrl_free_gpio(gpio); 1137 pinctrl_free_gpio(gpio);
1138} 1138}
1139 1139
1140static int at91_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1141{
1142 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1143 void __iomem *pio = at91_gpio->regbase;
1144 unsigned mask = 1 << offset;
1145 u32 osr;
1146
1147 osr = readl_relaxed(pio + PIO_OSR);
1148 return !(osr & mask);
1149}
1150
1140static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 1151static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1141{ 1152{
1142 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 1153 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
@@ -1325,6 +1336,31 @@ static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
1325 return 0; 1336 return 0;
1326} 1337}
1327 1338
1339static unsigned int gpio_irq_startup(struct irq_data *d)
1340{
1341 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1342 unsigned pin = d->hwirq;
1343 int ret;
1344
1345 ret = gpio_lock_as_irq(&at91_gpio->chip, pin);
1346 if (ret) {
1347 dev_err(at91_gpio->chip.dev, "unable to lock pind %lu IRQ\n",
1348 d->hwirq);
1349 return ret;
1350 }
1351 gpio_irq_unmask(d);
1352 return 0;
1353}
1354
1355static void gpio_irq_shutdown(struct irq_data *d)
1356{
1357 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1358 unsigned pin = d->hwirq;
1359
1360 gpio_irq_mask(d);
1361 gpio_unlock_as_irq(&at91_gpio->chip, pin);
1362}
1363
1328#ifdef CONFIG_PM 1364#ifdef CONFIG_PM
1329 1365
1330static u32 wakeups[MAX_GPIO_BANKS]; 1366static u32 wakeups[MAX_GPIO_BANKS];
@@ -1399,6 +1435,8 @@ void at91_pinctrl_gpio_resume(void)
1399 1435
1400static struct irq_chip gpio_irqchip = { 1436static struct irq_chip gpio_irqchip = {
1401 .name = "GPIO", 1437 .name = "GPIO",
1438 .irq_startup = gpio_irq_startup,
1439 .irq_shutdown = gpio_irq_shutdown,
1402 .irq_disable = gpio_irq_mask, 1440 .irq_disable = gpio_irq_mask,
1403 .irq_mask = gpio_irq_mask, 1441 .irq_mask = gpio_irq_mask,
1404 .irq_unmask = gpio_irq_unmask, 1442 .irq_unmask = gpio_irq_unmask,
@@ -1543,6 +1581,7 @@ static int at91_gpio_of_irq_setup(struct device_node *node,
1543static struct gpio_chip at91_gpio_template = { 1581static struct gpio_chip at91_gpio_template = {
1544 .request = at91_gpio_request, 1582 .request = at91_gpio_request,
1545 .free = at91_gpio_free, 1583 .free = at91_gpio_free,
1584 .get_direction = at91_gpio_get_direction,
1546 .direction_input = at91_gpio_direction_input, 1585 .direction_input = at91_gpio_direction_input,
1547 .get = at91_gpio_get, 1586 .get = at91_gpio_get,
1548 .direction_output = at91_gpio_direction_output, 1587 .direction_output = at91_gpio_direction_output,
diff --git a/drivers/pinctrl/pinctrl-baytrail.c b/drivers/pinctrl/pinctrl-baytrail.c
index 665b96bc0c3a..bf2b3f655469 100644
--- a/drivers/pinctrl/pinctrl-baytrail.c
+++ b/drivers/pinctrl/pinctrl-baytrail.c
@@ -60,6 +60,10 @@
60#define BYT_NGPIO_NCORE 28 60#define BYT_NGPIO_NCORE 28
61#define BYT_NGPIO_SUS 44 61#define BYT_NGPIO_SUS 44
62 62
63#define BYT_SCORE_ACPI_UID "1"
64#define BYT_NCORE_ACPI_UID "2"
65#define BYT_SUS_ACPI_UID "3"
66
63/* 67/*
64 * Baytrail gpio controller consist of three separate sub-controllers called 68 * Baytrail gpio controller consist of three separate sub-controllers called
65 * SCORE, NCORE and SUS. The sub-controllers are identified by their acpi UID. 69 * SCORE, NCORE and SUS. The sub-controllers are identified by their acpi UID.
@@ -102,17 +106,17 @@ static unsigned const sus_pins[BYT_NGPIO_SUS] = {
102 106
103static struct pinctrl_gpio_range byt_ranges[] = { 107static struct pinctrl_gpio_range byt_ranges[] = {
104 { 108 {
105 .name = "1", /* match with acpi _UID in probe */ 109 .name = BYT_SCORE_ACPI_UID, /* match with acpi _UID in probe */
106 .npins = BYT_NGPIO_SCORE, 110 .npins = BYT_NGPIO_SCORE,
107 .pins = score_pins, 111 .pins = score_pins,
108 }, 112 },
109 { 113 {
110 .name = "2", 114 .name = BYT_NCORE_ACPI_UID,
111 .npins = BYT_NGPIO_NCORE, 115 .npins = BYT_NGPIO_NCORE,
112 .pins = ncore_pins, 116 .pins = ncore_pins,
113 }, 117 },
114 { 118 {
115 .name = "3", 119 .name = BYT_SUS_ACPI_UID,
116 .npins = BYT_NGPIO_SUS, 120 .npins = BYT_NGPIO_SUS,
117 .pins = sus_pins, 121 .pins = sus_pins,
118 }, 122 },
@@ -145,9 +149,41 @@ static void __iomem *byt_gpio_reg(struct gpio_chip *chip, unsigned offset,
145 return vg->reg_base + reg_offset + reg; 149 return vg->reg_base + reg_offset + reg;
146} 150}
147 151
152static bool is_special_pin(struct byt_gpio *vg, unsigned offset)
153{
154 /* SCORE pin 92-93 */
155 if (!strcmp(vg->range->name, BYT_SCORE_ACPI_UID) &&
156 offset >= 92 && offset <= 93)
157 return true;
158
159 /* SUS pin 11-21 */
160 if (!strcmp(vg->range->name, BYT_SUS_ACPI_UID) &&
161 offset >= 11 && offset <= 21)
162 return true;
163
164 return false;
165}
166
148static int byt_gpio_request(struct gpio_chip *chip, unsigned offset) 167static int byt_gpio_request(struct gpio_chip *chip, unsigned offset)
149{ 168{
150 struct byt_gpio *vg = to_byt_gpio(chip); 169 struct byt_gpio *vg = to_byt_gpio(chip);
170 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_CONF0_REG);
171 u32 value;
172 bool special;
173
174 /*
175 * In most cases, func pin mux 000 means GPIO function.
176 * But, some pins may have func pin mux 001 represents
177 * GPIO function. Only allow user to export pin with
178 * func pin mux preset as GPIO function by BIOS/FW.
179 */
180 value = readl(reg) & BYT_PIN_MUX;
181 special = is_special_pin(vg, offset);
182 if ((special && value != 1) || (!special && value)) {
183 dev_err(&vg->pdev->dev,
184 "pin %u cannot be used as GPIO.\n", offset);
185 return -EINVAL;
186 }
151 187
152 pm_runtime_get(&vg->pdev->dev); 188 pm_runtime_get(&vg->pdev->dev);
153 189
diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index 155b1b3a0e7a..07c81306f2f3 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -1042,6 +1042,88 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
1042 }, 1042 },
1043}; 1043};
1044 1044
1045/* pin banks of exynos5260 pin-controller 0 */
1046static struct samsung_pin_bank exynos5260_pin_banks0[] = {
1047 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00),
1048 EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04),
1049 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
1050 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
1051 EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10),
1052 EXYNOS_PIN_BANK_EINTG(5, 0x0a0, "gpb2", 0x14),
1053 EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpb3", 0x18),
1054 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpb4", 0x1c),
1055 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20),
1056 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24),
1057 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28),
1058 EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c),
1059 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30),
1060 EXYNOS_PIN_BANK_EINTG(5, 0x1a0, "gpe1", 0x34),
1061 EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38),
1062 EXYNOS_PIN_BANK_EINTG(8, 0x1e0, "gpf1", 0x3c),
1063 EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40),
1064 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
1065 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
1066 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
1067 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
1068};
1069
1070/* pin banks of exynos5260 pin-controller 1 */
1071static struct samsung_pin_bank exynos5260_pin_banks1[] = {
1072 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00),
1073 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04),
1074 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
1075 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
1076 EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10),
1077};
1078
1079/* pin banks of exynos5260 pin-controller 2 */
1080static struct samsung_pin_bank exynos5260_pin_banks2[] = {
1081 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
1082 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
1083};
1084
1085/*
1086 * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes
1087 * three gpio/pin-mux/pinconfig controllers.
1088 */
1089struct samsung_pin_ctrl exynos5260_pin_ctrl[] = {
1090 {
1091 /* pin-controller instance 0 data */
1092 .pin_banks = exynos5260_pin_banks0,
1093 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks0),
1094 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1095 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1096 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1097 .weint_con = EXYNOS_WKUP_ECON_OFFSET,
1098 .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
1099 .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
1100 .svc = EXYNOS_SVC_OFFSET,
1101 .eint_gpio_init = exynos_eint_gpio_init,
1102 .eint_wkup_init = exynos_eint_wkup_init,
1103 .label = "exynos5260-gpio-ctrl0",
1104 }, {
1105 /* pin-controller instance 1 data */
1106 .pin_banks = exynos5260_pin_banks1,
1107 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks1),
1108 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1109 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1110 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1111 .svc = EXYNOS_SVC_OFFSET,
1112 .eint_gpio_init = exynos_eint_gpio_init,
1113 .label = "exynos5260-gpio-ctrl1",
1114 }, {
1115 /* pin-controller instance 2 data */
1116 .pin_banks = exynos5260_pin_banks2,
1117 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks2),
1118 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1119 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1120 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1121 .svc = EXYNOS_SVC_OFFSET,
1122 .eint_gpio_init = exynos_eint_gpio_init,
1123 .label = "exynos5260-gpio-ctrl2",
1124 },
1125};
1126
1045/* pin banks of exynos5420 pin-controller 0 */ 1127/* pin banks of exynos5420 pin-controller 0 */
1046static struct samsung_pin_bank exynos5420_pin_banks0[] = { 1128static struct samsung_pin_bank exynos5420_pin_banks0[] = {
1047 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00), 1129 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00),
diff --git a/drivers/pinctrl/pinctrl-imx.c b/drivers/pinctrl/pinctrl-imx.c
index 4779b8e0eee8..e118fb121e02 100644
--- a/drivers/pinctrl/pinctrl-imx.c
+++ b/drivers/pinctrl/pinctrl-imx.c
@@ -491,7 +491,7 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
491 pin->mux_mode |= IOMUXC_CONFIG_SION; 491 pin->mux_mode |= IOMUXC_CONFIG_SION;
492 pin->config = config & ~IMX_PAD_SION; 492 pin->config = config & ~IMX_PAD_SION;
493 493
494 dev_dbg(info->dev, "%s: %d 0x%08lx", info->pins[i].name, 494 dev_dbg(info->dev, "%s: %d 0x%08lx", info->pins[pin_id].name,
495 pin->mux_mode, pin->config); 495 pin->mux_mode, pin->config);
496 } 496 }
497 497
diff --git a/drivers/pinctrl/pinctrl-msm.c b/drivers/pinctrl/pinctrl-msm.c
index ef2bf3126da6..343f421c7696 100644
--- a/drivers/pinctrl/pinctrl-msm.c
+++ b/drivers/pinctrl/pinctrl-msm.c
@@ -28,7 +28,6 @@
28#include <linux/interrupt.h> 28#include <linux/interrupt.h>
29#include <linux/irq.h> 29#include <linux/irq.h>
30#include <linux/irqchip/chained_irq.h> 30#include <linux/irqchip/chained_irq.h>
31#include <linux/of_irq.h>
32#include <linux/spinlock.h> 31#include <linux/spinlock.h>
33 32
34#include "core.h" 33#include "core.h"
@@ -50,7 +49,6 @@
50 * @enabled_irqs: Bitmap of currently enabled irqs. 49 * @enabled_irqs: Bitmap of currently enabled irqs.
51 * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge 50 * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
52 * detection. 51 * detection.
53 * @wake_irqs: Bitmap of irqs with requested as wakeup source.
54 * @soc; Reference to soc_data of platform specific data. 52 * @soc; Reference to soc_data of platform specific data.
55 * @regs: Base address for the TLMM register map. 53 * @regs: Base address for the TLMM register map.
56 */ 54 */
@@ -65,7 +63,6 @@ struct msm_pinctrl {
65 63
66 DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO); 64 DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
67 DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO); 65 DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
68 DECLARE_BITMAP(wake_irqs, MAX_NR_GPIO);
69 66
70 const struct msm_pinctrl_soc_data *soc; 67 const struct msm_pinctrl_soc_data *soc;
71 void __iomem *regs; 68 void __iomem *regs;
@@ -203,42 +200,29 @@ static const struct pinmux_ops msm_pinmux_ops = {
203static int msm_config_reg(struct msm_pinctrl *pctrl, 200static int msm_config_reg(struct msm_pinctrl *pctrl,
204 const struct msm_pingroup *g, 201 const struct msm_pingroup *g,
205 unsigned param, 202 unsigned param,
206 s16 *reg,
207 unsigned *mask, 203 unsigned *mask,
208 unsigned *bit) 204 unsigned *bit)
209{ 205{
210 switch (param) { 206 switch (param) {
211 case PIN_CONFIG_BIAS_DISABLE: 207 case PIN_CONFIG_BIAS_DISABLE:
212 *reg = g->ctl_reg;
213 *bit = g->pull_bit;
214 *mask = 3;
215 break;
216 case PIN_CONFIG_BIAS_PULL_DOWN: 208 case PIN_CONFIG_BIAS_PULL_DOWN:
217 *reg = g->ctl_reg;
218 *bit = g->pull_bit;
219 *mask = 3;
220 break;
221 case PIN_CONFIG_BIAS_PULL_UP: 209 case PIN_CONFIG_BIAS_PULL_UP:
222 *reg = g->ctl_reg;
223 *bit = g->pull_bit; 210 *bit = g->pull_bit;
224 *mask = 3; 211 *mask = 3;
225 break; 212 break;
226 case PIN_CONFIG_DRIVE_STRENGTH: 213 case PIN_CONFIG_DRIVE_STRENGTH:
227 *reg = g->ctl_reg;
228 *bit = g->drv_bit; 214 *bit = g->drv_bit;
229 *mask = 7; 215 *mask = 7;
230 break; 216 break;
217 case PIN_CONFIG_OUTPUT:
218 *bit = g->oe_bit;
219 *mask = 1;
220 break;
231 default: 221 default:
232 dev_err(pctrl->dev, "Invalid config param %04x\n", param); 222 dev_err(pctrl->dev, "Invalid config param %04x\n", param);
233 return -ENOTSUPP; 223 return -ENOTSUPP;
234 } 224 }
235 225
236 if (*reg < 0) {
237 dev_err(pctrl->dev, "Config param %04x not supported on group %s\n",
238 param, g->name);
239 return -ENOTSUPP;
240 }
241
242 return 0; 226 return 0;
243} 227}
244 228
@@ -261,8 +245,10 @@ static int msm_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
261#define MSM_PULL_DOWN 1 245#define MSM_PULL_DOWN 1
262#define MSM_PULL_UP 3 246#define MSM_PULL_UP 3
263 247
264static const unsigned msm_regval_to_drive[] = { 2, 4, 6, 8, 10, 12, 14, 16 }; 248static unsigned msm_regval_to_drive(u32 val)
265static const unsigned msm_drive_to_regval[] = { -1, -1, 0, -1, 1, -1, 2, -1, 3, -1, 4, -1, 5, -1, 6, -1, 7 }; 249{
250 return (val + 1) * 2;
251}
266 252
267static int msm_config_group_get(struct pinctrl_dev *pctldev, 253static int msm_config_group_get(struct pinctrl_dev *pctldev,
268 unsigned int group, 254 unsigned int group,
@@ -274,17 +260,16 @@ static int msm_config_group_get(struct pinctrl_dev *pctldev,
274 unsigned mask; 260 unsigned mask;
275 unsigned arg; 261 unsigned arg;
276 unsigned bit; 262 unsigned bit;
277 s16 reg;
278 int ret; 263 int ret;
279 u32 val; 264 u32 val;
280 265
281 g = &pctrl->soc->groups[group]; 266 g = &pctrl->soc->groups[group];
282 267
283 ret = msm_config_reg(pctrl, g, param, &reg, &mask, &bit); 268 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
284 if (ret < 0) 269 if (ret < 0)
285 return ret; 270 return ret;
286 271
287 val = readl(pctrl->regs + reg); 272 val = readl(pctrl->regs + g->ctl_reg);
288 arg = (val >> bit) & mask; 273 arg = (val >> bit) & mask;
289 274
290 /* Convert register value to pinconf value */ 275 /* Convert register value to pinconf value */
@@ -299,7 +284,15 @@ static int msm_config_group_get(struct pinctrl_dev *pctldev,
299 arg = arg == MSM_PULL_UP; 284 arg = arg == MSM_PULL_UP;
300 break; 285 break;
301 case PIN_CONFIG_DRIVE_STRENGTH: 286 case PIN_CONFIG_DRIVE_STRENGTH:
302 arg = msm_regval_to_drive[arg]; 287 arg = msm_regval_to_drive(arg);
288 break;
289 case PIN_CONFIG_OUTPUT:
290 /* Pin is not output */
291 if (!arg)
292 return -EINVAL;
293
294 val = readl(pctrl->regs + g->io_reg);
295 arg = !!(val & BIT(g->in_bit));
303 break; 296 break;
304 default: 297 default:
305 dev_err(pctrl->dev, "Unsupported config parameter: %x\n", 298 dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
@@ -324,7 +317,6 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev,
324 unsigned mask; 317 unsigned mask;
325 unsigned arg; 318 unsigned arg;
326 unsigned bit; 319 unsigned bit;
327 s16 reg;
328 int ret; 320 int ret;
329 u32 val; 321 u32 val;
330 int i; 322 int i;
@@ -335,7 +327,7 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev,
335 param = pinconf_to_config_param(configs[i]); 327 param = pinconf_to_config_param(configs[i]);
336 arg = pinconf_to_config_argument(configs[i]); 328 arg = pinconf_to_config_argument(configs[i]);
337 329
338 ret = msm_config_reg(pctrl, g, param, &reg, &mask, &bit); 330 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
339 if (ret < 0) 331 if (ret < 0)
340 return ret; 332 return ret;
341 333
@@ -352,10 +344,24 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev,
352 break; 344 break;
353 case PIN_CONFIG_DRIVE_STRENGTH: 345 case PIN_CONFIG_DRIVE_STRENGTH:
354 /* Check for invalid values */ 346 /* Check for invalid values */
355 if (arg >= ARRAY_SIZE(msm_drive_to_regval)) 347 if (arg > 16 || arg < 2 || (arg % 2) != 0)
356 arg = -1; 348 arg = -1;
357 else 349 else
358 arg = msm_drive_to_regval[arg]; 350 arg = (arg / 2) - 1;
351 break;
352 case PIN_CONFIG_OUTPUT:
353 /* set output value */
354 spin_lock_irqsave(&pctrl->lock, flags);
355 val = readl(pctrl->regs + g->io_reg);
356 if (arg)
357 val |= BIT(g->out_bit);
358 else
359 val &= ~BIT(g->out_bit);
360 writel(val, pctrl->regs + g->io_reg);
361 spin_unlock_irqrestore(&pctrl->lock, flags);
362
363 /* enable output */
364 arg = 1;
359 break; 365 break;
360 default: 366 default:
361 dev_err(pctrl->dev, "Unsupported config parameter: %x\n", 367 dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
@@ -370,10 +376,10 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev,
370 } 376 }
371 377
372 spin_lock_irqsave(&pctrl->lock, flags); 378 spin_lock_irqsave(&pctrl->lock, flags);
373 val = readl(pctrl->regs + reg); 379 val = readl(pctrl->regs + g->ctl_reg);
374 val &= ~(mask << bit); 380 val &= ~(mask << bit);
375 val |= arg << bit; 381 val |= arg << bit;
376 writel(val, pctrl->regs + reg); 382 writel(val, pctrl->regs + g->ctl_reg);
377 spin_unlock_irqrestore(&pctrl->lock, flags); 383 spin_unlock_irqrestore(&pctrl->lock, flags);
378 } 384 }
379 385
@@ -402,8 +408,6 @@ static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
402 u32 val; 408 u32 val;
403 409
404 g = &pctrl->soc->groups[offset]; 410 g = &pctrl->soc->groups[offset];
405 if (WARN_ON(g->io_reg < 0))
406 return -EINVAL;
407 411
408 spin_lock_irqsave(&pctrl->lock, flags); 412 spin_lock_irqsave(&pctrl->lock, flags);
409 413
@@ -424,8 +428,6 @@ static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, in
424 u32 val; 428 u32 val;
425 429
426 g = &pctrl->soc->groups[offset]; 430 g = &pctrl->soc->groups[offset];
427 if (WARN_ON(g->io_reg < 0))
428 return -EINVAL;
429 431
430 spin_lock_irqsave(&pctrl->lock, flags); 432 spin_lock_irqsave(&pctrl->lock, flags);
431 433
@@ -452,8 +454,6 @@ static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
452 u32 val; 454 u32 val;
453 455
454 g = &pctrl->soc->groups[offset]; 456 g = &pctrl->soc->groups[offset];
455 if (WARN_ON(g->io_reg < 0))
456 return -EINVAL;
457 457
458 val = readl(pctrl->regs + g->io_reg); 458 val = readl(pctrl->regs + g->io_reg);
459 return !!(val & BIT(g->in_bit)); 459 return !!(val & BIT(g->in_bit));
@@ -467,8 +467,6 @@ static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
467 u32 val; 467 u32 val;
468 468
469 g = &pctrl->soc->groups[offset]; 469 g = &pctrl->soc->groups[offset];
470 if (WARN_ON(g->io_reg < 0))
471 return;
472 470
473 spin_lock_irqsave(&pctrl->lock, flags); 471 spin_lock_irqsave(&pctrl->lock, flags);
474 472
@@ -534,7 +532,7 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
534 pull = (ctl_reg >> g->pull_bit) & 3; 532 pull = (ctl_reg >> g->pull_bit) & 3;
535 533
536 seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func); 534 seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
537 seq_printf(s, " %dmA", msm_regval_to_drive[drive]); 535 seq_printf(s, " %dmA", msm_regval_to_drive(drive));
538 seq_printf(s, " %s", pulls[pull]); 536 seq_printf(s, " %s", pulls[pull]);
539} 537}
540 538
@@ -617,8 +615,6 @@ static void msm_gpio_irq_mask(struct irq_data *d)
617 615
618 pctrl = irq_data_get_irq_chip_data(d); 616 pctrl = irq_data_get_irq_chip_data(d);
619 g = &pctrl->soc->groups[d->hwirq]; 617 g = &pctrl->soc->groups[d->hwirq];
620 if (WARN_ON(g->intr_cfg_reg < 0))
621 return;
622 618
623 spin_lock_irqsave(&pctrl->lock, flags); 619 spin_lock_irqsave(&pctrl->lock, flags);
624 620
@@ -640,8 +636,6 @@ static void msm_gpio_irq_unmask(struct irq_data *d)
640 636
641 pctrl = irq_data_get_irq_chip_data(d); 637 pctrl = irq_data_get_irq_chip_data(d);
642 g = &pctrl->soc->groups[d->hwirq]; 638 g = &pctrl->soc->groups[d->hwirq];
643 if (WARN_ON(g->intr_status_reg < 0))
644 return;
645 639
646 spin_lock_irqsave(&pctrl->lock, flags); 640 spin_lock_irqsave(&pctrl->lock, flags);
647 641
@@ -667,8 +661,6 @@ static void msm_gpio_irq_ack(struct irq_data *d)
667 661
668 pctrl = irq_data_get_irq_chip_data(d); 662 pctrl = irq_data_get_irq_chip_data(d);
669 g = &pctrl->soc->groups[d->hwirq]; 663 g = &pctrl->soc->groups[d->hwirq];
670 if (WARN_ON(g->intr_status_reg < 0))
671 return;
672 664
673 spin_lock_irqsave(&pctrl->lock, flags); 665 spin_lock_irqsave(&pctrl->lock, flags);
674 666
@@ -693,8 +685,6 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
693 685
694 pctrl = irq_data_get_irq_chip_data(d); 686 pctrl = irq_data_get_irq_chip_data(d);
695 g = &pctrl->soc->groups[d->hwirq]; 687 g = &pctrl->soc->groups[d->hwirq];
696 if (WARN_ON(g->intr_cfg_reg < 0))
697 return -EINVAL;
698 688
699 spin_lock_irqsave(&pctrl->lock, flags); 689 spin_lock_irqsave(&pctrl->lock, flags);
700 690
@@ -783,22 +773,12 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
783{ 773{
784 struct msm_pinctrl *pctrl; 774 struct msm_pinctrl *pctrl;
785 unsigned long flags; 775 unsigned long flags;
786 unsigned ngpio;
787 776
788 pctrl = irq_data_get_irq_chip_data(d); 777 pctrl = irq_data_get_irq_chip_data(d);
789 ngpio = pctrl->chip.ngpio;
790 778
791 spin_lock_irqsave(&pctrl->lock, flags); 779 spin_lock_irqsave(&pctrl->lock, flags);
792 780
793 if (on) { 781 irq_set_irq_wake(pctrl->irq, on);
794 if (bitmap_empty(pctrl->wake_irqs, ngpio))
795 enable_irq_wake(pctrl->irq);
796 set_bit(d->hwirq, pctrl->wake_irqs);
797 } else {
798 clear_bit(d->hwirq, pctrl->wake_irqs);
799 if (bitmap_empty(pctrl->wake_irqs, ngpio))
800 disable_irq_wake(pctrl->irq);
801 }
802 782
803 spin_unlock_irqrestore(&pctrl->lock, flags); 783 spin_unlock_irqrestore(&pctrl->lock, flags);
804 784
@@ -869,6 +849,12 @@ static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
869 chained_irq_exit(chip, desc); 849 chained_irq_exit(chip, desc);
870} 850}
871 851
852/*
853 * This lock class tells lockdep that GPIO irqs are in a different
854 * category than their parents, so it won't report false recursion.
855 */
856static struct lock_class_key gpio_lock_class;
857
872static int msm_gpio_init(struct msm_pinctrl *pctrl) 858static int msm_gpio_init(struct msm_pinctrl *pctrl)
873{ 859{
874 struct gpio_chip *chip; 860 struct gpio_chip *chip;
@@ -876,10 +862,14 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
876 int ret; 862 int ret;
877 int i; 863 int i;
878 int r; 864 int r;
865 unsigned ngpio = pctrl->soc->ngpios;
866
867 if (WARN_ON(ngpio > MAX_NR_GPIO))
868 return -EINVAL;
879 869
880 chip = &pctrl->chip; 870 chip = &pctrl->chip;
881 chip->base = 0; 871 chip->base = 0;
882 chip->ngpio = pctrl->soc->ngpios; 872 chip->ngpio = ngpio;
883 chip->label = dev_name(pctrl->dev); 873 chip->label = dev_name(pctrl->dev);
884 chip->dev = pctrl->dev; 874 chip->dev = pctrl->dev;
885 chip->owner = THIS_MODULE; 875 chip->owner = THIS_MODULE;
@@ -907,6 +897,7 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
907 897
908 for (i = 0; i < chip->ngpio; i++) { 898 for (i = 0; i < chip->ngpio; i++) {
909 irq = irq_create_mapping(pctrl->domain, i); 899 irq = irq_create_mapping(pctrl->domain, i);
900 irq_set_lockdep_class(irq, &gpio_lock_class);
910 irq_set_chip_and_handler(irq, &msm_gpio_irq_chip, handle_edge_irq); 901 irq_set_chip_and_handler(irq, &msm_gpio_irq_chip, handle_edge_irq);
911 irq_set_chip_data(irq, pctrl); 902 irq_set_chip_data(irq, pctrl);
912 } 903 }
diff --git a/drivers/pinctrl/pinctrl-msm.h b/drivers/pinctrl/pinctrl-msm.h
index 206e782e2daa..8fbe9fb19f36 100644
--- a/drivers/pinctrl/pinctrl-msm.h
+++ b/drivers/pinctrl/pinctrl-msm.h
@@ -13,10 +13,7 @@
13#ifndef __PINCTRL_MSM_H__ 13#ifndef __PINCTRL_MSM_H__
14#define __PINCTRL_MSM_H__ 14#define __PINCTRL_MSM_H__
15 15
16#include <linux/pinctrl/pinctrl.h> 16struct pinctrl_pin_desc;
17#include <linux/pinctrl/pinmux.h>
18#include <linux/pinctrl/pinconf.h>
19#include <linux/pinctrl/machine.h>
20 17
21/** 18/**
22 * struct msm_function - a pinmux function 19 * struct msm_function - a pinmux function
diff --git a/drivers/pinctrl/pinctrl-msm8x74.c b/drivers/pinctrl/pinctrl-msm8x74.c
index f944bf2172ef..dde5529807aa 100644
--- a/drivers/pinctrl/pinctrl-msm8x74.c
+++ b/drivers/pinctrl/pinctrl-msm8x74.c
@@ -15,7 +15,6 @@
15#include <linux/of.h> 15#include <linux/of.h>
16#include <linux/platform_device.h> 16#include <linux/platform_device.h>
17#include <linux/pinctrl/pinctrl.h> 17#include <linux/pinctrl/pinctrl.h>
18#include <linux/pinctrl/pinmux.h>
19 18
20#include "pinctrl-msm.h" 19#include "pinctrl-msm.h"
21 20
@@ -406,6 +405,7 @@ enum msm8x74_functions {
406 MSM_MUX_blsp_i2c6, 405 MSM_MUX_blsp_i2c6,
407 MSM_MUX_blsp_i2c11, 406 MSM_MUX_blsp_i2c11,
408 MSM_MUX_blsp_spi1, 407 MSM_MUX_blsp_spi1,
408 MSM_MUX_blsp_spi8,
409 MSM_MUX_blsp_uart2, 409 MSM_MUX_blsp_uart2,
410 MSM_MUX_blsp_uart8, 410 MSM_MUX_blsp_uart8,
411 MSM_MUX_slimbus, 411 MSM_MUX_slimbus,
@@ -416,6 +416,9 @@ static const char * const blsp_i2c2_groups[] = { "gpio6", "gpio7" };
416static const char * const blsp_i2c6_groups[] = { "gpio29", "gpio30" }; 416static const char * const blsp_i2c6_groups[] = { "gpio29", "gpio30" };
417static const char * const blsp_i2c11_groups[] = { "gpio83", "gpio84" }; 417static const char * const blsp_i2c11_groups[] = { "gpio83", "gpio84" };
418static const char * const blsp_spi1_groups[] = { "gpio0", "gpio1", "gpio2", "gpio3" }; 418static const char * const blsp_spi1_groups[] = { "gpio0", "gpio1", "gpio2", "gpio3" };
419static const char * const blsp_spi8_groups[] = {
420 "gpio45", "gpio46", "gpio47", "gpio48"
421};
419static const char * const blsp_uart2_groups[] = { "gpio4", "gpio5" }; 422static const char * const blsp_uart2_groups[] = { "gpio4", "gpio5" };
420static const char * const blsp_uart8_groups[] = { "gpio45", "gpio46" }; 423static const char * const blsp_uart8_groups[] = { "gpio45", "gpio46" };
421static const char * const slimbus_groups[] = { "gpio70", "gpio71" }; 424static const char * const slimbus_groups[] = { "gpio70", "gpio71" };
@@ -425,6 +428,7 @@ static const struct msm_function msm8x74_functions[] = {
425 FUNCTION(blsp_i2c6), 428 FUNCTION(blsp_i2c6),
426 FUNCTION(blsp_i2c11), 429 FUNCTION(blsp_i2c11),
427 FUNCTION(blsp_spi1), 430 FUNCTION(blsp_spi1),
431 FUNCTION(blsp_spi8),
428 FUNCTION(blsp_uart2), 432 FUNCTION(blsp_uart2),
429 FUNCTION(blsp_uart8), 433 FUNCTION(blsp_uart8),
430 FUNCTION(slimbus), 434 FUNCTION(slimbus),
@@ -476,10 +480,10 @@ static const struct msm_pingroup msm8x74_groups[] = {
476 PINGROUP(42, NA, NA, NA, NA, NA, NA, NA), 480 PINGROUP(42, NA, NA, NA, NA, NA, NA, NA),
477 PINGROUP(43, NA, NA, NA, NA, NA, NA, NA), 481 PINGROUP(43, NA, NA, NA, NA, NA, NA, NA),
478 PINGROUP(44, NA, NA, NA, NA, NA, NA, NA), 482 PINGROUP(44, NA, NA, NA, NA, NA, NA, NA),
479 PINGROUP(45, NA, blsp_uart8, NA, NA, NA, NA, NA), 483 PINGROUP(45, blsp_spi8, blsp_uart8, NA, NA, NA, NA, NA),
480 PINGROUP(46, NA, blsp_uart8, NA, NA, NA, NA, NA), 484 PINGROUP(46, blsp_spi8, blsp_uart8, NA, NA, NA, NA, NA),
481 PINGROUP(47, NA, NA, NA, NA, NA, NA, NA), 485 PINGROUP(47, blsp_spi8, NA, NA, NA, NA, NA, NA),
482 PINGROUP(48, NA, NA, NA, NA, NA, NA, NA), 486 PINGROUP(48, blsp_spi8, NA, NA, NA, NA, NA, NA),
483 PINGROUP(49, NA, NA, NA, NA, NA, NA, NA), 487 PINGROUP(49, NA, NA, NA, NA, NA, NA, NA),
484 PINGROUP(50, NA, NA, NA, NA, NA, NA, NA), 488 PINGROUP(50, NA, NA, NA, NA, NA, NA, NA),
485 PINGROUP(51, NA, NA, NA, NA, NA, NA, NA), 489 PINGROUP(51, NA, NA, NA, NA, NA, NA, NA),
diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c
index 53a11114927f..cec7762cf335 100644
--- a/drivers/pinctrl/pinctrl-nomadik.c
+++ b/drivers/pinctrl/pinctrl-nomadik.c
@@ -2035,27 +2035,29 @@ static const struct of_device_id nmk_pinctrl_match[] = {
2035 {}, 2035 {},
2036}; 2036};
2037 2037
2038static int nmk_pinctrl_suspend(struct platform_device *pdev, pm_message_t state) 2038#ifdef CONFIG_PM_SLEEP
2039static int nmk_pinctrl_suspend(struct device *dev)
2039{ 2040{
2040 struct nmk_pinctrl *npct; 2041 struct nmk_pinctrl *npct;
2041 2042
2042 npct = platform_get_drvdata(pdev); 2043 npct = dev_get_drvdata(dev);
2043 if (!npct) 2044 if (!npct)
2044 return -EINVAL; 2045 return -EINVAL;
2045 2046
2046 return pinctrl_force_sleep(npct->pctl); 2047 return pinctrl_force_sleep(npct->pctl);
2047} 2048}
2048 2049
2049static int nmk_pinctrl_resume(struct platform_device *pdev) 2050static int nmk_pinctrl_resume(struct device *dev)
2050{ 2051{
2051 struct nmk_pinctrl *npct; 2052 struct nmk_pinctrl *npct;
2052 2053
2053 npct = platform_get_drvdata(pdev); 2054 npct = dev_get_drvdata(dev);
2054 if (!npct) 2055 if (!npct)
2055 return -EINVAL; 2056 return -EINVAL;
2056 2057
2057 return pinctrl_force_default(npct->pctl); 2058 return pinctrl_force_default(npct->pctl);
2058} 2059}
2060#endif
2059 2061
2060static int nmk_pinctrl_probe(struct platform_device *pdev) 2062static int nmk_pinctrl_probe(struct platform_device *pdev)
2061{ 2063{
@@ -2144,17 +2146,18 @@ static struct platform_driver nmk_gpio_driver = {
2144 .probe = nmk_gpio_probe, 2146 .probe = nmk_gpio_probe,
2145}; 2147};
2146 2148
2149static SIMPLE_DEV_PM_OPS(nmk_pinctrl_pm_ops,
2150 nmk_pinctrl_suspend,
2151 nmk_pinctrl_resume);
2152
2147static struct platform_driver nmk_pinctrl_driver = { 2153static struct platform_driver nmk_pinctrl_driver = {
2148 .driver = { 2154 .driver = {
2149 .owner = THIS_MODULE, 2155 .owner = THIS_MODULE,
2150 .name = "pinctrl-nomadik", 2156 .name = "pinctrl-nomadik",
2151 .of_match_table = nmk_pinctrl_match, 2157 .of_match_table = nmk_pinctrl_match,
2158 .pm = &nmk_pinctrl_pm_ops,
2152 }, 2159 },
2153 .probe = nmk_pinctrl_probe, 2160 .probe = nmk_pinctrl_probe,
2154#ifdef CONFIG_PM
2155 .suspend = nmk_pinctrl_suspend,
2156 .resume = nmk_pinctrl_resume,
2157#endif
2158}; 2161};
2159 2162
2160static int __init nmk_gpio_init(void) 2163static int __init nmk_gpio_init(void)
diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c
index 47ec2e8741e4..0324d4cb19b2 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -1120,6 +1120,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
1120 .data = (void *)exynos4x12_pin_ctrl }, 1120 .data = (void *)exynos4x12_pin_ctrl },
1121 { .compatible = "samsung,exynos5250-pinctrl", 1121 { .compatible = "samsung,exynos5250-pinctrl",
1122 .data = (void *)exynos5250_pin_ctrl }, 1122 .data = (void *)exynos5250_pin_ctrl },
1123 { .compatible = "samsung,exynos5260-pinctrl",
1124 .data = (void *)exynos5260_pin_ctrl },
1123 { .compatible = "samsung,exynos5420-pinctrl", 1125 { .compatible = "samsung,exynos5420-pinctrl",
1124 .data = (void *)exynos5420_pin_ctrl }, 1126 .data = (void *)exynos5420_pin_ctrl },
1125 { .compatible = "samsung,s5pv210-pinctrl", 1127 { .compatible = "samsung,s5pv210-pinctrl",
diff --git a/drivers/pinctrl/pinctrl-samsung.h b/drivers/pinctrl/pinctrl-samsung.h
index 30622d9afa2e..bab9c2122556 100644
--- a/drivers/pinctrl/pinctrl-samsung.h
+++ b/drivers/pinctrl/pinctrl-samsung.h
@@ -254,6 +254,7 @@ struct samsung_pmx_func {
254extern struct samsung_pin_ctrl exynos4210_pin_ctrl[]; 254extern struct samsung_pin_ctrl exynos4210_pin_ctrl[];
255extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[]; 255extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[];
256extern struct samsung_pin_ctrl exynos5250_pin_ctrl[]; 256extern struct samsung_pin_ctrl exynos5250_pin_ctrl[];
257extern struct samsung_pin_ctrl exynos5260_pin_ctrl[];
257extern struct samsung_pin_ctrl exynos5420_pin_ctrl[]; 258extern struct samsung_pin_ctrl exynos5420_pin_ctrl[];
258extern struct samsung_pin_ctrl s3c64xx_pin_ctrl[]; 259extern struct samsung_pin_ctrl s3c64xx_pin_ctrl[];
259extern struct samsung_pin_ctrl s3c2412_pin_ctrl[]; 260extern struct samsung_pin_ctrl s3c2412_pin_ctrl[];
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index de6459628b4f..81075f2a1d3f 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -662,6 +662,7 @@ static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
662 break; 662 break;
663 case PIN_CONFIG_DRIVE_STRENGTH: 663 case PIN_CONFIG_DRIVE_STRENGTH:
664 case PIN_CONFIG_SLEW_RATE: 664 case PIN_CONFIG_SLEW_RATE:
665 case PIN_CONFIG_LOW_POWER_MODE:
665 default: 666 default:
666 *config = data; 667 *config = data;
667 break; 668 break;
@@ -699,6 +700,7 @@ static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
699 case PIN_CONFIG_INPUT_SCHMITT: 700 case PIN_CONFIG_INPUT_SCHMITT:
700 case PIN_CONFIG_DRIVE_STRENGTH: 701 case PIN_CONFIG_DRIVE_STRENGTH:
701 case PIN_CONFIG_SLEW_RATE: 702 case PIN_CONFIG_SLEW_RATE:
703 case PIN_CONFIG_LOW_POWER_MODE:
702 shift = ffs(func->conf[i].mask) - 1; 704 shift = ffs(func->conf[i].mask) - 1;
703 data &= ~func->conf[i].mask; 705 data &= ~func->conf[i].mask;
704 data |= (arg << shift) & func->conf[i].mask; 706 data |= (arg << shift) & func->conf[i].mask;
@@ -1101,6 +1103,7 @@ static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
1101 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, }, 1103 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
1102 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, }, 1104 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
1103 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, }, 1105 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
1106 { "pinctrl-single,low-power-mode", PIN_CONFIG_LOW_POWER_MODE, },
1104 }; 1107 };
1105 struct pcs_conf_type prop4[] = { 1108 struct pcs_conf_type prop4[] = {
1106 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, }, 1109 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c
index 320c27363cc8..bd725b0a4341 100644
--- a/drivers/pinctrl/pinctrl-st.c
+++ b/drivers/pinctrl/pinctrl-st.c
@@ -13,7 +13,12 @@
13#include <linux/slab.h> 13#include <linux/slab.h>
14#include <linux/err.h> 14#include <linux/err.h>
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/irq.h>
17#include <linux/irqdesc.h>
18#include <linux/irqdomain.h>
19#include <linux/irqchip/chained_irq.h>
16#include <linux/of.h> 20#include <linux/of.h>
21#include <linux/of_irq.h>
17#include <linux/of_gpio.h> 22#include <linux/of_gpio.h>
18#include <linux/of_address.h> 23#include <linux/of_address.h>
19#include <linux/regmap.h> 24#include <linux/regmap.h>
@@ -266,11 +271,59 @@ struct st_pctl_group {
266 struct st_pinconf *pin_conf; 271 struct st_pinconf *pin_conf;
267}; 272};
268 273
274/*
275 * Edge triggers are not supported at hardware level, it is supported by
276 * software by exploiting the level trigger support in hardware.
277 * Software uses a virtual register (EDGE_CONF) for edge trigger configuration
278 * of each gpio pin in a GPIO bank.
279 *
280 * Each bank has a 32 bit EDGE_CONF register which is divided in to 8 parts of
281 * 4-bits. Each 4-bit space is allocated for each pin in a gpio bank.
282 *
283 * bit allocation per pin is:
284 * Bits: [0 - 3] | [4 - 7] [8 - 11] ... ... ... ... [ 28 - 31]
285 * --------------------------------------------------------
286 * | pin-0 | pin-2 | pin-3 | ... ... ... ... | pin -7 |
287 * --------------------------------------------------------
288 *
289 * A pin can have one of following the values in its edge configuration field.
290 *
291 * ------- ----------------------------
292 * [0-3] - Description
293 * ------- ----------------------------
294 * 0000 - No edge IRQ.
295 * 0001 - Falling edge IRQ.
296 * 0010 - Rising edge IRQ.
297 * 0011 - Rising and Falling edge IRQ.
298 * ------- ----------------------------
299 */
300
301#define ST_IRQ_EDGE_CONF_BITS_PER_PIN 4
302#define ST_IRQ_EDGE_MASK 0xf
303#define ST_IRQ_EDGE_FALLING BIT(0)
304#define ST_IRQ_EDGE_RISING BIT(1)
305#define ST_IRQ_EDGE_BOTH (BIT(0) | BIT(1))
306
307#define ST_IRQ_RISING_EDGE_CONF(pin) \
308 (ST_IRQ_EDGE_RISING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
309
310#define ST_IRQ_FALLING_EDGE_CONF(pin) \
311 (ST_IRQ_EDGE_FALLING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
312
313#define ST_IRQ_BOTH_EDGE_CONF(pin) \
314 (ST_IRQ_EDGE_BOTH << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
315
316#define ST_IRQ_EDGE_CONF(conf, pin) \
317 (conf >> (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN) & ST_IRQ_EDGE_MASK)
318
269struct st_gpio_bank { 319struct st_gpio_bank {
270 struct gpio_chip gpio_chip; 320 struct gpio_chip gpio_chip;
271 struct pinctrl_gpio_range range; 321 struct pinctrl_gpio_range range;
272 void __iomem *base; 322 void __iomem *base;
273 struct st_pio_control pc; 323 struct st_pio_control pc;
324 struct irq_domain *domain;
325 unsigned long irq_edge_conf;
326 spinlock_t lock;
274}; 327};
275 328
276struct st_pinctrl { 329struct st_pinctrl {
@@ -284,6 +337,7 @@ struct st_pinctrl {
284 int ngroups; 337 int ngroups;
285 struct regmap *regmap; 338 struct regmap *regmap;
286 const struct st_pctl_data *data; 339 const struct st_pctl_data *data;
340 void __iomem *irqmux_base;
287}; 341};
288 342
289/* SOC specific data */ 343/* SOC specific data */
@@ -330,12 +384,25 @@ static unsigned int stih416_delays[] = {0, 300, 500, 750, 1000, 1250, 1500,
330static const struct st_pctl_data stih416_data = { 384static const struct st_pctl_data stih416_data = {
331 .rt_style = st_retime_style_dedicated, 385 .rt_style = st_retime_style_dedicated,
332 .input_delays = stih416_delays, 386 .input_delays = stih416_delays,
333 .ninput_delays = 14, 387 .ninput_delays = ARRAY_SIZE(stih416_delays),
334 .output_delays = stih416_delays, 388 .output_delays = stih416_delays,
335 .noutput_delays = 14, 389 .noutput_delays = ARRAY_SIZE(stih416_delays),
336 .alt = 0, .oe = 40, .pu = 50, .od = 60, .rt = 100, 390 .alt = 0, .oe = 40, .pu = 50, .od = 60, .rt = 100,
337}; 391};
338 392
393static const struct st_pctl_data stih407_flashdata = {
394 .rt_style = st_retime_style_none,
395 .input_delays = stih416_delays,
396 .ninput_delays = ARRAY_SIZE(stih416_delays),
397 .output_delays = stih416_delays,
398 .noutput_delays = ARRAY_SIZE(stih416_delays),
399 .alt = 0,
400 .oe = -1, /* Not Available */
401 .pu = -1, /* Not Available */
402 .od = 60,
403 .rt = 100,
404};
405
339/* Low level functions.. */ 406/* Low level functions.. */
340static inline int st_gpio_bank(int gpio) 407static inline int st_gpio_bank(int gpio)
341{ 408{
@@ -356,25 +423,29 @@ static void st_pinconf_set_config(struct st_pio_control *pc,
356 unsigned int oe_value, pu_value, od_value; 423 unsigned int oe_value, pu_value, od_value;
357 unsigned long mask = BIT(pin); 424 unsigned long mask = BIT(pin);
358 425
359 regmap_field_read(output_enable, &oe_value); 426 if (output_enable) {
360 regmap_field_read(pull_up, &pu_value); 427 regmap_field_read(output_enable, &oe_value);
361 regmap_field_read(open_drain, &od_value); 428 oe_value &= ~mask;
362 429 if (config & ST_PINCONF_OE)
363 /* Clear old values */ 430 oe_value |= mask;
364 oe_value &= ~mask; 431 regmap_field_write(output_enable, oe_value);
365 pu_value &= ~mask; 432 }
366 od_value &= ~mask; 433
367 434 if (pull_up) {
368 if (config & ST_PINCONF_OE) 435 regmap_field_read(pull_up, &pu_value);
369 oe_value |= mask; 436 pu_value &= ~mask;
370 if (config & ST_PINCONF_PU) 437 if (config & ST_PINCONF_PU)
371 pu_value |= mask; 438 pu_value |= mask;
372 if (config & ST_PINCONF_OD) 439 regmap_field_write(pull_up, pu_value);
373 od_value |= mask; 440 }
374 441
375 regmap_field_write(output_enable, oe_value); 442 if (open_drain) {
376 regmap_field_write(pull_up, pu_value); 443 regmap_field_read(open_drain, &od_value);
377 regmap_field_write(open_drain, od_value); 444 od_value &= ~mask;
445 if (config & ST_PINCONF_OD)
446 od_value |= mask;
447 regmap_field_write(open_drain, od_value);
448 }
378} 449}
379 450
380static void st_pctl_set_function(struct st_pio_control *pc, 451static void st_pctl_set_function(struct st_pio_control *pc,
@@ -385,6 +456,9 @@ static void st_pctl_set_function(struct st_pio_control *pc,
385 int pin = st_gpio_pin(pin_id); 456 int pin = st_gpio_pin(pin_id);
386 int offset = pin * 4; 457 int offset = pin * 4;
387 458
459 if (!alt)
460 return;
461
388 regmap_field_read(alt, &val); 462 regmap_field_read(alt, &val);
389 val &= ~(0xf << offset); 463 val &= ~(0xf << offset);
390 val |= function << offset; 464 val |= function << offset;
@@ -522,17 +596,23 @@ static void st_pinconf_get_direction(struct st_pio_control *pc,
522{ 596{
523 unsigned int oe_value, pu_value, od_value; 597 unsigned int oe_value, pu_value, od_value;
524 598
525 regmap_field_read(pc->oe, &oe_value); 599 if (pc->oe) {
526 regmap_field_read(pc->pu, &pu_value); 600 regmap_field_read(pc->oe, &oe_value);
527 regmap_field_read(pc->od, &od_value); 601 if (oe_value & BIT(pin))
602 ST_PINCONF_PACK_OE(*config);
603 }
528 604
529 if (oe_value & BIT(pin)) 605 if (pc->pu) {
530 ST_PINCONF_PACK_OE(*config); 606 regmap_field_read(pc->pu, &pu_value);
531 if (pu_value & BIT(pin)) 607 if (pu_value & BIT(pin))
532 ST_PINCONF_PACK_PU(*config); 608 ST_PINCONF_PACK_PU(*config);
533 if (od_value & BIT(pin)) 609 }
534 ST_PINCONF_PACK_OD(*config);
535 610
611 if (pc->od) {
612 regmap_field_read(pc->od, &od_value);
613 if (od_value & BIT(pin))
614 ST_PINCONF_PACK_OD(*config);
615 }
536} 616}
537 617
538static int st_pinconf_get_retime_packed(struct st_pinctrl *info, 618static int st_pinconf_get_retime_packed(struct st_pinctrl *info,
@@ -1051,8 +1131,21 @@ static int st_pctl_dt_setup_retime(struct st_pinctrl *info,
1051 return -EINVAL; 1131 return -EINVAL;
1052} 1132}
1053 1133
1054static int st_parse_syscfgs(struct st_pinctrl *info, 1134
1055 int bank, struct device_node *np) 1135static struct regmap_field *st_pc_get_value(struct device *dev,
1136 struct regmap *regmap, int bank,
1137 int data, int lsb, int msb)
1138{
1139 struct reg_field reg = REG_FIELD((data + bank) * 4, lsb, msb);
1140
1141 if (data < 0)
1142 return NULL;
1143
1144 return devm_regmap_field_alloc(dev, regmap, reg);
1145}
1146
1147static void st_parse_syscfgs(struct st_pinctrl *info, int bank,
1148 struct device_node *np)
1056{ 1149{
1057 const struct st_pctl_data *data = info->data; 1150 const struct st_pctl_data *data = info->data;
1058 /** 1151 /**
@@ -1062,29 +1155,21 @@ static int st_parse_syscfgs(struct st_pinctrl *info,
1062 */ 1155 */
1063 int lsb = (bank%4) * ST_GPIO_PINS_PER_BANK; 1156 int lsb = (bank%4) * ST_GPIO_PINS_PER_BANK;
1064 int msb = lsb + ST_GPIO_PINS_PER_BANK - 1; 1157 int msb = lsb + ST_GPIO_PINS_PER_BANK - 1;
1065 struct reg_field alt_reg = REG_FIELD((data->alt + bank) * 4, 0, 31);
1066 struct reg_field oe_reg = REG_FIELD((data->oe + bank/4) * 4, lsb, msb);
1067 struct reg_field pu_reg = REG_FIELD((data->pu + bank/4) * 4, lsb, msb);
1068 struct reg_field od_reg = REG_FIELD((data->od + bank/4) * 4, lsb, msb);
1069 struct st_pio_control *pc = &info->banks[bank].pc; 1158 struct st_pio_control *pc = &info->banks[bank].pc;
1070 struct device *dev = info->dev; 1159 struct device *dev = info->dev;
1071 struct regmap *regmap = info->regmap; 1160 struct regmap *regmap = info->regmap;
1072 1161
1073 pc->alt = devm_regmap_field_alloc(dev, regmap, alt_reg); 1162 pc->alt = st_pc_get_value(dev, regmap, bank, data->alt, 0, 31);
1074 pc->oe = devm_regmap_field_alloc(dev, regmap, oe_reg); 1163 pc->oe = st_pc_get_value(dev, regmap, bank/4, data->oe, lsb, msb);
1075 pc->pu = devm_regmap_field_alloc(dev, regmap, pu_reg); 1164 pc->pu = st_pc_get_value(dev, regmap, bank/4, data->pu, lsb, msb);
1076 pc->od = devm_regmap_field_alloc(dev, regmap, od_reg); 1165 pc->od = st_pc_get_value(dev, regmap, bank/4, data->od, lsb, msb);
1077
1078 if (IS_ERR(pc->alt) || IS_ERR(pc->oe) ||
1079 IS_ERR(pc->pu) || IS_ERR(pc->od))
1080 return -EINVAL;
1081 1166
1082 /* retime avaiable for all pins by default */ 1167 /* retime avaiable for all pins by default */
1083 pc->rt_pin_mask = 0xff; 1168 pc->rt_pin_mask = 0xff;
1084 of_property_read_u32(np, "st,retime-pin-mask", &pc->rt_pin_mask); 1169 of_property_read_u32(np, "st,retime-pin-mask", &pc->rt_pin_mask);
1085 st_pctl_dt_setup_retime(info, bank, pc); 1170 st_pctl_dt_setup_retime(info, bank, pc);
1086 1171
1087 return 0; 1172 return;
1088} 1173}
1089 1174
1090/* 1175/*
@@ -1200,6 +1285,194 @@ static int st_pctl_parse_functions(struct device_node *np,
1200 return 0; 1285 return 0;
1201} 1286}
1202 1287
1288static int st_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
1289{
1290 struct st_gpio_bank *bank = gpio_chip_to_bank(chip);
1291 int irq = -ENXIO;
1292
1293 if (offset < chip->ngpio)
1294 irq = irq_find_mapping(bank->domain, offset);
1295
1296 dev_info(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
1297 chip->label, offset + chip->base, irq);
1298 return irq;
1299}
1300
1301static void st_gpio_irq_mask(struct irq_data *d)
1302{
1303 struct st_gpio_bank *bank = irq_data_get_irq_chip_data(d);
1304
1305 writel(BIT(d->hwirq), bank->base + REG_PIO_CLR_PMASK);
1306}
1307
1308static void st_gpio_irq_unmask(struct irq_data *d)
1309{
1310 struct st_gpio_bank *bank = irq_data_get_irq_chip_data(d);
1311
1312 writel(BIT(d->hwirq), bank->base + REG_PIO_SET_PMASK);
1313}
1314
1315static unsigned int st_gpio_irq_startup(struct irq_data *d)
1316{
1317 struct st_gpio_bank *bank = irq_data_get_irq_chip_data(d);
1318
1319 if (gpio_lock_as_irq(&bank->gpio_chip, d->hwirq))
1320 dev_err(bank->gpio_chip.dev,
1321 "unable to lock HW IRQ %lu for IRQ\n",
1322 d->hwirq);
1323
1324 st_gpio_irq_unmask(d);
1325
1326 return 0;
1327}
1328
1329static void st_gpio_irq_shutdown(struct irq_data *d)
1330{
1331 struct st_gpio_bank *bank = irq_data_get_irq_chip_data(d);
1332
1333 st_gpio_irq_mask(d);
1334 gpio_unlock_as_irq(&bank->gpio_chip, d->hwirq);
1335}
1336
1337static int st_gpio_irq_set_type(struct irq_data *d, unsigned type)
1338{
1339 struct st_gpio_bank *bank = irq_data_get_irq_chip_data(d);
1340 unsigned long flags;
1341 int comp, pin = d->hwirq;
1342 u32 val;
1343 u32 pin_edge_conf = 0;
1344
1345 switch (type) {
1346 case IRQ_TYPE_LEVEL_HIGH:
1347 comp = 0;
1348 break;
1349 case IRQ_TYPE_EDGE_FALLING:
1350 comp = 0;
1351 pin_edge_conf = ST_IRQ_FALLING_EDGE_CONF(pin);
1352 break;
1353 case IRQ_TYPE_LEVEL_LOW:
1354 comp = 1;
1355 break;
1356 case IRQ_TYPE_EDGE_RISING:
1357 comp = 1;
1358 pin_edge_conf = ST_IRQ_RISING_EDGE_CONF(pin);
1359 break;
1360 case IRQ_TYPE_EDGE_BOTH:
1361 comp = st_gpio_get(&bank->gpio_chip, pin);
1362 pin_edge_conf = ST_IRQ_BOTH_EDGE_CONF(pin);
1363 break;
1364 default:
1365 return -EINVAL;
1366 }
1367
1368 spin_lock_irqsave(&bank->lock, flags);
1369 bank->irq_edge_conf &= ~(ST_IRQ_EDGE_MASK << (
1370 pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN));
1371 bank->irq_edge_conf |= pin_edge_conf;
1372 spin_unlock_irqrestore(&bank->lock, flags);
1373
1374 val = readl(bank->base + REG_PIO_PCOMP);
1375 val &= ~BIT(pin);
1376 val |= (comp << pin);
1377 writel(val, bank->base + REG_PIO_PCOMP);
1378
1379 return 0;
1380}
1381
1382/*
1383 * As edge triggers are not supported at hardware level, it is supported by
1384 * software by exploiting the level trigger support in hardware.
1385 *
1386 * Steps for detection raising edge interrupt in software.
1387 *
1388 * Step 1: CONFIGURE pin to detect level LOW interrupts.
1389 *
1390 * Step 2: DETECT level LOW interrupt and in irqmux/gpio bank interrupt handler,
1391 * if the value of pin is low, then CONFIGURE pin for level HIGH interrupt.
1392 * IGNORE calling the actual interrupt handler for the pin at this stage.
1393 *
1394 * Step 3: DETECT level HIGH interrupt and in irqmux/gpio-bank interrupt handler
1395 * if the value of pin is HIGH, CONFIGURE pin for level LOW interrupt and then
1396 * DISPATCH the interrupt to the interrupt handler of the pin.
1397 *
1398 * step-1 ________ __________
1399 * | | step - 3
1400 * | |
1401 * step -2 |_____|
1402 *
1403 * falling edge is also detected int the same way.
1404 *
1405 */
1406static void __gpio_irq_handler(struct st_gpio_bank *bank)
1407{
1408 unsigned long port_in, port_mask, port_comp, active_irqs;
1409 unsigned long bank_edge_mask, flags;
1410 int n, val, ecfg;
1411
1412 spin_lock_irqsave(&bank->lock, flags);
1413 bank_edge_mask = bank->irq_edge_conf;
1414 spin_unlock_irqrestore(&bank->lock, flags);
1415
1416 for (;;) {
1417 port_in = readl(bank->base + REG_PIO_PIN);
1418 port_comp = readl(bank->base + REG_PIO_PCOMP);
1419 port_mask = readl(bank->base + REG_PIO_PMASK);
1420
1421 active_irqs = (port_in ^ port_comp) & port_mask;
1422
1423 if (active_irqs == 0)
1424 break;
1425
1426 for_each_set_bit(n, &active_irqs, BITS_PER_LONG) {
1427 /* check if we are detecting fake edges ... */
1428 ecfg = ST_IRQ_EDGE_CONF(bank_edge_mask, n);
1429
1430 if (ecfg) {
1431 /* edge detection. */
1432 val = st_gpio_get(&bank->gpio_chip, n);
1433
1434 writel(BIT(n),
1435 val ? bank->base + REG_PIO_SET_PCOMP :
1436 bank->base + REG_PIO_CLR_PCOMP);
1437
1438 if (ecfg != ST_IRQ_EDGE_BOTH &&
1439 !((ecfg & ST_IRQ_EDGE_FALLING) ^ val))
1440 continue;
1441 }
1442
1443 generic_handle_irq(irq_find_mapping(bank->domain, n));
1444 }
1445 }
1446}
1447
1448static void st_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
1449{
1450 /* interrupt dedicated per bank */
1451 struct irq_chip *chip = irq_get_chip(irq);
1452 struct st_gpio_bank *bank = irq_get_handler_data(irq);
1453
1454 chained_irq_enter(chip, desc);
1455 __gpio_irq_handler(bank);
1456 chained_irq_exit(chip, desc);
1457}
1458
1459static void st_gpio_irqmux_handler(unsigned irq, struct irq_desc *desc)
1460{
1461 struct irq_chip *chip = irq_get_chip(irq);
1462 struct st_pinctrl *info = irq_get_handler_data(irq);
1463 unsigned long status;
1464 int n;
1465
1466 chained_irq_enter(chip, desc);
1467
1468 status = readl(info->irqmux_base);
1469
1470 for_each_set_bit(n, &status, ST_GPIO_PINS_PER_BANK)
1471 __gpio_irq_handler(&info->banks[n]);
1472
1473 chained_irq_exit(chip, desc);
1474}
1475
1203static struct gpio_chip st_gpio_template = { 1476static struct gpio_chip st_gpio_template = {
1204 .request = st_gpio_request, 1477 .request = st_gpio_request,
1205 .free = st_gpio_free, 1478 .free = st_gpio_free,
@@ -1210,6 +1483,34 @@ static struct gpio_chip st_gpio_template = {
1210 .ngpio = ST_GPIO_PINS_PER_BANK, 1483 .ngpio = ST_GPIO_PINS_PER_BANK,
1211 .of_gpio_n_cells = 1, 1484 .of_gpio_n_cells = 1,
1212 .of_xlate = st_gpio_xlate, 1485 .of_xlate = st_gpio_xlate,
1486 .to_irq = st_gpio_to_irq,
1487};
1488
1489static struct irq_chip st_gpio_irqchip = {
1490 .name = "GPIO",
1491 .irq_mask = st_gpio_irq_mask,
1492 .irq_unmask = st_gpio_irq_unmask,
1493 .irq_set_type = st_gpio_irq_set_type,
1494 .irq_startup = st_gpio_irq_startup,
1495 .irq_shutdown = st_gpio_irq_shutdown,
1496};
1497
1498static int st_gpio_irq_domain_map(struct irq_domain *h,
1499 unsigned int virq, irq_hw_number_t hw)
1500{
1501 struct st_gpio_bank *bank = h->host_data;
1502
1503 irq_set_chip(virq, &st_gpio_irqchip);
1504 irq_set_handler(virq, handle_simple_irq);
1505 set_irq_flags(virq, IRQF_VALID);
1506 irq_set_chip_data(virq, bank);
1507
1508 return 0;
1509}
1510
1511static struct irq_domain_ops st_gpio_irq_ops = {
1512 .map = st_gpio_irq_domain_map,
1513 .xlate = irq_domain_xlate_twocell,
1213}; 1514};
1214 1515
1215static int st_gpiolib_register_bank(struct st_pinctrl *info, 1516static int st_gpiolib_register_bank(struct st_pinctrl *info,
@@ -1219,8 +1520,8 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info,
1219 struct pinctrl_gpio_range *range = &bank->range; 1520 struct pinctrl_gpio_range *range = &bank->range;
1220 struct device *dev = info->dev; 1521 struct device *dev = info->dev;
1221 int bank_num = of_alias_get_id(np, "gpio"); 1522 int bank_num = of_alias_get_id(np, "gpio");
1222 struct resource res; 1523 struct resource res, irq_res;
1223 int err; 1524 int gpio_irq = 0, err, i;
1224 1525
1225 if (of_address_to_resource(np, 0, &res)) 1526 if (of_address_to_resource(np, 0, &res))
1226 return -ENODEV; 1527 return -ENODEV;
@@ -1233,6 +1534,7 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info,
1233 bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK; 1534 bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK;
1234 bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK; 1535 bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK;
1235 bank->gpio_chip.of_node = np; 1536 bank->gpio_chip.of_node = np;
1537 spin_lock_init(&bank->lock);
1236 1538
1237 of_property_read_string(np, "st,bank-name", &range->name); 1539 of_property_read_string(np, "st,bank-name", &range->name);
1238 bank->gpio_chip.label = range->name; 1540 bank->gpio_chip.label = range->name;
@@ -1248,6 +1550,51 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info,
1248 } 1550 }
1249 dev_info(dev, "%s bank added.\n", range->name); 1551 dev_info(dev, "%s bank added.\n", range->name);
1250 1552
1553 /**
1554 * GPIO bank can have one of the two possible types of
1555 * interrupt-wirings.
1556 *
1557 * First type is via irqmux, single interrupt is used by multiple
1558 * gpio banks. This reduces number of overall interrupts numbers
1559 * required. All these banks belong to a single pincontroller.
1560 * _________
1561 * | |----> [gpio-bank (n) ]
1562 * | |----> [gpio-bank (n + 1)]
1563 * [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
1564 * | |----> [gpio-bank (... )]
1565 * |_________|----> [gpio-bank (n + 7)]
1566 *
1567 * Second type has a dedicated interrupt per each gpio bank.
1568 *
1569 * [irqN]----> [gpio-bank (n)]
1570 */
1571
1572 if (of_irq_to_resource(np, 0, &irq_res)) {
1573 gpio_irq = irq_res.start;
1574 irq_set_chained_handler(gpio_irq, st_gpio_irq_handler);
1575 irq_set_handler_data(gpio_irq, bank);
1576 }
1577
1578 if (info->irqmux_base > 0 || gpio_irq > 0) {
1579 /* Setup IRQ domain */
1580 bank->domain = irq_domain_add_linear(np,
1581 ST_GPIO_PINS_PER_BANK,
1582 &st_gpio_irq_ops, bank);
1583 if (!bank->domain) {
1584 dev_err(dev, "Failed to add irq domain for %s\n",
1585 np->full_name);
1586 } else {
1587 for (i = 0; i < ST_GPIO_PINS_PER_BANK; i++) {
1588 if (irq_create_mapping(bank->domain, i) < 0)
1589 dev_err(dev,
1590 "Failed to map IRQ %i\n", i);
1591 }
1592 }
1593
1594 } else {
1595 dev_info(dev, "No IRQ support for %s bank\n", np->full_name);
1596 }
1597
1251 return 0; 1598 return 0;
1252} 1599}
1253 1600
@@ -1264,6 +1611,10 @@ static struct of_device_id st_pctl_of_match[] = {
1264 { .compatible = "st,stih416-rear-pinctrl", .data = &stih416_data}, 1611 { .compatible = "st,stih416-rear-pinctrl", .data = &stih416_data},
1265 { .compatible = "st,stih416-fvdp-fe-pinctrl", .data = &stih416_data}, 1612 { .compatible = "st,stih416-fvdp-fe-pinctrl", .data = &stih416_data},
1266 { .compatible = "st,stih416-fvdp-lite-pinctrl", .data = &stih416_data}, 1613 { .compatible = "st,stih416-fvdp-lite-pinctrl", .data = &stih416_data},
1614 { .compatible = "st,stih407-sbc-pinctrl", .data = &stih416_data},
1615 { .compatible = "st,stih407-front-pinctrl", .data = &stih416_data},
1616 { .compatible = "st,stih407-rear-pinctrl", .data = &stih416_data},
1617 { .compatible = "st,stih407-flash-pinctrl", .data = &stih407_flashdata},
1267 { /* sentinel */ } 1618 { /* sentinel */ }
1268}; 1619};
1269 1620
@@ -1276,6 +1627,8 @@ static int st_pctl_probe_dt(struct platform_device *pdev,
1276 struct device_node *np = pdev->dev.of_node; 1627 struct device_node *np = pdev->dev.of_node;
1277 struct device_node *child; 1628 struct device_node *child;
1278 int grp_index = 0; 1629 int grp_index = 0;
1630 int irq = 0;
1631 struct resource *res;
1279 1632
1280 st_pctl_dt_child_count(info, np); 1633 st_pctl_dt_child_count(info, np);
1281 if (!info->nbanks) { 1634 if (!info->nbanks) {
@@ -1306,6 +1659,21 @@ static int st_pctl_probe_dt(struct platform_device *pdev,
1306 } 1659 }
1307 info->data = of_match_node(st_pctl_of_match, np)->data; 1660 info->data = of_match_node(st_pctl_of_match, np)->data;
1308 1661
1662 irq = platform_get_irq(pdev, 0);
1663
1664 if (irq > 0) {
1665 res = platform_get_resource_byname(pdev,
1666 IORESOURCE_MEM, "irqmux");
1667 info->irqmux_base = devm_ioremap_resource(&pdev->dev, res);
1668
1669 if (IS_ERR(info->irqmux_base))
1670 return PTR_ERR(info->irqmux_base);
1671
1672 irq_set_chained_handler(irq, st_gpio_irqmux_handler);
1673 irq_set_handler_data(irq, info);
1674
1675 }
1676
1309 pctl_desc->npins = info->nbanks * ST_GPIO_PINS_PER_BANK; 1677 pctl_desc->npins = info->nbanks * ST_GPIO_PINS_PER_BANK;
1310 pdesc = devm_kzalloc(&pdev->dev, 1678 pdesc = devm_kzalloc(&pdev->dev,
1311 sizeof(*pdesc) * pctl_desc->npins, GFP_KERNEL); 1679 sizeof(*pdesc) * pctl_desc->npins, GFP_KERNEL);
diff --git a/drivers/pinctrl/pinctrl-sunxi-pins.h b/drivers/pinctrl/pinctrl-sunxi-pins.h
index 6fd8d4d95140..3d6066988a72 100644
--- a/drivers/pinctrl/pinctrl-sunxi-pins.h
+++ b/drivers/pinctrl/pinctrl-sunxi-pins.h
@@ -1932,27 +1932,27 @@ static const struct sunxi_desc_pin sun5i_a13_pins[] = {
1932 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0, 1932 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
1933 SUNXI_FUNCTION(0x0, "gpio_in"), 1933 SUNXI_FUNCTION(0x0, "gpio_in"),
1934 SUNXI_FUNCTION(0x1, "gpio_out"), 1934 SUNXI_FUNCTION(0x1, "gpio_out"),
1935 SUNXI_FUNCTION(0x4, "mmc0")), /* D1 */ 1935 SUNXI_FUNCTION(0x2, "mmc0")), /* D1 */
1936 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1, 1936 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
1937 SUNXI_FUNCTION(0x0, "gpio_in"), 1937 SUNXI_FUNCTION(0x0, "gpio_in"),
1938 SUNXI_FUNCTION(0x1, "gpio_out"), 1938 SUNXI_FUNCTION(0x1, "gpio_out"),
1939 SUNXI_FUNCTION(0x4, "mmc0")), /* D0 */ 1939 SUNXI_FUNCTION(0x2, "mmc0")), /* D0 */
1940 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2, 1940 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
1941 SUNXI_FUNCTION(0x0, "gpio_in"), 1941 SUNXI_FUNCTION(0x0, "gpio_in"),
1942 SUNXI_FUNCTION(0x1, "gpio_out"), 1942 SUNXI_FUNCTION(0x1, "gpio_out"),
1943 SUNXI_FUNCTION(0x4, "mmc0")), /* CLK */ 1943 SUNXI_FUNCTION(0x2, "mmc0")), /* CLK */
1944 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3, 1944 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
1945 SUNXI_FUNCTION(0x0, "gpio_in"), 1945 SUNXI_FUNCTION(0x0, "gpio_in"),
1946 SUNXI_FUNCTION(0x1, "gpio_out"), 1946 SUNXI_FUNCTION(0x1, "gpio_out"),
1947 SUNXI_FUNCTION(0x4, "mmc0")), /* CMD */ 1947 SUNXI_FUNCTION(0x2, "mmc0")), /* CMD */
1948 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4, 1948 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
1949 SUNXI_FUNCTION(0x0, "gpio_in"), 1949 SUNXI_FUNCTION(0x0, "gpio_in"),
1950 SUNXI_FUNCTION(0x1, "gpio_out"), 1950 SUNXI_FUNCTION(0x1, "gpio_out"),
1951 SUNXI_FUNCTION(0x4, "mmc0")), /* D3 */ 1951 SUNXI_FUNCTION(0x2, "mmc0")), /* D3 */
1952 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5, 1952 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
1953 SUNXI_FUNCTION(0x0, "gpio_in"), 1953 SUNXI_FUNCTION(0x0, "gpio_in"),
1954 SUNXI_FUNCTION(0x1, "gpio_out"), 1954 SUNXI_FUNCTION(0x1, "gpio_out"),
1955 SUNXI_FUNCTION(0x4, "mmc0")), /* D2 */ 1955 SUNXI_FUNCTION(0x2, "mmc0")), /* D2 */
1956 /* Hole */ 1956 /* Hole */
1957 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0, 1957 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
1958 SUNXI_FUNCTION(0x0, "gpio_in"), 1958 SUNXI_FUNCTION(0x0, "gpio_in"),
diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/pinctrl-tegra.c
index e767355ab0ad..65458096f41e 100644
--- a/drivers/pinctrl/pinctrl-tegra.c
+++ b/drivers/pinctrl/pinctrl-tegra.c
@@ -39,6 +39,7 @@ struct tegra_pmx {
39 struct pinctrl_dev *pctl; 39 struct pinctrl_dev *pctl;
40 40
41 const struct tegra_pinctrl_soc_data *soc; 41 const struct tegra_pinctrl_soc_data *soc;
42 const char **group_pins;
42 43
43 int nbanks; 44 int nbanks;
44 void __iomem **regs; 45 void __iomem **regs;
@@ -620,6 +621,8 @@ int tegra_pinctrl_probe(struct platform_device *pdev,
620 struct tegra_pmx *pmx; 621 struct tegra_pmx *pmx;
621 struct resource *res; 622 struct resource *res;
622 int i; 623 int i;
624 const char **group_pins;
625 int fn, gn, gfn;
623 626
624 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); 627 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
625 if (!pmx) { 628 if (!pmx) {
@@ -629,6 +632,41 @@ int tegra_pinctrl_probe(struct platform_device *pdev,
629 pmx->dev = &pdev->dev; 632 pmx->dev = &pdev->dev;
630 pmx->soc = soc_data; 633 pmx->soc = soc_data;
631 634
635 /*
636 * Each mux group will appear in 4 functions' list of groups.
637 * This over-allocates slightly, since not all groups are mux groups.
638 */
639 pmx->group_pins = devm_kzalloc(&pdev->dev,
640 soc_data->ngroups * 4 * sizeof(*pmx->group_pins),
641 GFP_KERNEL);
642 if (!pmx->group_pins)
643 return -ENOMEM;
644
645 group_pins = pmx->group_pins;
646 for (fn = 0; fn < soc_data->nfunctions; fn++) {
647 struct tegra_function *func = &soc_data->functions[fn];
648
649 func->groups = group_pins;
650
651 for (gn = 0; gn < soc_data->ngroups; gn++) {
652 const struct tegra_pingroup *g = &soc_data->groups[gn];
653
654 if (g->mux_reg == -1)
655 continue;
656
657 for (gfn = 0; gfn < 4; gfn++)
658 if (g->funcs[gfn] == fn)
659 break;
660 if (gfn == 4)
661 continue;
662
663 BUG_ON(group_pins - pmx->group_pins >=
664 soc_data->ngroups * 4);
665 *group_pins++ = g->name;
666 func->ngroups++;
667 }
668 }
669
632 tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios; 670 tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
633 tegra_pinctrl_desc.name = dev_name(&pdev->dev); 671 tegra_pinctrl_desc.name = dev_name(&pdev->dev);
634 tegra_pinctrl_desc.pins = pmx->soc->pins; 672 tegra_pinctrl_desc.pins = pmx->soc->pins;
diff --git a/drivers/pinctrl/pinctrl-tegra.h b/drivers/pinctrl/pinctrl-tegra.h
index 817f7061dc4c..6053832d433e 100644
--- a/drivers/pinctrl/pinctrl-tegra.h
+++ b/drivers/pinctrl/pinctrl-tegra.h
@@ -72,7 +72,7 @@ enum tegra_pinconf_tristate {
72 */ 72 */
73struct tegra_function { 73struct tegra_function {
74 const char *name; 74 const char *name;
75 const char * const *groups; 75 const char **groups;
76 unsigned ngroups; 76 unsigned ngroups;
77}; 77};
78 78
@@ -193,7 +193,7 @@ struct tegra_pinctrl_soc_data {
193 unsigned ngpios; 193 unsigned ngpios;
194 const struct pinctrl_pin_desc *pins; 194 const struct pinctrl_pin_desc *pins;
195 unsigned npins; 195 unsigned npins;
196 const struct tegra_function *functions; 196 struct tegra_function *functions;
197 unsigned nfunctions; 197 unsigned nfunctions;
198 const struct tegra_pingroup *groups; 198 const struct tegra_pingroup *groups;
199 unsigned ngroups; 199 unsigned ngroups;
diff --git a/drivers/pinctrl/pinctrl-tegra114.c b/drivers/pinctrl/pinctrl-tegra114.c
index 93c9e3899d5e..63fe7619d3ff 100644
--- a/drivers/pinctrl/pinctrl-tegra114.c
+++ b/drivers/pinctrl/pinctrl-tegra114.c
@@ -1,10 +1,8 @@
1/* 1/*
2 * Pinctrl data and driver for the NVIDIA Tegra114 pinmux 2 * Pinctrl data for the NVIDIA Tegra114 pinmux
3 * 3 *
4 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Author: Pritesh Raithatha <praithatha@nvidia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License, 7 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation. 8 * version 2, as published by the Free Software Foundation.
@@ -13,9 +11,6 @@
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details. 13 * more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */ 14 */
20 15
21#include <linux/module.h> 16#include <linux/module.h>
@@ -203,8 +198,8 @@
203#define TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 _GPIO(245) 198#define TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 _GPIO(245)
204 199
205/* All non-GPIO pins follow */ 200/* All non-GPIO pins follow */
206#define NUM_GPIOS (TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 + 1) 201#define NUM_GPIOS (TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 + 1)
207#define _PIN(offset) (NUM_GPIOS + (offset)) 202#define _PIN(offset) (NUM_GPIOS + (offset))
208 203
209/* Non-GPIO pins */ 204/* Non-GPIO pins */
210#define TEGRA_PIN_CORE_PWR_REQ _PIN(0) 205#define TEGRA_PIN_CORE_PWR_REQ _PIN(0)
@@ -212,8 +207,11 @@
212#define TEGRA_PIN_PWR_INT_N _PIN(2) 207#define TEGRA_PIN_PWR_INT_N _PIN(2)
213#define TEGRA_PIN_RESET_OUT_N _PIN(3) 208#define TEGRA_PIN_RESET_OUT_N _PIN(3)
214#define TEGRA_PIN_OWR _PIN(4) 209#define TEGRA_PIN_OWR _PIN(4)
210#define TEGRA_PIN_JTAG_RTCK _PIN(5)
211#define TEGRA_PIN_CLK_32K_IN _PIN(6)
212#define TEGRA_PIN_GMI_CLK_LB _PIN(7)
215 213
216static const struct pinctrl_pin_desc tegra114_pins[] = { 214static const struct pinctrl_pin_desc tegra114_pins[] = {
217 PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"), 215 PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
218 PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"), 216 PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
219 PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"), 217 PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
@@ -385,9 +383,12 @@ static const struct pinctrl_pin_desc tegra114_pins[] = {
385 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, "SDMMC3_CLK_LB_IN PEE5"), 383 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, "SDMMC3_CLK_LB_IN PEE5"),
386 PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"), 384 PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
387 PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"), 385 PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
388 PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
389 PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"), 386 PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
390 PINCTRL_PIN(TEGRA_PIN_RESET_OUT_N, "RESET_OUT_N"), 387 PINCTRL_PIN(TEGRA_PIN_RESET_OUT_N, "RESET_OUT_N"),
388 PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
389 PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"),
390 PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
391 PINCTRL_PIN(TEGRA_PIN_GMI_CLK_LB, "GMI_CLK_LB"),
391}; 392};
392 393
393static const unsigned clk_32k_out_pa0_pins[] = { 394static const unsigned clk_32k_out_pa0_pins[] = {
@@ -1074,10 +1075,6 @@ static const unsigned cpu_pwr_req_pins[] = {
1074 TEGRA_PIN_CPU_PWR_REQ, 1075 TEGRA_PIN_CPU_PWR_REQ,
1075}; 1076};
1076 1077
1077static const unsigned owr_pins[] = {
1078 TEGRA_PIN_OWR,
1079};
1080
1081static const unsigned pwr_int_n_pins[] = { 1078static const unsigned pwr_int_n_pins[] = {
1082 TEGRA_PIN_PWR_INT_N, 1079 TEGRA_PIN_PWR_INT_N,
1083}; 1080};
@@ -1086,6 +1083,22 @@ static const unsigned reset_out_n_pins[] = {
1086 TEGRA_PIN_RESET_OUT_N, 1083 TEGRA_PIN_RESET_OUT_N,
1087}; 1084};
1088 1085
1086static const unsigned owr_pins[] = {
1087 TEGRA_PIN_OWR,
1088};
1089
1090static const unsigned jtag_rtck_pins[] = {
1091 TEGRA_PIN_JTAG_RTCK,
1092};
1093
1094static const unsigned clk_32k_in_pins[] = {
1095 TEGRA_PIN_CLK_32K_IN,
1096};
1097
1098static const unsigned gmi_clk_lb_pins[] = {
1099 TEGRA_PIN_GMI_CLK_LB,
1100};
1101
1089static const unsigned drive_ao1_pins[] = { 1102static const unsigned drive_ao1_pins[] = {
1090 TEGRA_PIN_KB_ROW0_PR0, 1103 TEGRA_PIN_KB_ROW0_PR0,
1091 TEGRA_PIN_KB_ROW1_PR1, 1104 TEGRA_PIN_KB_ROW1_PR1,
@@ -1127,7 +1140,6 @@ static const unsigned drive_at1_pins[] = {
1127 TEGRA_PIN_GMI_AD13_PH5, 1140 TEGRA_PIN_GMI_AD13_PH5,
1128 TEGRA_PIN_GMI_AD14_PH6, 1141 TEGRA_PIN_GMI_AD14_PH6,
1129 TEGRA_PIN_GMI_AD15_PH7, 1142 TEGRA_PIN_GMI_AD15_PH7,
1130
1131 TEGRA_PIN_GMI_IORDY_PI5, 1143 TEGRA_PIN_GMI_IORDY_PI5,
1132 TEGRA_PIN_GMI_CS7_N_PI6, 1144 TEGRA_PIN_GMI_CS7_N_PI6,
1133}; 1145};
@@ -1141,15 +1153,12 @@ static const unsigned drive_at2_pins[] = {
1141 TEGRA_PIN_GMI_AD5_PG5, 1153 TEGRA_PIN_GMI_AD5_PG5,
1142 TEGRA_PIN_GMI_AD6_PG6, 1154 TEGRA_PIN_GMI_AD6_PG6,
1143 TEGRA_PIN_GMI_AD7_PG7, 1155 TEGRA_PIN_GMI_AD7_PG7,
1144
1145 TEGRA_PIN_GMI_WR_N_PI0, 1156 TEGRA_PIN_GMI_WR_N_PI0,
1146 TEGRA_PIN_GMI_OE_N_PI1, 1157 TEGRA_PIN_GMI_OE_N_PI1,
1147 TEGRA_PIN_GMI_CS6_N_PI3, 1158 TEGRA_PIN_GMI_CS6_N_PI3,
1148 TEGRA_PIN_GMI_RST_N_PI4, 1159 TEGRA_PIN_GMI_RST_N_PI4,
1149 TEGRA_PIN_GMI_WAIT_PI7, 1160 TEGRA_PIN_GMI_WAIT_PI7,
1150
1151 TEGRA_PIN_GMI_DQS_P_PJ3, 1161 TEGRA_PIN_GMI_DQS_P_PJ3,
1152
1153 TEGRA_PIN_GMI_ADV_N_PK0, 1162 TEGRA_PIN_GMI_ADV_N_PK0,
1154 TEGRA_PIN_GMI_CLK_PK1, 1163 TEGRA_PIN_GMI_CLK_PK1,
1155 TEGRA_PIN_GMI_CS4_N_PK2, 1164 TEGRA_PIN_GMI_CS4_N_PK2,
@@ -1342,14 +1351,37 @@ static const unsigned drive_uda_pins[] = {
1342}; 1351};
1343 1352
1344static const unsigned drive_dev3_pins[] = { 1353static const unsigned drive_dev3_pins[] = {
1345 TEGRA_PIN_CLK3_OUT_PEE0, 1354};
1346 TEGRA_PIN_CLK3_REQ_PEE1, 1355
1356static const unsigned drive_cec_pins[] = {
1357};
1358
1359static const unsigned drive_at6_pins[] = {
1360};
1361
1362static const unsigned drive_dap5_pins[] = {
1363};
1364
1365static const unsigned drive_usb_vbus_en_pins[] = {
1366};
1367
1368static const unsigned drive_ao3_pins[] = {
1369};
1370
1371static const unsigned drive_hv0_pins[] = {
1372};
1373
1374static const unsigned drive_sdio4_pins[] = {
1375};
1376
1377static const unsigned drive_ao0_pins[] = {
1347}; 1378};
1348 1379
1349enum tegra_mux { 1380enum tegra_mux {
1350 TEGRA_MUX_BLINK, 1381 TEGRA_MUX_BLINK,
1351 TEGRA_MUX_CEC, 1382 TEGRA_MUX_CEC,
1352 TEGRA_MUX_CLDVFS, 1383 TEGRA_MUX_CLDVFS,
1384 TEGRA_MUX_CLK,
1353 TEGRA_MUX_CLK12, 1385 TEGRA_MUX_CLK12,
1354 TEGRA_MUX_CPU, 1386 TEGRA_MUX_CPU,
1355 TEGRA_MUX_DAP, 1387 TEGRA_MUX_DAP,
@@ -1394,6 +1426,7 @@ enum tegra_mux {
1394 TEGRA_MUX_RSVD2, 1426 TEGRA_MUX_RSVD2,
1395 TEGRA_MUX_RSVD3, 1427 TEGRA_MUX_RSVD3,
1396 TEGRA_MUX_RSVD4, 1428 TEGRA_MUX_RSVD4,
1429 TEGRA_MUX_RTCK,
1397 TEGRA_MUX_SDMMC1, 1430 TEGRA_MUX_SDMMC1,
1398 TEGRA_MUX_SDMMC2, 1431 TEGRA_MUX_SDMMC2,
1399 TEGRA_MUX_SDMMC3, 1432 TEGRA_MUX_SDMMC3,
@@ -1425,944 +1458,16 @@ enum tegra_mux {
1425 TEGRA_MUX_VI_ALT3, 1458 TEGRA_MUX_VI_ALT3,
1426}; 1459};
1427 1460
1428static const char * const blink_groups[] = {
1429 "clk_32k_out_pa0",
1430};
1431
1432static const char * const cec_groups[] = {
1433 "hdmi_cec_pee3",
1434};
1435
1436static const char * const cldvfs_groups[] = {
1437 "gmi_ad9_ph1",
1438 "gmi_ad10_ph2",
1439 "kb_row7_pr7",
1440 "kb_row8_ps0",
1441 "dvfs_pwm_px0",
1442 "dvfs_clk_px2",
1443};
1444
1445static const char * const clk12_groups[] = {
1446 "sdmmc1_wp_n_pv3",
1447 "sdmmc1_clk_pz0",
1448};
1449
1450static const char * const cpu_groups[] = {
1451 "cpu_pwr_req",
1452};
1453
1454static const char * const dap_groups[] = {
1455 "clk1_req_pee2",
1456 "clk2_req_pcc5",
1457};
1458
1459static const char * const dap1_groups[] = {
1460 "clk1_req_pee2",
1461};
1462
1463static const char * const dap2_groups[] = {
1464 "clk1_out_pw4",
1465 "gpio_x4_aud_px4",
1466};
1467
1468static const char * const dev3_groups[] = {
1469 "clk3_req_pee1",
1470};
1471
1472static const char * const displaya_groups[] = {
1473 "dap3_fs_pp0",
1474 "dap3_din_pp1",
1475 "dap3_dout_pp2",
1476 "dap3_sclk_pp3",
1477 "uart3_rts_n_pc0",
1478 "pu3",
1479 "pu4",
1480 "pu5",
1481 "pbb3",
1482 "pbb4",
1483 "pbb5",
1484 "pbb6",
1485 "kb_row3_pr3",
1486 "kb_row4_pr4",
1487 "kb_row5_pr5",
1488 "kb_row6_pr6",
1489 "kb_col3_pq3",
1490 "sdmmc3_dat2_pb5",
1491};
1492
1493static const char * const displaya_alt_groups[] = {
1494 "kb_row6_pr6",
1495};
1496
1497static const char * const displayb_groups[] = {
1498 "dap3_fs_pp0",
1499 "dap3_din_pp1",
1500 "dap3_dout_pp2",
1501 "dap3_sclk_pp3",
1502 "pu3",
1503 "pu4",
1504 "pu5",
1505 "pu6",
1506 "pbb3",
1507 "pbb4",
1508 "pbb5",
1509 "pbb6",
1510 "kb_row3_pr3",
1511 "kb_row4_pr4",
1512 "kb_row5_pr5",
1513 "kb_row6_pr6",
1514 "sdmmc3_dat3_pb4",
1515};
1516
1517static const char * const dtv_groups[] = {
1518 "uart3_cts_n_pa1",
1519 "uart3_rts_n_pc0",
1520 "dap4_fs_pp4",
1521 "dap4_dout_pp6",
1522 "gmi_wait_pi7",
1523 "gmi_ad8_ph0",
1524 "gmi_ad14_ph6",
1525 "gmi_ad15_ph7",
1526};
1527
1528static const char * const emc_dll_groups[] = {
1529 "kb_col0_pq0",
1530 "kb_col1_pq1",
1531};
1532
1533static const char * const extperiph1_groups[] = {
1534 "clk1_out_pw4",
1535};
1536
1537static const char * const extperiph2_groups[] = {
1538 "clk2_out_pw5",
1539};
1540
1541static const char * const extperiph3_groups[] = {
1542 "clk3_out_pee0",
1543};
1544
1545static const char * const gmi_groups[] = {
1546 "gmi_wp_n_pc7",
1547
1548 "gmi_ad0_pg0",
1549 "gmi_ad1_pg1",
1550 "gmi_ad2_pg2",
1551 "gmi_ad3_pg3",
1552 "gmi_ad4_pg4",
1553 "gmi_ad5_pg5",
1554 "gmi_ad6_pg6",
1555 "gmi_ad7_pg7",
1556 "gmi_ad8_ph0",
1557 "gmi_ad9_ph1",
1558 "gmi_ad10_ph2",
1559 "gmi_ad11_ph3",
1560 "gmi_ad12_ph4",
1561 "gmi_ad13_ph5",
1562 "gmi_ad14_ph6",
1563 "gmi_ad15_ph7",
1564 "gmi_wr_n_pi0",
1565 "gmi_oe_n_pi1",
1566 "gmi_cs6_n_pi3",
1567 "gmi_rst_n_pi4",
1568 "gmi_iordy_pi5",
1569 "gmi_cs7_n_pi6",
1570 "gmi_wait_pi7",
1571 "gmi_cs0_n_pj0",
1572 "gmi_cs1_n_pj2",
1573 "gmi_dqs_p_pj3",
1574 "gmi_adv_n_pk0",
1575 "gmi_clk_pk1",
1576 "gmi_cs4_n_pk2",
1577 "gmi_cs2_n_pk3",
1578 "gmi_cs3_n_pk4",
1579 "gmi_a16_pj7",
1580 "gmi_a17_pb0",
1581 "gmi_a18_pb1",
1582 "gmi_a19_pk7",
1583 "gen2_i2c_scl_pt5",
1584 "gen2_i2c_sda_pt6",
1585 "sdmmc4_dat0_paa0",
1586 "sdmmc4_dat1_paa1",
1587 "sdmmc4_dat2_paa2",
1588 "sdmmc4_dat3_paa3",
1589 "sdmmc4_dat4_paa4",
1590 "sdmmc4_dat5_paa5",
1591 "sdmmc4_dat6_paa6",
1592 "sdmmc4_dat7_paa7",
1593 "sdmmc4_clk_pcc4",
1594 "sdmmc4_cmd_pt7",
1595 "dap1_fs_pn0",
1596 "dap1_din_pn1",
1597 "dap1_dout_pn2",
1598 "dap1_sclk_pn3",
1599};
1600
1601static const char * const gmi_alt_groups[] = {
1602 "gmi_wp_n_pc7",
1603 "gmi_cs3_n_pk4",
1604 "gmi_a16_pj7",
1605};
1606
1607static const char * const hda_groups[] = {
1608 "dap1_fs_pn0",
1609 "dap1_din_pn1",
1610 "dap1_dout_pn2",
1611 "dap1_sclk_pn3",
1612 "dap2_fs_pa2",
1613 "dap2_sclk_pa3",
1614 "dap2_din_pa4",
1615 "dap2_dout_pa5",
1616};
1617
1618static const char * const hsi_groups[] = {
1619 "ulpi_data0_po1",
1620 "ulpi_data1_po2",
1621 "ulpi_data2_po3",
1622 "ulpi_data3_po4",
1623 "ulpi_data4_po5",
1624 "ulpi_data5_po6",
1625 "ulpi_data6_po7",
1626 "ulpi_data7_po0",
1627};
1628
1629static const char * const i2c1_groups[] = {
1630 "gen1_i2c_scl_pc4",
1631 "gen1_i2c_sda_pc5",
1632 "gpio_w2_aud_pw2",
1633 "gpio_w3_aud_pw3",
1634};
1635
1636static const char * const i2c2_groups[] = {
1637 "gen2_i2c_scl_pt5",
1638 "gen2_i2c_sda_pt6",
1639};
1640
1641static const char * const i2c3_groups[] = {
1642 "cam_i2c_scl_pbb1",
1643 "cam_i2c_sda_pbb2",
1644};
1645
1646static const char * const i2c4_groups[] = {
1647 "ddc_scl_pv4",
1648 "ddc_sda_pv5",
1649};
1650
1651static const char * const i2cpwr_groups[] = {
1652 "pwr_i2c_scl_pz6",
1653 "pwr_i2c_sda_pz7",
1654};
1655
1656static const char * const i2s0_groups[] = {
1657 "dap1_fs_pn0",
1658 "dap1_din_pn1",
1659 "dap1_dout_pn2",
1660 "dap1_sclk_pn3",
1661};
1662
1663static const char * const i2s1_groups[] = {
1664 "dap2_fs_pa2",
1665 "dap2_sclk_pa3",
1666 "dap2_din_pa4",
1667 "dap2_dout_pa5",
1668};
1669
1670static const char * const i2s2_groups[] = {
1671 "dap3_fs_pp0",
1672 "dap3_din_pp1",
1673 "dap3_dout_pp2",
1674 "dap3_sclk_pp3",
1675};
1676
1677static const char * const i2s3_groups[] = {
1678 "dap4_fs_pp4",
1679 "dap4_din_pp5",
1680 "dap4_dout_pp6",
1681 "dap4_sclk_pp7",
1682};
1683
1684static const char * const i2s4_groups[] = {
1685 "pcc1",
1686 "pbb0",
1687 "pbb7",
1688 "pcc2",
1689};
1690
1691static const char * const irda_groups[] = {
1692 "uart2_rxd_pc3",
1693 "uart2_txd_pc2",
1694};
1695
1696static const char * const kbc_groups[] = {
1697 "kb_row0_pr0",
1698 "kb_row1_pr1",
1699 "kb_row2_pr2",
1700 "kb_row3_pr3",
1701 "kb_row4_pr4",
1702 "kb_row5_pr5",
1703 "kb_row6_pr6",
1704 "kb_row7_pr7",
1705 "kb_row8_ps0",
1706 "kb_row9_ps1",
1707 "kb_row10_ps2",
1708 "kb_col0_pq0",
1709 "kb_col1_pq1",
1710 "kb_col2_pq2",
1711 "kb_col3_pq3",
1712 "kb_col4_pq4",
1713 "kb_col5_pq5",
1714 "kb_col6_pq6",
1715 "kb_col7_pq7",
1716};
1717
1718static const char * const nand_groups[] = {
1719 "gmi_wp_n_pc7",
1720 "gmi_wait_pi7",
1721 "gmi_adv_n_pk0",
1722 "gmi_clk_pk1",
1723 "gmi_cs0_n_pj0",
1724 "gmi_cs1_n_pj2",
1725 "gmi_cs2_n_pk3",
1726 "gmi_cs3_n_pk4",
1727 "gmi_cs4_n_pk2",
1728 "gmi_cs6_n_pi3",
1729 "gmi_cs7_n_pi6",
1730 "gmi_ad0_pg0",
1731 "gmi_ad1_pg1",
1732 "gmi_ad2_pg2",
1733 "gmi_ad3_pg3",
1734 "gmi_ad4_pg4",
1735 "gmi_ad5_pg5",
1736 "gmi_ad6_pg6",
1737 "gmi_ad7_pg7",
1738 "gmi_ad8_ph0",
1739 "gmi_ad9_ph1",
1740 "gmi_ad10_ph2",
1741 "gmi_ad11_ph3",
1742 "gmi_ad12_ph4",
1743 "gmi_ad13_ph5",
1744 "gmi_ad14_ph6",
1745 "gmi_ad15_ph7",
1746 "gmi_wr_n_pi0",
1747 "gmi_oe_n_pi1",
1748 "gmi_dqs_p_pj3",
1749 "gmi_rst_n_pi4",
1750};
1751
1752static const char * const nand_alt_groups[] = {
1753 "gmi_cs6_n_pi3",
1754 "gmi_cs7_n_pi6",
1755 "gmi_rst_n_pi4",
1756};
1757
1758static const char * const owr_groups[] = {
1759 "pu0",
1760 "kb_col4_pq4",
1761 "owr",
1762 "sdmmc3_cd_n_pv2",
1763};
1764
1765static const char * const pmi_groups[] = {
1766 "pwr_int_n",
1767};
1768
1769static const char * const pwm0_groups[] = {
1770 "sdmmc1_dat2_py5",
1771 "uart3_rts_n_pc0",
1772 "pu3",
1773 "gmi_ad8_ph0",
1774 "sdmmc3_dat3_pb4",
1775};
1776
1777static const char * const pwm1_groups[] = {
1778 "sdmmc1_dat1_py6",
1779 "pu4",
1780 "gmi_ad9_ph1",
1781 "sdmmc3_dat2_pb5",
1782};
1783
1784static const char * const pwm2_groups[] = {
1785 "pu5",
1786 "gmi_ad10_ph2",
1787 "kb_col3_pq3",
1788 "sdmmc3_dat1_pb6",
1789};
1790
1791static const char * const pwm3_groups[] = {
1792 "pu6",
1793 "gmi_ad11_ph3",
1794 "sdmmc3_cmd_pa7",
1795};
1796
1797static const char * const pwron_groups[] = {
1798 "core_pwr_req",
1799};
1800
1801static const char * const reset_out_n_groups[] = {
1802 "reset_out_n",
1803};
1804
1805static const char * const rsvd1_groups[] = {
1806 "pv1",
1807 "hdmi_int_pn7",
1808 "pu1",
1809 "pu2",
1810 "gmi_wp_n_pc7",
1811 "gmi_adv_n_pk0",
1812 "gmi_cs0_n_pj0",
1813 "gmi_cs1_n_pj2",
1814 "gmi_ad0_pg0",
1815 "gmi_ad1_pg1",
1816 "gmi_ad2_pg2",
1817 "gmi_ad3_pg3",
1818 "gmi_ad4_pg4",
1819 "gmi_ad5_pg5",
1820 "gmi_ad6_pg6",
1821 "gmi_ad7_pg7",
1822 "gmi_wr_n_pi0",
1823 "gmi_oe_n_pi1",
1824 "gpio_x4_aud_px4",
1825 "gpio_x5_aud_px5",
1826 "gpio_x7_aud_px7",
1827
1828 "reset_out_n",
1829};
1830
1831static const char * const rsvd2_groups[] = {
1832 "pv0",
1833 "pv1",
1834 "sdmmc1_dat0_py7",
1835 "clk2_out_pw5",
1836 "clk2_req_pcc5",
1837 "hdmi_int_pn7",
1838 "ddc_scl_pv4",
1839 "ddc_sda_pv5",
1840 "uart3_txd_pw6",
1841 "uart3_rxd_pw7",
1842 "gen1_i2c_scl_pc4",
1843 "gen1_i2c_sda_pc5",
1844 "dap4_fs_pp4",
1845 "dap4_din_pp5",
1846 "dap4_dout_pp6",
1847 "dap4_sclk_pp7",
1848 "clk3_out_pee0",
1849 "clk3_req_pee1",
1850 "gmi_iordy_pi5",
1851 "gmi_a17_pb0",
1852 "gmi_a18_pb1",
1853 "gen2_i2c_scl_pt5",
1854 "gen2_i2c_sda_pt6",
1855 "sdmmc4_clk_pcc4",
1856 "sdmmc4_cmd_pt7",
1857 "sdmmc4_dat7_paa7",
1858 "pcc1",
1859 "pbb7",
1860 "pcc2",
1861 "pwr_i2c_scl_pz6",
1862 "pwr_i2c_sda_pz7",
1863 "kb_row0_pr0",
1864 "kb_row1_pr1",
1865 "kb_row2_pr2",
1866 "kb_row7_pr7",
1867 "kb_row8_ps0",
1868 "kb_row9_ps1",
1869 "kb_row10_ps2",
1870 "kb_col1_pq1",
1871 "kb_col2_pq2",
1872 "kb_col5_pq5",
1873 "kb_col6_pq6",
1874 "kb_col7_pq7",
1875 "sys_clk_req_pz5",
1876 "core_pwr_req",
1877 "cpu_pwr_req",
1878 "pwr_int_n",
1879 "owr",
1880 "spdif_out_pk5",
1881 "gpio_x1_aud_px1",
1882 "sdmmc3_clk_pa6",
1883 "sdmmc3_dat0_pb7",
1884 "gpio_w2_aud_pw2",
1885 "usb_vbus_en0_pn4",
1886 "usb_vbus_en1_pn5",
1887 "sdmmc3_clk_lb_out_pee4",
1888 "sdmmc3_clk_lb_in_pee5",
1889 "reset_out_n",
1890};
1891
1892static const char * const rsvd3_groups[] = {
1893 "pv0",
1894 "pv1",
1895 "sdmmc1_clk_pz0",
1896 "clk2_out_pw5",
1897 "clk2_req_pcc5",
1898 "hdmi_int_pn7",
1899 "ddc_scl_pv4",
1900 "ddc_sda_pv5",
1901 "uart2_rts_n_pj6",
1902 "uart2_cts_n_pj5",
1903 "uart3_txd_pw6",
1904 "uart3_rxd_pw7",
1905 "pu0",
1906 "pu1",
1907 "pu2",
1908 "gen1_i2c_scl_pc4",
1909 "gen1_i2c_sda_pc5",
1910 "dap4_din_pp5",
1911 "dap4_sclk_pp7",
1912 "clk3_out_pee0",
1913 "clk3_req_pee1",
1914 "pcc1",
1915 "cam_i2c_scl_pbb1",
1916 "cam_i2c_sda_pbb2",
1917 "pbb7",
1918 "pcc2",
1919 "pwr_i2c_scl_pz6",
1920 "pwr_i2c_sda_pz7",
1921 "kb_row0_pr0",
1922 "kb_row1_pr1",
1923 "kb_row2_pr2",
1924 "kb_row3_pr3",
1925 "kb_row9_ps1",
1926 "kb_row10_ps2",
1927 "clk_32k_out_pa0",
1928 "sys_clk_req_pz5",
1929 "core_pwr_req",
1930 "cpu_pwr_req",
1931 "pwr_int_n",
1932 "owr",
1933 "clk1_req_pee2",
1934 "clk1_out_pw4",
1935 "spdif_out_pk5",
1936 "spdif_in_pk6",
1937 "dap2_fs_pa2",
1938 "dap2_sclk_pa3",
1939 "dap2_din_pa4",
1940 "dap2_dout_pa5",
1941 "dvfs_pwm_px0",
1942 "gpio_x1_aud_px1",
1943 "gpio_x3_aud_px3",
1944 "dvfs_clk_px2",
1945 "sdmmc3_clk_pa6",
1946 "sdmmc3_dat0_pb7",
1947 "hdmi_cec_pee3",
1948 "sdmmc3_cd_n_pv2",
1949 "usb_vbus_en0_pn4",
1950 "usb_vbus_en1_pn5",
1951 "sdmmc3_clk_lb_out_pee4",
1952 "sdmmc3_clk_lb_in_pee5",
1953 "reset_out_n",
1954};
1955
1956static const char * const rsvd4_groups[] = {
1957 "pv0",
1958 "pv1",
1959 "sdmmc1_clk_pz0",
1960 "clk2_out_pw5",
1961 "clk2_req_pcc5",
1962 "hdmi_int_pn7",
1963 "ddc_scl_pv4",
1964 "ddc_sda_pv5",
1965 "pu0",
1966 "pu1",
1967 "pu2",
1968 "gen1_i2c_scl_pc4",
1969 "gen1_i2c_sda_pc5",
1970 "dap4_fs_pp4",
1971 "dap4_din_pp5",
1972 "dap4_dout_pp6",
1973 "dap4_sclk_pp7",
1974 "clk3_out_pee0",
1975 "clk3_req_pee1",
1976 "gmi_ad0_pg0",
1977 "gmi_ad1_pg1",
1978 "gmi_ad2_pg2",
1979 "gmi_ad3_pg3",
1980 "gmi_ad4_pg4",
1981 "gmi_ad12_ph4",
1982 "gmi_ad13_ph5",
1983 "gmi_rst_n_pi4",
1984 "gen2_i2c_scl_pt5",
1985 "gen2_i2c_sda_pt6",
1986 "sdmmc4_clk_pcc4",
1987 "sdmmc4_cmd_pt7",
1988 "sdmmc4_dat0_paa0",
1989 "sdmmc4_dat1_paa1",
1990 "sdmmc4_dat2_paa2",
1991 "sdmmc4_dat3_paa3",
1992 "sdmmc4_dat4_paa4",
1993 "sdmmc4_dat5_paa5",
1994 "sdmmc4_dat6_paa6",
1995 "sdmmc4_dat7_paa7",
1996 "cam_mclk_pcc0",
1997 "pcc1",
1998 "cam_i2c_scl_pbb1",
1999 "cam_i2c_sda_pbb2",
2000 "pbb3",
2001 "pbb4",
2002 "pbb5",
2003 "pbb6",
2004 "pbb7",
2005 "pcc2",
2006 "pwr_i2c_scl_pz6",
2007 "pwr_i2c_sda_pz7",
2008 "kb_row0_pr0",
2009 "kb_row1_pr1",
2010 "kb_row2_pr2",
2011 "kb_col2_pq2",
2012 "kb_col5_pq5",
2013 "kb_col6_pq6",
2014 "kb_col7_pq7",
2015 "clk_32k_out_pa0",
2016 "sys_clk_req_pz5",
2017 "core_pwr_req",
2018 "cpu_pwr_req",
2019 "pwr_int_n",
2020 "owr",
2021 "dap1_fs_pn0",
2022 "dap1_din_pn1",
2023 "dap1_dout_pn2",
2024 "dap1_sclk_pn3",
2025 "clk1_req_pee2",
2026 "clk1_out_pw4",
2027 "spdif_in_pk6",
2028 "spdif_out_pk5",
2029 "dap2_fs_pa2",
2030 "dap2_sclk_pa3",
2031 "dap2_din_pa4",
2032 "dap2_dout_pa5",
2033 "dvfs_pwm_px0",
2034 "gpio_x1_aud_px1",
2035 "gpio_x3_aud_px3",
2036 "dvfs_clk_px2",
2037 "gpio_x5_aud_px5",
2038 "gpio_x6_aud_px6",
2039 "gpio_x7_aud_px7",
2040 "sdmmc3_cd_n_pv2",
2041 "usb_vbus_en0_pn4",
2042 "usb_vbus_en1_pn5",
2043 "sdmmc3_clk_lb_in_pee5",
2044 "sdmmc3_clk_lb_out_pee4",
2045};
2046
2047static const char * const sdmmc1_groups[] = {
2048
2049 "sdmmc1_clk_pz0",
2050 "sdmmc1_cmd_pz1",
2051 "sdmmc1_dat3_py4",
2052 "sdmmc1_dat2_py5",
2053 "sdmmc1_dat1_py6",
2054 "sdmmc1_dat0_py7",
2055 "uart3_cts_n_pa1",
2056 "kb_col5_pq5",
2057 "sdmmc1_wp_n_pv3",
2058};
2059
2060static const char * const sdmmc2_groups[] = {
2061 "gmi_iordy_pi5",
2062 "gmi_clk_pk1",
2063 "gmi_cs2_n_pk3",
2064 "gmi_cs3_n_pk4",
2065 "gmi_cs7_n_pi6",
2066 "gmi_ad12_ph4",
2067 "gmi_ad13_ph5",
2068 "gmi_ad14_ph6",
2069 "gmi_ad15_ph7",
2070 "gmi_dqs_p_pj3",
2071};
2072
2073static const char * const sdmmc3_groups[] = {
2074 "kb_col4_pq4",
2075 "sdmmc3_clk_pa6",
2076 "sdmmc3_cmd_pa7",
2077 "sdmmc3_dat0_pb7",
2078 "sdmmc3_dat1_pb6",
2079 "sdmmc3_dat2_pb5",
2080 "sdmmc3_dat3_pb4",
2081 "hdmi_cec_pee3",
2082 "sdmmc3_cd_n_pv2",
2083 "sdmmc3_clk_lb_in_pee5",
2084 "sdmmc3_clk_lb_out_pee4",
2085};
2086
2087static const char * const sdmmc4_groups[] = {
2088 "sdmmc4_clk_pcc4",
2089 "sdmmc4_cmd_pt7",
2090 "sdmmc4_dat0_paa0",
2091 "sdmmc4_dat1_paa1",
2092 "sdmmc4_dat2_paa2",
2093 "sdmmc4_dat3_paa3",
2094 "sdmmc4_dat4_paa4",
2095 "sdmmc4_dat5_paa5",
2096 "sdmmc4_dat6_paa6",
2097 "sdmmc4_dat7_paa7",
2098};
2099
2100static const char * const soc_groups[] = {
2101 "gmi_cs1_n_pj2",
2102 "gmi_oe_n_pi1",
2103 "clk_32k_out_pa0",
2104 "hdmi_cec_pee3",
2105};
2106
2107static const char * const spdif_groups[] = {
2108 "sdmmc1_cmd_pz1",
2109 "sdmmc1_dat3_py4",
2110 "uart2_rxd_pc3",
2111 "uart2_txd_pc2",
2112 "spdif_in_pk6",
2113 "spdif_out_pk5",
2114};
2115
2116static const char * const spi1_groups[] = {
2117 "ulpi_clk_py0",
2118 "ulpi_dir_py1",
2119 "ulpi_nxt_py2",
2120 "ulpi_stp_py3",
2121 "gpio_x3_aud_px3",
2122 "gpio_x4_aud_px4",
2123 "gpio_x5_aud_px5",
2124 "gpio_x6_aud_px6",
2125 "gpio_x7_aud_px7",
2126 "gpio_w3_aud_pw3",
2127};
2128
2129static const char * const spi2_groups[] = {
2130 "ulpi_data4_po5",
2131 "ulpi_data5_po6",
2132 "ulpi_data6_po7",
2133 "ulpi_data7_po0",
2134 "kb_row4_pr4",
2135 "kb_row5_pr5",
2136 "kb_col0_pq0",
2137 "kb_col1_pq1",
2138 "kb_col2_pq2",
2139 "kb_col6_pq6",
2140 "kb_col7_pq7",
2141 "gpio_x4_aud_px4",
2142 "gpio_x5_aud_px5",
2143 "gpio_x6_aud_px6",
2144 "gpio_x7_aud_px7",
2145 "gpio_w2_aud_pw2",
2146 "gpio_w3_aud_pw3",
2147};
2148
2149static const char * const spi3_groups[] = {
2150 "ulpi_data0_po1",
2151 "ulpi_data1_po2",
2152 "ulpi_data2_po3",
2153 "ulpi_data3_po4",
2154 "sdmmc4_dat0_paa0",
2155 "sdmmc4_dat1_paa1",
2156 "sdmmc4_dat2_paa2",
2157 "sdmmc4_dat3_paa3",
2158 "sdmmc4_dat4_paa4",
2159 "sdmmc4_dat5_paa5",
2160 "sdmmc4_dat6_paa6",
2161 "sdmmc3_clk_pa6",
2162 "sdmmc3_cmd_pa7",
2163 "sdmmc3_dat0_pb7",
2164 "sdmmc3_dat1_pb6",
2165 "sdmmc3_dat2_pb5",
2166 "sdmmc3_dat3_pb4",
2167};
2168
2169static const char * const spi4_groups[] = {
2170 "sdmmc1_cmd_pz1",
2171 "sdmmc1_dat3_py4",
2172 "sdmmc1_dat2_py5",
2173 "sdmmc1_dat1_py6",
2174 "sdmmc1_dat0_py7",
2175 "uart2_rxd_pc3",
2176 "uart2_txd_pc2",
2177 "uart2_rts_n_pj6",
2178 "uart2_cts_n_pj5",
2179 "uart3_txd_pw6",
2180 "uart3_rxd_pw7",
2181 "uart3_cts_n_pa1",
2182 "gmi_wait_pi7",
2183 "gmi_cs6_n_pi3",
2184 "gmi_ad5_pg5",
2185 "gmi_ad6_pg6",
2186 "gmi_ad7_pg7",
2187 "gmi_a19_pk7",
2188 "gmi_wr_n_pi0",
2189 "sdmmc1_wp_n_pv3",
2190};
2191
2192static const char * const spi5_groups[] = {
2193 "ulpi_clk_py0",
2194 "ulpi_dir_py1",
2195 "ulpi_nxt_py2",
2196 "ulpi_stp_py3",
2197 "dap3_fs_pp0",
2198 "dap3_din_pp1",
2199 "dap3_dout_pp2",
2200 "dap3_sclk_pp3",
2201};
2202
2203static const char * const spi6_groups[] = {
2204 "dvfs_pwm_px0",
2205 "gpio_x1_aud_px1",
2206 "gpio_x3_aud_px3",
2207 "dvfs_clk_px2",
2208 "gpio_x6_aud_px6",
2209 "gpio_w2_aud_pw2",
2210 "gpio_w3_aud_pw3",
2211};
2212
2213static const char * const sysclk_groups[] = {
2214 "sys_clk_req_pz5",
2215};
2216
2217static const char * const trace_groups[] = {
2218 "gmi_iordy_pi5",
2219 "gmi_adv_n_pk0",
2220 "gmi_clk_pk1",
2221 "gmi_cs2_n_pk3",
2222 "gmi_cs4_n_pk2",
2223 "gmi_a16_pj7",
2224 "gmi_a17_pb0",
2225 "gmi_a18_pb1",
2226 "gmi_a19_pk7",
2227 "gmi_dqs_p_pj3",
2228};
2229
2230static const char * const uarta_groups[] = {
2231 "ulpi_data0_po1",
2232 "ulpi_data1_po2",
2233 "ulpi_data2_po3",
2234 "ulpi_data3_po4",
2235 "ulpi_data4_po5",
2236 "ulpi_data5_po6",
2237 "ulpi_data6_po7",
2238 "ulpi_data7_po0",
2239 "sdmmc1_cmd_pz1",
2240 "sdmmc1_dat3_py4",
2241 "sdmmc1_dat2_py5",
2242 "sdmmc1_dat1_py6",
2243 "sdmmc1_dat0_py7",
2244 "uart2_rxd_pc3",
2245 "uart2_txd_pc2",
2246 "uart2_rts_n_pj6",
2247 "uart2_cts_n_pj5",
2248 "pu0",
2249 "pu1",
2250 "pu2",
2251 "pu3",
2252 "pu4",
2253 "pu5",
2254 "pu6",
2255 "kb_row7_pr7",
2256 "kb_row8_ps0",
2257 "kb_row9_ps1",
2258 "kb_row10_ps2",
2259 "kb_col3_pq3",
2260 "kb_col4_pq4",
2261 "sdmmc3_cmd_pa7",
2262 "sdmmc3_dat1_pb6",
2263 "sdmmc1_wp_n_pv3",
2264};
2265
2266static const char * const uartb_groups[] = {
2267 "uart2_rts_n_pj6",
2268 "uart2_cts_n_pj5",
2269};
2270
2271static const char * const uartc_groups[] = {
2272 "uart3_txd_pw6",
2273 "uart3_rxd_pw7",
2274 "uart3_cts_n_pa1",
2275 "uart3_rts_n_pc0",
2276};
2277
2278static const char * const uartd_groups[] = {
2279 "ulpi_clk_py0",
2280 "ulpi_dir_py1",
2281 "ulpi_nxt_py2",
2282 "ulpi_stp_py3",
2283 "gmi_a16_pj7",
2284 "gmi_a17_pb0",
2285 "gmi_a18_pb1",
2286 "gmi_a19_pk7",
2287};
2288
2289static const char * const ulpi_groups[] = {
2290 "ulpi_data0_po1",
2291 "ulpi_data1_po2",
2292 "ulpi_data2_po3",
2293 "ulpi_data3_po4",
2294 "ulpi_data4_po5",
2295 "ulpi_data5_po6",
2296 "ulpi_data6_po7",
2297 "ulpi_data7_po0",
2298 "ulpi_clk_py0",
2299 "ulpi_dir_py1",
2300 "ulpi_nxt_py2",
2301 "ulpi_stp_py3",
2302};
2303
2304static const char * const usb_groups[] = {
2305 "pv0",
2306 "pu6",
2307 "gmi_cs0_n_pj0",
2308 "gmi_cs4_n_pk2",
2309 "gmi_ad11_ph3",
2310 "kb_col0_pq0",
2311 "spdif_in_pk6",
2312 "usb_vbus_en0_pn4",
2313 "usb_vbus_en1_pn5",
2314};
2315
2316static const char * const vgp1_groups[] = {
2317 "cam_i2c_scl_pbb1",
2318};
2319
2320static const char * const vgp2_groups[] = {
2321 "cam_i2c_sda_pbb2",
2322};
2323
2324static const char * const vgp3_groups[] = {
2325 "pbb3",
2326};
2327
2328static const char * const vgp4_groups[] = {
2329 "pbb4",
2330};
2331
2332static const char * const vgp5_groups[] = {
2333 "pbb5",
2334};
2335
2336static const char * const vgp6_groups[] = {
2337 "pbb6",
2338};
2339
2340static const char * const vi_groups[] = {
2341 "cam_mclk_pcc0",
2342 "pbb0",
2343};
2344
2345static const char * const vi_alt1_groups[] = {
2346 "cam_mclk_pcc0",
2347 "pbb0",
2348};
2349
2350static const char * const vi_alt3_groups[] = {
2351 "cam_mclk_pcc0",
2352 "pbb0",
2353};
2354
2355#define FUNCTION(fname) \ 1461#define FUNCTION(fname) \
2356 { \ 1462 { \
2357 .name = #fname, \ 1463 .name = #fname, \
2358 .groups = fname##_groups, \
2359 .ngroups = ARRAY_SIZE(fname##_groups), \
2360 } 1464 }
2361 1465
2362static const struct tegra_function tegra114_functions[] = { 1466static struct tegra_function tegra114_functions[] = {
2363 FUNCTION(blink), 1467 FUNCTION(blink),
2364 FUNCTION(cec), 1468 FUNCTION(cec),
2365 FUNCTION(cldvfs), 1469 FUNCTION(cldvfs),
1470 FUNCTION(clk),
2366 FUNCTION(clk12), 1471 FUNCTION(clk12),
2367 FUNCTION(cpu), 1472 FUNCTION(cpu),
2368 FUNCTION(dap), 1473 FUNCTION(dap),
@@ -2407,6 +1512,7 @@ static const struct tegra_function tegra114_functions[] = {
2407 FUNCTION(rsvd2), 1512 FUNCTION(rsvd2),
2408 FUNCTION(rsvd3), 1513 FUNCTION(rsvd3),
2409 FUNCTION(rsvd4), 1514 FUNCTION(rsvd4),
1515 FUNCTION(rtck),
2410 FUNCTION(sdmmc1), 1516 FUNCTION(sdmmc1),
2411 FUNCTION(sdmmc2), 1517 FUNCTION(sdmmc2),
2412 FUNCTION(sdmmc3), 1518 FUNCTION(sdmmc3),
@@ -2438,11 +1544,11 @@ static const struct tegra_function tegra114_functions[] = {
2438 FUNCTION(vi_alt3), 1544 FUNCTION(vi_alt3),
2439}; 1545};
2440 1546
2441#define DRV_PINGROUP_REG_START 0x868 /* bank 0 */ 1547#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
2442#define PINGROUP_REG_START 0x3000 /* bank 1 */ 1548#define PINGROUP_REG_A 0x3000 /* bank 1 */
2443 1549
2444#define PINGROUP_REG_Y(r) ((r) - PINGROUP_REG_START) 1550#define PINGROUP_REG_Y(r) ((r) - PINGROUP_REG_A)
2445#define PINGROUP_REG_N(r) -1 1551#define PINGROUP_REG_N(r) -1
2446 1552
2447#define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior, rcv_sel) \ 1553#define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior, rcv_sel) \
2448 { \ 1554 { \
@@ -2484,13 +1590,14 @@ static const struct tegra_function tegra114_functions[] = {
2484 .drvtype_reg = -1, \ 1590 .drvtype_reg = -1, \
2485 } 1591 }
2486 1592
2487#define DRV_PINGROUP_DVRTYPE_Y(r) ((r) - DRV_PINGROUP_REG_START) 1593#define DRV_PINGROUP_REG_Y(r) ((r) - DRV_PINGROUP_REG_A)
2488#define DRV_PINGROUP_DVRTYPE_N(r) -1 1594#define DRV_PINGROUP_REG_N(r) -1
1595
2489 1596
2490#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \ 1597#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \
2491 drvdn_b, drvdn_w, drvup_b, drvup_w, \ 1598 drvdn_b, drvdn_w, drvup_b, drvup_w, \
2492 slwr_b, slwr_w, slwf_b, slwf_w, \ 1599 slwr_b, slwr_w, slwf_b, slwf_w, \
2493 drvtype) \ 1600 drvtype) \
2494 { \ 1601 { \
2495 .name = "drive_" #pg_name, \ 1602 .name = "drive_" #pg_name, \
2496 .pins = drive_##pg_name##_pins, \ 1603 .pins = drive_##pg_name##_pins, \
@@ -2503,7 +1610,7 @@ static const struct tegra_function tegra114_functions[] = {
2503 .lock_reg = -1, \ 1610 .lock_reg = -1, \
2504 .ioreset_reg = -1, \ 1611 .ioreset_reg = -1, \
2505 .rcv_sel_reg = -1, \ 1612 .rcv_sel_reg = -1, \
2506 .drv_reg = DRV_PINGROUP_DVRTYPE_Y(r), \ 1613 .drv_reg = DRV_PINGROUP_REG_Y(r), \
2507 .drv_bank = 0, \ 1614 .drv_bank = 0, \
2508 .hsm_bit = hsm_b, \ 1615 .hsm_bit = hsm_b, \
2509 .schmitt_bit = schmitt_b, \ 1616 .schmitt_bit = schmitt_b, \
@@ -2516,14 +1623,13 @@ static const struct tegra_function tegra114_functions[] = {
2516 .slwr_width = slwr_w, \ 1623 .slwr_width = slwr_w, \
2517 .slwf_bit = slwf_b, \ 1624 .slwf_bit = slwf_b, \
2518 .slwf_width = slwf_w, \ 1625 .slwf_width = slwf_w, \
2519 .drvtype_reg = DRV_PINGROUP_DVRTYPE_##drvtype(r), \ 1626 .drvtype_reg = DRV_PINGROUP_REG_##drvtype(r), \
2520 .drvtype_bank = 0, \ 1627 .drvtype_bank = 0, \
2521 .drvtype_bit = 6, \ 1628 .drvtype_bit = 6, \
2522 } 1629 }
2523 1630
2524static const struct tegra_pingroup tegra114_groups[] = { 1631static const struct tegra_pingroup tegra114_groups[] = {
2525 /* pg_name, f0, f1, f2, f3, safe, r, od, ior, rcv_sel */ 1632 /* pg_name, f0, f1, f2, f3, safe, r, od, ior, rcv_sel */
2526 /* FIXME: Fill in correct data in safe column */
2527 PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, ULPI, 0x3000, N, N, N), 1633 PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, ULPI, 0x3000, N, N, N),
2528 PINGROUP(ulpi_data1_po2, SPI3, HSI, UARTA, ULPI, ULPI, 0x3004, N, N, N), 1634 PINGROUP(ulpi_data1_po2, SPI3, HSI, UARTA, ULPI, ULPI, 0x3004, N, N, N),
2529 PINGROUP(ulpi_data2_po3, SPI3, HSI, UARTA, ULPI, ULPI, 0x3008, N, N, N), 1635 PINGROUP(ulpi_data2_po3, SPI3, HSI, UARTA, ULPI, ULPI, 0x3008, N, N, N),
@@ -2635,6 +1741,7 @@ static const struct tegra_pingroup tegra114_groups[] = {
2635 PINGROUP(pbb6, VGP6, DISPLAYA, DISPLAYB, RSVD4, RSVD4, 0x32a4, N, N, N), 1741 PINGROUP(pbb6, VGP6, DISPLAYA, DISPLAYB, RSVD4, RSVD4, 0x32a4, N, N, N),
2636 PINGROUP(pbb7, I2S4, RSVD2, RSVD3, RSVD4, RSVD4, 0x32a8, N, N, N), 1742 PINGROUP(pbb7, I2S4, RSVD2, RSVD3, RSVD4, RSVD4, 0x32a8, N, N, N),
2637 PINGROUP(pcc2, I2S4, RSVD2, RSVD3, RSVD4, RSVD4, 0x32ac, N, N, N), 1743 PINGROUP(pcc2, I2S4, RSVD2, RSVD3, RSVD4, RSVD4, 0x32ac, N, N, N),
1744 PINGROUP(jtag_rtck, RTCK, RSVD2, RSVD3, RSVD4, RTCK, 0x32b0, N, N, N),
2638 PINGROUP(pwr_i2c_scl_pz6, I2CPWR, RSVD2, RSVD3, RSVD4, RSVD4, 0x32b4, Y, N, N), 1745 PINGROUP(pwr_i2c_scl_pz6, I2CPWR, RSVD2, RSVD3, RSVD4, RSVD4, 0x32b4, Y, N, N),
2639 PINGROUP(pwr_i2c_sda_pz7, I2CPWR, RSVD2, RSVD3, RSVD4, RSVD4, 0x32b8, Y, N, N), 1746 PINGROUP(pwr_i2c_sda_pz7, I2CPWR, RSVD2, RSVD3, RSVD4, RSVD4, 0x32b8, Y, N, N),
2640 PINGROUP(kb_row0_pr0, KBC, RSVD2, RSVD3, RSVD4, RSVD4, 0x32bc, N, N, N), 1747 PINGROUP(kb_row0_pr0, KBC, RSVD2, RSVD3, RSVD4, RSVD4, 0x32bc, N, N, N),
@@ -2661,6 +1768,7 @@ static const struct tegra_pingroup tegra114_groups[] = {
2661 PINGROUP(core_pwr_req, PWRON, RSVD2, RSVD3, RSVD4, RSVD4, 0x3324, N, N, N), 1768 PINGROUP(core_pwr_req, PWRON, RSVD2, RSVD3, RSVD4, RSVD4, 0x3324, N, N, N),
2662 PINGROUP(cpu_pwr_req, CPU, RSVD2, RSVD3, RSVD4, RSVD4, 0x3328, N, N, N), 1769 PINGROUP(cpu_pwr_req, CPU, RSVD2, RSVD3, RSVD4, RSVD4, 0x3328, N, N, N),
2663 PINGROUP(pwr_int_n, PMI, RSVD2, RSVD3, RSVD4, RSVD4, 0x332c, N, N, N), 1770 PINGROUP(pwr_int_n, PMI, RSVD2, RSVD3, RSVD4, RSVD4, 0x332c, N, N, N),
1771 PINGROUP(clk_32k_in, CLK, RSVD2, RSVD3, RSVD4, CLK, 0x3330, N, N, N),
2664 PINGROUP(owr, OWR, RSVD2, RSVD3, RSVD4, RSVD4, 0x3334, N, N, Y), 1772 PINGROUP(owr, OWR, RSVD2, RSVD3, RSVD4, RSVD4, 0x3334, N, N, Y),
2665 PINGROUP(dap1_fs_pn0, I2S0, HDA, GMI, RSVD4, RSVD4, 0x3338, N, N, N), 1773 PINGROUP(dap1_fs_pn0, I2S0, HDA, GMI, RSVD4, RSVD4, 0x3338, N, N, N),
2666 PINGROUP(dap1_din_pn1, I2S0, HDA, GMI, RSVD4, RSVD4, 0x333c, N, N, N), 1774 PINGROUP(dap1_din_pn1, I2S0, HDA, GMI, RSVD4, RSVD4, 0x333c, N, N, N),
@@ -2697,38 +1805,48 @@ static const struct tegra_pingroup tegra114_groups[] = {
2697 PINGROUP(usb_vbus_en1_pn5, USB, RSVD2, RSVD3, RSVD4, RSVD4, 0x33f8, Y, N, N), 1805 PINGROUP(usb_vbus_en1_pn5, USB, RSVD2, RSVD3, RSVD4, RSVD4, 0x33f8, Y, N, N),
2698 PINGROUP(sdmmc3_clk_lb_in_pee5, SDMMC3, RSVD2, RSVD3, RSVD4, RSVD4, 0x33fc, N, N, N), 1806 PINGROUP(sdmmc3_clk_lb_in_pee5, SDMMC3, RSVD2, RSVD3, RSVD4, RSVD4, 0x33fc, N, N, N),
2699 PINGROUP(sdmmc3_clk_lb_out_pee4, SDMMC3, RSVD2, RSVD3, RSVD4, RSVD4, 0x3400, N, N, N), 1807 PINGROUP(sdmmc3_clk_lb_out_pee4, SDMMC3, RSVD2, RSVD3, RSVD4, RSVD4, 0x3400, N, N, N),
1808 PINGROUP(gmi_clk_lb, SDMMC2, NAND, GMI, RSVD4, GMI, 0x3404, N, N, N),
2700 PINGROUP(reset_out_n, RSVD1, RSVD2, RSVD3, RESET_OUT_N, RSVD3, 0x3408, N, N, N), 1809 PINGROUP(reset_out_n, RSVD1, RSVD2, RSVD3, RESET_OUT_N, RSVD3, 0x3408, N, N, N),
2701 1810
2702 /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w, drvtype */ 1811 /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w, drvtype */
2703 DRV_PINGROUP(ao1, 0x868, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1812 DRV_PINGROUP(ao1, 0x868, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2704 DRV_PINGROUP(ao2, 0x86c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1813 DRV_PINGROUP(ao2, 0x86c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2705 DRV_PINGROUP(at1, 0x870, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y), 1814 DRV_PINGROUP(at1, 0x870, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, Y),
2706 DRV_PINGROUP(at2, 0x874, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y), 1815 DRV_PINGROUP(at2, 0x874, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, Y),
2707 DRV_PINGROUP(at3, 0x878, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y), 1816 DRV_PINGROUP(at3, 0x878, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, Y),
2708 DRV_PINGROUP(at4, 0x87c, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y), 1817 DRV_PINGROUP(at4, 0x87c, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, Y),
2709 DRV_PINGROUP(at5, 0x880, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N), 1818 DRV_PINGROUP(at5, 0x880, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
2710 DRV_PINGROUP(cdev1, 0x884, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1819 DRV_PINGROUP(cdev1, 0x884, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2711 DRV_PINGROUP(cdev2, 0x888, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1820 DRV_PINGROUP(cdev2, 0x888, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2712 DRV_PINGROUP(dap1, 0x890, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1821 DRV_PINGROUP(dap1, 0x890, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2713 DRV_PINGROUP(dap2, 0x894, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1822 DRV_PINGROUP(dap2, 0x894, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2714 DRV_PINGROUP(dap3, 0x898, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1823 DRV_PINGROUP(dap3, 0x898, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2715 DRV_PINGROUP(dap4, 0x89c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1824 DRV_PINGROUP(dap4, 0x89c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2716 DRV_PINGROUP(dbg, 0x8a0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1825 DRV_PINGROUP(dbg, 0x8a0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2717 DRV_PINGROUP(sdio3, 0x8b0, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N), 1826 DRV_PINGROUP(sdio3, 0x8b0, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N),
2718 DRV_PINGROUP(spi, 0x8b4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1827 DRV_PINGROUP(spi, 0x8b4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2719 DRV_PINGROUP(uaa, 0x8b8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1828 DRV_PINGROUP(uaa, 0x8b8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2720 DRV_PINGROUP(uab, 0x8bc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1829 DRV_PINGROUP(uab, 0x8bc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2721 DRV_PINGROUP(uart2, 0x8c0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1830 DRV_PINGROUP(uart2, 0x8c0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2722 DRV_PINGROUP(uart3, 0x8c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1831 DRV_PINGROUP(uart3, 0x8c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2723 DRV_PINGROUP(sdio1, 0x8ec, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N), 1832 DRV_PINGROUP(sdio1, 0x8ec, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N),
2724 DRV_PINGROUP(ddc, 0x8fc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1833 DRV_PINGROUP(ddc, 0x8fc, 2, 3, -1, 12, 5, 20, 5, 28, 2, 30, 2, N),
2725 DRV_PINGROUP(gma, 0x900, 2, 3, 4, 14, 5, 20, 5, 28, 2, 30, 2, Y), 1834 DRV_PINGROUP(gma, 0x900, 2, 3, -1, 14, 5, 20, 5, 28, 2, 30, 2, N),
2726 DRV_PINGROUP(gme, 0x910, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N), 1835 DRV_PINGROUP(gme, 0x910, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
2727 DRV_PINGROUP(gmf, 0x914, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N), 1836 DRV_PINGROUP(gmf, 0x914, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
2728 DRV_PINGROUP(gmg, 0x918, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N), 1837 DRV_PINGROUP(gmg, 0x918, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
2729 DRV_PINGROUP(gmh, 0x91c, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N), 1838 DRV_PINGROUP(gmh, 0x91c, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
2730 DRV_PINGROUP(owr, 0x920, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1839 DRV_PINGROUP(owr, 0x920, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2731 DRV_PINGROUP(uda, 0x924, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1840 DRV_PINGROUP(uda, 0x924, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
1841 DRV_PINGROUP(dev3, 0x92c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
1842 DRV_PINGROUP(cec, 0x938, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
1843 DRV_PINGROUP(at6, 0x994, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, Y),
1844 DRV_PINGROUP(dap5, 0x998, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
1845 DRV_PINGROUP(usb_vbus_en, 0x99c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
1846 DRV_PINGROUP(ao3, 0x9a0, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N),
1847 DRV_PINGROUP(hv0, 0x9a4, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N),
1848 DRV_PINGROUP(sdio4, 0x9a8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
1849 DRV_PINGROUP(ao0, 0x9ac, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2732}; 1850};
2733 1851
2734static const struct tegra_pinctrl_soc_data tegra114_pinctrl = { 1852static const struct tegra_pinctrl_soc_data tegra114_pinctrl = {
diff --git a/drivers/pinctrl/pinctrl-tegra124.c b/drivers/pinctrl/pinctrl-tegra124.c
index c20e0e1dda83..73773706755b 100644
--- a/drivers/pinctrl/pinctrl-tegra124.c
+++ b/drivers/pinctrl/pinctrl-tegra124.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Pinctrl data for the NVIDIA Tegra124 pinmux 2 * Pinctrl data for the NVIDIA Tegra124 pinmux
3 * 3 *
4 * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License, 7 * under the terms and conditions of the GNU General Public License,
@@ -212,8 +212,8 @@
212#define TEGRA_PIN_PFF2 _GPIO(250) 212#define TEGRA_PIN_PFF2 _GPIO(250)
213 213
214/* All non-GPIO pins follow */ 214/* All non-GPIO pins follow */
215#define NUM_GPIOS (TEGRA_PIN_PFF2 + 1) 215#define NUM_GPIOS (TEGRA_PIN_PFF2 + 1)
216#define _PIN(offset) (NUM_GPIOS + (offset)) 216#define _PIN(offset) (NUM_GPIOS + (offset))
217 217
218/* Non-GPIO pins */ 218/* Non-GPIO pins */
219#define TEGRA_PIN_CORE_PWR_REQ _PIN(0) 219#define TEGRA_PIN_CORE_PWR_REQ _PIN(0)
@@ -325,13 +325,13 @@ static const struct pinctrl_pin_desc tegra124_pins[] = {
325 PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"), 325 PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
326 PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"), 326 PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
327 PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"), 327 PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
328 PINCTRL_PIN(TEGRA_PIN_KB_ROW11_PS3, "KB_ROW10 PS3"), 328 PINCTRL_PIN(TEGRA_PIN_KB_ROW11_PS3, "KB_ROW11 PS3"),
329 PINCTRL_PIN(TEGRA_PIN_KB_ROW12_PS4, "KB_ROW10 PS4"), 329 PINCTRL_PIN(TEGRA_PIN_KB_ROW12_PS4, "KB_ROW12 PS4"),
330 PINCTRL_PIN(TEGRA_PIN_KB_ROW13_PS5, "KB_ROW10 PS5"), 330 PINCTRL_PIN(TEGRA_PIN_KB_ROW13_PS5, "KB_ROW13 PS5"),
331 PINCTRL_PIN(TEGRA_PIN_KB_ROW14_PS6, "KB_ROW10 PS6"), 331 PINCTRL_PIN(TEGRA_PIN_KB_ROW14_PS6, "KB_ROW14 PS6"),
332 PINCTRL_PIN(TEGRA_PIN_KB_ROW15_PS7, "KB_ROW10 PS7"), 332 PINCTRL_PIN(TEGRA_PIN_KB_ROW15_PS7, "KB_ROW15 PS7"),
333 PINCTRL_PIN(TEGRA_PIN_KB_ROW16_PT0, "KB_ROW10 PT0"), 333 PINCTRL_PIN(TEGRA_PIN_KB_ROW16_PT0, "KB_ROW16 PT0"),
334 PINCTRL_PIN(TEGRA_PIN_KB_ROW17_PT1, "KB_ROW10 PT1"), 334 PINCTRL_PIN(TEGRA_PIN_KB_ROW17_PT1, "KB_ROW17 PT1"),
335 PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"), 335 PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
336 PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"), 336 PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
337 PINCTRL_PIN(TEGRA_PIN_SDMMC4_CMD_PT7, "SDMMC4_CMD PT7"), 337 PINCTRL_PIN(TEGRA_PIN_SDMMC4_CMD_PT7, "SDMMC4_CMD PT7"),
@@ -406,16 +406,16 @@ static const struct pinctrl_pin_desc tegra124_pins[] = {
406 PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PEE3, "HDMI_CEC PEE3"), 406 PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PEE3, "HDMI_CEC PEE3"),
407 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4, "SDMMC3_CLK_LB_OUT PEE4"), 407 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4, "SDMMC3_CLK_LB_OUT PEE4"),
408 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, "SDMMC3_CLK_LB_IN PEE5"), 408 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, "SDMMC3_CLK_LB_IN PEE5"),
409 PINCTRL_PIN(TEGRA_PIN_DP_HPD_PFF0, "DP_HPD PFF0"),
410 PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN2_PFF1, "USB_VBUS_EN2 PFF1"),
411 PINCTRL_PIN(TEGRA_PIN_PFF2, "PFF2"),
409 PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"), 412 PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
410 PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"), 413 PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
411 PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
412 PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"), 414 PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
415 PINCTRL_PIN(TEGRA_PIN_GMI_CLK_LB, "GMI_CLK_LB"),
413 PINCTRL_PIN(TEGRA_PIN_RESET_OUT_N, "RESET_OUT_N"), 416 PINCTRL_PIN(TEGRA_PIN_RESET_OUT_N, "RESET_OUT_N"),
414 PINCTRL_PIN(TEGRA_PIN_DP_HPD_PFF0, "DP_HPD PFF0"), 417 PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
415 PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN2_PFF1, "USB_VBUS_EN2 PFF1"),
416 PINCTRL_PIN(TEGRA_PIN_PFF2, "PFF2"),
417 PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"), 418 PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
418 PINCTRL_PIN(TEGRA_PIN_GMI_CLK_LB, "GMI_CLK_LB"),
419 PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"), 419 PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"),
420}; 420};
421 421
@@ -1138,6 +1138,7 @@ static const unsigned sdmmc3_clk_lb_out_pee4_pins[] = {
1138static const unsigned sdmmc3_clk_lb_in_pee5_pins[] = { 1138static const unsigned sdmmc3_clk_lb_in_pee5_pins[] = {
1139 TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, 1139 TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
1140}; 1140};
1141
1141static const unsigned dp_hpd_pff0_pins[] = { 1142static const unsigned dp_hpd_pff0_pins[] = {
1142 TEGRA_PIN_DP_HPD_PFF0, 1143 TEGRA_PIN_DP_HPD_PFF0,
1143}; 1144};
@@ -1158,24 +1159,24 @@ static const unsigned cpu_pwr_req_pins[] = {
1158 TEGRA_PIN_CPU_PWR_REQ, 1159 TEGRA_PIN_CPU_PWR_REQ,
1159}; 1160};
1160 1161
1161static const unsigned owr_pins[] = {
1162 TEGRA_PIN_OWR,
1163};
1164
1165static const unsigned pwr_int_n_pins[] = { 1162static const unsigned pwr_int_n_pins[] = {
1166 TEGRA_PIN_PWR_INT_N, 1163 TEGRA_PIN_PWR_INT_N,
1167}; 1164};
1168 1165
1166static const unsigned gmi_clk_lb_pins[] = {
1167 TEGRA_PIN_GMI_CLK_LB,
1168};
1169
1169static const unsigned reset_out_n_pins[] = { 1170static const unsigned reset_out_n_pins[] = {
1170 TEGRA_PIN_RESET_OUT_N, 1171 TEGRA_PIN_RESET_OUT_N,
1171}; 1172};
1172 1173
1173static const unsigned clk_32k_in_pins[] = { 1174static const unsigned owr_pins[] = {
1174 TEGRA_PIN_CLK_32K_IN, 1175 TEGRA_PIN_OWR,
1175}; 1176};
1176 1177
1177static const unsigned gmi_clk_lb_pins[] = { 1178static const unsigned clk_32k_in_pins[] = {
1178 TEGRA_PIN_GMI_CLK_LB, 1179 TEGRA_PIN_CLK_32K_IN,
1179}; 1180};
1180 1181
1181static const unsigned jtag_rtck_pins[] = { 1182static const unsigned jtag_rtck_pins[] = {
@@ -1441,15 +1442,15 @@ static const unsigned drive_gpv_pins[] = {
1441 TEGRA_PIN_PFF2, 1442 TEGRA_PIN_PFF2,
1442}; 1443};
1443 1444
1444static const unsigned drive_cec_pins[] = {
1445 TEGRA_PIN_HDMI_CEC_PEE3,
1446};
1447
1448static const unsigned drive_dev3_pins[] = { 1445static const unsigned drive_dev3_pins[] = {
1449 TEGRA_PIN_CLK3_OUT_PEE0, 1446 TEGRA_PIN_CLK3_OUT_PEE0,
1450 TEGRA_PIN_CLK3_REQ_PEE1, 1447 TEGRA_PIN_CLK3_REQ_PEE1,
1451}; 1448};
1452 1449
1450static const unsigned drive_cec_pins[] = {
1451 TEGRA_PIN_HDMI_CEC_PEE3,
1452};
1453
1453static const unsigned drive_at6_pins[] = { 1454static const unsigned drive_at6_pins[] = {
1454 TEGRA_PIN_PK1, 1455 TEGRA_PIN_PK1,
1455 TEGRA_PIN_PK3, 1456 TEGRA_PIN_PK3,
@@ -1496,8 +1497,10 @@ static const unsigned drive_ao4_pins[] = {
1496 1497
1497enum tegra_mux { 1498enum tegra_mux {
1498 TEGRA_MUX_BLINK, 1499 TEGRA_MUX_BLINK,
1500 TEGRA_MUX_CCLA,
1499 TEGRA_MUX_CEC, 1501 TEGRA_MUX_CEC,
1500 TEGRA_MUX_CLDVFS, 1502 TEGRA_MUX_CLDVFS,
1503 TEGRA_MUX_CLK,
1501 TEGRA_MUX_CLK12, 1504 TEGRA_MUX_CLK12,
1502 TEGRA_MUX_CPU, 1505 TEGRA_MUX_CPU,
1503 TEGRA_MUX_DAP, 1506 TEGRA_MUX_DAP,
@@ -1507,6 +1510,7 @@ enum tegra_mux {
1507 TEGRA_MUX_DISPLAYA, 1510 TEGRA_MUX_DISPLAYA,
1508 TEGRA_MUX_DISPLAYA_ALT, 1511 TEGRA_MUX_DISPLAYA_ALT,
1509 TEGRA_MUX_DISPLAYB, 1512 TEGRA_MUX_DISPLAYB,
1513 TEGRA_MUX_DP,
1510 TEGRA_MUX_DTV, 1514 TEGRA_MUX_DTV,
1511 TEGRA_MUX_EXTPERIPH1, 1515 TEGRA_MUX_EXTPERIPH1,
1512 TEGRA_MUX_EXTPERIPH2, 1516 TEGRA_MUX_EXTPERIPH2,
@@ -1528,6 +1532,9 @@ enum tegra_mux {
1528 TEGRA_MUX_IRDA, 1532 TEGRA_MUX_IRDA,
1529 TEGRA_MUX_KBC, 1533 TEGRA_MUX_KBC,
1530 TEGRA_MUX_OWR, 1534 TEGRA_MUX_OWR,
1535 TEGRA_MUX_PE,
1536 TEGRA_MUX_PE0,
1537 TEGRA_MUX_PE1,
1531 TEGRA_MUX_PMI, 1538 TEGRA_MUX_PMI,
1532 TEGRA_MUX_PWM0, 1539 TEGRA_MUX_PWM0,
1533 TEGRA_MUX_PWM1, 1540 TEGRA_MUX_PWM1,
@@ -1539,6 +1546,8 @@ enum tegra_mux {
1539 TEGRA_MUX_RSVD2, 1546 TEGRA_MUX_RSVD2,
1540 TEGRA_MUX_RSVD3, 1547 TEGRA_MUX_RSVD3,
1541 TEGRA_MUX_RSVD4, 1548 TEGRA_MUX_RSVD4,
1549 TEGRA_MUX_RTCK,
1550 TEGRA_MUX_SATA,
1542 TEGRA_MUX_SDMMC1, 1551 TEGRA_MUX_SDMMC1,
1543 TEGRA_MUX_SDMMC2, 1552 TEGRA_MUX_SDMMC2,
1544 TEGRA_MUX_SDMMC3, 1553 TEGRA_MUX_SDMMC3,
@@ -1551,6 +1560,8 @@ enum tegra_mux {
1551 TEGRA_MUX_SPI4, 1560 TEGRA_MUX_SPI4,
1552 TEGRA_MUX_SPI5, 1561 TEGRA_MUX_SPI5,
1553 TEGRA_MUX_SPI6, 1562 TEGRA_MUX_SPI6,
1563 TEGRA_MUX_SYS,
1564 TEGRA_MUX_TMDS,
1554 TEGRA_MUX_TRACE, 1565 TEGRA_MUX_TRACE,
1555 TEGRA_MUX_UARTA, 1566 TEGRA_MUX_UARTA,
1556 TEGRA_MUX_UARTB, 1567 TEGRA_MUX_UARTB,
@@ -1569,1134 +1580,19 @@ enum tegra_mux {
1569 TEGRA_MUX_VI_ALT3, 1580 TEGRA_MUX_VI_ALT3,
1570 TEGRA_MUX_VIMCLK2, 1581 TEGRA_MUX_VIMCLK2,
1571 TEGRA_MUX_VIMCLK2_ALT, 1582 TEGRA_MUX_VIMCLK2_ALT,
1572 TEGRA_MUX_SATA,
1573 TEGRA_MUX_CCLA,
1574 TEGRA_MUX_PE0,
1575 TEGRA_MUX_PE,
1576 TEGRA_MUX_PE1,
1577 TEGRA_MUX_DP,
1578 TEGRA_MUX_RTCK,
1579 TEGRA_MUX_SYS,
1580 TEGRA_MUX_CLK,
1581 TEGRA_MUX_TMDS,
1582};
1583
1584static const char * const blink_groups[] = {
1585 "clk_32k_out_pa0",
1586};
1587
1588static const char * const cec_groups[] = {
1589 "hdmi_cec_pee3",
1590};
1591
1592static const char * const cldvfs_groups[] = {
1593 "ph2",
1594 "ph3",
1595 "kb_row7_pr7",
1596 "kb_row8_ps0",
1597 "dvfs_pwm_px0",
1598 "dvfs_clk_px2",
1599};
1600
1601static const char * const clk12_groups[] = {
1602 "sdmmc1_wp_n_pv3",
1603 "sdmmc1_clk_pz0",
1604};
1605
1606static const char * const cpu_groups[] = {
1607 "cpu_pwr_req",
1608};
1609
1610static const char * const dap_groups[] = {
1611 "dap_mclk1_pee2",
1612 "clk2_req_pcc5",
1613};
1614
1615static const char * const dap1_groups[] = {
1616 "dap_mclk1_pee2",
1617};
1618
1619static const char * const dap2_groups[] = {
1620 "dap_mclk1_pw4",
1621 "gpio_x4_aud_px4",
1622};
1623
1624static const char * const dev3_groups[] = {
1625 "clk3_req_pee1",
1626};
1627
1628static const char * const displaya_groups[] = {
1629 "dap3_fs_pp0",
1630 "dap3_din_pp1",
1631 "dap3_dout_pp2",
1632 "ph1",
1633 "pi4",
1634 "pbb3",
1635 "pbb4",
1636 "pbb5",
1637 "kb_row3_pr3",
1638 "kb_row4_pr4",
1639 "kb_row5_pr5",
1640 "kb_row6_pr6",
1641 "kb_col3_pq3",
1642 "sdmmc3_dat2_pb5",
1643};
1644
1645static const char * const displaya_alt_groups[] = {
1646 "kb_row6_pr6",
1647};
1648
1649static const char * const displayb_groups[] = {
1650 "dap3_fs_pp0",
1651 "dap3_din_pp1",
1652 "dap3_sclk_pp3",
1653
1654 "pu3",
1655 "pu4",
1656 "pu5",
1657
1658 "pbb3",
1659 "pbb4",
1660 "pbb6",
1661
1662 "kb_row3_pr3",
1663 "kb_row4_pr4",
1664 "kb_row5_pr5",
1665 "kb_row6_pr6",
1666
1667 "sdmmc3_dat3_pb4",
1668};
1669
1670static const char * const dtv_groups[] = {
1671 "uart3_cts_n_pa1",
1672 "uart3_rts_n_pc0",
1673 "dap4_fs_pp4",
1674 "dap4_dout_pp6",
1675 "pi7",
1676 "ph0",
1677 "ph6",
1678 "ph7",
1679};
1680
1681static const char * const extperiph1_groups[] = {
1682 "dap_mclk1_pw4",
1683};
1684
1685static const char * const extperiph2_groups[] = {
1686 "clk2_out_pw5",
1687};
1688
1689static const char * const extperiph3_groups[] = {
1690 "clk3_out_pee0",
1691};
1692
1693static const char * const gmi_groups[] = {
1694 "uart2_cts_n_pj5",
1695 "uart2_rts_n_pj6",
1696 "uart3_txd_pw6",
1697 "uart3_rxd_pw7",
1698 "uart3_cts_n_pa1",
1699 "uart3_rts_n_pc0",
1700
1701 "pu0",
1702 "pu1",
1703 "pu2",
1704 "pu3",
1705 "pu4",
1706 "pu5",
1707 "pu6",
1708
1709 "dap4_fs_pp4",
1710 "dap4_din_pp5",
1711 "dap4_dout_pp6",
1712 "dap4_sclk_pp7",
1713
1714 "pc7",
1715
1716 "pg0",
1717 "pg1",
1718 "pg2",
1719 "pg3",
1720 "pg4",
1721 "pg5",
1722 "pg6",
1723 "pg7",
1724
1725 "ph0",
1726 "ph1",
1727 "ph2",
1728 "ph3",
1729 "ph4",
1730 "ph5",
1731 "ph6",
1732 "ph7",
1733
1734 "pi0",
1735 "pi1",
1736 "pi2",
1737 "pi3",
1738 "pi4",
1739 "pi5",
1740 "pi6",
1741 "pi7",
1742
1743 "pj0",
1744 "pj2",
1745
1746 "pk0",
1747 "pk1",
1748 "pk2",
1749 "pk3",
1750 "pk4",
1751
1752 "pj7",
1753 "pb0",
1754 "pb1",
1755 "pk7",
1756
1757 "gen2_i2c_scl_pt5",
1758 "gen2_i2c_sda_pt6",
1759
1760 "sdmmc4_dat0_paa0",
1761 "sdmmc4_dat1_paa1",
1762 "sdmmc4_dat2_paa2",
1763 "sdmmc4_dat3_paa3",
1764 "sdmmc4_dat4_paa4",
1765 "sdmmc4_dat6_paa6",
1766 "sdmmc4_dat7_paa7",
1767 "sdmmc4_clk_pcc4",
1768 "sdmmc4_cmd_pt7",
1769 "gmi_clk_lb",
1770
1771 "dap1_fs_pn0",
1772 "dap1_din_pn1",
1773 "dap1_dout_pn2",
1774 "dap1_sclk_pn3",
1775
1776 "dap2_fs_pa2",
1777 "dap2_din_pa4",
1778 "dap2_dout_pa5",
1779 "dap2_sclk_pa3",
1780
1781 "dvfs_pwm_px0",
1782 "dvfs_clk_px2",
1783 "gpio_x1_aud_px1",
1784 "gpio_x3_aud_px3",
1785 "gpio_x4_aud_px4",
1786 "gpio_x5_aud_px5",
1787 "gpio_x6_aud_px6",
1788};
1789
1790static const char * const gmi_alt_groups[] = {
1791 "pc7",
1792 "pk4",
1793 "pj7",
1794};
1795
1796static const char * const hda_groups[] = {
1797 "dap1_fs_pn0",
1798 "dap1_din_pn1",
1799 "dap1_dout_pn2",
1800 "dap1_sclk_pn3",
1801 "dap2_fs_pa2",
1802 "dap2_sclk_pa3",
1803 "dap2_din_pa4",
1804 "dap2_dout_pa5",
1805};
1806
1807static const char * const hsi_groups[] = {
1808 "ulpi_data0_po1",
1809 "ulpi_data1_po2",
1810 "ulpi_data2_po3",
1811 "ulpi_data3_po4",
1812 "ulpi_data4_po5",
1813 "ulpi_data5_po6",
1814 "ulpi_data6_po7",
1815 "ulpi_data7_po0",
1816};
1817
1818static const char * const i2c1_groups[] = {
1819 "gen1_i2c_scl_pc4",
1820 "gen1_i2c_sda_pc5",
1821 "gpio_w2_aud_pw2",
1822 "gpio_w3_aud_pw3",
1823};
1824
1825static const char * const i2c2_groups[] = {
1826 "gen2_i2c_scl_pt5",
1827 "gen2_i2c_sda_pt6",
1828};
1829
1830static const char * const i2c3_groups[] = {
1831 "spdif_in_pk6",
1832 "spdif_out_pk5",
1833 "cam_i2c_scl_pbb1",
1834 "cam_i2c_sda_pbb2",
1835};
1836
1837static const char * const i2c4_groups[] = {
1838 "ddc_scl_pv4",
1839 "ddc_sda_pv5",
1840};
1841
1842static const char * const i2cpwr_groups[] = {
1843 "pwr_i2c_scl_pz6",
1844 "pwr_i2c_sda_pz7",
1845};
1846
1847static const char * const i2s0_groups[] = {
1848 "dap1_fs_pn0",
1849 "dap1_din_pn1",
1850 "dap1_dout_pn2",
1851 "dap1_sclk_pn3",
1852};
1853
1854static const char * const i2s1_groups[] = {
1855 "dap2_fs_pa2",
1856 "dap2_sclk_pa3",
1857 "dap2_din_pa4",
1858 "dap2_dout_pa5",
1859};
1860
1861static const char * const i2s2_groups[] = {
1862 "dap3_fs_pp0",
1863 "dap3_din_pp1",
1864 "dap3_dout_pp2",
1865 "dap3_sclk_pp3",
1866};
1867
1868static const char * const i2s3_groups[] = {
1869 "dap4_fs_pp4",
1870 "dap4_din_pp5",
1871 "dap4_dout_pp6",
1872 "dap4_sclk_pp7",
1873};
1874
1875static const char * const i2s4_groups[] = {
1876 "pcc1",
1877 "pbb6",
1878 "pbb7",
1879 "pcc2",
1880};
1881
1882static const char * const irda_groups[] = {
1883 "uart2_rxd_pc3",
1884 "uart2_txd_pc2",
1885 "kb_row11_ps3",
1886 "kb_row12_ps4",
1887};
1888
1889static const char * const kbc_groups[] = {
1890 "kb_row0_pr0",
1891 "kb_row1_pr1",
1892 "kb_row2_pr2",
1893 "kb_row3_pr3",
1894 "kb_row4_pr4",
1895 "kb_row5_pr5",
1896 "kb_row6_pr6",
1897 "kb_row7_pr7",
1898 "kb_row8_ps0",
1899 "kb_row9_ps1",
1900 "kb_row10_ps2",
1901 "kb_row11_ps3",
1902 "kb_row12_ps4",
1903 "kb_row13_ps5",
1904 "kb_row14_ps6",
1905 "kb_row15_ps7",
1906 "kb_row16_pt0",
1907 "kb_row17_pt1",
1908
1909 "kb_col0_pq0",
1910 "kb_col1_pq1",
1911 "kb_col2_pq2",
1912 "kb_col3_pq3",
1913 "kb_col4_pq4",
1914 "kb_col5_pq5",
1915 "kb_col6_pq6",
1916 "kb_col7_pq7",
1917};
1918
1919static const char * const owr_groups[] = {
1920 "pu0",
1921 "kb_col4_pq4",
1922 "owr",
1923 "sdmmc3_cd_n_pv2",
1924};
1925
1926static const char * const pmi_groups[] = {
1927 "pwr_int_n",
1928};
1929
1930static const char * const pwm0_groups[] = {
1931 "sdmmc1_dat2_py5",
1932 "uart3_rts_n_pc0",
1933 "pu3",
1934 "ph0",
1935 "sdmmc3_dat3_pb4",
1936};
1937
1938static const char * const pwm1_groups[] = {
1939 "sdmmc1_dat1_py6",
1940 "pu4",
1941 "ph1",
1942 "sdmmc3_dat2_pb5",
1943};
1944
1945static const char * const pwm2_groups[] = {
1946 "pu5",
1947 "ph2",
1948 "kb_col3_pq3",
1949 "sdmmc3_dat1_pb6",
1950};
1951
1952static const char * const pwm3_groups[] = {
1953 "pu6",
1954 "ph3",
1955 "sdmmc3_cmd_pa7",
1956};
1957
1958static const char * const pwron_groups[] = {
1959 "core_pwr_req",
1960};
1961
1962static const char * const reset_out_n_groups[] = {
1963 "reset_out_n",
1964};
1965
1966static const char * const rsvd1_groups[] = {
1967 "pv0",
1968 "pv1",
1969
1970 "hdmi_int_pn7",
1971 "pu1",
1972 "pu2",
1973 "pc7",
1974 "pi7",
1975 "pk0",
1976 "pj0",
1977 "pj2",
1978 "pk2",
1979 "pi3",
1980 "pi6",
1981
1982 "pg0",
1983 "pg1",
1984 "pg2",
1985 "pg3",
1986 "pg4",
1987 "pg5",
1988 "pg6",
1989 "pg7",
1990
1991 "pi0",
1992 "pi1",
1993
1994 "gpio_x7_aud_px7",
1995
1996 "reset_out_n",
1997};
1998
1999static const char * const rsvd2_groups[] = {
2000 "pv0",
2001 "pv1",
2002
2003 "sdmmc1_dat0_py7",
2004 "clk2_out_pw5",
2005 "clk2_req_pcc5",
2006 "hdmi_int_pn7",
2007 "ddc_scl_pv4",
2008 "ddc_sda_pv5",
2009
2010 "uart3_txd_pw6",
2011 "uart3_rxd_pw7",
2012
2013 "gen1_i2c_scl_pc4",
2014 "gen1_i2c_sda_pc5",
2015
2016 "clk2_out_pee0",
2017 "clk2_req_pee1",
2018 "pc7",
2019 "pi5",
2020 "pj0",
2021 "pj2",
2022
2023 "pk4",
2024 "pk2",
2025 "pi3",
2026 "pi6",
2027 "pg0",
2028 "pg1",
2029 "pg5",
2030 "pg6",
2031 "pg7",
2032
2033 "ph4",
2034 "ph5",
2035 "pj7",
2036 "pb0",
2037 "pb1",
2038 "pk7",
2039 "pi0",
2040 "pi1",
2041
2042 "gen2_i2c_scl_pt5",
2043 "gen2_i2c_sda_pt6",
2044 "sdmmc4_clk_pcc4",
2045 "sdmmc4_cmd_pt7",
2046 "sdmmc4_dat7_paa7",
2047 "pcc1",
2048 "pbb6",
2049 "pbb7",
2050 "pcc2",
2051 "jtag_rtck",
2052
2053 "pwr_i2c_scl_pz6",
2054 "pwr_i2c_sda_pz7",
2055
2056 "kb_row0_pr0",
2057 "kb_row1_pr1",
2058 "kb_row2_pr2",
2059 "kb_row7_pr7",
2060 "kb_row8_ps0",
2061 "kb_row9_ps1",
2062 "kb_row10_ps2",
2063 "kb_row11_ps3",
2064 "kb_row12_ps4",
2065 "kb_row13_ps5",
2066 "kb_row14_ps6",
2067
2068 "kb_col0_pq0",
2069 "kb_col1_pq1",
2070 "kb_col2_pq2",
2071 "kb_col5_pq5",
2072 "kb_col6_pq6",
2073 "kb_col7_pq7",
2074
2075 "core_pwr_req",
2076 "cpu_pwr_req",
2077 "pwr_int_n",
2078 "clk_32k_in",
2079 "owr",
2080
2081 "spdif_in_pk6",
2082 "spdif_out_pk5",
2083 "gpio_x1_aud_px1",
2084
2085 "sdmmc3_clk_pa6",
2086 "sdmmc3_dat0_pb7",
2087
2088 "pex_l0_rst_n_pdd1",
2089 "pex_l0_clkreq_n_pdd2",
2090 "pex_wake_n_pdd3",
2091 "pex_l1_rst_n_pdd5",
2092 "pex_l1_clkreq_n_pdd6",
2093 "hdmi_cec_pee3",
2094
2095 "gpio_w2_aud_pw2",
2096 "usb_vbus_en0_pn4",
2097 "usb_vbus_en1_pn5",
2098 "sdmmc3_clk_lb_out_pee4",
2099 "sdmmc3_clk_lb_in_pee5",
2100 "gmi_clk_lb",
2101 "reset_out_n",
2102 "kb_row16_pt0",
2103 "kb_row17_pt1",
2104 "dp_hpd_pff0",
2105 "usb_vbus_en2_pff1",
2106 "pff2",
2107};
2108
2109static const char * const rsvd3_groups[] = {
2110 "dap3_sclk_pp3",
2111 "pv0",
2112 "pv1",
2113 "sdmmc1_clk_pz0",
2114 "clk2_out_pw5",
2115 "clk2_req_pcc5",
2116 "hdmi_int_pn7",
2117
2118 "ddc_scl_pv4",
2119 "ddc_sda_pv5",
2120
2121 "pu6",
2122
2123 "gen1_i2c_scl_pc4",
2124 "gen1_i2c_sda_pc5",
2125
2126 "dap4_din_pp5",
2127 "dap4_sclk_pp7",
2128
2129 "clk3_out_pee0",
2130 "clk3_req_pee1",
2131
2132 "sdmmc4_dat5_paa5",
2133 "gpio_pcc1",
2134 "cam_i2c_scl_pbb1",
2135 "cam_i2c_sda_pbb2",
2136 "pbb5",
2137 "pbb7",
2138 "jtag_rtck",
2139 "pwr_i2c_scl_pz6",
2140 "pwr_i2c_sda_pz7",
2141
2142 "kb_row0_pr0",
2143 "kb_row1_pr1",
2144 "kb_row2_pr2",
2145 "kb_row4_pr4",
2146 "kb_row5_pr5",
2147 "kb_row9_ps1",
2148 "kb_row10_ps2",
2149 "kb_row11_ps3",
2150 "kb_row12_ps4",
2151 "kb_row15_ps7",
2152
2153 "clk_32k_out_pa0",
2154 "core_pwr_req",
2155 "cpu_pwr_req",
2156 "pwr_int_n",
2157 "clk_32k_in",
2158 "owr",
2159
2160 "dap_mclk1_pw4",
2161 "spdif_in_pk6",
2162 "spdif_out_pk5",
2163 "sdmmc3_clk_pa6",
2164 "sdmmc3_dat0_pb7",
2165
2166 "pex_l0_rst_n_pdd1",
2167 "pex_l0_clkreq_n_pdd2",
2168 "pex_wake_n_pdd3",
2169 "pex_l1_rst_n_pdd5",
2170 "pex_l1_clkreq_n_pdd6",
2171 "hdmi_cec_pee3",
2172
2173 "sdmmc3_cd_n_pv2",
2174 "usb_vbus_en0_pn4",
2175 "usb_vbus_en1_pn5",
2176 "sdmmc3_clk_lb_out_pee4",
2177 "sdmmc3_clk_lb_in_pee5",
2178 "reset_out_n",
2179 "kb_row16_pt0",
2180 "kb_row17_pt1",
2181 "dp_hpd_pff0",
2182 "usb_vbus_en2_pff1",
2183 "pff2",
2184};
2185
2186static const char * const rsvd4_groups[] = {
2187 "dap3_dout_pp2",
2188 "pv0",
2189 "pv1",
2190 "sdmmc1_clk_pz0",
2191
2192 "clk2_out_pw5",
2193 "clk2_req_pcc5",
2194 "hdmi_int_pn7",
2195 "ddc_scl_pv4",
2196 "ddc_sda_pv5",
2197
2198 "uart2_rts_n_pj6",
2199 "uart2_cts_n_pj5",
2200 "uart3_txd_pw6",
2201 "uart3_rxd_pw7",
2202
2203 "pu0",
2204 "pu1",
2205 "pu2",
2206
2207 "gen1_i2c_scl_pc4",
2208 "gen1_i2c_sda_pc5",
2209
2210 "dap4_fs_pp4",
2211 "dap4_dout_pp6",
2212 "dap4_din_pp5",
2213 "dap4_sclk_pp7",
2214
2215 "clk3_out_pee0",
2216 "clk3_req_pee1",
2217
2218 "pi5",
2219 "pk1",
2220 "pk2",
2221 "pg0",
2222 "pg1",
2223 "pg2",
2224 "pg3",
2225 "ph4",
2226 "ph5",
2227 "pb0",
2228 "pb1",
2229 "pk7",
2230 "pi0",
2231 "pi1",
2232 "pi2",
2233
2234 "gen2_i2c_scl_pt5",
2235 "gen2_i2c_sda_pt6",
2236
2237 "sdmmc4_cmd_pt7",
2238 "sdmmc4_dat0_paa0",
2239 "sdmmc4_dat1_paa1",
2240 "sdmmc4_dat2_paa2",
2241 "sdmmc4_dat3_paa3",
2242 "sdmmc4_dat4_paa4",
2243 "sdmmc4_dat5_paa5",
2244 "sdmmc4_dat6_paa6",
2245 "sdmmc4_dat7_paa7",
2246
2247 "jtag_rtck",
2248 "pwr_i2c_scl_pz6",
2249 "pwr_i2c_sda_pz7",
2250
2251 "kb_row0_pr0",
2252 "kb_row1_pr1",
2253 "kb_row2_pr2",
2254 "kb_row13_ps5",
2255 "kb_row14_ps6",
2256 "kb_row15_ps7",
2257
2258 "kb_col0_pq0",
2259 "kb_col1_pq1",
2260 "kb_col2_pq2",
2261 "kb_col5_pq5",
2262
2263 "clk_32k_out_pa0",
2264 "core_pwr_req",
2265 "cpu_pwr_req",
2266 "pwr_int_n",
2267 "clk_32k_in",
2268 "owr",
2269
2270 "dap1_fs_pn0",
2271 "dap1_din_pn1",
2272 "dap1_sclk_pn3",
2273 "dap_mclk1_req_pee2",
2274 "dap_mclk1_pw5",
2275
2276 "dap2_fs_pa2",
2277 "dap2_din_pa4",
2278 "dap2_dout_pa5",
2279 "dap2_sclk_pa3",
2280
2281 "dvfs_pwm_px0",
2282 "dvfs_clk_px2",
2283 "gpio_x1_aud_px1",
2284 "gpio_x3_aud_px3",
2285
2286 "gpio_x5_aud_px5",
2287 "gpio_x7_aud_px7",
2288
2289 "pex_l0_rst_n_pdd1",
2290 "pex_l0_clkreq_n_pdd2",
2291 "pex_wake_n_pdd3",
2292 "pex_l1_rst_n_pdd5",
2293 "pex_l1_clkreq_n_pdd6",
2294 "hdmi_cec_pee3",
2295
2296 "sdmmc3_cd_n_pv2",
2297 "usb_vbus_en0_pn4",
2298 "usb_vbus_en1_pn5",
2299 "sdmmc3_clk_lb_out_pee4",
2300 "sdmmc3_clk_lb_in_pee5",
2301 "gmi_clk_lb",
2302
2303 "dp_hpd_pff0",
2304 "usb_vbus_en2_pff1",
2305 "pff2",
2306};
2307
2308static const char * const sdmmc1_groups[] = {
2309 "sdmmc1_clk_pz0",
2310 "sdmmc1_cmd_pz1",
2311 "sdmmc1_dat3_py4",
2312 "sdmmc1_dat2_py5",
2313 "sdmmc1_dat1_py6",
2314 "sdmmc1_dat0_py7",
2315 "clk2_out_pw5",
2316 "clk2_req_pcc",
2317 "uart3_cts_n_pa1",
2318 "sdmmc1_wp_n_pv3",
2319};
2320
2321static const char * const sdmmc2_groups[] = {
2322 "pi5",
2323 "pk1",
2324 "pk3",
2325 "pk4",
2326 "pi6",
2327 "ph4",
2328 "ph5",
2329 "ph6",
2330 "ph7",
2331 "pi2",
2332 "cam_mclk_pcc0",
2333 "pcc1",
2334 "pbb0",
2335 "cam_i2c_scl_pbb1",
2336 "cam_i2c_sda_pbb2",
2337 "pbb3",
2338 "pbb4",
2339 "pbb5",
2340 "pbb6",
2341 "pbb7",
2342 "pcc2",
2343 "gmi_clk_lb",
2344};
2345
2346static const char * const sdmmc3_groups[] = {
2347 "pk0",
2348 "pcc2",
2349
2350 "kb_col4_pq4",
2351 "kb_col5_pq5",
2352
2353 "sdmmc3_clk_pa6",
2354 "sdmmc3_cmd_pa7",
2355 "sdmmc3_dat0_pb7",
2356 "sdmmc3_dat1_pb6",
2357 "sdmmc3_dat2_pb5",
2358 "sdmmc3_dat3_pb4",
2359
2360 "sdmmc3_cd_n_pv2",
2361 "sdmmc3_clk_lb_in_pee5",
2362 "sdmmc3_clk_lb_out_pee4",
2363};
2364
2365static const char * const sdmmc4_groups[] = {
2366 "sdmmc4_clk_pcc4",
2367 "sdmmc4_cmd_pt7",
2368 "sdmmc4_dat0_paa0",
2369 "sdmmc4_dat1_paa1",
2370 "sdmmc4_dat2_paa2",
2371 "sdmmc4_dat3_paa3",
2372 "sdmmc4_dat4_paa4",
2373 "sdmmc4_dat5_paa5",
2374 "sdmmc4_dat6_paa6",
2375 "sdmmc4_dat7_paa7",
2376};
2377
2378static const char * const soc_groups[] = {
2379 "pk0",
2380 "pj2",
2381 "kb_row15_ps7",
2382 "clk_32k_out_pa0",
2383};
2384
2385static const char * const spdif_groups[] = {
2386 "sdmmc1_cmd_pz1",
2387 "sdmmc1_dat3_py4",
2388 "uart2_rxd_pc3",
2389 "uart2_txd_pc2",
2390 "spdif_in_pk6",
2391 "spdif_out_pk5",
2392};
2393
2394static const char * const spi1_groups[] = {
2395 "ulpi_clk_py0",
2396 "ulpi_dir_py1",
2397 "ulpi_nxt_py2",
2398 "ulpi_stp_py3",
2399 "gpio_x3_aud_px3",
2400 "gpio_x4_aud_px4",
2401 "gpio_x5_aud_px5",
2402 "gpio_x6_aud_px6",
2403 "gpio_x7_aud_px7",
2404 "gpio_w3_aud_pw3",
2405};
2406
2407static const char * const spi2_groups[] = {
2408 "ulpi_data4_po5",
2409 "ulpi_data5_po6",
2410 "ulpi_data6_po7",
2411 "ulpi_data7_po0",
2412
2413 "kb_row13_ps5",
2414 "kb_row14_ps6",
2415 "kb_row15_ps7",
2416 "kb_col0_pq0",
2417 "kb_col1_pq1",
2418 "kb_col2_pq2",
2419 "kb_col6_pq6",
2420 "kb_col7_pq7",
2421 "gpio_x4_aud_px4",
2422 "gpio_x5_aud_px5",
2423 "gpio_x6_aud_px6",
2424 "gpio_x7_aud_px7",
2425 "gpio_w2_aud_pw2",
2426 "gpio_w3_aud_pw3",
2427};
2428
2429static const char * const spi3_groups[] = {
2430 "ulpi_data0_po1",
2431 "ulpi_data1_po2",
2432 "ulpi_data2_po3",
2433 "ulpi_data3_po4",
2434 "sdmmc4_dat0_paa0",
2435 "sdmmc4_dat1_paa1",
2436 "sdmmc4_dat2_paa2",
2437 "sdmmc4_dat3_paa3",
2438 "sdmmc4_dat4_paa4",
2439 "sdmmc4_dat5_paa5",
2440 "sdmmc4_dat6_paa6",
2441 "sdmmc3_clk_pa6",
2442 "sdmmc3_cmd_pa7",
2443 "sdmmc3_dat0_pb7",
2444 "sdmmc3_dat1_pb6",
2445 "sdmmc3_dat2_pb5",
2446 "sdmmc3_dat3_pb4",
2447};
2448
2449static const char * const spi4_groups[] = {
2450 "sdmmc1_cmd_pz1",
2451 "sdmmc1_dat3_py4",
2452 "sdmmc1_dat2_py5",
2453 "sdmmc1_dat1_py6",
2454 "sdmmc1_dat0_py7",
2455
2456 "uart2_rxd_pc3",
2457 "uart2_txd_pc2",
2458 "uart2_rts_n_pj6",
2459 "uart2_cts_n_pj5",
2460 "uart3_txd_pw6",
2461 "uart3_rxd_pw7",
2462
2463 "pi3",
2464 "pg4",
2465 "pg5",
2466 "pg6",
2467 "pg7",
2468 "ph3",
2469 "pi4",
2470 "sdmmc1_wp_n_pv3",
2471};
2472
2473static const char * const spi5_groups[] = {
2474 "ulpi_clk_py0",
2475 "ulpi_dir_py1",
2476 "ulpi_nxt_py2",
2477 "ulpi_stp_py3",
2478 "dap3_fs_pp0",
2479 "dap3_din_pp1",
2480 "dap3_dout_pp2",
2481 "dap3_sclk_pp3",
2482};
2483
2484static const char * const spi6_groups[] = {
2485 "dvfs_pwm_px0",
2486 "gpio_x1_aud_px1",
2487 "gpio_x3_aud_px3",
2488 "dvfs_clk_px2",
2489 "gpio_x6_aud_px6",
2490 "gpio_w2_aud_pw2",
2491 "gpio_w3_aud_pw3",
2492};
2493
2494static const char * const trace_groups[] = {
2495 "pi2",
2496 "pi4",
2497 "pi7",
2498 "ph0",
2499 "ph6",
2500 "ph7",
2501 "pg2",
2502 "pg3",
2503 "pk1",
2504 "pk3",
2505};
2506
2507static const char * const uarta_groups[] = {
2508 "ulpi_data0_po1",
2509 "ulpi_data1_po2",
2510 "ulpi_data2_po3",
2511 "ulpi_data3_po4",
2512 "ulpi_data4_po5",
2513 "ulpi_data5_po6",
2514 "ulpi_data6_po7",
2515 "ulpi_data7_po0",
2516
2517 "sdmmc1_cmd_pz1",
2518 "sdmmc1_dat3_py4",
2519 "sdmmc1_dat2_py5",
2520 "sdmmc1_dat1_py6",
2521 "sdmmc1_dat0_py7",
2522
2523
2524 "uart2_rxd_pc3",
2525 "uart2_txd_pc2",
2526 "uart2_rts_n_pj6",
2527 "uart2_cts_n_pj5",
2528
2529 "pu0",
2530 "pu1",
2531 "pu2",
2532 "pu3",
2533 "pu4",
2534 "pu5",
2535 "pu6",
2536
2537 "kb_row7_pr7",
2538 "kb_row8_ps0",
2539 "kb_row9_ps1",
2540 "kb_row10_ps2",
2541 "kb_col3_pq3",
2542 "kb_col4_pq4",
2543
2544 "sdmmc3_cmd_pa7",
2545 "sdmmc3_dat1_pb6",
2546 "sdmmc1_wp_n_pv3",
2547
2548};
2549
2550static const char * const uartb_groups[] = {
2551 "uart2_rts_n_pj6",
2552 "uart2_cts_n_pj5",
2553};
2554
2555static const char * const uartc_groups[] = {
2556 "uart3_txd_pw6",
2557 "uart3_rxd_pw7",
2558 "uart3_cts_n_pa1",
2559 "uart3_rts_n_pc0",
2560 "kb_row16_pt0",
2561 "kn_row17_pt1",
2562};
2563
2564static const char * const uartd_groups[] = {
2565 "ulpi_clk_py0",
2566 "ulpi_dir_py1",
2567 "ulpi_nxt_py2",
2568 "ulpi_stp_py3",
2569 "pj7",
2570 "pb0",
2571 "pb1",
2572 "pk7",
2573 "kb_col6_pq6",
2574 "kb_col7_pq7",
2575};
2576
2577static const char * const ulpi_groups[] = {
2578 "ulpi_data0_po1",
2579 "ulpi_data1_po2",
2580 "ulpi_data2_po3",
2581 "ulpi_data3_po4",
2582 "ulpi_data4_po5",
2583 "ulpi_data5_po6",
2584 "ulpi_data6_po7",
2585 "ulpi_data7_po0",
2586 "ulpi_clk_py0",
2587 "ulpi_dir_py1",
2588 "ulpi_nxt_py2",
2589 "ulpi_stp_py3",
2590};
2591
2592static const char * const usb_groups[] = {
2593 "pj0",
2594 "usb_vbus_en0_pn4",
2595 "usb_vbus_en1_pn5",
2596 "usb_vbus_en2_pff1",
2597};
2598
2599static const char * const vgp1_groups[] = {
2600 "cam_i2c_scl_pbb1",
2601};
2602
2603static const char * const vgp2_groups[] = {
2604 "cam_i2c_sda_pbb2",
2605};
2606
2607static const char * const vgp3_groups[] = {
2608 "pbb3",
2609};
2610
2611static const char * const vgp4_groups[] = {
2612 "pbb4",
2613};
2614
2615static const char * const vgp5_groups[] = {
2616 "pbb5",
2617};
2618
2619static const char * const vgp6_groups[] = {
2620 "pbb0",
2621};
2622
2623static const char * const vi_groups[] = {
2624 "cam_mclk_pcc0",
2625};
2626
2627static const char * const vi_alt1_groups[] = {
2628 "cam_mclk_pcc0",
2629};
2630
2631static const char * const vi_alt3_groups[] = {
2632 "cam_mclk_pcc0",
2633};
2634
2635static const char * const vimclk2_groups[] = {
2636 "pbb0",
2637};
2638
2639static const char * const vimclk2_alt_groups[] = {
2640 "pbb0",
2641};
2642
2643static const char * const sata_groups[] = {
2644 "dap_mclk1_req_pee2",
2645 "dap1_dout_pn2",
2646 "pff2",
2647};
2648
2649static const char * const ccla_groups[] = {
2650 "pk3",
2651};
2652
2653static const char * const rtck_groups[] = {
2654 "jtag_rtck",
2655};
2656
2657static const char * const sys_groups[] = {
2658 "kb_row3_pr3",
2659};
2660
2661static const char * const pe0_groups[] = {
2662 "pex_l0_rst_n_pdd1",
2663 "pex_l0_clkreq_n_pdd2",
2664};
2665
2666static const char * const pe_groups[] = {
2667 "pex_wake_n_pdd3",
2668};
2669
2670static const char * const pe1_groups[] = {
2671 "pex_l1_rst_n_pdd5",
2672 "pex_l1_clkreq_n_pdd6",
2673};
2674
2675static const char * const dp_groups[] = {
2676 "dp_hpd_pff0",
2677};
2678
2679static const char * const clk_groups[] = {
2680 "clk_32k_in",
2681};
2682
2683static const char * const tmds_groups[] = {
2684 "pg4",
2685 "ph1",
2686 "ph2",
2687}; 1583};
2688 1584
2689#define FUNCTION(fname) \ 1585#define FUNCTION(fname) \
2690 { \ 1586 { \
2691 .name = #fname, \ 1587 .name = #fname, \
2692 .groups = fname##_groups, \
2693 .ngroups = ARRAY_SIZE(fname##_groups), \
2694 } 1588 }
2695 1589
2696static const struct tegra_function tegra124_functions[] = { 1590static struct tegra_function tegra124_functions[] = {
2697 FUNCTION(blink), 1591 FUNCTION(blink),
1592 FUNCTION(ccla),
2698 FUNCTION(cec), 1593 FUNCTION(cec),
2699 FUNCTION(cldvfs), 1594 FUNCTION(cldvfs),
1595 FUNCTION(clk),
2700 FUNCTION(clk12), 1596 FUNCTION(clk12),
2701 FUNCTION(cpu), 1597 FUNCTION(cpu),
2702 FUNCTION(dap), 1598 FUNCTION(dap),
@@ -2706,6 +1602,7 @@ static const struct tegra_function tegra124_functions[] = {
2706 FUNCTION(displaya), 1602 FUNCTION(displaya),
2707 FUNCTION(displaya_alt), 1603 FUNCTION(displaya_alt),
2708 FUNCTION(displayb), 1604 FUNCTION(displayb),
1605 FUNCTION(dp),
2709 FUNCTION(dtv), 1606 FUNCTION(dtv),
2710 FUNCTION(extperiph1), 1607 FUNCTION(extperiph1),
2711 FUNCTION(extperiph2), 1608 FUNCTION(extperiph2),
@@ -2727,6 +1624,9 @@ static const struct tegra_function tegra124_functions[] = {
2727 FUNCTION(irda), 1624 FUNCTION(irda),
2728 FUNCTION(kbc), 1625 FUNCTION(kbc),
2729 FUNCTION(owr), 1626 FUNCTION(owr),
1627 FUNCTION(pe),
1628 FUNCTION(pe0),
1629 FUNCTION(pe1),
2730 FUNCTION(pmi), 1630 FUNCTION(pmi),
2731 FUNCTION(pwm0), 1631 FUNCTION(pwm0),
2732 FUNCTION(pwm1), 1632 FUNCTION(pwm1),
@@ -2738,6 +1638,8 @@ static const struct tegra_function tegra124_functions[] = {
2738 FUNCTION(rsvd2), 1638 FUNCTION(rsvd2),
2739 FUNCTION(rsvd3), 1639 FUNCTION(rsvd3),
2740 FUNCTION(rsvd4), 1640 FUNCTION(rsvd4),
1641 FUNCTION(rtck),
1642 FUNCTION(sata),
2741 FUNCTION(sdmmc1), 1643 FUNCTION(sdmmc1),
2742 FUNCTION(sdmmc2), 1644 FUNCTION(sdmmc2),
2743 FUNCTION(sdmmc3), 1645 FUNCTION(sdmmc3),
@@ -2750,6 +1652,8 @@ static const struct tegra_function tegra124_functions[] = {
2750 FUNCTION(spi4), 1652 FUNCTION(spi4),
2751 FUNCTION(spi5), 1653 FUNCTION(spi5),
2752 FUNCTION(spi6), 1654 FUNCTION(spi6),
1655 FUNCTION(sys),
1656 FUNCTION(tmds),
2753 FUNCTION(trace), 1657 FUNCTION(trace),
2754 FUNCTION(uarta), 1658 FUNCTION(uarta),
2755 FUNCTION(uartb), 1659 FUNCTION(uartb),
@@ -2768,23 +1672,13 @@ static const struct tegra_function tegra124_functions[] = {
2768 FUNCTION(vi_alt3), 1672 FUNCTION(vi_alt3),
2769 FUNCTION(vimclk2), 1673 FUNCTION(vimclk2),
2770 FUNCTION(vimclk2_alt), 1674 FUNCTION(vimclk2_alt),
2771 FUNCTION(sata),
2772 FUNCTION(ccla),
2773 FUNCTION(pe0),
2774 FUNCTION(pe),
2775 FUNCTION(pe1),
2776 FUNCTION(dp),
2777 FUNCTION(rtck),
2778 FUNCTION(sys),
2779 FUNCTION(clk),
2780 FUNCTION(tmds),
2781}; 1675};
2782 1676
2783#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */ 1677#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
2784#define PINGROUP_REG_A 0x3000 /* bank 1 */ 1678#define PINGROUP_REG_A 0x3000 /* bank 1 */
2785 1679
2786#define PINGROUP_REG_Y(r) ((r) - PINGROUP_REG_A) 1680#define PINGROUP_REG_Y(r) ((r) - PINGROUP_REG_A)
2787#define PINGROUP_REG_N(r) -1 1681#define PINGROUP_REG_N(r) -1
2788 1682
2789#define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior, rcv_sel) \ 1683#define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior, rcv_sel) \
2790 { \ 1684 { \
@@ -2792,12 +1686,12 @@ static const struct tegra_function tegra124_functions[] = {
2792 .pins = pg_name##_pins, \ 1686 .pins = pg_name##_pins, \
2793 .npins = ARRAY_SIZE(pg_name##_pins), \ 1687 .npins = ARRAY_SIZE(pg_name##_pins), \
2794 .funcs = { \ 1688 .funcs = { \
2795 TEGRA_MUX_ ## f0, \ 1689 TEGRA_MUX_##f0, \
2796 TEGRA_MUX_ ## f1, \ 1690 TEGRA_MUX_##f1, \
2797 TEGRA_MUX_ ## f2, \ 1691 TEGRA_MUX_##f2, \
2798 TEGRA_MUX_ ## f3, \ 1692 TEGRA_MUX_##f3, \
2799 }, \ 1693 }, \
2800 .func_safe = TEGRA_MUX_ ## f_safe, \ 1694 .func_safe = TEGRA_MUX_##f_safe, \
2801 .mux_reg = PINGROUP_REG_Y(r), \ 1695 .mux_reg = PINGROUP_REG_Y(r), \
2802 .mux_bank = 1, \ 1696 .mux_bank = 1, \
2803 .mux_bit = 0, \ 1697 .mux_bit = 0, \
@@ -2826,8 +1720,9 @@ static const struct tegra_function tegra124_functions[] = {
2826 .drvtype_reg = -1, \ 1720 .drvtype_reg = -1, \
2827 } 1721 }
2828 1722
2829#define DRV_PINGROUP_DVRTYPE_Y(r) ((r) - DRV_PINGROUP_REG_A) 1723#define DRV_PINGROUP_REG_Y(r) ((r) - DRV_PINGROUP_REG_A)
2830#define DRV_PINGROUP_DVRTYPE_N(r) -1 1724#define DRV_PINGROUP_REG_N(r) -1
1725
2831 1726
2832#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \ 1727#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \
2833 drvdn_b, drvdn_w, drvup_b, drvup_w, \ 1728 drvdn_b, drvdn_w, drvup_b, drvup_w, \
@@ -2845,7 +1740,7 @@ static const struct tegra_function tegra124_functions[] = {
2845 .lock_reg = -1, \ 1740 .lock_reg = -1, \
2846 .ioreset_reg = -1, \ 1741 .ioreset_reg = -1, \
2847 .rcv_sel_reg = -1, \ 1742 .rcv_sel_reg = -1, \
2848 .drv_reg = DRV_PINGROUP_DVRTYPE_Y(r), \ 1743 .drv_reg = DRV_PINGROUP_REG_Y(r), \
2849 .drv_bank = 0, \ 1744 .drv_bank = 0, \
2850 .hsm_bit = hsm_b, \ 1745 .hsm_bit = hsm_b, \
2851 .schmitt_bit = schmitt_b, \ 1746 .schmitt_bit = schmitt_b, \
@@ -2858,7 +1753,7 @@ static const struct tegra_function tegra124_functions[] = {
2858 .slwr_width = slwr_w, \ 1753 .slwr_width = slwr_w, \
2859 .slwf_bit = slwf_b, \ 1754 .slwf_bit = slwf_b, \
2860 .slwf_width = slwf_w, \ 1755 .slwf_width = slwf_w, \
2861 .drvtype_reg = DRV_PINGROUP_DVRTYPE_##drvtype(r), \ 1756 .drvtype_reg = DRV_PINGROUP_REG_##drvtype(r), \
2862 .drvtype_bank = 0, \ 1757 .drvtype_bank = 0, \
2863 .drvtype_bit = 6, \ 1758 .drvtype_bit = 6, \
2864 } 1759 }
@@ -2909,8 +1804,8 @@ static const struct tegra_pingroup tegra124_groups[] = {
2909 PINGROUP(pu4, PWM1, UARTA, GMI, DISPLAYB, PWM1, 0x3194, N, N, N), 1804 PINGROUP(pu4, PWM1, UARTA, GMI, DISPLAYB, PWM1, 0x3194, N, N, N),
2910 PINGROUP(pu5, PWM2, UARTA, GMI, DISPLAYB, PWM2, 0x3198, N, N, N), 1805 PINGROUP(pu5, PWM2, UARTA, GMI, DISPLAYB, PWM2, 0x3198, N, N, N),
2911 PINGROUP(pu6, PWM3, UARTA, RSVD3, GMI, RSVD3, 0x319c, N, N, N), 1806 PINGROUP(pu6, PWM3, UARTA, RSVD3, GMI, RSVD3, 0x319c, N, N, N),
2912 PINGROUP(gen1_i2c_scl_pc4, I2C1, RSVD2, RSVD3, RSVD4, I2C1, 0x31a0, Y, N, N), 1807 PINGROUP(gen1_i2c_sda_pc5, I2C1, RSVD2, RSVD3, RSVD4, I2C1, 0x31a0, Y, N, N),
2913 PINGROUP(gen1_i2c_sda_pc5, I2C1, RSVD2, RSVD3, RSVD4, I2C1, 0x31a4, Y, N, N), 1808 PINGROUP(gen1_i2c_scl_pc4, I2C1, RSVD2, RSVD3, RSVD4, I2C1, 0x31a4, Y, N, N),
2914 PINGROUP(dap4_fs_pp4, I2S3, GMI, DTV, RSVD4, I2S3, 0x31a8, N, N, N), 1809 PINGROUP(dap4_fs_pp4, I2S3, GMI, DTV, RSVD4, I2S3, 0x31a8, N, N, N),
2915 PINGROUP(dap4_din_pp5, I2S3, GMI, RSVD3, RSVD4, I2S3, 0x31ac, N, N, N), 1810 PINGROUP(dap4_din_pp5, I2S3, GMI, RSVD3, RSVD4, I2S3, 0x31ac, N, N, N),
2916 PINGROUP(dap4_dout_pp6, I2S3, GMI, DTV, RSVD4, I2S3, 0x31b0, N, N, N), 1811 PINGROUP(dap4_dout_pp6, I2S3, GMI, DTV, RSVD4, I2S3, 0x31b0, N, N, N),
@@ -2964,9 +1859,9 @@ static const struct tegra_pingroup tegra124_groups[] = {
2964 PINGROUP(sdmmc4_dat4_paa4, SDMMC4, SPI3, GMI, RSVD4, SDMMC4, 0x3270, N, Y, N), 1859 PINGROUP(sdmmc4_dat4_paa4, SDMMC4, SPI3, GMI, RSVD4, SDMMC4, 0x3270, N, Y, N),
2965 PINGROUP(sdmmc4_dat5_paa5, SDMMC4, SPI3, RSVD3, RSVD4, SDMMC4, 0x3274, N, Y, N), 1860 PINGROUP(sdmmc4_dat5_paa5, SDMMC4, SPI3, RSVD3, RSVD4, SDMMC4, 0x3274, N, Y, N),
2966 PINGROUP(sdmmc4_dat6_paa6, SDMMC4, SPI3, GMI, RSVD4, SDMMC4, 0x3278, N, Y, N), 1861 PINGROUP(sdmmc4_dat6_paa6, SDMMC4, SPI3, GMI, RSVD4, SDMMC4, 0x3278, N, Y, N),
2967 PINGROUP(sdmmc4_dat7_paa7, SDMMC4, RSVD1, GMI, RSVD4, SDMMC4, 0x327c, N, Y, N), 1862 PINGROUP(sdmmc4_dat7_paa7, SDMMC4, RSVD2, GMI, RSVD4, SDMMC4, 0x327c, N, Y, N),
2968 PINGROUP(cam_mclk_pcc0, VI, VI_ALT1, VI_ALT3, SDMMC2, VI, 0x3284, N, N, N), 1863 PINGROUP(cam_mclk_pcc0, VI, VI_ALT1, VI_ALT3, SDMMC2, VI, 0x3284, N, N, N),
2969 PINGROUP(pcc1, I2S4, RSVD1, RSVD3, SDMMC2, I2S4, 0x3288, N, N, N), 1864 PINGROUP(pcc1, I2S4, RSVD2, RSVD3, SDMMC2, I2S4, 0x3288, N, N, N),
2970 PINGROUP(pbb0, VGP6, VIMCLK2, SDMMC2, VIMCLK2_ALT, VGP6, 0x328c, N, N, N), 1865 PINGROUP(pbb0, VGP6, VIMCLK2, SDMMC2, VIMCLK2_ALT, VGP6, 0x328c, N, N, N),
2971 PINGROUP(cam_i2c_scl_pbb1, VGP1, I2C3, RSVD3, SDMMC2, VGP1, 0x3290, Y, N, N), 1866 PINGROUP(cam_i2c_scl_pbb1, VGP1, I2C3, RSVD3, SDMMC2, VGP1, 0x3290, Y, N, N),
2972 PINGROUP(cam_i2c_sda_pbb2, VGP2, I2C3, RSVD3, SDMMC2, VGP2, 0x3294, Y, N, N), 1867 PINGROUP(cam_i2c_sda_pbb2, VGP2, I2C3, RSVD3, SDMMC2, VGP2, 0x3294, Y, N, N),
@@ -3047,8 +1942,8 @@ static const struct tegra_pingroup tegra124_groups[] = {
3047 PINGROUP(gpio_w3_aud_pw3, SPI6, SPI1, SPI2, I2C1, SPI1, 0x33f0, N, N, N), 1942 PINGROUP(gpio_w3_aud_pw3, SPI6, SPI1, SPI2, I2C1, SPI1, 0x33f0, N, N, N),
3048 PINGROUP(usb_vbus_en0_pn4, USB, RSVD2, RSVD3, RSVD4, USB, 0x33f4, Y, N, N), 1943 PINGROUP(usb_vbus_en0_pn4, USB, RSVD2, RSVD3, RSVD4, USB, 0x33f4, Y, N, N),
3049 PINGROUP(usb_vbus_en1_pn5, USB, RSVD2, RSVD3, RSVD4, USB, 0x33f8, Y, N, N), 1944 PINGROUP(usb_vbus_en1_pn5, USB, RSVD2, RSVD3, RSVD4, USB, 0x33f8, Y, N, N),
3050 PINGROUP(sdmmc3_clk_lb_out_pee4, SDMMC3, RSVD2, RSVD3, RSVD4, SDMMC3, 0x33fc, N, N, N), 1945 PINGROUP(sdmmc3_clk_lb_in_pee5, SDMMC3, RSVD2, RSVD3, RSVD4, SDMMC3, 0x33fc, N, N, N),
3051 PINGROUP(sdmmc3_clk_lb_in_pee5, SDMMC3, RSVD2, RSVD3, RSVD4, SDMMC3, 0x3400, N, N, N), 1946 PINGROUP(sdmmc3_clk_lb_out_pee4, SDMMC3, RSVD2, RSVD3, RSVD4, SDMMC3, 0x3400, N, N, N),
3052 PINGROUP(gmi_clk_lb, SDMMC2, RSVD2, GMI, RSVD4, SDMMC2, 0x3404, N, N, N), 1947 PINGROUP(gmi_clk_lb, SDMMC2, RSVD2, GMI, RSVD4, SDMMC2, 0x3404, N, N, N),
3053 PINGROUP(reset_out_n, RSVD1, RSVD2, RSVD3, RESET_OUT_N, RSVD1, 0x3408, N, N, N), 1948 PINGROUP(reset_out_n, RSVD1, RSVD2, RSVD3, RESET_OUT_N, RSVD1, 0x3408, N, N, N),
3054 PINGROUP(kb_row16_pt0, KBC, RSVD2, RSVD3, UARTC, KBC, 0x340c, N, N, N), 1949 PINGROUP(kb_row16_pt0, KBC, RSVD2, RSVD3, UARTC, KBC, 0x340c, N, N, N),
diff --git a/drivers/pinctrl/pinctrl-tegra20.c b/drivers/pinctrl/pinctrl-tegra20.c
index fcfb7d012c5b..e0b504088387 100644
--- a/drivers/pinctrl/pinctrl-tegra20.c
+++ b/drivers/pinctrl/pinctrl-tegra20.c
@@ -1894,637 +1894,12 @@ enum tegra_mux {
1894 TEGRA_MUX_XIO, 1894 TEGRA_MUX_XIO,
1895}; 1895};
1896 1896
1897static const char * const ahb_clk_groups[] = {
1898 "cdev2",
1899};
1900
1901static const char * const apb_clk_groups[] = {
1902 "cdev2",
1903};
1904
1905static const char * const audio_sync_groups[] = {
1906 "cdev1",
1907};
1908
1909static const char * const crt_groups[] = {
1910 "crtp",
1911 "lm1",
1912};
1913
1914static const char * const dap1_groups[] = {
1915 "dap1",
1916};
1917
1918static const char * const dap2_groups[] = {
1919 "dap2",
1920};
1921
1922static const char * const dap3_groups[] = {
1923 "dap3",
1924};
1925
1926static const char * const dap4_groups[] = {
1927 "dap4",
1928};
1929
1930static const char * const dap5_groups[] = {
1931 "gme",
1932};
1933
1934static const char * const displaya_groups[] = {
1935 "lcsn",
1936 "ld0",
1937 "ld1",
1938 "ld10",
1939 "ld11",
1940 "ld12",
1941 "ld13",
1942 "ld14",
1943 "ld15",
1944 "ld16",
1945 "ld17",
1946 "ld2",
1947 "ld3",
1948 "ld4",
1949 "ld5",
1950 "ld6",
1951 "ld7",
1952 "ld8",
1953 "ld9",
1954 "ldc",
1955 "ldi",
1956 "lhp0",
1957 "lhp1",
1958 "lhp2",
1959 "lhs",
1960 "lm0",
1961 "lm1",
1962 "lpp",
1963 "lpw0",
1964 "lpw1",
1965 "lpw2",
1966 "lsc0",
1967 "lsc1",
1968 "lsck",
1969 "lsda",
1970 "lsdi",
1971 "lspi",
1972 "lvp0",
1973 "lvp1",
1974 "lvs",
1975};
1976
1977static const char * const displayb_groups[] = {
1978 "lcsn",
1979 "ld0",
1980 "ld1",
1981 "ld10",
1982 "ld11",
1983 "ld12",
1984 "ld13",
1985 "ld14",
1986 "ld15",
1987 "ld16",
1988 "ld17",
1989 "ld2",
1990 "ld3",
1991 "ld4",
1992 "ld5",
1993 "ld6",
1994 "ld7",
1995 "ld8",
1996 "ld9",
1997 "ldc",
1998 "ldi",
1999 "lhp0",
2000 "lhp1",
2001 "lhp2",
2002 "lhs",
2003 "lm0",
2004 "lm1",
2005 "lpp",
2006 "lpw0",
2007 "lpw1",
2008 "lpw2",
2009 "lsc0",
2010 "lsc1",
2011 "lsck",
2012 "lsda",
2013 "lsdi",
2014 "lspi",
2015 "lvp0",
2016 "lvp1",
2017 "lvs",
2018};
2019
2020static const char * const emc_test0_dll_groups[] = {
2021 "kbca",
2022};
2023
2024static const char * const emc_test1_dll_groups[] = {
2025 "kbcc",
2026};
2027
2028static const char * const gmi_groups[] = {
2029 "ata",
2030 "atb",
2031 "atc",
2032 "atd",
2033 "ate",
2034 "dap1",
2035 "dap2",
2036 "dap4",
2037 "gma",
2038 "gmb",
2039 "gmc",
2040 "gmd",
2041 "gme",
2042 "gpu",
2043 "irrx",
2044 "irtx",
2045 "pta",
2046 "spia",
2047 "spib",
2048 "spic",
2049 "spid",
2050 "spie",
2051 "uca",
2052 "ucb",
2053};
2054
2055static const char * const gmi_int_groups[] = {
2056 "gmb",
2057};
2058
2059static const char * const hdmi_groups[] = {
2060 "hdint",
2061 "lpw0",
2062 "lpw2",
2063 "lsc1",
2064 "lsck",
2065 "lsda",
2066 "lspi",
2067 "pta",
2068};
2069
2070static const char * const i2cp_groups[] = {
2071 "i2cp",
2072};
2073
2074static const char * const i2c1_groups[] = {
2075 "rm",
2076 "spdi",
2077 "spdo",
2078 "spig",
2079 "spih",
2080};
2081
2082static const char * const i2c2_groups[] = {
2083 "ddc",
2084 "pta",
2085};
2086
2087static const char * const i2c3_groups[] = {
2088 "dtf",
2089};
2090
2091static const char * const ide_groups[] = {
2092 "ata",
2093 "atb",
2094 "atc",
2095 "atd",
2096 "ate",
2097 "gmb",
2098};
2099
2100static const char * const irda_groups[] = {
2101 "uad",
2102};
2103
2104static const char * const kbc_groups[] = {
2105 "kbca",
2106 "kbcb",
2107 "kbcc",
2108 "kbcd",
2109 "kbce",
2110 "kbcf",
2111};
2112
2113static const char * const mio_groups[] = {
2114 "kbcb",
2115 "kbcd",
2116 "kbcf",
2117};
2118
2119static const char * const mipi_hs_groups[] = {
2120 "uaa",
2121 "uab",
2122};
2123
2124static const char * const nand_groups[] = {
2125 "ata",
2126 "atb",
2127 "atc",
2128 "atd",
2129 "ate",
2130 "gmb",
2131 "gmd",
2132 "kbca",
2133 "kbcb",
2134 "kbcc",
2135 "kbcd",
2136 "kbce",
2137 "kbcf",
2138};
2139
2140static const char * const osc_groups[] = {
2141 "cdev1",
2142 "cdev2",
2143};
2144
2145static const char * const owr_groups[] = {
2146 "kbce",
2147 "owc",
2148 "uac",
2149};
2150
2151static const char * const pcie_groups[] = {
2152 "gpv",
2153 "slxa",
2154 "slxk",
2155};
2156
2157static const char * const plla_out_groups[] = {
2158 "cdev1",
2159};
2160
2161static const char * const pllc_out1_groups[] = {
2162 "csus",
2163};
2164
2165static const char * const pllm_out1_groups[] = {
2166 "cdev1",
2167};
2168
2169static const char * const pllp_out2_groups[] = {
2170 "csus",
2171};
2172
2173static const char * const pllp_out3_groups[] = {
2174 "csus",
2175};
2176
2177static const char * const pllp_out4_groups[] = {
2178 "cdev2",
2179};
2180
2181static const char * const pwm_groups[] = {
2182 "gpu",
2183 "sdb",
2184 "sdc",
2185 "sdd",
2186 "ucb",
2187};
2188
2189static const char * const pwr_intr_groups[] = {
2190 "pmc",
2191};
2192
2193static const char * const pwr_on_groups[] = {
2194 "pmc",
2195};
2196
2197static const char * const rsvd1_groups[] = {
2198 "dta",
2199 "dtb",
2200 "dtc",
2201 "dtd",
2202 "dte",
2203 "gmd",
2204 "gme",
2205};
2206
2207static const char * const rsvd2_groups[] = {
2208 "crtp",
2209 "dap1",
2210 "dap3",
2211 "dap4",
2212 "ddc",
2213 "dtb",
2214 "dtc",
2215 "dte",
2216 "dtf",
2217 "gpu7",
2218 "gpv",
2219 "hdint",
2220 "i2cp",
2221 "owc",
2222 "rm",
2223 "sdio1",
2224 "spdi",
2225 "spdo",
2226 "uac",
2227 "uca",
2228 "uda",
2229};
2230
2231static const char * const rsvd3_groups[] = {
2232 "crtp",
2233 "dap2",
2234 "dap3",
2235 "ddc",
2236 "gpu7",
2237 "gpv",
2238 "hdint",
2239 "i2cp",
2240 "ld17",
2241 "ldc",
2242 "ldi",
2243 "lhp0",
2244 "lhp1",
2245 "lhp2",
2246 "lm1",
2247 "lpp",
2248 "lpw1",
2249 "lvp0",
2250 "lvp1",
2251 "owc",
2252 "pmc",
2253 "rm",
2254 "uac",
2255};
2256
2257static const char * const rsvd4_groups[] = {
2258 "ata",
2259 "ate",
2260 "crtp",
2261 "dap3",
2262 "dap4",
2263 "ddc",
2264 "dta",
2265 "dtc",
2266 "dtd",
2267 "dtf",
2268 "gpu",
2269 "gpu7",
2270 "gpv",
2271 "hdint",
2272 "i2cp",
2273 "kbce",
2274 "lcsn",
2275 "ld0",
2276 "ld1",
2277 "ld2",
2278 "ld3",
2279 "ld4",
2280 "ld5",
2281 "ld6",
2282 "ld7",
2283 "ld8",
2284 "ld9",
2285 "ld10",
2286 "ld11",
2287 "ld12",
2288 "ld13",
2289 "ld14",
2290 "ld15",
2291 "ld16",
2292 "ld17",
2293 "ldc",
2294 "ldi",
2295 "lhp0",
2296 "lhp1",
2297 "lhp2",
2298 "lhs",
2299 "lm0",
2300 "lpp",
2301 "lpw1",
2302 "lsc0",
2303 "lsdi",
2304 "lvp0",
2305 "lvp1",
2306 "lvs",
2307 "owc",
2308 "pmc",
2309 "pta",
2310 "rm",
2311 "spif",
2312 "uac",
2313 "uca",
2314 "ucb",
2315};
2316
2317static const char * const rtck_groups[] = {
2318 "gpu7",
2319};
2320
2321static const char * const sdio1_groups[] = {
2322 "sdio1",
2323};
2324
2325static const char * const sdio2_groups[] = {
2326 "dap1",
2327 "dta",
2328 "dtd",
2329 "kbca",
2330 "kbcb",
2331 "kbcd",
2332 "spdi",
2333 "spdo",
2334};
2335
2336static const char * const sdio3_groups[] = {
2337 "sdb",
2338 "sdc",
2339 "sdd",
2340 "slxa",
2341 "slxc",
2342 "slxd",
2343 "slxk",
2344};
2345
2346static const char * const sdio4_groups[] = {
2347 "atb",
2348 "atc",
2349 "atd",
2350 "gma",
2351 "gme",
2352};
2353
2354static const char * const sflash_groups[] = {
2355 "gmc",
2356 "gmd",
2357};
2358
2359static const char * const spdif_groups[] = {
2360 "slxc",
2361 "slxd",
2362 "spdi",
2363 "spdo",
2364 "uad",
2365};
2366
2367static const char * const spi1_groups[] = {
2368 "dtb",
2369 "dte",
2370 "spia",
2371 "spib",
2372 "spic",
2373 "spid",
2374 "spie",
2375 "spif",
2376 "uda",
2377};
2378
2379static const char * const spi2_groups[] = {
2380 "sdb",
2381 "slxa",
2382 "slxc",
2383 "slxd",
2384 "slxk",
2385 "spia",
2386 "spib",
2387 "spic",
2388 "spid",
2389 "spie",
2390 "spif",
2391 "spig",
2392 "spih",
2393 "uab",
2394};
2395
2396static const char * const spi2_alt_groups[] = {
2397 "spid",
2398 "spie",
2399 "spig",
2400 "spih",
2401};
2402
2403static const char * const spi3_groups[] = {
2404 "gma",
2405 "lcsn",
2406 "lm0",
2407 "lpw0",
2408 "lpw2",
2409 "lsc1",
2410 "lsck",
2411 "lsda",
2412 "lsdi",
2413 "sdc",
2414 "sdd",
2415 "spia",
2416 "spib",
2417 "spic",
2418 "spif",
2419 "spig",
2420 "spih",
2421 "uaa",
2422};
2423
2424static const char * const spi4_groups[] = {
2425 "gmc",
2426 "irrx",
2427 "irtx",
2428 "slxa",
2429 "slxc",
2430 "slxd",
2431 "slxk",
2432 "uad",
2433};
2434
2435static const char * const trace_groups[] = {
2436 "kbcc",
2437 "kbcf",
2438};
2439
2440static const char * const twc_groups[] = {
2441 "dap2",
2442 "sdc",
2443};
2444
2445static const char * const uarta_groups[] = {
2446 "gpu",
2447 "irrx",
2448 "irtx",
2449 "sdb",
2450 "sdd",
2451 "sdio1",
2452 "uaa",
2453 "uab",
2454 "uad",
2455};
2456
2457static const char * const uartb_groups[] = {
2458 "irrx",
2459 "irtx",
2460};
2461
2462static const char * const uartc_groups[] = {
2463 "uca",
2464 "ucb",
2465};
2466
2467static const char * const uartd_groups[] = {
2468 "gmc",
2469 "uda",
2470};
2471
2472static const char * const uarte_groups[] = {
2473 "gma",
2474 "sdio1",
2475};
2476
2477static const char * const ulpi_groups[] = {
2478 "uaa",
2479 "uab",
2480 "uda",
2481};
2482
2483static const char * const vi_groups[] = {
2484 "dta",
2485 "dtb",
2486 "dtc",
2487 "dtd",
2488 "dte",
2489 "dtf",
2490};
2491
2492static const char * const vi_sensor_clk_groups[] = {
2493 "csus",
2494};
2495
2496static const char * const xio_groups[] = {
2497 "ld0",
2498 "ld1",
2499 "ld10",
2500 "ld11",
2501 "ld12",
2502 "ld13",
2503 "ld14",
2504 "ld15",
2505 "ld16",
2506 "ld2",
2507 "ld3",
2508 "ld4",
2509 "ld5",
2510 "ld6",
2511 "ld7",
2512 "ld8",
2513 "ld9",
2514 "lhs",
2515 "lsc0",
2516 "lspi",
2517 "lvs",
2518};
2519
2520#define FUNCTION(fname) \ 1897#define FUNCTION(fname) \
2521 { \ 1898 { \
2522 .name = #fname, \ 1899 .name = #fname, \
2523 .groups = fname##_groups, \
2524 .ngroups = ARRAY_SIZE(fname##_groups), \
2525 } 1900 }
2526 1901
2527static const struct tegra_function tegra20_functions[] = { 1902static struct tegra_function tegra20_functions[] = {
2528 FUNCTION(ahb_clk), 1903 FUNCTION(ahb_clk),
2529 FUNCTION(apb_clk), 1904 FUNCTION(apb_clk),
2530 FUNCTION(audio_sync), 1905 FUNCTION(audio_sync),
@@ -2881,18 +2256,7 @@ static struct platform_driver tegra20_pinctrl_driver = {
2881 .probe = tegra20_pinctrl_probe, 2256 .probe = tegra20_pinctrl_probe,
2882 .remove = tegra_pinctrl_remove, 2257 .remove = tegra_pinctrl_remove,
2883}; 2258};
2884 2259module_platform_driver(tegra20_pinctrl_driver);
2885static int __init tegra20_pinctrl_init(void)
2886{
2887 return platform_driver_register(&tegra20_pinctrl_driver);
2888}
2889arch_initcall(tegra20_pinctrl_init);
2890
2891static void __exit tegra20_pinctrl_exit(void)
2892{
2893 platform_driver_unregister(&tegra20_pinctrl_driver);
2894}
2895module_exit(tegra20_pinctrl_exit);
2896 2260
2897MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>"); 2261MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
2898MODULE_DESCRIPTION("NVIDIA Tegra20 pinctrl driver"); 2262MODULE_DESCRIPTION("NVIDIA Tegra20 pinctrl driver");
diff --git a/drivers/pinctrl/pinctrl-tegra30.c b/drivers/pinctrl/pinctrl-tegra30.c
index 2300deba25bd..41d24f5c2854 100644
--- a/drivers/pinctrl/pinctrl-tegra30.c
+++ b/drivers/pinctrl/pinctrl-tegra30.c
@@ -25,7 +25,7 @@
25 * Most pins affected by the pinmux can also be GPIOs. Define these first. 25 * Most pins affected by the pinmux can also be GPIOs. Define these first.
26 * These must match how the GPIO driver names/numbers its pins. 26 * These must match how the GPIO driver names/numbers its pins.
27 */ 27 */
28#define _GPIO(offset) (offset) 28#define _GPIO(offset) (offset)
29 29
30#define TEGRA_PIN_CLK_32K_OUT_PA0 _GPIO(0) 30#define TEGRA_PIN_CLK_32K_OUT_PA0 _GPIO(0)
31#define TEGRA_PIN_UART3_CTS_N_PA1 _GPIO(1) 31#define TEGRA_PIN_UART3_CTS_N_PA1 _GPIO(1)
@@ -277,8 +277,8 @@
277#define TEGRA_PIN_PEE7 _GPIO(247) 277#define TEGRA_PIN_PEE7 _GPIO(247)
278 278
279/* All non-GPIO pins follow */ 279/* All non-GPIO pins follow */
280#define NUM_GPIOS (TEGRA_PIN_PEE7 + 1) 280#define NUM_GPIOS (TEGRA_PIN_PEE7 + 1)
281#define _PIN(offset) (NUM_GPIOS + (offset)) 281#define _PIN(offset) (NUM_GPIOS + (offset))
282 282
283/* Non-GPIO pins */ 283/* Non-GPIO pins */
284#define TEGRA_PIN_CLK_32K_IN _PIN(0) 284#define TEGRA_PIN_CLK_32K_IN _PIN(0)
@@ -2015,1253 +2015,13 @@ enum tegra_mux {
2015 TEGRA_MUX_VI_ALT2, 2015 TEGRA_MUX_VI_ALT2,
2016 TEGRA_MUX_VI_ALT3, 2016 TEGRA_MUX_VI_ALT3,
2017}; 2017};
2018static const char * const blink_groups[] = {
2019 "clk_32k_out_pa0",
2020};
2021
2022static const char * const cec_groups[] = {
2023 "hdmi_cec_pee3",
2024 "owr",
2025};
2026
2027static const char * const clk_12m_out_groups[] = {
2028 "pv3",
2029};
2030
2031static const char * const clk_32k_in_groups[] = {
2032 "clk_32k_in",
2033};
2034
2035static const char * const core_pwr_req_groups[] = {
2036 "core_pwr_req",
2037};
2038
2039static const char * const cpu_pwr_req_groups[] = {
2040 "cpu_pwr_req",
2041};
2042
2043static const char * const crt_groups[] = {
2044 "crt_hsync_pv6",
2045 "crt_vsync_pv7",
2046};
2047
2048static const char * const dap_groups[] = {
2049 "clk1_req_pee2",
2050 "clk2_req_pcc5",
2051};
2052
2053static const char * const ddr_groups[] = {
2054 "vi_d0_pt4",
2055 "vi_d1_pd5",
2056 "vi_d10_pt2",
2057 "vi_d11_pt3",
2058 "vi_d2_pl0",
2059 "vi_d3_pl1",
2060 "vi_d4_pl2",
2061 "vi_d5_pl3",
2062 "vi_d6_pl4",
2063 "vi_d7_pl5",
2064 "vi_d8_pl6",
2065 "vi_d9_pl7",
2066 "vi_hsync_pd7",
2067 "vi_vsync_pd6",
2068};
2069
2070static const char * const dev3_groups[] = {
2071 "clk3_req_pee1",
2072};
2073
2074static const char * const displaya_groups[] = {
2075 "dap3_din_pp1",
2076 "dap3_dout_pp2",
2077 "dap3_fs_pp0",
2078 "dap3_sclk_pp3",
2079 "pbb3",
2080 "pbb4",
2081 "pbb5",
2082 "pbb6",
2083 "lcd_cs0_n_pn4",
2084 "lcd_cs1_n_pw0",
2085 "lcd_d0_pe0",
2086 "lcd_d1_pe1",
2087 "lcd_d10_pf2",
2088 "lcd_d11_pf3",
2089 "lcd_d12_pf4",
2090 "lcd_d13_pf5",
2091 "lcd_d14_pf6",
2092 "lcd_d15_pf7",
2093 "lcd_d16_pm0",
2094 "lcd_d17_pm1",
2095 "lcd_d18_pm2",
2096 "lcd_d19_pm3",
2097 "lcd_d2_pe2",
2098 "lcd_d20_pm4",
2099 "lcd_d21_pm5",
2100 "lcd_d22_pm6",
2101 "lcd_d23_pm7",
2102 "lcd_d3_pe3",
2103 "lcd_d4_pe4",
2104 "lcd_d5_pe5",
2105 "lcd_d6_pe6",
2106 "lcd_d7_pe7",
2107 "lcd_d8_pf0",
2108 "lcd_d9_pf1",
2109 "lcd_dc0_pn6",
2110 "lcd_dc1_pd2",
2111 "lcd_de_pj1",
2112 "lcd_hsync_pj3",
2113 "lcd_m1_pw1",
2114 "lcd_pclk_pb3",
2115 "lcd_pwr0_pb2",
2116 "lcd_pwr1_pc1",
2117 "lcd_pwr2_pc6",
2118 "lcd_sck_pz4",
2119 "lcd_sdin_pz2",
2120 "lcd_sdout_pn5",
2121 "lcd_vsync_pj4",
2122 "lcd_wr_n_pz3",
2123};
2124
2125static const char * const displayb_groups[] = {
2126 "dap3_din_pp1",
2127 "dap3_dout_pp2",
2128 "dap3_fs_pp0",
2129 "dap3_sclk_pp3",
2130 "pbb3",
2131 "pbb4",
2132 "pbb5",
2133 "pbb6",
2134 "lcd_cs0_n_pn4",
2135 "lcd_cs1_n_pw0",
2136 "lcd_d0_pe0",
2137 "lcd_d1_pe1",
2138 "lcd_d10_pf2",
2139 "lcd_d11_pf3",
2140 "lcd_d12_pf4",
2141 "lcd_d13_pf5",
2142 "lcd_d14_pf6",
2143 "lcd_d15_pf7",
2144 "lcd_d16_pm0",
2145 "lcd_d17_pm1",
2146 "lcd_d18_pm2",
2147 "lcd_d19_pm3",
2148 "lcd_d2_pe2",
2149 "lcd_d20_pm4",
2150 "lcd_d21_pm5",
2151 "lcd_d22_pm6",
2152 "lcd_d23_pm7",
2153 "lcd_d3_pe3",
2154 "lcd_d4_pe4",
2155 "lcd_d5_pe5",
2156 "lcd_d6_pe6",
2157 "lcd_d7_pe7",
2158 "lcd_d8_pf0",
2159 "lcd_d9_pf1",
2160 "lcd_dc0_pn6",
2161 "lcd_dc1_pd2",
2162 "lcd_de_pj1",
2163 "lcd_hsync_pj3",
2164 "lcd_m1_pw1",
2165 "lcd_pclk_pb3",
2166 "lcd_pwr0_pb2",
2167 "lcd_pwr1_pc1",
2168 "lcd_pwr2_pc6",
2169 "lcd_sck_pz4",
2170 "lcd_sdin_pz2",
2171 "lcd_sdout_pn5",
2172 "lcd_vsync_pj4",
2173 "lcd_wr_n_pz3",
2174};
2175
2176static const char * const dtv_groups[] = {
2177 "gmi_a17_pb0",
2178 "gmi_a18_pb1",
2179 "gmi_cs0_n_pj0",
2180 "gmi_cs1_n_pj2",
2181};
2182
2183static const char * const extperiph1_groups[] = {
2184 "clk1_out_pw4",
2185};
2186
2187static const char * const extperiph2_groups[] = {
2188 "clk2_out_pw5",
2189};
2190
2191static const char * const extperiph3_groups[] = {
2192 "clk3_out_pee0",
2193};
2194
2195static const char * const gmi_groups[] = {
2196 "dap1_din_pn1",
2197 "dap1_dout_pn2",
2198 "dap1_fs_pn0",
2199 "dap1_sclk_pn3",
2200 "dap2_din_pa4",
2201 "dap2_dout_pa5",
2202 "dap2_fs_pa2",
2203 "dap2_sclk_pa3",
2204 "dap4_din_pp5",
2205 "dap4_dout_pp6",
2206 "dap4_fs_pp4",
2207 "dap4_sclk_pp7",
2208 "gen2_i2c_scl_pt5",
2209 "gen2_i2c_sda_pt6",
2210 "gmi_a16_pj7",
2211 "gmi_a17_pb0",
2212 "gmi_a18_pb1",
2213 "gmi_a19_pk7",
2214 "gmi_ad0_pg0",
2215 "gmi_ad1_pg1",
2216 "gmi_ad10_ph2",
2217 "gmi_ad11_ph3",
2218 "gmi_ad12_ph4",
2219 "gmi_ad13_ph5",
2220 "gmi_ad14_ph6",
2221 "gmi_ad15_ph7",
2222 "gmi_ad2_pg2",
2223 "gmi_ad3_pg3",
2224 "gmi_ad4_pg4",
2225 "gmi_ad5_pg5",
2226 "gmi_ad6_pg6",
2227 "gmi_ad7_pg7",
2228 "gmi_ad8_ph0",
2229 "gmi_ad9_ph1",
2230 "gmi_adv_n_pk0",
2231 "gmi_clk_pk1",
2232 "gmi_cs0_n_pj0",
2233 "gmi_cs1_n_pj2",
2234 "gmi_cs2_n_pk3",
2235 "gmi_cs3_n_pk4",
2236 "gmi_cs4_n_pk2",
2237 "gmi_cs6_n_pi3",
2238 "gmi_cs7_n_pi6",
2239 "gmi_dqs_pi2",
2240 "gmi_iordy_pi5",
2241 "gmi_oe_n_pi1",
2242 "gmi_rst_n_pi4",
2243 "gmi_wait_pi7",
2244 "gmi_wp_n_pc7",
2245 "gmi_wr_n_pi0",
2246 "pu0",
2247 "pu1",
2248 "pu2",
2249 "pu3",
2250 "pu4",
2251 "pu5",
2252 "pu6",
2253 "sdmmc4_clk_pcc4",
2254 "sdmmc4_cmd_pt7",
2255 "sdmmc4_dat0_paa0",
2256 "sdmmc4_dat1_paa1",
2257 "sdmmc4_dat2_paa2",
2258 "sdmmc4_dat3_paa3",
2259 "sdmmc4_dat4_paa4",
2260 "sdmmc4_dat5_paa5",
2261 "sdmmc4_dat6_paa6",
2262 "sdmmc4_dat7_paa7",
2263 "spi1_cs0_n_px6",
2264 "spi1_mosi_px4",
2265 "spi1_sck_px5",
2266 "spi2_cs0_n_px3",
2267 "spi2_miso_px1",
2268 "spi2_mosi_px0",
2269 "spi2_sck_px2",
2270 "uart2_cts_n_pj5",
2271 "uart2_rts_n_pj6",
2272 "uart3_cts_n_pa1",
2273 "uart3_rts_n_pc0",
2274 "uart3_rxd_pw7",
2275 "uart3_txd_pw6",
2276};
2277
2278static const char * const gmi_alt_groups[] = {
2279 "gmi_a16_pj7",
2280 "gmi_cs3_n_pk4",
2281 "gmi_cs7_n_pi6",
2282 "gmi_wp_n_pc7",
2283};
2284
2285static const char * const hda_groups[] = {
2286 "clk1_req_pee2",
2287 "dap1_din_pn1",
2288 "dap1_dout_pn2",
2289 "dap1_fs_pn0",
2290 "dap1_sclk_pn3",
2291 "dap2_din_pa4",
2292 "dap2_dout_pa5",
2293 "dap2_fs_pa2",
2294 "dap2_sclk_pa3",
2295 "pex_l0_clkreq_n_pdd2",
2296 "pex_l0_prsnt_n_pdd0",
2297 "pex_l0_rst_n_pdd1",
2298 "pex_l1_clkreq_n_pdd6",
2299 "pex_l1_prsnt_n_pdd4",
2300 "pex_l1_rst_n_pdd5",
2301 "pex_l2_clkreq_n_pcc7",
2302 "pex_l2_prsnt_n_pdd7",
2303 "pex_l2_rst_n_pcc6",
2304 "pex_wake_n_pdd3",
2305 "spdif_in_pk6",
2306};
2307
2308static const char * const hdcp_groups[] = {
2309 "gen2_i2c_scl_pt5",
2310 "gen2_i2c_sda_pt6",
2311 "lcd_pwr0_pb2",
2312 "lcd_pwr2_pc6",
2313 "lcd_sck_pz4",
2314 "lcd_sdout_pn5",
2315 "lcd_wr_n_pz3",
2316};
2317
2318static const char * const hdmi_groups[] = {
2319 "hdmi_int_pn7",
2320};
2321
2322static const char * const hsi_groups[] = {
2323 "ulpi_data0_po1",
2324 "ulpi_data1_po2",
2325 "ulpi_data2_po3",
2326 "ulpi_data3_po4",
2327 "ulpi_data4_po5",
2328 "ulpi_data5_po6",
2329 "ulpi_data6_po7",
2330 "ulpi_data7_po0",
2331};
2332
2333static const char * const i2c1_groups[] = {
2334 "gen1_i2c_scl_pc4",
2335 "gen1_i2c_sda_pc5",
2336 "spdif_in_pk6",
2337 "spdif_out_pk5",
2338 "spi2_cs1_n_pw2",
2339 "spi2_cs2_n_pw3",
2340};
2341
2342static const char * const i2c2_groups[] = {
2343 "gen2_i2c_scl_pt5",
2344 "gen2_i2c_sda_pt6",
2345};
2346
2347static const char * const i2c3_groups[] = {
2348 "cam_i2c_scl_pbb1",
2349 "cam_i2c_sda_pbb2",
2350 "sdmmc4_cmd_pt7",
2351 "sdmmc4_dat4_paa4",
2352};
2353
2354static const char * const i2c4_groups[] = {
2355 "ddc_scl_pv4",
2356 "ddc_sda_pv5",
2357};
2358
2359static const char * const i2cpwr_groups[] = {
2360 "pwr_i2c_scl_pz6",
2361 "pwr_i2c_sda_pz7",
2362};
2363
2364static const char * const i2s0_groups[] = {
2365 "dap1_din_pn1",
2366 "dap1_dout_pn2",
2367 "dap1_fs_pn0",
2368 "dap1_sclk_pn3",
2369};
2370
2371static const char * const i2s1_groups[] = {
2372 "dap2_din_pa4",
2373 "dap2_dout_pa5",
2374 "dap2_fs_pa2",
2375 "dap2_sclk_pa3",
2376};
2377
2378static const char * const i2s2_groups[] = {
2379 "dap3_din_pp1",
2380 "dap3_dout_pp2",
2381 "dap3_fs_pp0",
2382 "dap3_sclk_pp3",
2383};
2384
2385static const char * const i2s3_groups[] = {
2386 "dap4_din_pp5",
2387 "dap4_dout_pp6",
2388 "dap4_fs_pp4",
2389 "dap4_sclk_pp7",
2390};
2391
2392static const char * const i2s4_groups[] = {
2393 "pbb0",
2394 "pbb7",
2395 "pcc1",
2396 "pcc2",
2397 "sdmmc4_dat4_paa4",
2398 "sdmmc4_dat5_paa5",
2399 "sdmmc4_dat6_paa6",
2400 "sdmmc4_dat7_paa7",
2401};
2402
2403static const char * const invalid_groups[] = {
2404 "kb_row3_pr3",
2405 "sdmmc4_clk_pcc4",
2406};
2407
2408static const char * const kbc_groups[] = {
2409 "kb_col0_pq0",
2410 "kb_col1_pq1",
2411 "kb_col2_pq2",
2412 "kb_col3_pq3",
2413 "kb_col4_pq4",
2414 "kb_col5_pq5",
2415 "kb_col6_pq6",
2416 "kb_col7_pq7",
2417 "kb_row0_pr0",
2418 "kb_row1_pr1",
2419 "kb_row10_ps2",
2420 "kb_row11_ps3",
2421 "kb_row12_ps4",
2422 "kb_row13_ps5",
2423 "kb_row14_ps6",
2424 "kb_row15_ps7",
2425 "kb_row2_pr2",
2426 "kb_row3_pr3",
2427 "kb_row4_pr4",
2428 "kb_row5_pr5",
2429 "kb_row6_pr6",
2430 "kb_row7_pr7",
2431 "kb_row8_ps0",
2432 "kb_row9_ps1",
2433};
2434
2435static const char * const mio_groups[] = {
2436 "kb_col6_pq6",
2437 "kb_col7_pq7",
2438 "kb_row10_ps2",
2439 "kb_row11_ps3",
2440 "kb_row12_ps4",
2441 "kb_row13_ps5",
2442 "kb_row14_ps6",
2443 "kb_row15_ps7",
2444 "kb_row6_pr6",
2445 "kb_row7_pr7",
2446 "kb_row8_ps0",
2447 "kb_row9_ps1",
2448};
2449
2450static const char * const nand_groups[] = {
2451 "gmi_ad0_pg0",
2452 "gmi_ad1_pg1",
2453 "gmi_ad10_ph2",
2454 "gmi_ad11_ph3",
2455 "gmi_ad12_ph4",
2456 "gmi_ad13_ph5",
2457 "gmi_ad14_ph6",
2458 "gmi_ad15_ph7",
2459 "gmi_ad2_pg2",
2460 "gmi_ad3_pg3",
2461 "gmi_ad4_pg4",
2462 "gmi_ad5_pg5",
2463 "gmi_ad6_pg6",
2464 "gmi_ad7_pg7",
2465 "gmi_ad8_ph0",
2466 "gmi_ad9_ph1",
2467 "gmi_adv_n_pk0",
2468 "gmi_clk_pk1",
2469 "gmi_cs0_n_pj0",
2470 "gmi_cs1_n_pj2",
2471 "gmi_cs2_n_pk3",
2472 "gmi_cs3_n_pk4",
2473 "gmi_cs4_n_pk2",
2474 "gmi_cs6_n_pi3",
2475 "gmi_cs7_n_pi6",
2476 "gmi_dqs_pi2",
2477 "gmi_iordy_pi5",
2478 "gmi_oe_n_pi1",
2479 "gmi_rst_n_pi4",
2480 "gmi_wait_pi7",
2481 "gmi_wp_n_pc7",
2482 "gmi_wr_n_pi0",
2483 "kb_col0_pq0",
2484 "kb_col1_pq1",
2485 "kb_col2_pq2",
2486 "kb_col3_pq3",
2487 "kb_col4_pq4",
2488 "kb_col5_pq5",
2489 "kb_col6_pq6",
2490 "kb_col7_pq7",
2491 "kb_row0_pr0",
2492 "kb_row1_pr1",
2493 "kb_row10_ps2",
2494 "kb_row11_ps3",
2495 "kb_row12_ps4",
2496 "kb_row13_ps5",
2497 "kb_row14_ps6",
2498 "kb_row15_ps7",
2499 "kb_row2_pr2",
2500 "kb_row3_pr3",
2501 "kb_row4_pr4",
2502 "kb_row5_pr5",
2503 "kb_row6_pr6",
2504 "kb_row7_pr7",
2505 "kb_row8_ps0",
2506 "kb_row9_ps1",
2507 "sdmmc4_clk_pcc4",
2508 "sdmmc4_cmd_pt7",
2509};
2510
2511static const char * const nand_alt_groups[] = {
2512 "gmi_cs6_n_pi3",
2513 "gmi_cs7_n_pi6",
2514 "gmi_rst_n_pi4",
2515};
2516
2517static const char * const owr_groups[] = {
2518 "pu0",
2519 "pv2",
2520 "kb_row5_pr5",
2521 "owr",
2522};
2523
2524static const char * const pcie_groups[] = {
2525 "pex_l0_clkreq_n_pdd2",
2526 "pex_l0_prsnt_n_pdd0",
2527 "pex_l0_rst_n_pdd1",
2528 "pex_l1_clkreq_n_pdd6",
2529 "pex_l1_prsnt_n_pdd4",
2530 "pex_l1_rst_n_pdd5",
2531 "pex_l2_clkreq_n_pcc7",
2532 "pex_l2_prsnt_n_pdd7",
2533 "pex_l2_rst_n_pcc6",
2534 "pex_wake_n_pdd3",
2535};
2536
2537static const char * const pwm0_groups[] = {
2538 "gmi_ad8_ph0",
2539 "pu3",
2540 "sdmmc3_dat3_pb4",
2541 "sdmmc3_dat5_pd0",
2542 "uart3_rts_n_pc0",
2543};
2544
2545static const char * const pwm1_groups[] = {
2546 "gmi_ad9_ph1",
2547 "pu4",
2548 "sdmmc3_dat2_pb5",
2549 "sdmmc3_dat4_pd1",
2550};
2551
2552static const char * const pwm2_groups[] = {
2553 "gmi_ad10_ph2",
2554 "pu5",
2555 "sdmmc3_clk_pa6",
2556};
2557
2558static const char * const pwm3_groups[] = {
2559 "gmi_ad11_ph3",
2560 "pu6",
2561 "sdmmc3_cmd_pa7",
2562};
2563
2564static const char * const pwr_int_n_groups[] = {
2565 "pwr_int_n",
2566};
2567
2568static const char * const rsvd1_groups[] = {
2569 "gmi_ad0_pg0",
2570 "gmi_ad1_pg1",
2571 "gmi_ad12_ph4",
2572 "gmi_ad13_ph5",
2573 "gmi_ad14_ph6",
2574 "gmi_ad15_ph7",
2575 "gmi_ad2_pg2",
2576 "gmi_ad3_pg3",
2577 "gmi_ad4_pg4",
2578 "gmi_ad5_pg5",
2579 "gmi_ad6_pg6",
2580 "gmi_ad7_pg7",
2581 "gmi_adv_n_pk0",
2582 "gmi_clk_pk1",
2583 "gmi_cs0_n_pj0",
2584 "gmi_cs1_n_pj2",
2585 "gmi_cs2_n_pk3",
2586 "gmi_cs3_n_pk4",
2587 "gmi_cs4_n_pk2",
2588 "gmi_dqs_pi2",
2589 "gmi_iordy_pi5",
2590 "gmi_oe_n_pi1",
2591 "gmi_wait_pi7",
2592 "gmi_wp_n_pc7",
2593 "gmi_wr_n_pi0",
2594 "pu1",
2595 "pu2",
2596 "pv0",
2597 "pv1",
2598 "sdmmc3_dat0_pb7",
2599 "sdmmc3_dat1_pb6",
2600 "sdmmc3_dat2_pb5",
2601 "sdmmc3_dat3_pb4",
2602 "vi_pclk_pt0",
2603};
2604
2605static const char * const rsvd2_groups[] = {
2606 "clk1_out_pw4",
2607 "clk2_out_pw5",
2608 "clk2_req_pcc5",
2609 "clk3_out_pee0",
2610 "clk3_req_pee1",
2611 "clk_32k_in",
2612 "clk_32k_out_pa0",
2613 "core_pwr_req",
2614 "cpu_pwr_req",
2615 "crt_hsync_pv6",
2616 "crt_vsync_pv7",
2617 "dap3_din_pp1",
2618 "dap3_dout_pp2",
2619 "dap3_fs_pp0",
2620 "dap3_sclk_pp3",
2621 "dap4_din_pp5",
2622 "dap4_dout_pp6",
2623 "dap4_fs_pp4",
2624 "dap4_sclk_pp7",
2625 "ddc_scl_pv4",
2626 "ddc_sda_pv5",
2627 "gen1_i2c_scl_pc4",
2628 "gen1_i2c_sda_pc5",
2629 "pbb0",
2630 "pbb7",
2631 "pcc1",
2632 "pcc2",
2633 "pv0",
2634 "pv1",
2635 "pv2",
2636 "pv3",
2637 "hdmi_cec_pee3",
2638 "hdmi_int_pn7",
2639 "jtag_rtck_pu7",
2640 "pwr_i2c_scl_pz6",
2641 "pwr_i2c_sda_pz7",
2642 "pwr_int_n",
2643 "sdmmc1_clk_pz0",
2644 "sdmmc1_cmd_pz1",
2645 "sdmmc1_dat0_py7",
2646 "sdmmc1_dat1_py6",
2647 "sdmmc1_dat2_py5",
2648 "sdmmc1_dat3_py4",
2649 "sdmmc3_dat0_pb7",
2650 "sdmmc3_dat1_pb6",
2651 "sdmmc4_rst_n_pcc3",
2652 "spdif_out_pk5",
2653 "sys_clk_req_pz5",
2654 "uart3_cts_n_pa1",
2655 "uart3_rxd_pw7",
2656 "uart3_txd_pw6",
2657 "ulpi_clk_py0",
2658 "ulpi_dir_py1",
2659 "ulpi_nxt_py2",
2660 "ulpi_stp_py3",
2661 "vi_d0_pt4",
2662 "vi_d10_pt2",
2663 "vi_d11_pt3",
2664 "vi_hsync_pd7",
2665 "vi_vsync_pd6",
2666};
2667
2668static const char * const rsvd3_groups[] = {
2669 "cam_i2c_scl_pbb1",
2670 "cam_i2c_sda_pbb2",
2671 "clk1_out_pw4",
2672 "clk1_req_pee2",
2673 "clk2_out_pw5",
2674 "clk2_req_pcc5",
2675 "clk3_out_pee0",
2676 "clk3_req_pee1",
2677 "clk_32k_in",
2678 "clk_32k_out_pa0",
2679 "core_pwr_req",
2680 "cpu_pwr_req",
2681 "crt_hsync_pv6",
2682 "crt_vsync_pv7",
2683 "dap2_din_pa4",
2684 "dap2_dout_pa5",
2685 "dap2_fs_pa2",
2686 "dap2_sclk_pa3",
2687 "ddc_scl_pv4",
2688 "ddc_sda_pv5",
2689 "gen1_i2c_scl_pc4",
2690 "gen1_i2c_sda_pc5",
2691 "pbb0",
2692 "pbb7",
2693 "pcc1",
2694 "pcc2",
2695 "pv0",
2696 "pv1",
2697 "pv2",
2698 "pv3",
2699 "hdmi_cec_pee3",
2700 "hdmi_int_pn7",
2701 "jtag_rtck_pu7",
2702 "kb_row0_pr0",
2703 "kb_row1_pr1",
2704 "kb_row2_pr2",
2705 "kb_row3_pr3",
2706 "lcd_d0_pe0",
2707 "lcd_d1_pe1",
2708 "lcd_d10_pf2",
2709 "lcd_d11_pf3",
2710 "lcd_d12_pf4",
2711 "lcd_d13_pf5",
2712 "lcd_d14_pf6",
2713 "lcd_d15_pf7",
2714 "lcd_d16_pm0",
2715 "lcd_d17_pm1",
2716 "lcd_d18_pm2",
2717 "lcd_d19_pm3",
2718 "lcd_d2_pe2",
2719 "lcd_d20_pm4",
2720 "lcd_d21_pm5",
2721 "lcd_d22_pm6",
2722 "lcd_d23_pm7",
2723 "lcd_d3_pe3",
2724 "lcd_d4_pe4",
2725 "lcd_d5_pe5",
2726 "lcd_d6_pe6",
2727 "lcd_d7_pe7",
2728 "lcd_d8_pf0",
2729 "lcd_d9_pf1",
2730 "lcd_dc0_pn6",
2731 "lcd_dc1_pd2",
2732 "lcd_de_pj1",
2733 "lcd_hsync_pj3",
2734 "lcd_m1_pw1",
2735 "lcd_pclk_pb3",
2736 "lcd_pwr1_pc1",
2737 "lcd_vsync_pj4",
2738 "owr",
2739 "pex_l0_clkreq_n_pdd2",
2740 "pex_l0_prsnt_n_pdd0",
2741 "pex_l0_rst_n_pdd1",
2742 "pex_l1_clkreq_n_pdd6",
2743 "pex_l1_prsnt_n_pdd4",
2744 "pex_l1_rst_n_pdd5",
2745 "pex_l2_clkreq_n_pcc7",
2746 "pex_l2_prsnt_n_pdd7",
2747 "pex_l2_rst_n_pcc6",
2748 "pex_wake_n_pdd3",
2749 "pwr_i2c_scl_pz6",
2750 "pwr_i2c_sda_pz7",
2751 "pwr_int_n",
2752 "sdmmc1_clk_pz0",
2753 "sdmmc1_cmd_pz1",
2754 "sdmmc4_rst_n_pcc3",
2755 "sys_clk_req_pz5",
2756};
2757
2758static const char * const rsvd4_groups[] = {
2759 "clk1_out_pw4",
2760 "clk1_req_pee2",
2761 "clk2_out_pw5",
2762 "clk2_req_pcc5",
2763 "clk3_out_pee0",
2764 "clk3_req_pee1",
2765 "clk_32k_in",
2766 "clk_32k_out_pa0",
2767 "core_pwr_req",
2768 "cpu_pwr_req",
2769 "crt_hsync_pv6",
2770 "crt_vsync_pv7",
2771 "dap4_din_pp5",
2772 "dap4_dout_pp6",
2773 "dap4_fs_pp4",
2774 "dap4_sclk_pp7",
2775 "ddc_scl_pv4",
2776 "ddc_sda_pv5",
2777 "gen1_i2c_scl_pc4",
2778 "gen1_i2c_sda_pc5",
2779 "gen2_i2c_scl_pt5",
2780 "gen2_i2c_sda_pt6",
2781 "gmi_a19_pk7",
2782 "gmi_ad0_pg0",
2783 "gmi_ad1_pg1",
2784 "gmi_ad10_ph2",
2785 "gmi_ad11_ph3",
2786 "gmi_ad12_ph4",
2787 "gmi_ad13_ph5",
2788 "gmi_ad14_ph6",
2789 "gmi_ad15_ph7",
2790 "gmi_ad2_pg2",
2791 "gmi_ad3_pg3",
2792 "gmi_ad4_pg4",
2793 "gmi_ad5_pg5",
2794 "gmi_ad6_pg6",
2795 "gmi_ad7_pg7",
2796 "gmi_ad8_ph0",
2797 "gmi_ad9_ph1",
2798 "gmi_adv_n_pk0",
2799 "gmi_clk_pk1",
2800 "gmi_cs2_n_pk3",
2801 "gmi_cs4_n_pk2",
2802 "gmi_dqs_pi2",
2803 "gmi_iordy_pi5",
2804 "gmi_oe_n_pi1",
2805 "gmi_rst_n_pi4",
2806 "gmi_wait_pi7",
2807 "gmi_wr_n_pi0",
2808 "pcc2",
2809 "pu0",
2810 "pu1",
2811 "pu2",
2812 "pu3",
2813 "pu4",
2814 "pu5",
2815 "pu6",
2816 "pv0",
2817 "pv1",
2818 "pv2",
2819 "pv3",
2820 "hdmi_cec_pee3",
2821 "hdmi_int_pn7",
2822 "jtag_rtck_pu7",
2823 "kb_col2_pq2",
2824 "kb_col3_pq3",
2825 "kb_col4_pq4",
2826 "kb_col5_pq5",
2827 "kb_row0_pr0",
2828 "kb_row1_pr1",
2829 "kb_row2_pr2",
2830 "kb_row4_pr4",
2831 "lcd_cs0_n_pn4",
2832 "lcd_cs1_n_pw0",
2833 "lcd_d0_pe0",
2834 "lcd_d1_pe1",
2835 "lcd_d10_pf2",
2836 "lcd_d11_pf3",
2837 "lcd_d12_pf4",
2838 "lcd_d13_pf5",
2839 "lcd_d14_pf6",
2840 "lcd_d15_pf7",
2841 "lcd_d16_pm0",
2842 "lcd_d17_pm1",
2843 "lcd_d18_pm2",
2844 "lcd_d19_pm3",
2845 "lcd_d2_pe2",
2846 "lcd_d20_pm4",
2847 "lcd_d21_pm5",
2848 "lcd_d22_pm6",
2849 "lcd_d23_pm7",
2850 "lcd_d3_pe3",
2851 "lcd_d4_pe4",
2852 "lcd_d5_pe5",
2853 "lcd_d6_pe6",
2854 "lcd_d7_pe7",
2855 "lcd_d8_pf0",
2856 "lcd_d9_pf1",
2857 "lcd_dc0_pn6",
2858 "lcd_dc1_pd2",
2859 "lcd_de_pj1",
2860 "lcd_hsync_pj3",
2861 "lcd_m1_pw1",
2862 "lcd_pclk_pb3",
2863 "lcd_pwr1_pc1",
2864 "lcd_sdin_pz2",
2865 "lcd_vsync_pj4",
2866 "owr",
2867 "pex_l0_clkreq_n_pdd2",
2868 "pex_l0_prsnt_n_pdd0",
2869 "pex_l0_rst_n_pdd1",
2870 "pex_l1_clkreq_n_pdd6",
2871 "pex_l1_prsnt_n_pdd4",
2872 "pex_l1_rst_n_pdd5",
2873 "pex_l2_clkreq_n_pcc7",
2874 "pex_l2_prsnt_n_pdd7",
2875 "pex_l2_rst_n_pcc6",
2876 "pex_wake_n_pdd3",
2877 "pwr_i2c_scl_pz6",
2878 "pwr_i2c_sda_pz7",
2879 "pwr_int_n",
2880 "spi1_miso_px7",
2881 "sys_clk_req_pz5",
2882 "uart3_cts_n_pa1",
2883 "uart3_rts_n_pc0",
2884 "uart3_rxd_pw7",
2885 "uart3_txd_pw6",
2886 "vi_d0_pt4",
2887 "vi_d1_pd5",
2888 "vi_d10_pt2",
2889 "vi_d11_pt3",
2890 "vi_d2_pl0",
2891 "vi_d3_pl1",
2892 "vi_d4_pl2",
2893 "vi_d5_pl3",
2894 "vi_d6_pl4",
2895 "vi_d7_pl5",
2896 "vi_d8_pl6",
2897 "vi_d9_pl7",
2898 "vi_hsync_pd7",
2899 "vi_pclk_pt0",
2900 "vi_vsync_pd6",
2901};
2902
2903static const char * const rtck_groups[] = {
2904 "jtag_rtck_pu7",
2905};
2906
2907static const char * const sata_groups[] = {
2908 "gmi_cs6_n_pi3",
2909};
2910
2911static const char * const sdmmc1_groups[] = {
2912 "sdmmc1_clk_pz0",
2913 "sdmmc1_cmd_pz1",
2914 "sdmmc1_dat0_py7",
2915 "sdmmc1_dat1_py6",
2916 "sdmmc1_dat2_py5",
2917 "sdmmc1_dat3_py4",
2918};
2919
2920static const char * const sdmmc2_groups[] = {
2921 "dap1_din_pn1",
2922 "dap1_dout_pn2",
2923 "dap1_fs_pn0",
2924 "dap1_sclk_pn3",
2925 "kb_row10_ps2",
2926 "kb_row11_ps3",
2927 "kb_row12_ps4",
2928 "kb_row13_ps5",
2929 "kb_row14_ps6",
2930 "kb_row15_ps7",
2931 "kb_row6_pr6",
2932 "kb_row7_pr7",
2933 "kb_row8_ps0",
2934 "kb_row9_ps1",
2935 "spdif_in_pk6",
2936 "spdif_out_pk5",
2937 "vi_d1_pd5",
2938 "vi_d2_pl0",
2939 "vi_d3_pl1",
2940 "vi_d4_pl2",
2941 "vi_d5_pl3",
2942 "vi_d6_pl4",
2943 "vi_d7_pl5",
2944 "vi_d8_pl6",
2945 "vi_d9_pl7",
2946 "vi_pclk_pt0",
2947};
2948
2949static const char * const sdmmc3_groups[] = {
2950 "sdmmc3_clk_pa6",
2951 "sdmmc3_cmd_pa7",
2952 "sdmmc3_dat0_pb7",
2953 "sdmmc3_dat1_pb6",
2954 "sdmmc3_dat2_pb5",
2955 "sdmmc3_dat3_pb4",
2956 "sdmmc3_dat4_pd1",
2957 "sdmmc3_dat5_pd0",
2958 "sdmmc3_dat6_pd3",
2959 "sdmmc3_dat7_pd4",
2960};
2961
2962static const char * const sdmmc4_groups[] = {
2963 "cam_i2c_scl_pbb1",
2964 "cam_i2c_sda_pbb2",
2965 "cam_mclk_pcc0",
2966 "pbb0",
2967 "pbb3",
2968 "pbb4",
2969 "pbb5",
2970 "pbb6",
2971 "pbb7",
2972 "pcc1",
2973 "sdmmc4_clk_pcc4",
2974 "sdmmc4_cmd_pt7",
2975 "sdmmc4_dat0_paa0",
2976 "sdmmc4_dat1_paa1",
2977 "sdmmc4_dat2_paa2",
2978 "sdmmc4_dat3_paa3",
2979 "sdmmc4_dat4_paa4",
2980 "sdmmc4_dat5_paa5",
2981 "sdmmc4_dat6_paa6",
2982 "sdmmc4_dat7_paa7",
2983 "sdmmc4_rst_n_pcc3",
2984};
2985
2986static const char * const spdif_groups[] = {
2987 "sdmmc3_dat6_pd3",
2988 "sdmmc3_dat7_pd4",
2989 "spdif_in_pk6",
2990 "spdif_out_pk5",
2991 "uart2_rxd_pc3",
2992 "uart2_txd_pc2",
2993};
2994
2995static const char * const spi1_groups[] = {
2996 "spi1_cs0_n_px6",
2997 "spi1_miso_px7",
2998 "spi1_mosi_px4",
2999 "spi1_sck_px5",
3000 "ulpi_clk_py0",
3001 "ulpi_dir_py1",
3002 "ulpi_nxt_py2",
3003 "ulpi_stp_py3",
3004};
3005
3006static const char * const spi2_groups[] = {
3007 "sdmmc3_cmd_pa7",
3008 "sdmmc3_dat4_pd1",
3009 "sdmmc3_dat5_pd0",
3010 "sdmmc3_dat6_pd3",
3011 "sdmmc3_dat7_pd4",
3012 "spi1_cs0_n_px6",
3013 "spi1_mosi_px4",
3014 "spi1_sck_px5",
3015 "spi2_cs0_n_px3",
3016 "spi2_cs1_n_pw2",
3017 "spi2_cs2_n_pw3",
3018 "spi2_miso_px1",
3019 "spi2_mosi_px0",
3020 "spi2_sck_px2",
3021 "ulpi_data4_po5",
3022 "ulpi_data5_po6",
3023 "ulpi_data6_po7",
3024 "ulpi_data7_po0",
3025};
3026
3027static const char * const spi2_alt_groups[] = {
3028 "spi1_cs0_n_px6",
3029 "spi1_miso_px7",
3030 "spi1_mosi_px4",
3031 "spi1_sck_px5",
3032 "spi2_cs1_n_pw2",
3033 "spi2_cs2_n_pw3",
3034};
3035
3036static const char * const spi3_groups[] = {
3037 "sdmmc3_clk_pa6",
3038 "sdmmc3_dat0_pb7",
3039 "sdmmc3_dat1_pb6",
3040 "sdmmc3_dat2_pb5",
3041 "sdmmc3_dat3_pb4",
3042 "sdmmc4_dat0_paa0",
3043 "sdmmc4_dat1_paa1",
3044 "sdmmc4_dat2_paa2",
3045 "sdmmc4_dat3_paa3",
3046 "spi1_miso_px7",
3047 "spi2_cs0_n_px3",
3048 "spi2_cs1_n_pw2",
3049 "spi2_cs2_n_pw3",
3050 "spi2_miso_px1",
3051 "spi2_mosi_px0",
3052 "spi2_sck_px2",
3053 "ulpi_data0_po1",
3054 "ulpi_data1_po2",
3055 "ulpi_data2_po3",
3056 "ulpi_data3_po4",
3057};
3058
3059static const char * const spi4_groups[] = {
3060 "gmi_a16_pj7",
3061 "gmi_a17_pb0",
3062 "gmi_a18_pb1",
3063 "gmi_a19_pk7",
3064 "sdmmc3_dat4_pd1",
3065 "sdmmc3_dat5_pd0",
3066 "sdmmc3_dat6_pd3",
3067 "sdmmc3_dat7_pd4",
3068 "uart2_cts_n_pj5",
3069 "uart2_rts_n_pj6",
3070 "uart2_rxd_pc3",
3071 "uart2_txd_pc2",
3072};
3073
3074static const char * const spi5_groups[] = {
3075 "lcd_cs0_n_pn4",
3076 "lcd_cs1_n_pw0",
3077 "lcd_pwr0_pb2",
3078 "lcd_pwr2_pc6",
3079 "lcd_sck_pz4",
3080 "lcd_sdin_pz2",
3081 "lcd_sdout_pn5",
3082 "lcd_wr_n_pz3",
3083};
3084
3085static const char * const spi6_groups[] = {
3086 "spi2_cs0_n_px3",
3087 "spi2_miso_px1",
3088 "spi2_mosi_px0",
3089 "spi2_sck_px2",
3090};
3091
3092static const char * const sysclk_groups[] = {
3093 "sys_clk_req_pz5",
3094};
3095
3096static const char * const test_groups[] = {
3097 "kb_col0_pq0",
3098 "kb_col1_pq1",
3099};
3100
3101static const char * const trace_groups[] = {
3102 "kb_col0_pq0",
3103 "kb_col1_pq1",
3104 "kb_col2_pq2",
3105 "kb_col3_pq3",
3106 "kb_col4_pq4",
3107 "kb_col5_pq5",
3108 "kb_col6_pq6",
3109 "kb_col7_pq7",
3110 "kb_row4_pr4",
3111 "kb_row5_pr5",
3112};
3113
3114static const char * const uarta_groups[] = {
3115 "pu0",
3116 "pu1",
3117 "pu2",
3118 "pu3",
3119 "pu4",
3120 "pu5",
3121 "pu6",
3122 "sdmmc1_clk_pz0",
3123 "sdmmc1_cmd_pz1",
3124 "sdmmc1_dat0_py7",
3125 "sdmmc1_dat1_py6",
3126 "sdmmc1_dat2_py5",
3127 "sdmmc1_dat3_py4",
3128 "sdmmc3_clk_pa6",
3129 "sdmmc3_cmd_pa7",
3130 "uart2_cts_n_pj5",
3131 "uart2_rts_n_pj6",
3132 "uart2_rxd_pc3",
3133 "uart2_txd_pc2",
3134 "ulpi_data0_po1",
3135 "ulpi_data1_po2",
3136 "ulpi_data2_po3",
3137 "ulpi_data3_po4",
3138 "ulpi_data4_po5",
3139 "ulpi_data5_po6",
3140 "ulpi_data6_po7",
3141 "ulpi_data7_po0",
3142};
3143
3144static const char * const uartb_groups[] = {
3145 "uart2_cts_n_pj5",
3146 "uart2_rts_n_pj6",
3147 "uart2_rxd_pc3",
3148 "uart2_txd_pc2",
3149};
3150
3151static const char * const uartc_groups[] = {
3152 "uart3_cts_n_pa1",
3153 "uart3_rts_n_pc0",
3154 "uart3_rxd_pw7",
3155 "uart3_txd_pw6",
3156};
3157
3158static const char * const uartd_groups[] = {
3159 "gmi_a16_pj7",
3160 "gmi_a17_pb0",
3161 "gmi_a18_pb1",
3162 "gmi_a19_pk7",
3163 "ulpi_clk_py0",
3164 "ulpi_dir_py1",
3165 "ulpi_nxt_py2",
3166 "ulpi_stp_py3",
3167};
3168
3169static const char * const uarte_groups[] = {
3170 "sdmmc1_dat0_py7",
3171 "sdmmc1_dat1_py6",
3172 "sdmmc1_dat2_py5",
3173 "sdmmc1_dat3_py4",
3174 "sdmmc4_dat0_paa0",
3175 "sdmmc4_dat1_paa1",
3176 "sdmmc4_dat2_paa2",
3177 "sdmmc4_dat3_paa3",
3178};
3179
3180static const char * const ulpi_groups[] = {
3181 "ulpi_clk_py0",
3182 "ulpi_data0_po1",
3183 "ulpi_data1_po2",
3184 "ulpi_data2_po3",
3185 "ulpi_data3_po4",
3186 "ulpi_data4_po5",
3187 "ulpi_data5_po6",
3188 "ulpi_data6_po7",
3189 "ulpi_data7_po0",
3190 "ulpi_dir_py1",
3191 "ulpi_nxt_py2",
3192 "ulpi_stp_py3",
3193};
3194
3195static const char * const vgp1_groups[] = {
3196 "cam_i2c_scl_pbb1",
3197};
3198
3199static const char * const vgp2_groups[] = {
3200 "cam_i2c_sda_pbb2",
3201};
3202
3203static const char * const vgp3_groups[] = {
3204 "pbb3",
3205 "sdmmc4_dat5_paa5",
3206};
3207
3208static const char * const vgp4_groups[] = {
3209 "pbb4",
3210 "sdmmc4_dat6_paa6",
3211};
3212
3213static const char * const vgp5_groups[] = {
3214 "pbb5",
3215 "sdmmc4_dat7_paa7",
3216};
3217
3218static const char * const vgp6_groups[] = {
3219 "pbb6",
3220 "sdmmc4_rst_n_pcc3",
3221};
3222
3223static const char * const vi_groups[] = {
3224 "cam_mclk_pcc0",
3225 "vi_d0_pt4",
3226 "vi_d1_pd5",
3227 "vi_d10_pt2",
3228 "vi_d11_pt3",
3229 "vi_d2_pl0",
3230 "vi_d3_pl1",
3231 "vi_d4_pl2",
3232 "vi_d5_pl3",
3233 "vi_d6_pl4",
3234 "vi_d7_pl5",
3235 "vi_d8_pl6",
3236 "vi_d9_pl7",
3237 "vi_hsync_pd7",
3238 "vi_mclk_pt1",
3239 "vi_pclk_pt0",
3240 "vi_vsync_pd6",
3241};
3242
3243static const char * const vi_alt1_groups[] = {
3244 "cam_mclk_pcc0",
3245 "vi_mclk_pt1",
3246};
3247
3248static const char * const vi_alt2_groups[] = {
3249 "vi_mclk_pt1",
3250};
3251
3252static const char * const vi_alt3_groups[] = {
3253 "cam_mclk_pcc0",
3254 "vi_mclk_pt1",
3255};
3256 2018
3257#define FUNCTION(fname) \ 2019#define FUNCTION(fname) \
3258 { \ 2020 { \
3259 .name = #fname, \ 2021 .name = #fname, \
3260 .groups = fname##_groups, \
3261 .ngroups = ARRAY_SIZE(fname##_groups), \
3262 } 2022 }
3263 2023
3264static const struct tegra_function tegra30_functions[] = { 2024static struct tegra_function tegra30_functions[] = {
3265 FUNCTION(blink), 2025 FUNCTION(blink),
3266 FUNCTION(cec), 2026 FUNCTION(cec),
3267 FUNCTION(clk_12m_out), 2027 FUNCTION(clk_12m_out),
@@ -3345,11 +2105,11 @@ static const struct tegra_function tegra30_functions[] = {
3345 FUNCTION(vi_alt3), 2105 FUNCTION(vi_alt3),
3346}; 2106};
3347 2107
3348#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */ 2108#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
3349#define PINGROUP_REG_A 0x3000 /* bank 1 */ 2109#define PINGROUP_REG_A 0x3000 /* bank 1 */
3350 2110
3351#define PINGROUP_REG_Y(r) ((r) - PINGROUP_REG_A) 2111#define PINGROUP_REG_Y(r) ((r) - PINGROUP_REG_A)
3352#define PINGROUP_REG_N(r) -1 2112#define PINGROUP_REG_N(r) -1
3353 2113
3354#define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior) \ 2114#define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior) \
3355 { \ 2115 { \
@@ -3357,12 +2117,12 @@ static const struct tegra_function tegra30_functions[] = {
3357 .pins = pg_name##_pins, \ 2117 .pins = pg_name##_pins, \
3358 .npins = ARRAY_SIZE(pg_name##_pins), \ 2118 .npins = ARRAY_SIZE(pg_name##_pins), \
3359 .funcs = { \ 2119 .funcs = { \
3360 TEGRA_MUX_ ## f0, \ 2120 TEGRA_MUX_##f0, \
3361 TEGRA_MUX_ ## f1, \ 2121 TEGRA_MUX_##f1, \
3362 TEGRA_MUX_ ## f2, \ 2122 TEGRA_MUX_##f2, \
3363 TEGRA_MUX_ ## f3, \ 2123 TEGRA_MUX_##f3, \
3364 }, \ 2124 }, \
3365 .func_safe = TEGRA_MUX_ ## f_safe, \ 2125 .func_safe = TEGRA_MUX_##f_safe, \
3366 .mux_reg = PINGROUP_REG_Y(r), \ 2126 .mux_reg = PINGROUP_REG_Y(r), \
3367 .mux_bank = 1, \ 2127 .mux_bank = 1, \
3368 .mux_bit = 0, \ 2128 .mux_bit = 0, \
@@ -3389,6 +2149,9 @@ static const struct tegra_function tegra30_functions[] = {
3389 .drvtype_reg = -1, \ 2149 .drvtype_reg = -1, \
3390 } 2150 }
3391 2151
2152#define DRV_PINGROUP_REG_Y(r) ((r) - DRV_PINGROUP_REG_A)
2153#define DRV_PINGROUP_REG_N(r) -1
2154
3392#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \ 2155#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \
3393 drvdn_b, drvdn_w, drvup_b, drvup_w, \ 2156 drvdn_b, drvdn_w, drvup_b, drvup_w, \
3394 slwr_b, slwr_w, slwf_b, slwf_w) \ 2157 slwr_b, slwr_w, slwf_b, slwf_w) \
@@ -3404,7 +2167,7 @@ static const struct tegra_function tegra30_functions[] = {
3404 .lock_reg = -1, \ 2167 .lock_reg = -1, \
3405 .ioreset_reg = -1, \ 2168 .ioreset_reg = -1, \
3406 .rcv_sel_reg = -1, \ 2169 .rcv_sel_reg = -1, \
3407 .drv_reg = ((r) - DRV_PINGROUP_REG_A), \ 2170 .drv_reg = DRV_PINGROUP_REG_Y(r), \
3408 .drv_bank = 0, \ 2171 .drv_bank = 0, \
3409 .hsm_bit = hsm_b, \ 2172 .hsm_bit = hsm_b, \
3410 .schmitt_bit = schmitt_b, \ 2173 .schmitt_bit = schmitt_b, \
@@ -3422,7 +2185,6 @@ static const struct tegra_function tegra30_functions[] = {
3422 2185
3423static const struct tegra_pingroup tegra30_groups[] = { 2186static const struct tegra_pingroup tegra30_groups[] = {
3424 /* pg_name, f0, f1, f2, f3, safe, r, od, ior */ 2187 /* pg_name, f0, f1, f2, f3, safe, r, od, ior */
3425 /* FIXME: Fill in correct data in safe column */
3426 PINGROUP(clk_32k_out_pa0, BLINK, RSVD2, RSVD3, RSVD4, RSVD4, 0x331c, N, N), 2188 PINGROUP(clk_32k_out_pa0, BLINK, RSVD2, RSVD3, RSVD4, RSVD4, 0x331c, N, N),
3427 PINGROUP(uart3_cts_n_pa1, UARTC, RSVD2, GMI, RSVD4, RSVD4, 0x317c, N, N), 2189 PINGROUP(uart3_cts_n_pa1, UARTC, RSVD2, GMI, RSVD4, RSVD4, 0x317c, N, N),
3428 PINGROUP(dap2_fs_pa2, I2S1, HDA, RSVD3, GMI, RSVD3, 0x3358, N, N), 2190 PINGROUP(dap2_fs_pa2, I2S1, HDA, RSVD3, GMI, RSVD3, 0x3358, N, N),
@@ -3735,6 +2497,7 @@ static struct of_device_id tegra30_pinctrl_of_match[] = {
3735 { .compatible = "nvidia,tegra30-pinmux", }, 2497 { .compatible = "nvidia,tegra30-pinmux", },
3736 { }, 2498 { },
3737}; 2499};
2500MODULE_DEVICE_TABLE(of, tegra30_pinctrl_of_match);
3738 2501
3739static struct platform_driver tegra30_pinctrl_driver = { 2502static struct platform_driver tegra30_pinctrl_driver = {
3740 .driver = { 2503 .driver = {
@@ -3745,20 +2508,8 @@ static struct platform_driver tegra30_pinctrl_driver = {
3745 .probe = tegra30_pinctrl_probe, 2508 .probe = tegra30_pinctrl_probe,
3746 .remove = tegra_pinctrl_remove, 2509 .remove = tegra_pinctrl_remove,
3747}; 2510};
3748 2511module_platform_driver(tegra30_pinctrl_driver);
3749static int __init tegra30_pinctrl_init(void)
3750{
3751 return platform_driver_register(&tegra30_pinctrl_driver);
3752}
3753arch_initcall(tegra30_pinctrl_init);
3754
3755static void __exit tegra30_pinctrl_exit(void)
3756{
3757 platform_driver_unregister(&tegra30_pinctrl_driver);
3758}
3759module_exit(tegra30_pinctrl_exit);
3760 2512
3761MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>"); 2513MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
3762MODULE_DESCRIPTION("NVIDIA Tegra30 pinctrl driver"); 2514MODULE_DESCRIPTION("NVIDIA Tegra30 pinctrl driver");
3763MODULE_LICENSE("GPL v2"); 2515MODULE_LICENSE("GPL v2");
3764MODULE_DEVICE_TABLE(of, tegra30_pinctrl_of_match);
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index c381ae63c508..48093719167a 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -2260,6 +2260,42 @@ static const unsigned int msiof0_tx_pins[] = {
2260static const unsigned int msiof0_tx_mux[] = { 2260static const unsigned int msiof0_tx_mux[] = {
2261 MSIOF0_TXD_MARK, 2261 MSIOF0_TXD_MARK,
2262}; 2262};
2263
2264static const unsigned int msiof0_clk_b_pins[] = {
2265 /* SCK */
2266 RCAR_GP_PIN(1, 23),
2267};
2268static const unsigned int msiof0_clk_b_mux[] = {
2269 MSIOF0_SCK_B_MARK,
2270};
2271static const unsigned int msiof0_ss1_b_pins[] = {
2272 /* SS1 */
2273 RCAR_GP_PIN(1, 12),
2274};
2275static const unsigned int msiof0_ss1_b_mux[] = {
2276 MSIOF0_SS1_B_MARK,
2277};
2278static const unsigned int msiof0_ss2_b_pins[] = {
2279 /* SS2 */
2280 RCAR_GP_PIN(1, 10),
2281};
2282static const unsigned int msiof0_ss2_b_mux[] = {
2283 MSIOF0_SS2_B_MARK,
2284};
2285static const unsigned int msiof0_rx_b_pins[] = {
2286 /* RXD */
2287 RCAR_GP_PIN(1, 29),
2288};
2289static const unsigned int msiof0_rx_b_mux[] = {
2290 MSIOF0_RXD_B_MARK,
2291};
2292static const unsigned int msiof0_tx_b_pins[] = {
2293 /* TXD */
2294 RCAR_GP_PIN(1, 28),
2295};
2296static const unsigned int msiof0_tx_b_mux[] = {
2297 MSIOF0_TXD_B_MARK,
2298};
2263/* - MSIOF1 ----------------------------------------------------------------- */ 2299/* - MSIOF1 ----------------------------------------------------------------- */
2264static const unsigned int msiof1_clk_pins[] = { 2300static const unsigned int msiof1_clk_pins[] = {
2265 /* SCK */ 2301 /* SCK */
@@ -2303,6 +2339,42 @@ static const unsigned int msiof1_tx_pins[] = {
2303static const unsigned int msiof1_tx_mux[] = { 2339static const unsigned int msiof1_tx_mux[] = {
2304 MSIOF1_TXD_MARK, 2340 MSIOF1_TXD_MARK,
2305}; 2341};
2342
2343static const unsigned int msiof1_clk_b_pins[] = {
2344 /* SCK */
2345 RCAR_GP_PIN(1, 16),
2346};
2347static const unsigned int msiof1_clk_b_mux[] = {
2348 MSIOF1_SCK_B_MARK,
2349};
2350static const unsigned int msiof1_ss1_b_pins[] = {
2351 /* SS1 */
2352 RCAR_GP_PIN(0, 18),
2353};
2354static const unsigned int msiof1_ss1_b_mux[] = {
2355 MSIOF1_SS1_B_MARK,
2356};
2357static const unsigned int msiof1_ss2_b_pins[] = {
2358 /* SS2 */
2359 RCAR_GP_PIN(0, 19),
2360};
2361static const unsigned int msiof1_ss2_b_mux[] = {
2362 MSIOF1_SS2_B_MARK,
2363};
2364static const unsigned int msiof1_rx_b_pins[] = {
2365 /* RXD */
2366 RCAR_GP_PIN(1, 17),
2367};
2368static const unsigned int msiof1_rx_b_mux[] = {
2369 MSIOF1_RXD_B_MARK,
2370};
2371static const unsigned int msiof1_tx_b_pins[] = {
2372 /* TXD */
2373 RCAR_GP_PIN(0, 20),
2374};
2375static const unsigned int msiof1_tx_b_mux[] = {
2376 MSIOF1_TXD_B_MARK,
2377};
2306/* - MSIOF2 ----------------------------------------------------------------- */ 2378/* - MSIOF2 ----------------------------------------------------------------- */
2307static const unsigned int msiof2_clk_pins[] = { 2379static const unsigned int msiof2_clk_pins[] = {
2308 /* SCK */ 2380 /* SCK */
@@ -2389,6 +2461,58 @@ static const unsigned int msiof3_tx_pins[] = {
2389static const unsigned int msiof3_tx_mux[] = { 2461static const unsigned int msiof3_tx_mux[] = {
2390 MSIOF3_TXD_MARK, 2462 MSIOF3_TXD_MARK,
2391}; 2463};
2464
2465static const unsigned int msiof3_clk_b_pins[] = {
2466 /* SCK */
2467 RCAR_GP_PIN(0, 0),
2468};
2469static const unsigned int msiof3_clk_b_mux[] = {
2470 MSIOF3_SCK_B_MARK,
2471};
2472static const unsigned int msiof3_sync_b_pins[] = {
2473 /* SYNC */
2474 RCAR_GP_PIN(0, 1),
2475};
2476static const unsigned int msiof3_sync_b_mux[] = {
2477 MSIOF3_SYNC_B_MARK,
2478};
2479static const unsigned int msiof3_rx_b_pins[] = {
2480 /* RXD */
2481 RCAR_GP_PIN(0, 2),
2482};
2483static const unsigned int msiof3_rx_b_mux[] = {
2484 MSIOF3_RXD_B_MARK,
2485};
2486static const unsigned int msiof3_tx_b_pins[] = {
2487 /* TXD */
2488 RCAR_GP_PIN(0, 3),
2489};
2490static const unsigned int msiof3_tx_b_mux[] = {
2491 MSIOF3_TXD_B_MARK,
2492};
2493/* - QSPI ------------------------------------------------------------------- */
2494static const unsigned int qspi_ctrl_pins[] = {
2495 /* SPCLK, SSL */
2496 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
2497};
2498static const unsigned int qspi_ctrl_mux[] = {
2499 SPCLK_MARK, SSL_MARK,
2500};
2501static const unsigned int qspi_data2_pins[] = {
2502 /* MOSI_IO0, MISO_IO1 */
2503 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
2504};
2505static const unsigned int qspi_data2_mux[] = {
2506 MOSI_IO0_MARK, MISO_IO1_MARK,
2507};
2508static const unsigned int qspi_data4_pins[] = {
2509 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2510 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2511 RCAR_GP_PIN(1, 8),
2512};
2513static const unsigned int qspi_data4_mux[] = {
2514 MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
2515};
2392/* - SCIF0 ------------------------------------------------------------------ */ 2516/* - SCIF0 ------------------------------------------------------------------ */
2393static const unsigned int scif0_data_pins[] = { 2517static const unsigned int scif0_data_pins[] = {
2394 /* RX, TX */ 2518 /* RX, TX */
@@ -3231,6 +3355,13 @@ static const unsigned int usb0_pins[] = {
3231static const unsigned int usb0_mux[] = { 3355static const unsigned int usb0_mux[] = {
3232 USB0_PWEN_MARK, USB0_OVC_VBUS_MARK, 3356 USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
3233}; 3357};
3358static const unsigned int usb0_ovc_vbus_pins[] = {
3359 /* OVC/VBUS */
3360 RCAR_GP_PIN(5, 19),
3361};
3362static const unsigned int usb0_ovc_vbus_mux[] = {
3363 USB0_OVC_VBUS_MARK,
3364};
3234/* - USB1 ------------------------------------------------------------------- */ 3365/* - USB1 ------------------------------------------------------------------- */
3235static const unsigned int usb1_pins[] = { 3366static const unsigned int usb1_pins[] = {
3236 /* PWEN, OVC */ 3367 /* PWEN, OVC */
@@ -3653,12 +3784,22 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
3653 SH_PFC_PIN_GROUP(msiof0_ss2), 3784 SH_PFC_PIN_GROUP(msiof0_ss2),
3654 SH_PFC_PIN_GROUP(msiof0_rx), 3785 SH_PFC_PIN_GROUP(msiof0_rx),
3655 SH_PFC_PIN_GROUP(msiof0_tx), 3786 SH_PFC_PIN_GROUP(msiof0_tx),
3787 SH_PFC_PIN_GROUP(msiof0_clk_b),
3788 SH_PFC_PIN_GROUP(msiof0_ss1_b),
3789 SH_PFC_PIN_GROUP(msiof0_ss2_b),
3790 SH_PFC_PIN_GROUP(msiof0_rx_b),
3791 SH_PFC_PIN_GROUP(msiof0_tx_b),
3656 SH_PFC_PIN_GROUP(msiof1_clk), 3792 SH_PFC_PIN_GROUP(msiof1_clk),
3657 SH_PFC_PIN_GROUP(msiof1_sync), 3793 SH_PFC_PIN_GROUP(msiof1_sync),
3658 SH_PFC_PIN_GROUP(msiof1_ss1), 3794 SH_PFC_PIN_GROUP(msiof1_ss1),
3659 SH_PFC_PIN_GROUP(msiof1_ss2), 3795 SH_PFC_PIN_GROUP(msiof1_ss2),
3660 SH_PFC_PIN_GROUP(msiof1_rx), 3796 SH_PFC_PIN_GROUP(msiof1_rx),
3661 SH_PFC_PIN_GROUP(msiof1_tx), 3797 SH_PFC_PIN_GROUP(msiof1_tx),
3798 SH_PFC_PIN_GROUP(msiof1_clk_b),
3799 SH_PFC_PIN_GROUP(msiof1_ss1_b),
3800 SH_PFC_PIN_GROUP(msiof1_ss2_b),
3801 SH_PFC_PIN_GROUP(msiof1_rx_b),
3802 SH_PFC_PIN_GROUP(msiof1_tx_b),
3662 SH_PFC_PIN_GROUP(msiof2_clk), 3803 SH_PFC_PIN_GROUP(msiof2_clk),
3663 SH_PFC_PIN_GROUP(msiof2_sync), 3804 SH_PFC_PIN_GROUP(msiof2_sync),
3664 SH_PFC_PIN_GROUP(msiof2_ss1), 3805 SH_PFC_PIN_GROUP(msiof2_ss1),
@@ -3671,6 +3812,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
3671 SH_PFC_PIN_GROUP(msiof3_ss2), 3812 SH_PFC_PIN_GROUP(msiof3_ss2),
3672 SH_PFC_PIN_GROUP(msiof3_rx), 3813 SH_PFC_PIN_GROUP(msiof3_rx),
3673 SH_PFC_PIN_GROUP(msiof3_tx), 3814 SH_PFC_PIN_GROUP(msiof3_tx),
3815 SH_PFC_PIN_GROUP(msiof3_clk_b),
3816 SH_PFC_PIN_GROUP(msiof3_sync_b),
3817 SH_PFC_PIN_GROUP(msiof3_rx_b),
3818 SH_PFC_PIN_GROUP(msiof3_tx_b),
3819 SH_PFC_PIN_GROUP(qspi_ctrl),
3820 SH_PFC_PIN_GROUP(qspi_data2),
3821 SH_PFC_PIN_GROUP(qspi_data4),
3674 SH_PFC_PIN_GROUP(scif0_data), 3822 SH_PFC_PIN_GROUP(scif0_data),
3675 SH_PFC_PIN_GROUP(scif0_clk), 3823 SH_PFC_PIN_GROUP(scif0_clk),
3676 SH_PFC_PIN_GROUP(scif0_ctrl), 3824 SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -3789,6 +3937,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
3789 SH_PFC_PIN_GROUP(tpu0_to2), 3937 SH_PFC_PIN_GROUP(tpu0_to2),
3790 SH_PFC_PIN_GROUP(tpu0_to3), 3938 SH_PFC_PIN_GROUP(tpu0_to3),
3791 SH_PFC_PIN_GROUP(usb0), 3939 SH_PFC_PIN_GROUP(usb0),
3940 SH_PFC_PIN_GROUP(usb0_ovc_vbus),
3792 SH_PFC_PIN_GROUP(usb1), 3941 SH_PFC_PIN_GROUP(usb1),
3793 SH_PFC_PIN_GROUP(usb2), 3942 SH_PFC_PIN_GROUP(usb2),
3794 VIN_DATA_PIN_GROUP(vin0_data, 24), 3943 VIN_DATA_PIN_GROUP(vin0_data, 24),
@@ -3941,6 +4090,11 @@ static const char * const msiof0_groups[] = {
3941 "msiof0_ss2", 4090 "msiof0_ss2",
3942 "msiof0_rx", 4091 "msiof0_rx",
3943 "msiof0_tx", 4092 "msiof0_tx",
4093 "msiof0_clk_b",
4094 "msiof0_ss1_b",
4095 "msiof0_ss2_b",
4096 "msiof0_rx_b",
4097 "msiof0_tx_b",
3944}; 4098};
3945 4099
3946static const char * const msiof1_groups[] = { 4100static const char * const msiof1_groups[] = {
@@ -3950,6 +4104,11 @@ static const char * const msiof1_groups[] = {
3950 "msiof1_ss2", 4104 "msiof1_ss2",
3951 "msiof1_rx", 4105 "msiof1_rx",
3952 "msiof1_tx", 4106 "msiof1_tx",
4107 "msiof1_clk_b",
4108 "msiof1_ss1_b",
4109 "msiof1_ss2_b",
4110 "msiof1_rx_b",
4111 "msiof1_tx_b",
3953}; 4112};
3954 4113
3955static const char * const msiof2_groups[] = { 4114static const char * const msiof2_groups[] = {
@@ -3968,6 +4127,16 @@ static const char * const msiof3_groups[] = {
3968 "msiof3_ss2", 4127 "msiof3_ss2",
3969 "msiof3_rx", 4128 "msiof3_rx",
3970 "msiof3_tx", 4129 "msiof3_tx",
4130 "msiof3_clk_b",
4131 "msiof3_sync_b",
4132 "msiof3_rx_b",
4133 "msiof3_tx_b",
4134};
4135
4136static const char * const qspi_groups[] = {
4137 "qspi_ctrl",
4138 "qspi_data2",
4139 "qspi_data4",
3971}; 4140};
3972 4141
3973static const char * const scif0_groups[] = { 4142static const char * const scif0_groups[] = {
@@ -4134,6 +4303,7 @@ static const char * const tpu0_groups[] = {
4134 4303
4135static const char * const usb0_groups[] = { 4304static const char * const usb0_groups[] = {
4136 "usb0", 4305 "usb0",
4306 "usb0_ovc_vbus",
4137}; 4307};
4138 4308
4139static const char * const usb1_groups[] = { 4309static const char * const usb1_groups[] = {
@@ -4213,6 +4383,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
4213 SH_PFC_FUNCTION(msiof1), 4383 SH_PFC_FUNCTION(msiof1),
4214 SH_PFC_FUNCTION(msiof2), 4384 SH_PFC_FUNCTION(msiof2),
4215 SH_PFC_FUNCTION(msiof3), 4385 SH_PFC_FUNCTION(msiof3),
4386 SH_PFC_FUNCTION(qspi),
4216 SH_PFC_FUNCTION(scif0), 4387 SH_PFC_FUNCTION(scif0),
4217 SH_PFC_FUNCTION(scif1), 4388 SH_PFC_FUNCTION(scif1),
4218 SH_PFC_FUNCTION(scif2), 4389 SH_PFC_FUNCTION(scif2),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
index 567d6918d50b..5186d70c49d4 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
@@ -1945,6 +1945,50 @@ static const unsigned int i2c4_c_pins[] = {
1945static const unsigned int i2c4_c_mux[] = { 1945static const unsigned int i2c4_c_mux[] = {
1946 SCL4_C_MARK, SDA4_C_MARK, 1946 SCL4_C_MARK, SDA4_C_MARK,
1947}; 1947};
1948/* - I2C7 ------------------------------------------------------------------- */
1949static const unsigned int i2c7_pins[] = {
1950 /* SCL, SDA */
1951 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
1952};
1953static const unsigned int i2c7_mux[] = {
1954 SCL7_MARK, SDA7_MARK,
1955};
1956static const unsigned int i2c7_b_pins[] = {
1957 /* SCL, SDA */
1958 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1959};
1960static const unsigned int i2c7_b_mux[] = {
1961 SCL7_B_MARK, SDA7_B_MARK,
1962};
1963static const unsigned int i2c7_c_pins[] = {
1964 /* SCL, SDA */
1965 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
1966};
1967static const unsigned int i2c7_c_mux[] = {
1968 SCL7_C_MARK, SDA7_C_MARK,
1969};
1970/* - I2C8 ------------------------------------------------------------------- */
1971static const unsigned int i2c8_pins[] = {
1972 /* SCL, SDA */
1973 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
1974};
1975static const unsigned int i2c8_mux[] = {
1976 SCL8_MARK, SDA8_MARK,
1977};
1978static const unsigned int i2c8_b_pins[] = {
1979 /* SCL, SDA */
1980 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1981};
1982static const unsigned int i2c8_b_mux[] = {
1983 SCL8_B_MARK, SDA8_B_MARK,
1984};
1985static const unsigned int i2c8_c_pins[] = {
1986 /* SCL, SDA */
1987 RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
1988};
1989static const unsigned int i2c8_c_mux[] = {
1990 SCL8_C_MARK, SDA8_C_MARK,
1991};
1948/* - INTC ------------------------------------------------------------------- */ 1992/* - INTC ------------------------------------------------------------------- */
1949static const unsigned int intc_irq0_pins[] = { 1993static const unsigned int intc_irq0_pins[] = {
1950 /* IRQ */ 1994 /* IRQ */
@@ -2051,6 +2095,92 @@ static const unsigned int msiof0_tx_pins[] = {
2051static const unsigned int msiof0_tx_mux[] = { 2095static const unsigned int msiof0_tx_mux[] = {
2052 MSIOF0_TXD_MARK, 2096 MSIOF0_TXD_MARK,
2053}; 2097};
2098
2099static const unsigned int msiof0_clk_b_pins[] = {
2100 /* SCK */
2101 RCAR_GP_PIN(0, 16),
2102};
2103static const unsigned int msiof0_clk_b_mux[] = {
2104 MSIOF0_SCK_B_MARK,
2105};
2106static const unsigned int msiof0_sync_b_pins[] = {
2107 /* SYNC */
2108 RCAR_GP_PIN(0, 17),
2109};
2110static const unsigned int msiof0_sync_b_mux[] = {
2111 MSIOF0_SYNC_B_MARK,
2112};
2113static const unsigned int msiof0_ss1_b_pins[] = {
2114 /* SS1 */
2115 RCAR_GP_PIN(0, 18),
2116};
2117static const unsigned int msiof0_ss1_b_mux[] = {
2118 MSIOF0_SS1_B_MARK,
2119};
2120static const unsigned int msiof0_ss2_b_pins[] = {
2121 /* SS2 */
2122 RCAR_GP_PIN(0, 19),
2123};
2124static const unsigned int msiof0_ss2_b_mux[] = {
2125 MSIOF0_SS2_B_MARK,
2126};
2127static const unsigned int msiof0_rx_b_pins[] = {
2128 /* RXD */
2129 RCAR_GP_PIN(0, 21),
2130};
2131static const unsigned int msiof0_rx_b_mux[] = {
2132 MSIOF0_RXD_B_MARK,
2133};
2134static const unsigned int msiof0_tx_b_pins[] = {
2135 /* TXD */
2136 RCAR_GP_PIN(0, 20),
2137};
2138static const unsigned int msiof0_tx_b_mux[] = {
2139 MSIOF0_TXD_B_MARK,
2140};
2141
2142static const unsigned int msiof0_clk_c_pins[] = {
2143 /* SCK */
2144 RCAR_GP_PIN(5, 26),
2145};
2146static const unsigned int msiof0_clk_c_mux[] = {
2147 MSIOF0_SCK_C_MARK,
2148};
2149static const unsigned int msiof0_sync_c_pins[] = {
2150 /* SYNC */
2151 RCAR_GP_PIN(5, 25),
2152};
2153static const unsigned int msiof0_sync_c_mux[] = {
2154 MSIOF0_SYNC_C_MARK,
2155};
2156static const unsigned int msiof0_ss1_c_pins[] = {
2157 /* SS1 */
2158 RCAR_GP_PIN(5, 27),
2159};
2160static const unsigned int msiof0_ss1_c_mux[] = {
2161 MSIOF0_SS1_C_MARK,
2162};
2163static const unsigned int msiof0_ss2_c_pins[] = {
2164 /* SS2 */
2165 RCAR_GP_PIN(5, 28),
2166};
2167static const unsigned int msiof0_ss2_c_mux[] = {
2168 MSIOF0_SS2_C_MARK,
2169};
2170static const unsigned int msiof0_rx_c_pins[] = {
2171 /* RXD */
2172 RCAR_GP_PIN(5, 29),
2173};
2174static const unsigned int msiof0_rx_c_mux[] = {
2175 MSIOF0_RXD_C_MARK,
2176};
2177static const unsigned int msiof0_tx_c_pins[] = {
2178 /* TXD */
2179 RCAR_GP_PIN(5, 30),
2180};
2181static const unsigned int msiof0_tx_c_mux[] = {
2182 MSIOF0_TXD_C_MARK,
2183};
2054/* - MSIOF1 ----------------------------------------------------------------- */ 2184/* - MSIOF1 ----------------------------------------------------------------- */
2055static const unsigned int msiof1_clk_pins[] = { 2185static const unsigned int msiof1_clk_pins[] = {
2056 /* SCK */ 2186 /* SCK */
@@ -2094,6 +2224,143 @@ static const unsigned int msiof1_tx_pins[] = {
2094static const unsigned int msiof1_tx_mux[] = { 2224static const unsigned int msiof1_tx_mux[] = {
2095 MSIOF1_TXD_MARK, 2225 MSIOF1_TXD_MARK,
2096}; 2226};
2227
2228static const unsigned int msiof1_clk_b_pins[] = {
2229 /* SCK */
2230 RCAR_GP_PIN(2, 29),
2231};
2232static const unsigned int msiof1_clk_b_mux[] = {
2233 MSIOF1_SCK_B_MARK,
2234};
2235static const unsigned int msiof1_sync_b_pins[] = {
2236 /* SYNC */
2237 RCAR_GP_PIN(2, 30),
2238};
2239static const unsigned int msiof1_sync_b_mux[] = {
2240 MSIOF1_SYNC_B_MARK,
2241};
2242static const unsigned int msiof1_ss1_b_pins[] = {
2243 /* SS1 */
2244 RCAR_GP_PIN(2, 31),
2245};
2246static const unsigned int msiof1_ss1_b_mux[] = {
2247 MSIOF1_SS1_B_MARK,
2248};
2249static const unsigned int msiof1_ss2_b_pins[] = {
2250 /* SS2 */
2251 RCAR_GP_PIN(7, 16),
2252};
2253static const unsigned int msiof1_ss2_b_mux[] = {
2254 MSIOF1_SS2_B_MARK,
2255};
2256static const unsigned int msiof1_rx_b_pins[] = {
2257 /* RXD */
2258 RCAR_GP_PIN(7, 18),
2259};
2260static const unsigned int msiof1_rx_b_mux[] = {
2261 MSIOF1_RXD_B_MARK,
2262};
2263static const unsigned int msiof1_tx_b_pins[] = {
2264 /* TXD */
2265 RCAR_GP_PIN(7, 17),
2266};
2267static const unsigned int msiof1_tx_b_mux[] = {
2268 MSIOF1_TXD_B_MARK,
2269};
2270
2271static const unsigned int msiof1_clk_c_pins[] = {
2272 /* SCK */
2273 RCAR_GP_PIN(2, 15),
2274};
2275static const unsigned int msiof1_clk_c_mux[] = {
2276 MSIOF1_SCK_C_MARK,
2277};
2278static const unsigned int msiof1_sync_c_pins[] = {
2279 /* SYNC */
2280 RCAR_GP_PIN(2, 16),
2281};
2282static const unsigned int msiof1_sync_c_mux[] = {
2283 MSIOF1_SYNC_C_MARK,
2284};
2285static const unsigned int msiof1_rx_c_pins[] = {
2286 /* RXD */
2287 RCAR_GP_PIN(2, 18),
2288};
2289static const unsigned int msiof1_rx_c_mux[] = {
2290 MSIOF1_RXD_C_MARK,
2291};
2292static const unsigned int msiof1_tx_c_pins[] = {
2293 /* TXD */
2294 RCAR_GP_PIN(2, 17),
2295};
2296static const unsigned int msiof1_tx_c_mux[] = {
2297 MSIOF1_TXD_C_MARK,
2298};
2299
2300static const unsigned int msiof1_clk_d_pins[] = {
2301 /* SCK */
2302 RCAR_GP_PIN(0, 28),
2303};
2304static const unsigned int msiof1_clk_d_mux[] = {
2305 MSIOF1_SCK_D_MARK,
2306};
2307static const unsigned int msiof1_sync_d_pins[] = {
2308 /* SYNC */
2309 RCAR_GP_PIN(0, 30),
2310};
2311static const unsigned int msiof1_sync_d_mux[] = {
2312 MSIOF1_SYNC_D_MARK,
2313};
2314static const unsigned int msiof1_ss1_d_pins[] = {
2315 /* SS1 */
2316 RCAR_GP_PIN(0, 29),
2317};
2318static const unsigned int msiof1_ss1_d_mux[] = {
2319 MSIOF1_SS1_D_MARK,
2320};
2321static const unsigned int msiof1_rx_d_pins[] = {
2322 /* RXD */
2323 RCAR_GP_PIN(0, 27),
2324};
2325static const unsigned int msiof1_rx_d_mux[] = {
2326 MSIOF1_RXD_D_MARK,
2327};
2328static const unsigned int msiof1_tx_d_pins[] = {
2329 /* TXD */
2330 RCAR_GP_PIN(0, 26),
2331};
2332static const unsigned int msiof1_tx_d_mux[] = {
2333 MSIOF1_TXD_D_MARK,
2334};
2335
2336static const unsigned int msiof1_clk_e_pins[] = {
2337 /* SCK */
2338 RCAR_GP_PIN(5, 18),
2339};
2340static const unsigned int msiof1_clk_e_mux[] = {
2341 MSIOF1_SCK_E_MARK,
2342};
2343static const unsigned int msiof1_sync_e_pins[] = {
2344 /* SYNC */
2345 RCAR_GP_PIN(5, 19),
2346};
2347static const unsigned int msiof1_sync_e_mux[] = {
2348 MSIOF1_SYNC_E_MARK,
2349};
2350static const unsigned int msiof1_rx_e_pins[] = {
2351 /* RXD */
2352 RCAR_GP_PIN(5, 17),
2353};
2354static const unsigned int msiof1_rx_e_mux[] = {
2355 MSIOF1_RXD_E_MARK,
2356};
2357static const unsigned int msiof1_tx_e_pins[] = {
2358 /* TXD */
2359 RCAR_GP_PIN(5, 20),
2360};
2361static const unsigned int msiof1_tx_e_mux[] = {
2362 MSIOF1_TXD_E_MARK,
2363};
2097/* - MSIOF2 ----------------------------------------------------------------- */ 2364/* - MSIOF2 ----------------------------------------------------------------- */
2098static const unsigned int msiof2_clk_pins[] = { 2365static const unsigned int msiof2_clk_pins[] = {
2099 /* SCK */ 2366 /* SCK */
@@ -2137,6 +2404,197 @@ static const unsigned int msiof2_tx_pins[] = {
2137static const unsigned int msiof2_tx_mux[] = { 2404static const unsigned int msiof2_tx_mux[] = {
2138 MSIOF2_TXD_MARK, 2405 MSIOF2_TXD_MARK,
2139}; 2406};
2407
2408static const unsigned int msiof2_clk_b_pins[] = {
2409 /* SCK */
2410 RCAR_GP_PIN(3, 0),
2411};
2412static const unsigned int msiof2_clk_b_mux[] = {
2413 MSIOF2_SCK_B_MARK,
2414};
2415static const unsigned int msiof2_sync_b_pins[] = {
2416 /* SYNC */
2417 RCAR_GP_PIN(3, 1),
2418};
2419static const unsigned int msiof2_sync_b_mux[] = {
2420 MSIOF2_SYNC_B_MARK,
2421};
2422static const unsigned int msiof2_ss1_b_pins[] = {
2423 /* SS1 */
2424 RCAR_GP_PIN(3, 8),
2425};
2426static const unsigned int msiof2_ss1_b_mux[] = {
2427 MSIOF2_SS1_B_MARK,
2428};
2429static const unsigned int msiof2_ss2_b_pins[] = {
2430 /* SS2 */
2431 RCAR_GP_PIN(3, 9),
2432};
2433static const unsigned int msiof2_ss2_b_mux[] = {
2434 MSIOF2_SS2_B_MARK,
2435};
2436static const unsigned int msiof2_rx_b_pins[] = {
2437 /* RXD */
2438 RCAR_GP_PIN(3, 17),
2439};
2440static const unsigned int msiof2_rx_b_mux[] = {
2441 MSIOF2_RXD_B_MARK,
2442};
2443static const unsigned int msiof2_tx_b_pins[] = {
2444 /* TXD */
2445 RCAR_GP_PIN(3, 16),
2446};
2447static const unsigned int msiof2_tx_b_mux[] = {
2448 MSIOF2_TXD_B_MARK,
2449};
2450
2451static const unsigned int msiof2_clk_c_pins[] = {
2452 /* SCK */
2453 RCAR_GP_PIN(2, 2),
2454};
2455static const unsigned int msiof2_clk_c_mux[] = {
2456 MSIOF2_SCK_C_MARK,
2457};
2458static const unsigned int msiof2_sync_c_pins[] = {
2459 /* SYNC */
2460 RCAR_GP_PIN(2, 3),
2461};
2462static const unsigned int msiof2_sync_c_mux[] = {
2463 MSIOF2_SYNC_C_MARK,
2464};
2465static const unsigned int msiof2_rx_c_pins[] = {
2466 /* RXD */
2467 RCAR_GP_PIN(2, 5),
2468};
2469static const unsigned int msiof2_rx_c_mux[] = {
2470 MSIOF2_RXD_C_MARK,
2471};
2472static const unsigned int msiof2_tx_c_pins[] = {
2473 /* TXD */
2474 RCAR_GP_PIN(2, 4),
2475};
2476static const unsigned int msiof2_tx_c_mux[] = {
2477 MSIOF2_TXD_C_MARK,
2478};
2479
2480static const unsigned int msiof2_clk_d_pins[] = {
2481 /* SCK */
2482 RCAR_GP_PIN(2, 14),
2483};
2484static const unsigned int msiof2_clk_d_mux[] = {
2485 MSIOF2_SCK_D_MARK,
2486};
2487static const unsigned int msiof2_sync_d_pins[] = {
2488 /* SYNC */
2489 RCAR_GP_PIN(2, 15),
2490};
2491static const unsigned int msiof2_sync_d_mux[] = {
2492 MSIOF2_SYNC_D_MARK,
2493};
2494static const unsigned int msiof2_ss1_d_pins[] = {
2495 /* SS1 */
2496 RCAR_GP_PIN(2, 17),
2497};
2498static const unsigned int msiof2_ss1_d_mux[] = {
2499 MSIOF2_SS1_D_MARK,
2500};
2501static const unsigned int msiof2_ss2_d_pins[] = {
2502 /* SS2 */
2503 RCAR_GP_PIN(2, 19),
2504};
2505static const unsigned int msiof2_ss2_d_mux[] = {
2506 MSIOF2_SS2_D_MARK,
2507};
2508static const unsigned int msiof2_rx_d_pins[] = {
2509 /* RXD */
2510 RCAR_GP_PIN(2, 18),
2511};
2512static const unsigned int msiof2_rx_d_mux[] = {
2513 MSIOF2_RXD_D_MARK,
2514};
2515static const unsigned int msiof2_tx_d_pins[] = {
2516 /* TXD */
2517 RCAR_GP_PIN(2, 16),
2518};
2519static const unsigned int msiof2_tx_d_mux[] = {
2520 MSIOF2_TXD_D_MARK,
2521};
2522
2523static const unsigned int msiof2_clk_e_pins[] = {
2524 /* SCK */
2525 RCAR_GP_PIN(7, 15),
2526};
2527static const unsigned int msiof2_clk_e_mux[] = {
2528 MSIOF2_SCK_E_MARK,
2529};
2530static const unsigned int msiof2_sync_e_pins[] = {
2531 /* SYNC */
2532 RCAR_GP_PIN(7, 16),
2533};
2534static const unsigned int msiof2_sync_e_mux[] = {
2535 MSIOF2_SYNC_E_MARK,
2536};
2537static const unsigned int msiof2_rx_e_pins[] = {
2538 /* RXD */
2539 RCAR_GP_PIN(7, 14),
2540};
2541static const unsigned int msiof2_rx_e_mux[] = {
2542 MSIOF2_RXD_E_MARK,
2543};
2544static const unsigned int msiof2_tx_e_pins[] = {
2545 /* TXD */
2546 RCAR_GP_PIN(7, 13),
2547};
2548static const unsigned int msiof2_tx_e_mux[] = {
2549 MSIOF2_TXD_E_MARK,
2550};
2551/* - QSPI ------------------------------------------------------------------- */
2552static const unsigned int qspi_ctrl_pins[] = {
2553 /* SPCLK, SSL */
2554 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
2555};
2556static const unsigned int qspi_ctrl_mux[] = {
2557 SPCLK_MARK, SSL_MARK,
2558};
2559static const unsigned int qspi_data2_pins[] = {
2560 /* MOSI_IO0, MISO_IO1 */
2561 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
2562};
2563static const unsigned int qspi_data2_mux[] = {
2564 MOSI_IO0_MARK, MISO_IO1_MARK,
2565};
2566static const unsigned int qspi_data4_pins[] = {
2567 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2568 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2569 RCAR_GP_PIN(1, 8),
2570};
2571static const unsigned int qspi_data4_mux[] = {
2572 MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
2573};
2574
2575static const unsigned int qspi_ctrl_b_pins[] = {
2576 /* SPCLK, SSL */
2577 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5),
2578};
2579static const unsigned int qspi_ctrl_b_mux[] = {
2580 SPCLK_B_MARK, SSL_B_MARK,
2581};
2582static const unsigned int qspi_data2_b_pins[] = {
2583 /* MOSI_IO0, MISO_IO1 */
2584 RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2),
2585};
2586static const unsigned int qspi_data2_b_mux[] = {
2587 MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
2588};
2589static const unsigned int qspi_data4_b_pins[] = {
2590 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2591 RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
2592 RCAR_GP_PIN(6, 4),
2593};
2594static const unsigned int qspi_data4_b_mux[] = {
2595 SPCLK_B_MARK, MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
2596 IO2_B_MARK, IO3_B_MARK, SSL_B_MARK,
2597};
2140/* - SCIF0 ------------------------------------------------------------------ */ 2598/* - SCIF0 ------------------------------------------------------------------ */
2141static const unsigned int scif0_data_pins[] = { 2599static const unsigned int scif0_data_pins[] = {
2142 /* RX, TX */ 2600 /* RX, TX */
@@ -3125,6 +3583,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
3125 SH_PFC_PIN_GROUP(i2c4), 3583 SH_PFC_PIN_GROUP(i2c4),
3126 SH_PFC_PIN_GROUP(i2c4_b), 3584 SH_PFC_PIN_GROUP(i2c4_b),
3127 SH_PFC_PIN_GROUP(i2c4_c), 3585 SH_PFC_PIN_GROUP(i2c4_c),
3586 SH_PFC_PIN_GROUP(i2c7),
3587 SH_PFC_PIN_GROUP(i2c7_b),
3588 SH_PFC_PIN_GROUP(i2c7_c),
3589 SH_PFC_PIN_GROUP(i2c8),
3590 SH_PFC_PIN_GROUP(i2c8_b),
3591 SH_PFC_PIN_GROUP(i2c8_c),
3128 SH_PFC_PIN_GROUP(intc_irq0), 3592 SH_PFC_PIN_GROUP(intc_irq0),
3129 SH_PFC_PIN_GROUP(intc_irq1), 3593 SH_PFC_PIN_GROUP(intc_irq1),
3130 SH_PFC_PIN_GROUP(intc_irq2), 3594 SH_PFC_PIN_GROUP(intc_irq2),
@@ -3139,18 +3603,75 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
3139 SH_PFC_PIN_GROUP(msiof0_ss2), 3603 SH_PFC_PIN_GROUP(msiof0_ss2),
3140 SH_PFC_PIN_GROUP(msiof0_rx), 3604 SH_PFC_PIN_GROUP(msiof0_rx),
3141 SH_PFC_PIN_GROUP(msiof0_tx), 3605 SH_PFC_PIN_GROUP(msiof0_tx),
3606 SH_PFC_PIN_GROUP(msiof0_clk_b),
3607 SH_PFC_PIN_GROUP(msiof0_sync_b),
3608 SH_PFC_PIN_GROUP(msiof0_ss1_b),
3609 SH_PFC_PIN_GROUP(msiof0_ss2_b),
3610 SH_PFC_PIN_GROUP(msiof0_rx_b),
3611 SH_PFC_PIN_GROUP(msiof0_tx_b),
3612 SH_PFC_PIN_GROUP(msiof0_clk_c),
3613 SH_PFC_PIN_GROUP(msiof0_sync_c),
3614 SH_PFC_PIN_GROUP(msiof0_ss1_c),
3615 SH_PFC_PIN_GROUP(msiof0_ss2_c),
3616 SH_PFC_PIN_GROUP(msiof0_rx_c),
3617 SH_PFC_PIN_GROUP(msiof0_tx_c),
3142 SH_PFC_PIN_GROUP(msiof1_clk), 3618 SH_PFC_PIN_GROUP(msiof1_clk),
3143 SH_PFC_PIN_GROUP(msiof1_sync), 3619 SH_PFC_PIN_GROUP(msiof1_sync),
3144 SH_PFC_PIN_GROUP(msiof1_ss1), 3620 SH_PFC_PIN_GROUP(msiof1_ss1),
3145 SH_PFC_PIN_GROUP(msiof1_ss2), 3621 SH_PFC_PIN_GROUP(msiof1_ss2),
3146 SH_PFC_PIN_GROUP(msiof1_rx), 3622 SH_PFC_PIN_GROUP(msiof1_rx),
3147 SH_PFC_PIN_GROUP(msiof1_tx), 3623 SH_PFC_PIN_GROUP(msiof1_tx),
3624 SH_PFC_PIN_GROUP(msiof1_clk_b),
3625 SH_PFC_PIN_GROUP(msiof1_sync_b),
3626 SH_PFC_PIN_GROUP(msiof1_ss1_b),
3627 SH_PFC_PIN_GROUP(msiof1_ss2_b),
3628 SH_PFC_PIN_GROUP(msiof1_rx_b),
3629 SH_PFC_PIN_GROUP(msiof1_tx_b),
3630 SH_PFC_PIN_GROUP(msiof1_clk_c),
3631 SH_PFC_PIN_GROUP(msiof1_sync_c),
3632 SH_PFC_PIN_GROUP(msiof1_rx_c),
3633 SH_PFC_PIN_GROUP(msiof1_tx_c),
3634 SH_PFC_PIN_GROUP(msiof1_clk_d),
3635 SH_PFC_PIN_GROUP(msiof1_sync_d),
3636 SH_PFC_PIN_GROUP(msiof1_ss1_d),
3637 SH_PFC_PIN_GROUP(msiof1_rx_d),
3638 SH_PFC_PIN_GROUP(msiof1_tx_d),
3639 SH_PFC_PIN_GROUP(msiof1_clk_e),
3640 SH_PFC_PIN_GROUP(msiof1_sync_e),
3641 SH_PFC_PIN_GROUP(msiof1_rx_e),
3642 SH_PFC_PIN_GROUP(msiof1_tx_e),
3148 SH_PFC_PIN_GROUP(msiof2_clk), 3643 SH_PFC_PIN_GROUP(msiof2_clk),
3149 SH_PFC_PIN_GROUP(msiof2_sync), 3644 SH_PFC_PIN_GROUP(msiof2_sync),
3150 SH_PFC_PIN_GROUP(msiof2_ss1), 3645 SH_PFC_PIN_GROUP(msiof2_ss1),
3151 SH_PFC_PIN_GROUP(msiof2_ss2), 3646 SH_PFC_PIN_GROUP(msiof2_ss2),
3152 SH_PFC_PIN_GROUP(msiof2_rx), 3647 SH_PFC_PIN_GROUP(msiof2_rx),
3153 SH_PFC_PIN_GROUP(msiof2_tx), 3648 SH_PFC_PIN_GROUP(msiof2_tx),
3649 SH_PFC_PIN_GROUP(msiof2_clk_b),
3650 SH_PFC_PIN_GROUP(msiof2_sync_b),
3651 SH_PFC_PIN_GROUP(msiof2_ss1_b),
3652 SH_PFC_PIN_GROUP(msiof2_ss2_b),
3653 SH_PFC_PIN_GROUP(msiof2_rx_b),
3654 SH_PFC_PIN_GROUP(msiof2_tx_b),
3655 SH_PFC_PIN_GROUP(msiof2_clk_c),
3656 SH_PFC_PIN_GROUP(msiof2_sync_c),
3657 SH_PFC_PIN_GROUP(msiof2_rx_c),
3658 SH_PFC_PIN_GROUP(msiof2_tx_c),
3659 SH_PFC_PIN_GROUP(msiof2_clk_d),
3660 SH_PFC_PIN_GROUP(msiof2_sync_d),
3661 SH_PFC_PIN_GROUP(msiof2_ss1_d),
3662 SH_PFC_PIN_GROUP(msiof2_ss2_d),
3663 SH_PFC_PIN_GROUP(msiof2_rx_d),
3664 SH_PFC_PIN_GROUP(msiof2_tx_d),
3665 SH_PFC_PIN_GROUP(msiof2_clk_e),
3666 SH_PFC_PIN_GROUP(msiof2_sync_e),
3667 SH_PFC_PIN_GROUP(msiof2_rx_e),
3668 SH_PFC_PIN_GROUP(msiof2_tx_e),
3669 SH_PFC_PIN_GROUP(qspi_ctrl),
3670 SH_PFC_PIN_GROUP(qspi_data2),
3671 SH_PFC_PIN_GROUP(qspi_data4),
3672 SH_PFC_PIN_GROUP(qspi_ctrl_b),
3673 SH_PFC_PIN_GROUP(qspi_data2_b),
3674 SH_PFC_PIN_GROUP(qspi_data4_b),
3154 SH_PFC_PIN_GROUP(scif0_data), 3675 SH_PFC_PIN_GROUP(scif0_data),
3155 SH_PFC_PIN_GROUP(scif0_data_b), 3676 SH_PFC_PIN_GROUP(scif0_data_b),
3156 SH_PFC_PIN_GROUP(scif0_data_c), 3677 SH_PFC_PIN_GROUP(scif0_data_c),
@@ -3337,6 +3858,18 @@ static const char * const i2c4_groups[] = {
3337 "i2c4_c", 3858 "i2c4_c",
3338}; 3859};
3339 3860
3861static const char * const i2c7_groups[] = {
3862 "i2c7",
3863 "i2c7_b",
3864 "i2c7_c",
3865};
3866
3867static const char * const i2c8_groups[] = {
3868 "i2c8",
3869 "i2c8_b",
3870 "i2c8_c",
3871};
3872
3340static const char * const intc_groups[] = { 3873static const char * const intc_groups[] = {
3341 "intc_irq0", 3874 "intc_irq0",
3342 "intc_irq1", 3875 "intc_irq1",
@@ -3358,6 +3891,18 @@ static const char * const msiof0_groups[] = {
3358 "msiof0_ss2", 3891 "msiof0_ss2",
3359 "msiof0_rx", 3892 "msiof0_rx",
3360 "msiof0_tx", 3893 "msiof0_tx",
3894 "msiof0_clk_b",
3895 "msiof0_sync_b",
3896 "msiof0_ss1_b",
3897 "msiof0_ss2_b",
3898 "msiof0_rx_b",
3899 "msiof0_tx_b",
3900 "msiof0_clk_c",
3901 "msiof0_sync_c",
3902 "msiof0_ss1_c",
3903 "msiof0_ss2_c",
3904 "msiof0_rx_c",
3905 "msiof0_tx_c",
3361}; 3906};
3362 3907
3363static const char * const msiof1_groups[] = { 3908static const char * const msiof1_groups[] = {
@@ -3367,6 +3912,25 @@ static const char * const msiof1_groups[] = {
3367 "msiof1_ss2", 3912 "msiof1_ss2",
3368 "msiof1_rx", 3913 "msiof1_rx",
3369 "msiof1_tx", 3914 "msiof1_tx",
3915 "msiof1_clk_b",
3916 "msiof1_sync_b",
3917 "msiof1_ss1_b",
3918 "msiof1_ss2_b",
3919 "msiof1_rx_b",
3920 "msiof1_tx_b",
3921 "msiof1_clk_c",
3922 "msiof1_sync_c",
3923 "msiof1_rx_c",
3924 "msiof1_tx_c",
3925 "msiof1_clk_d",
3926 "msiof1_sync_d",
3927 "msiof1_ss1_d",
3928 "msiof1_rx_d",
3929 "msiof1_tx_d",
3930 "msiof1_clk_e",
3931 "msiof1_sync_e",
3932 "msiof1_rx_e",
3933 "msiof1_tx_e",
3370}; 3934};
3371 3935
3372static const char * const msiof2_groups[] = { 3936static const char * const msiof2_groups[] = {
@@ -3376,6 +3940,35 @@ static const char * const msiof2_groups[] = {
3376 "msiof2_ss2", 3940 "msiof2_ss2",
3377 "msiof2_rx", 3941 "msiof2_rx",
3378 "msiof2_tx", 3942 "msiof2_tx",
3943 "msiof2_clk_b",
3944 "msiof2_sync_b",
3945 "msiof2_ss1_b",
3946 "msiof2_ss2_b",
3947 "msiof2_rx_b",
3948 "msiof2_tx_b",
3949 "msiof2_clk_c",
3950 "msiof2_sync_c",
3951 "msiof2_rx_c",
3952 "msiof2_tx_c",
3953 "msiof2_clk_d",
3954 "msiof2_sync_d",
3955 "msiof2_ss1_d",
3956 "msiof2_ss2_d",
3957 "msiof2_rx_d",
3958 "msiof2_tx_d",
3959 "msiof2_clk_e",
3960 "msiof2_sync_e",
3961 "msiof2_rx_e",
3962 "msiof2_tx_e",
3963};
3964
3965static const char * const qspi_groups[] = {
3966 "qspi_ctrl",
3967 "qspi_data2",
3968 "qspi_data4",
3969 "qspi_ctrl_b",
3970 "qspi_data2_b",
3971 "qspi_data4_b",
3379}; 3972};
3380 3973
3381static const char * const scif0_groups[] = { 3974static const char * const scif0_groups[] = {
@@ -3568,11 +4161,14 @@ static const struct sh_pfc_function pinmux_functions[] = {
3568 SH_PFC_FUNCTION(i2c2), 4161 SH_PFC_FUNCTION(i2c2),
3569 SH_PFC_FUNCTION(i2c3), 4162 SH_PFC_FUNCTION(i2c3),
3570 SH_PFC_FUNCTION(i2c4), 4163 SH_PFC_FUNCTION(i2c4),
4164 SH_PFC_FUNCTION(i2c7),
4165 SH_PFC_FUNCTION(i2c8),
3571 SH_PFC_FUNCTION(intc), 4166 SH_PFC_FUNCTION(intc),
3572 SH_PFC_FUNCTION(mmc), 4167 SH_PFC_FUNCTION(mmc),
3573 SH_PFC_FUNCTION(msiof0), 4168 SH_PFC_FUNCTION(msiof0),
3574 SH_PFC_FUNCTION(msiof1), 4169 SH_PFC_FUNCTION(msiof1),
3575 SH_PFC_FUNCTION(msiof2), 4170 SH_PFC_FUNCTION(msiof2),
4171 SH_PFC_FUNCTION(qspi),
3576 SH_PFC_FUNCTION(scif0), 4172 SH_PFC_FUNCTION(scif0),
3577 SH_PFC_FUNCTION(scif1), 4173 SH_PFC_FUNCTION(scif1),
3578 SH_PFC_FUNCTION(scif2), 4174 SH_PFC_FUNCTION(scif2),
diff --git a/drivers/pinctrl/sirf/pinctrl-atlas6.c b/drivers/pinctrl/sirf/pinctrl-atlas6.c
index 2b9f32065920..c4dd3d5cf9c3 100644
--- a/drivers/pinctrl/sirf/pinctrl-atlas6.c
+++ b/drivers/pinctrl/sirf/pinctrl-atlas6.c
@@ -1,7 +1,8 @@
1/* 1/*
2 * pinctrl pads, groups, functions for CSR SiRFatlasVI 2 * pinctrl pads, groups, functions for CSR SiRFatlasVI
3 * 3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. 4 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
5 * company.
5 * 6 *
6 * Licensed under GPLv2 or later. 7 * Licensed under GPLv2 or later.
7 */ 8 */
@@ -529,6 +530,40 @@ static const struct sirfsoc_padmux usp0_padmux = {
529 530
530static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 }; 531static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 };
531 532
533static const struct sirfsoc_muxmask usp0_only_utfs_muxmask[] = {
534 {
535 .group = 1,
536 .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22),
537 },
538};
539
540static const struct sirfsoc_padmux usp0_only_utfs_padmux = {
541 .muxmask_counts = ARRAY_SIZE(usp0_only_utfs_muxmask),
542 .muxmask = usp0_only_utfs_muxmask,
543 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
544 .funcmask = BIT(1) | BIT(2) | BIT(6),
545 .funcval = 0,
546};
547
548static const unsigned usp0_only_utfs_pins[] = { 51, 52, 53, 54 };
549
550static const struct sirfsoc_muxmask usp0_only_urfs_muxmask[] = {
551 {
552 .group = 1,
553 .mask = BIT(19) | BIT(20) | BIT(21) | BIT(23),
554 },
555};
556
557static const struct sirfsoc_padmux usp0_only_urfs_padmux = {
558 .muxmask_counts = ARRAY_SIZE(usp0_only_urfs_muxmask),
559 .muxmask = usp0_only_urfs_muxmask,
560 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
561 .funcmask = BIT(1) | BIT(2) | BIT(9),
562 .funcval = 0,
563};
564
565static const unsigned usp0_only_urfs_pins[] = { 51, 52, 53, 55 };
566
532static const struct sirfsoc_muxmask usp0_uart_nostreamctrl_muxmask[] = { 567static const struct sirfsoc_muxmask usp0_uart_nostreamctrl_muxmask[] = {
533 { 568 {
534 .group = 1, 569 .group = 1,
@@ -905,6 +940,8 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
905 SIRFSOC_PIN_GROUP("usp0grp", usp0_pins), 940 SIRFSOC_PIN_GROUP("usp0grp", usp0_pins),
906 SIRFSOC_PIN_GROUP("usp0_uart_nostreamctrl_grp", 941 SIRFSOC_PIN_GROUP("usp0_uart_nostreamctrl_grp",
907 usp0_uart_nostreamctrl_pins), 942 usp0_uart_nostreamctrl_pins),
943 SIRFSOC_PIN_GROUP("usp0_only_utfs_grp", usp0_only_utfs_pins),
944 SIRFSOC_PIN_GROUP("usp0_only_urfs_grp", usp0_only_urfs_pins),
908 SIRFSOC_PIN_GROUP("usp1grp", usp1_pins), 945 SIRFSOC_PIN_GROUP("usp1grp", usp1_pins),
909 SIRFSOC_PIN_GROUP("usp1_uart_nostreamctrl_grp", 946 SIRFSOC_PIN_GROUP("usp1_uart_nostreamctrl_grp",
910 usp1_uart_nostreamctrl_pins), 947 usp1_uart_nostreamctrl_pins),
@@ -953,6 +990,9 @@ static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
953static const char * const usp0_uart_nostreamctrl_grp[] = { 990static const char * const usp0_uart_nostreamctrl_grp[] = {
954 "usp0_uart_nostreamctrl_grp" }; 991 "usp0_uart_nostreamctrl_grp" };
955static const char * const usp0grp[] = { "usp0grp" }; 992static const char * const usp0grp[] = { "usp0grp" };
993static const char * const usp0_only_utfs_grp[] = { "usp0_only_utfs_grp" };
994static const char * const usp0_only_urfs_grp[] = { "usp0_only_urfs_grp" };
995
956static const char * const usp1grp[] = { "usp1grp" }; 996static const char * const usp1grp[] = { "usp1grp" };
957static const char * const usp1_uart_nostreamctrl_grp[] = { 997static const char * const usp1_uart_nostreamctrl_grp[] = {
958 "usp1_uart_nostreamctrl_grp" }; 998 "usp1_uart_nostreamctrl_grp" };
@@ -1003,6 +1043,10 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
1003 SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl", 1043 SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl",
1004 usp0_uart_nostreamctrl_grp, 1044 usp0_uart_nostreamctrl_grp,
1005 usp0_uart_nostreamctrl_padmux), 1045 usp0_uart_nostreamctrl_padmux),
1046 SIRFSOC_PMX_FUNCTION("usp0_only_utfs", usp0_only_utfs_grp,
1047 usp0_only_utfs_padmux),
1048 SIRFSOC_PMX_FUNCTION("usp0_only_urfs", usp0_only_urfs_grp,
1049 usp0_only_urfs_padmux),
1006 SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux), 1050 SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
1007 SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl", 1051 SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl",
1008 usp1_uart_nostreamctrl_grp, 1052 usp1_uart_nostreamctrl_grp,
diff --git a/drivers/pinctrl/sirf/pinctrl-prima2.c b/drivers/pinctrl/sirf/pinctrl-prima2.c
index dde0285544d6..8aa76f0776d7 100644
--- a/drivers/pinctrl/sirf/pinctrl-prima2.c
+++ b/drivers/pinctrl/sirf/pinctrl-prima2.c
@@ -1,7 +1,8 @@
1/* 1/*
2 * pinctrl pads, groups, functions for CSR SiRFprimaII 2 * pinctrl pads, groups, functions for CSR SiRFprimaII
3 * 3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. 4 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
5 * company.
5 * 6 *
6 * Licensed under GPLv2 or later. 7 * Licensed under GPLv2 or later.
7 */ 8 */
diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c
index 617a4916b50f..5f3adb87c1ef 100644
--- a/drivers/pinctrl/sirf/pinctrl-sirf.c
+++ b/drivers/pinctrl/sirf/pinctrl-sirf.c
@@ -1,7 +1,8 @@
1/* 1/*
2 * pinmux driver for CSR SiRFprimaII 2 * pinmux driver for CSR SiRFprimaII
3 * 3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. 4 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
5 * company.
5 * 6 *
6 * Licensed under GPLv2 or later. 7 * Licensed under GPLv2 or later.
7 */ 8 */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-22 00:17:13 -0400