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authorJunzhi Zhao <junzhi.zhao@mediatek.com>2016-09-28 23:02:13 -0400
committerCK Hu <ck.hu@mediatek.com>2016-10-18 21:06:41 -0400
commitd542b7c473f0eb34455974d66ea93653b3eb40ce (patch)
tree943e56930457879851d2af382f2cd50a6327dc92
parent56e4b1e183555c74097fa012f1606b22223f027b (diff)
drm/mediatek: do mtk_hdmi_send_infoframe after HDMI clock enable
The mtk_hdmi_send_infoframe have to be run after PLL and PIXEL clock of HDMI enable. Make sure that HDMI inforframes can be sent successfully. Signed-off-by: Junzhi Zhao <junzhi.zhao@mediatek.com> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
-rw-r--r--drivers/gpu/drm/mediatek/mtk_hdmi.c17
1 files changed, 11 insertions, 6 deletions
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 71227deef21b..0e8c4d9af340 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -1133,12 +1133,6 @@ static int mtk_hdmi_output_set_display_mode(struct mtk_hdmi *hdmi,
1133 phy_power_on(hdmi->phy); 1133 phy_power_on(hdmi->phy);
1134 mtk_hdmi_aud_output_config(hdmi, mode); 1134 mtk_hdmi_aud_output_config(hdmi, mode);
1135 1135
1136 mtk_hdmi_setup_audio_infoframe(hdmi);
1137 mtk_hdmi_setup_avi_infoframe(hdmi, mode);
1138 mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI");
1139 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
1140 mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode);
1141
1142 mtk_hdmi_hw_vid_black(hdmi, false); 1136 mtk_hdmi_hw_vid_black(hdmi, false);
1143 mtk_hdmi_hw_aud_unmute(hdmi); 1137 mtk_hdmi_hw_aud_unmute(hdmi);
1144 mtk_hdmi_hw_send_av_unmute(hdmi); 1138 mtk_hdmi_hw_send_av_unmute(hdmi);
@@ -1401,6 +1395,16 @@ static void mtk_hdmi_bridge_pre_enable(struct drm_bridge *bridge)
1401 hdmi->powered = true; 1395 hdmi->powered = true;
1402} 1396}
1403 1397
1398static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi,
1399 struct drm_display_mode *mode)
1400{
1401 mtk_hdmi_setup_audio_infoframe(hdmi);
1402 mtk_hdmi_setup_avi_infoframe(hdmi, mode);
1403 mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI");
1404 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
1405 mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode);
1406}
1407
1404static void mtk_hdmi_bridge_enable(struct drm_bridge *bridge) 1408static void mtk_hdmi_bridge_enable(struct drm_bridge *bridge)
1405{ 1409{
1406 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1410 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
@@ -1409,6 +1413,7 @@ static void mtk_hdmi_bridge_enable(struct drm_bridge *bridge)
1409 clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]); 1413 clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
1410 clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]); 1414 clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]);
1411 phy_power_on(hdmi->phy); 1415 phy_power_on(hdmi->phy);
1416 mtk_hdmi_send_infoframe(hdmi, &hdmi->mode);
1412 1417
1413 hdmi->enabled = true; 1418 hdmi->enabled = true;
1414} 1419}