Merge branch 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm

Pull ARM updates from Russell King:

 - nommu updates from Afzal Mohammed cleaning up the vectors support

 - allow DMA memory "mapping" for nommu Benjamin Gaignard

 - fixing a correctness issue with R_ARM_PREL31 relocations in the
   module linker

 - add strlen() prototype for the decompressor

 - support for DEBUG_VIRTUAL from Florian Fainelli

 - adjusting memory bounds after memory reservations have been
   registered

 - unipher cache handling updates from Masahiro Yamada

 - initrd and Thumb Kconfig cleanups

* 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm: (23 commits)
  ARM: mm: round the initrd reservation to page boundaries
  ARM: mm: clean up initrd initialisation
  ARM: mm: move initrd init code out of arm_memblock_init()
  ARM: 8655/1: improve NOMMU definition of pgprot_*()
  ARM: 8654/1: decompressor: add strlen prototype
  ARM: 8652/1: cache-uniphier: clean up active way setup code
  ARM: 8651/1: cache-uniphier: include <linux/errno.h> instead of <linux/types.h>
  ARM: 8650/1: module: handle negative R_ARM_PREL31 addends correctly
  ARM: 8649/2: nommu: remove Hivecs configuration is asm
  ARM: 8648/2: nommu: display vectors base
  ARM: 8647/2: nommu: dynamic exception base address setting
  ARM: 8646/1: mmu: decouple VECTORS_BASE from Kconfig
  ARM: 8644/1: Reduce "CPU: shutdown" message to debug level
  ARM: 8641/1: treewide: Replace uses of virt_to_phys with __pa_symbol
  ARM: 8640/1: Add support for CONFIG_DEBUG_VIRTUAL
  ARM: 8639/1: Define KERNEL_START and KERNEL_END
  ARM: 8638/1: mtd: lart: Rename partition defines to be prefixed with PART_
  ARM: 8637/1: Adjust memory boundaries after reservations
  ARM: 8636/1: Cleanup sanity_check_meminfo
  ARM: add CPU_THUMB_CAPABLE to indicate possible Thumb support
  ...

75 files changed, 382 insertions, 214 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index fda6a46d27cf..0d4e71b42c77 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -2,6 +2,7 @@ config ARM
         bool
         default y
         select ARCH_CLOCKSOURCE_DATA
+        select ARCH_HAS_DEBUG_VIRTUAL
         select ARCH_HAS_DEVMEM_IS_ALLOWED
         select ARCH_HAS_ELF_RANDOMIZE
         select ARCH_HAS_SET_MEMORY
diff --git a/arch/arm/Kconfig-nommu b/arch/arm/Kconfig-nommu
index aed66d5df7f1..b7576349528c 100644
--- a/arch/arm/Kconfig-nommu
+++ b/arch/arm/Kconfig-nommu
@@ -34,8 +34,7 @@ config PROCESSOR_ID
           used instead of the auto-probing which utilizes the register.
 
 config REMAP_VECTORS_TO_RAM
-        bool 'Install vectors to the beginning of RAM' if DRAM_BASE
-        depends on DRAM_BASE
+        bool 'Install vectors to the beginning of RAM'
         help
           The kernel needs to change the hardware exception vectors.
           In nommu mode, the hardware exception vectors are normally
diff --git a/arch/arm/boot/compressed/decompress.c b/arch/arm/boot/compressed/decompress.c
index a0765e7ed6c7..ea7832702a8f 100644
--- a/arch/arm/boot/compressed/decompress.c
+++ b/arch/arm/boot/compressed/decompress.c
@@ -32,6 +32,7 @@ extern void error(char *);
 
 /* Not needed, but used in some headers pulled in by decompressors */
 extern char * strstr(const char * s1, const char *s2);
+extern size_t strlen(const char *s);
 
 #ifdef CONFIG_KERNEL_GZIP
 #include "../../../../lib/decompress_inflate.c"
diff --git a/arch/arm/common/mcpm_entry.c b/arch/arm/common/mcpm_entry.c
index a923524d1040..cf062472e07b 100644
--- a/arch/arm/common/mcpm_entry.c
+++ b/arch/arm/common/mcpm_entry.c
@@ -144,7 +144,7 @@ extern unsigned long mcpm_entry_vectors[MAX_NR_CLUSTERS][MAX_CPUS_PER_CLUSTER];
 
 void mcpm_set_entry_vector(unsigned cpu, unsigned cluster, void *ptr)
 {
-        unsigned long val = ptr ? virt_to_phys(ptr) : 0;
+        unsigned long val = ptr ? __pa_symbol(ptr) : 0;
         mcpm_entry_vectors[cluster][cpu] = val;
         sync_cache_w(&mcpm_entry_vectors[cluster][cpu]);
 }
@@ -299,8 +299,8 @@ void mcpm_cpu_power_down(void)
          * the kernel as if the power_up method just had deasserted reset
          * on the CPU.
          */
-        phys_reset = (phys_reset_t)(unsigned long)virt_to_phys(cpu_reset);
-        phys_reset(virt_to_phys(mcpm_entry_point));
+        phys_reset = (phys_reset_t)(unsigned long)__pa_symbol(cpu_reset);
+        phys_reset(__pa_symbol(mcpm_entry_point));
 
         /* should never get here */
         BUG();
@@ -388,8 +388,8 @@ static int __init nocache_trampoline(unsigned long _arg)
         __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
         __mcpm_cpu_down(cpu, cluster);
 
-        phys_reset = (phys_reset_t)(unsigned long)virt_to_phys(cpu_reset);
-        phys_reset(virt_to_phys(mcpm_entry_point));
+        phys_reset = (phys_reset_t)(unsigned long)__pa_symbol(cpu_reset);
+        phys_reset(__pa_symbol(mcpm_entry_point));
         BUG();
 }
 
@@ -449,7 +449,7 @@ int __init mcpm_sync_init(
         sync_cache_w(&mcpm_sync);
 
         if (power_up_setup) {
-                mcpm_power_up_setup_phys = virt_to_phys(power_up_setup);
+                mcpm_power_up_setup_phys = __pa_symbol(power_up_setup);
                 sync_cache_w(&mcpm_power_up_setup_phys);
         }
 
diff --git a/arch/arm/include/asm/hardware/cache-uniphier.h b/arch/arm/include/asm/hardware/cache-uniphier.h
index eaa60da7dac3..0ef42ae75b6c 100644
--- a/arch/arm/include/asm/hardware/cache-uniphier.h
+++ b/arch/arm/include/asm/hardware/cache-uniphier.h
@@ -16,7 +16,7 @@
 #ifndef __CACHE_UNIPHIER_H
 #define __CACHE_UNIPHIER_H
 
-#include <linux/types.h>
+#include <linux/errno.h>
 
 #ifdef CONFIG_CACHE_UNIPHIER
 int uniphier_cache_init(void);
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 76cbd9c674df..1f54e4e98c1e 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -83,8 +83,15 @@
 #define IOREMAP_MAX_ORDER       24
 #endif
 
+#define VECTORS_BASE            UL(0xffff0000)
+
 #else /* CONFIG_MMU */
 
+#ifndef __ASSEMBLY__
+extern unsigned long vectors_base;
+#define VECTORS_BASE            vectors_base
+#endif
+
 /*
  * The limitation of user task size can grow up to the end of free ram region.
  * It is difficult to define and perhaps will never meet the original meaning
@@ -111,6 +118,13 @@
 
 #endif /* !CONFIG_MMU */
 
+#ifdef CONFIG_XIP_KERNEL
+#define KERNEL_START            _sdata
+#else
+#define KERNEL_START            _stext
+#endif
+#define KERNEL_END              _end
+
 /*
  * We fix the TCM memories max 32 KiB ITCM resp DTCM at these
  * locations
@@ -206,7 +220,7 @@ extern const void *__pv_table_begin, *__pv_table_end;
         : "r" (x), "I" (__PV_BITS_31_24)                \
         : "cc")
 
-static inline phys_addr_t __virt_to_phys(unsigned long x)
+static inline phys_addr_t __virt_to_phys_nodebug(unsigned long x)
 {
         phys_addr_t t;
 
@@ -238,7 +252,7 @@ static inline unsigned long __phys_to_virt(phys_addr_t x)
 #define PHYS_OFFSET     PLAT_PHYS_OFFSET
 #define PHYS_PFN_OFFSET ((unsigned long)(PHYS_OFFSET >> PAGE_SHIFT))
 
-static inline phys_addr_t __virt_to_phys(unsigned long x)
+static inline phys_addr_t __virt_to_phys_nodebug(unsigned long x)
 {
         return (phys_addr_t)x - PAGE_OFFSET + PHYS_OFFSET;
 }
@@ -254,6 +268,16 @@ static inline unsigned long __phys_to_virt(phys_addr_t x)
         ((((unsigned long)(kaddr) - PAGE_OFFSET) >> PAGE_SHIFT) + \
          PHYS_PFN_OFFSET)
 
+#define __pa_symbol_nodebug(x)  __virt_to_phys_nodebug((x))
+
+#ifdef CONFIG_DEBUG_VIRTUAL
+extern phys_addr_t __virt_to_phys(unsigned long x);
+extern phys_addr_t __phys_addr_symbol(unsigned long x);
+#else
+#define __virt_to_phys(x)       __virt_to_phys_nodebug(x)
+#define __phys_addr_symbol(x)   __pa_symbol_nodebug(x)
+#endif
+
 /*
  * These are *only* valid on the kernel direct mapped RAM memory.
  * Note: Drivers should NOT use these.  They are the wrong
@@ -276,6 +300,7 @@ static inline void *phys_to_virt(phys_addr_t x)
  * Drivers should NOT use these either.
  */
 #define __pa(x)                 __virt_to_phys((unsigned long)(x))
+#define __pa_symbol(x)          __phys_addr_symbol(RELOC_HIDE((unsigned long)(x), 0))
 #define __va(x)                 ((void *)__phys_to_virt((phys_addr_t)(x)))
 #define pfn_to_kaddr(pfn)       __va((phys_addr_t)(pfn) << PAGE_SHIFT)
 
diff --git a/arch/arm/include/asm/pgtable-nommu.h b/arch/arm/include/asm/pgtable-nommu.h
index add094d09e3e..302240c19a5a 100644
--- a/arch/arm/include/asm/pgtable-nommu.h
+++ b/arch/arm/include/asm/pgtable-nommu.h
@@ -63,9 +63,9 @@ typedef pte_t *pte_addr_t;
 /*
  * Mark the prot value as uncacheable and unbufferable.
  */
-#define pgprot_noncached(prot)  __pgprot(0)
-#define pgprot_writecombine(prot) __pgprot(0)
-#define pgprot_dmacoherent(prot) __pgprot(0)
+#define pgprot_noncached(prot)  (prot)
+#define pgprot_writecombine(prot) (prot)
+#define pgprot_dmacoherent(prot) (prot)
 
 
 /*
diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index 6b4eb27b8758..2e21e08de747 100644
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -152,11 +152,6 @@ __after_proc_init:
 #ifdef CONFIG_CPU_ICACHE_DISABLE
         bic     r0, r0, #CR_I
 #endif
-#ifdef CONFIG_CPU_HIGH_VECTOR
-        orr     r0, r0, #CR_V
-#else
-        bic     r0, r0, #CR_V
-#endif
         mcr     p15, 0, r0, c1, c0, 0           @ write control reg
 #elif defined (CONFIG_CPU_V7M)
         /* For V7M systems we want to modify the CCR similarly to the SCTLR */
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index 4f14b5ce6535..80254b47dc34 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -155,8 +155,17 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
                        break;
 
                 case R_ARM_PREL31:
-                        offset = *(u32 *)loc + sym->st_value - loc;
-                        *(u32 *)loc = offset & 0x7fffffff;
+                        offset = (*(s32 *)loc << 1) >> 1; /* sign extend */
+                        offset += sym->st_value - loc;
+                        if (offset >= 0x40000000 || offset < -0x40000000) {
+                                pr_err("%s: section %u reloc %u sym '%s': relocation %u out of range (%#lx -> %#x)\n",
+                                       module->name, relindex, i, symname,
+                                       ELF32_R_TYPE(rel->r_info), loc,
+                                       sym->st_value);
+                                return -ENOEXEC;
+                        }
+                        *(u32 *)loc &= 0x80000000;
+                        *(u32 *)loc |= offset & 0x7fffffff;
                         break;
 
                 case R_ARM_MOVW_ABS_NC:
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 34e3f3c45634..f4e54503afa9 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -81,7 +81,7 @@ __setup("fpe=", fpe_setup);
 extern void init_default_cache_policy(unsigned long);
 extern void paging_init(const struct machine_desc *desc);
 extern void early_paging_init(const struct machine_desc *);
-extern void sanity_check_meminfo(void);
+extern void adjust_lowmem_bounds(void);
 extern enum reboot_mode reboot_mode;
 extern void setup_dma_zone(const struct machine_desc *desc);
 
@@ -1093,8 +1093,14 @@ void __init setup_arch(char **cmdline_p)
         setup_dma_zone(mdesc);
         xen_early_init();
         efi_init();
-        sanity_check_meminfo();
+        /*
+         * Make sure the calculation for lowmem/highmem is set appropriately
+         * before reserving/allocating any mmeory
+         */
+        adjust_lowmem_bounds();
         arm_memblock_init(mdesc);
+        /* Memory may have been removed so recalculate the bounds. */
+        adjust_lowmem_bounds();
 
         early_ioremap_reset();
 
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index c6514ce0fcbc..5a07c5a4b894 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -251,7 +251,7 @@ void __cpu_die(unsigned int cpu)
                 pr_err("CPU%u: cpu didn't die\n", cpu);
                 return;
         }
-        pr_notice("CPU%u: shutdown\n", cpu);
+        pr_debug("CPU%u: shutdown\n", cpu);
 
         /*
          * platform_cpu_kill() is generally expected to do the powering off
diff --git a/arch/arm/mach-alpine/platsmp.c b/arch/arm/mach-alpine/platsmp.c
index dd77ea25e7ca..6dc6d491f88a 100644
--- a/arch/arm/mach-alpine/platsmp.c
+++ b/arch/arm/mach-alpine/platsmp.c
@@ -27,7 +27,7 @@ static int alpine_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         phys_addr_t addr;
 
-        addr = virt_to_phys(secondary_startup);
+        addr = __pa_symbol(secondary_startup);
 
         if (addr > (phys_addr_t)(uint32_t)(-1)) {
                 pr_err("FAIL: resume address over 32bit (%pa)", &addr);
diff --git a/arch/arm/mach-axxia/platsmp.c b/arch/arm/mach-axxia/platsmp.c
index ffbd71d45008..502e3df69f69 100644
--- a/arch/arm/mach-axxia/platsmp.c
+++ b/arch/arm/mach-axxia/platsmp.c
@@ -25,7 +25,7 @@
 static void write_release_addr(u32 release_phys)
 {
         u32 *virt = (u32 *) phys_to_virt(release_phys);
-        writel_relaxed(virt_to_phys(secondary_startup), virt);
+        writel_relaxed(__pa_symbol(secondary_startup), virt);
         /* Make sure this store is visible to other CPUs */
         smp_wmb();
         __cpuc_flush_dcache_area(virt, sizeof(u32));
diff --git a/arch/arm/mach-bcm/bcm63xx_smp.c b/arch/arm/mach-bcm/bcm63xx_smp.c
index 9b6727ed68cd..f5fb10b4376f 100644
--- a/arch/arm/mach-bcm/bcm63xx_smp.c
+++ b/arch/arm/mach-bcm/bcm63xx_smp.c
@@ -135,7 +135,7 @@ static int bcm63138_smp_boot_secondary(unsigned int cpu,
         }
 
         /* Write the secondary init routine to the BootLUT reset vector */
-        val = virt_to_phys(secondary_startup);
+        val = __pa_symbol(secondary_startup);
         writel_relaxed(val, bootlut_base + BOOTLUT_RESET_VECT);
 
         /* Power up the core, will jump straight to its reset vector when we
diff --git a/arch/arm/mach-bcm/platsmp-brcmstb.c b/arch/arm/mach-bcm/platsmp-brcmstb.c
index 40dc8448445e..12379960e982 100644
--- a/arch/arm/mach-bcm/platsmp-brcmstb.c
+++ b/arch/arm/mach-bcm/platsmp-brcmstb.c
@@ -151,7 +151,7 @@ static void brcmstb_cpu_boot(u32 cpu)
          * Set the reset vector to point to the secondary_startup
          * routine
          */
-        cpu_set_boot_addr(cpu, virt_to_phys(secondary_startup));
+        cpu_set_boot_addr(cpu, __pa_symbol(secondary_startup));
 
         /* Unhalt the cpu */
         cpu_rst_cfg_set(cpu, 0);
diff --git a/arch/arm/mach-bcm/platsmp.c b/arch/arm/mach-bcm/platsmp.c
index 3ac3a9bc663c..582886d0d02f 100644
--- a/arch/arm/mach-bcm/platsmp.c
+++ b/arch/arm/mach-bcm/platsmp.c
@@ -116,7 +116,7 @@ static int nsp_write_lut(unsigned int cpu)
                 return -ENOMEM;
         }
 
-        secondary_startup_phy = virt_to_phys(secondary_startup);
+        secondary_startup_phy = __pa_symbol(secondary_startup);
         BUG_ON(secondary_startup_phy > (phys_addr_t)U32_MAX);
 
         writel_relaxed(secondary_startup_phy, sku_rom_lut);
@@ -189,7 +189,7 @@ static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle)
          * Secondary cores will start in secondary_startup(),
          * defined in "arch/arm/kernel/head.S"
          */
-        boot_func = virt_to_phys(secondary_startup);
+        boot_func = __pa_symbol(secondary_startup);
         BUG_ON(boot_func & BOOT_ADDR_CPUID_MASK);
         BUG_ON(boot_func > (phys_addr_t)U32_MAX);
 
diff --git a/arch/arm/mach-berlin/platsmp.c b/arch/arm/mach-berlin/platsmp.c
index 93f90688db18..7586b7aec272 100644
--- a/arch/arm/mach-berlin/platsmp.c
+++ b/arch/arm/mach-berlin/platsmp.c
@@ -15,6 +15,7 @@
 
 #include <asm/cacheflush.h>
 #include <asm/cp15.h>
+#include <asm/memory.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
 
@@ -75,7 +76,7 @@ static void __init berlin_smp_prepare_cpus(unsigned int max_cpus)
         if (!cpu_ctrl)
                 goto unmap_scu;
 
-        vectors_base = ioremap(CONFIG_VECTORS_BASE, SZ_32K);
+        vectors_base = ioremap(VECTORS_BASE, SZ_32K);
         if (!vectors_base)
                 goto unmap_scu;
 
@@ -92,7 +93,7 @@ static void __init berlin_smp_prepare_cpus(unsigned int max_cpus)
          * Write the secondary startup address into the SW reset address
          * vector. This is used by boot_inst.
          */
-        writel(virt_to_phys(secondary_startup), vectors_base + SW_RESET_ADDR);
+        writel(__pa_symbol(secondary_startup), vectors_base + SW_RESET_ADDR);
 
         iounmap(vectors_base);
 unmap_scu:
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index fd6da5419b51..e81a78b125d9 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -41,7 +41,7 @@ static int exynos_do_idle(unsigned long mode)
         case FW_DO_IDLE_AFTR:
                 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
                         exynos_save_cp15();
-                writel_relaxed(virt_to_phys(exynos_cpu_resume_ns),
+                writel_relaxed(__pa_symbol(exynos_cpu_resume_ns),
                                sysram_ns_base_addr + 0x24);
                 writel_relaxed(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20);
                 if (soc_is_exynos3250()) {
@@ -135,7 +135,7 @@ static int exynos_suspend(void)
                 exynos_save_cp15();
 
         writel(EXYNOS_SLEEP_MAGIC, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
-        writel(virt_to_phys(exynos_cpu_resume_ns),
+        writel(__pa_symbol(exynos_cpu_resume_ns),
                 sysram_ns_base_addr + EXYNOS_BOOT_ADDR);
 
         return cpu_suspend(0, exynos_cpu_suspend);
diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c
index 038fd8c993d0..b42622562ea7 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -221,7 +221,7 @@ static void exynos_mcpm_setup_entry_point(void)
          */
         __raw_writel(0xe59f0000, ns_sram_base_addr);     /* ldr r0, [pc, #0] */
         __raw_writel(0xe12fff10, ns_sram_base_addr + 4); /* bx  r0 */
-        __raw_writel(virt_to_phys(mcpm_entry_point), ns_sram_base_addr + 8);
+        __raw_writel(__pa_symbol(mcpm_entry_point), ns_sram_base_addr + 8);
 }
 
 static struct syscore_ops exynos_mcpm_syscore_ops = {
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index a5d68411a037..5a03bffe7226 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -353,7 +353,7 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
 
                 smp_rmb();
 
-                boot_addr = virt_to_phys(exynos4_secondary_startup);
+                boot_addr = __pa_symbol(exynos4_secondary_startup);
 
                 ret = exynos_set_boot_addr(core_id, boot_addr);
                 if (ret)
@@ -413,7 +413,7 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
 
                 mpidr = cpu_logical_map(i);
                 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
-                boot_addr = virt_to_phys(exynos4_secondary_startup);
+                boot_addr = __pa_symbol(exynos4_secondary_startup);
 
                 ret = exynos_set_boot_addr(core_id, boot_addr);
                 if (ret)
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 487295f4a56b..1a7e5b5d08d8 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -132,7 +132,7 @@ static void exynos_set_wakeupmask(long mask)
 
 static void exynos_cpu_set_boot_vector(long flags)
 {
-        writel_relaxed(virt_to_phys(exynos_cpu_resume),
+        writel_relaxed(__pa_symbol(exynos_cpu_resume),
                        exynos_boot_vector_addr());
         writel_relaxed(flags, exynos_boot_vector_flag());
 }
@@ -238,7 +238,7 @@ static int exynos_cpu0_enter_aftr(void)
 
 abort:
         if (cpu_online(1)) {
-                unsigned long boot_addr = virt_to_phys(exynos_cpu_resume);
+                unsigned long boot_addr = __pa_symbol(exynos_cpu_resume);
 
                 /*
                  * Set the boot vector to something non-zero
@@ -330,7 +330,7 @@ cpu1_aborted:
 
 static void exynos_pre_enter_aftr(void)
 {
-        unsigned long boot_addr = virt_to_phys(exynos_cpu_resume);
+        unsigned long boot_addr = __pa_symbol(exynos_cpu_resume);
 
         (void)exynos_set_boot_addr(1, boot_addr);
 }
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index adf4e8f182bd..748cfb8d5212 100644
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -301,7 +301,7 @@ static void exynos_pm_prepare(void)
         exynos_pm_enter_sleep_mode();
 
         /* ensure at least INFORM0 has the resume address */
-        pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
+        pmu_raw_writel(__pa_symbol(exynos_cpu_resume), S5P_INFORM0);
 }
 
 static void exynos3250_pm_prepare(void)
@@ -318,7 +318,7 @@ static void exynos3250_pm_prepare(void)
         exynos_pm_enter_sleep_mode();
 
         /* ensure at least INFORM0 has the resume address */
-        pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
+        pmu_raw_writel(__pa_symbol(exynos_cpu_resume), S5P_INFORM0);
 }
 
 static void exynos5420_pm_prepare(void)
@@ -343,7 +343,7 @@ static void exynos5420_pm_prepare(void)
 
         /* ensure at least INFORM0 has the resume address */
         if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
-                pmu_raw_writel(virt_to_phys(mcpm_entry_point), S5P_INFORM0);
+                pmu_raw_writel(__pa_symbol(mcpm_entry_point), S5P_INFORM0);
 
         tmp = pmu_raw_readl(EXYNOS_L2_OPTION(0));
         tmp &= ~EXYNOS_L2_USE_RETENTION;
diff --git a/arch/arm/mach-hisi/platmcpm.c b/arch/arm/mach-hisi/platmcpm.c
index 4b653a8cb75c..a6c117622d67 100644
--- a/arch/arm/mach-hisi/platmcpm.c
+++ b/arch/arm/mach-hisi/platmcpm.c
@@ -327,7 +327,7 @@ static int __init hip04_smp_init(void)
          */
         writel_relaxed(hip04_boot_method[0], relocation);
         writel_relaxed(0xa5a5a5a5, relocation + 4);     /* magic number */
-        writel_relaxed(virt_to_phys(secondary_startup), relocation + 8);
+        writel_relaxed(__pa_symbol(secondary_startup), relocation + 8);
         writel_relaxed(0, relocation + 12);
         iounmap(relocation);
 
diff --git a/arch/arm/mach-hisi/platsmp.c b/arch/arm/mach-hisi/platsmp.c
index e1d67648d5d0..91bb02dec20f 100644
--- a/arch/arm/mach-hisi/platsmp.c
+++ b/arch/arm/mach-hisi/platsmp.c
@@ -28,7 +28,7 @@ void hi3xxx_set_cpu_jump(int cpu, void *jump_addr)
         cpu = cpu_logical_map(cpu);
         if (!cpu || !ctrl_base)
                 return;
-        writel_relaxed(virt_to_phys(jump_addr), ctrl_base + ((cpu - 1) << 2));
+        writel_relaxed(__pa_symbol(jump_addr), ctrl_base + ((cpu - 1) << 2));
 }
 
 int hi3xxx_get_cpu_jump(int cpu)
@@ -118,7 +118,7 @@ static int hix5hd2_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         phys_addr_t jumpaddr;
 
-        jumpaddr = virt_to_phys(secondary_startup);
+        jumpaddr = __pa_symbol(secondary_startup);
         hix5hd2_set_scu_boot_addr(HIX5HD2_BOOT_ADDRESS, jumpaddr);
         hix5hd2_set_cpu(cpu, true);
         arch_send_wakeup_ipi_mask(cpumask_of(cpu));
@@ -156,7 +156,7 @@ static int hip01_boot_secondary(unsigned int cpu, struct task_struct *idle)
         struct device_node *node;
 
 
-        jumpaddr = virt_to_phys(secondary_startup);
+        jumpaddr = __pa_symbol(secondary_startup);
         hip01_set_boot_addr(HIP01_BOOT_ADDRESS, jumpaddr);
 
         node = of_find_compatible_node(NULL, NULL, "hisilicon,hip01-sysctrl");
diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
index 711dbbd5badd..c2d1b329fba1 100644
--- a/arch/arm/mach-imx/platsmp.c
+++ b/arch/arm/mach-imx/platsmp.c
@@ -117,7 +117,7 @@ static void __init ls1021a_smp_prepare_cpus(unsigned int max_cpus)
         dcfg_base = of_iomap(np, 0);
         BUG_ON(!dcfg_base);
 
-        paddr = virt_to_phys(secondary_startup);
+        paddr = __pa_symbol(secondary_startup);
         writel_relaxed(cpu_to_be32(paddr), dcfg_base + DCFG_CCSR_SCRATCHRW1);
 
         iounmap(dcfg_base);
diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c
index 1515e498d348..e61b1d1027e1 100644
--- a/arch/arm/mach-imx/pm-imx6.c
+++ b/arch/arm/mach-imx/pm-imx6.c
@@ -499,7 +499,7 @@ static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata)
         memset(suspend_ocram_base, 0, sizeof(*pm_info));
         pm_info = suspend_ocram_base;
         pm_info->pbase = ocram_pbase;
-        pm_info->resume_addr = virt_to_phys(v7_cpu_resume);
+        pm_info->resume_addr = __pa_symbol(v7_cpu_resume);
         pm_info->pm_info_size = sizeof(*pm_info);
 
         /*
diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c
index 70b083fe934a..495d85d0fe7e 100644
--- a/arch/arm/mach-imx/src.c
+++ b/arch/arm/mach-imx/src.c
@@ -99,7 +99,7 @@ void imx_enable_cpu(int cpu, bool enable)
 void imx_set_cpu_jump(int cpu, void *jump_addr)
 {
         cpu = cpu_logical_map(cpu);
-        writel_relaxed(virt_to_phys(jump_addr),
+        writel_relaxed(__pa_symbol(jump_addr),
                        src_base + SRC_GPR1 + cpu * 8);
 }
 
diff --git a/arch/arm/mach-mediatek/platsmp.c b/arch/arm/mach-mediatek/platsmp.c
index b821e34474b6..726eb69bb655 100644
--- a/arch/arm/mach-mediatek/platsmp.c
+++ b/arch/arm/mach-mediatek/platsmp.c
@@ -122,7 +122,7 @@ static void __init __mtk_smp_prepare_cpus(unsigned int max_cpus, int trustzone)
          * write the address of slave startup address into the system-wide
          * jump register
          */
-        writel_relaxed(virt_to_phys(secondary_startup_arm),
+        writel_relaxed(__pa_symbol(secondary_startup_arm),
                         mtk_smp_base + mtk_smp_info->jump_reg);
 }
 
diff --git a/arch/arm/mach-mvebu/pm.c b/arch/arm/mach-mvebu/pm.c
index 2990c5269b18..c487be61d6d8 100644
--- a/arch/arm/mach-mvebu/pm.c
+++ b/arch/arm/mach-mvebu/pm.c
@@ -110,7 +110,7 @@ static void mvebu_pm_store_armadaxp_bootinfo(u32 *store_addr)
 {
         phys_addr_t resume_pc;
 
-        resume_pc = virt_to_phys(armada_370_xp_cpu_resume);
+        resume_pc = __pa_symbol(armada_370_xp_cpu_resume);
 
         /*
          * The bootloader expects the first two words to be a magic
diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
index f39bd51bce18..27a78c80e5b1 100644
--- a/arch/arm/mach-mvebu/pmsu.c
+++ b/arch/arm/mach-mvebu/pmsu.c
@@ -112,7 +112,7 @@ static const struct of_device_id of_pmsu_table[] = {
 
 void mvebu_pmsu_set_cpu_boot_addr(int hw_cpu, void *boot_addr)
 {
-        writel(virt_to_phys(boot_addr), pmsu_mp_base +
+        writel(__pa_symbol(boot_addr), pmsu_mp_base +
                 PMSU_BOOT_ADDR_REDIRECT_OFFSET(hw_cpu));
 }
 
diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c
index 76cbc82a7407..04d9ebe6a90a 100644
--- a/arch/arm/mach-mvebu/system-controller.c
+++ b/arch/arm/mach-mvebu/system-controller.c
@@ -153,7 +153,7 @@ void mvebu_system_controller_set_cpu_boot_addr(void *boot_addr)
         if (of_machine_is_compatible("marvell,armada375"))
                 mvebu_armada375_smp_wa_init();
 
-        writel(virt_to_phys(boot_addr), system_controller_base +
+        writel(__pa_symbol(boot_addr), system_controller_base +
                mvebu_sc->resume_boot_addr);
 }
 #endif
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 1662071bb2cc..bd8089ff929f 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -315,15 +315,15 @@ void omap3_save_scratchpad_contents(void)
         scratchpad_contents.boot_config_ptr = 0x0;
         if (cpu_is_omap3630())
                 scratchpad_contents.public_restore_ptr =
-                        virt_to_phys(omap3_restore_3630);
+                        __pa_symbol(omap3_restore_3630);
         else if (omap_rev() != OMAP3430_REV_ES3_0 &&
                                         omap_rev() != OMAP3430_REV_ES3_1 &&
                                         omap_rev() != OMAP3430_REV_ES3_1_2)
                 scratchpad_contents.public_restore_ptr =
-                        virt_to_phys(omap3_restore);
+                        __pa_symbol(omap3_restore);
         else
                 scratchpad_contents.public_restore_ptr =
-                        virt_to_phys(omap3_restore_es3);
+                        __pa_symbol(omap3_restore_es3);
 
         if (omap_type() == OMAP2_DEVICE_TYPE_GP)
                 scratchpad_contents.secure_ram_restore_ptr = 0x0;
@@ -395,7 +395,7 @@ void omap3_save_scratchpad_contents(void)
         sdrc_block_contents.flags = 0x0;
         sdrc_block_contents.block_size = 0x0;
 
-        arm_context_addr = virt_to_phys(omap3_arm_context);
+        arm_context_addr = __pa_symbol(omap3_arm_context);
 
         /* Copy all the contents to the scratchpad location */
         scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index 7d62ad48c7c9..113ab2dd2ee9 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -273,7 +273,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
         cpu_clear_prev_logic_pwrst(cpu);
         pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
         pwrdm_set_logic_retst(pm_info->pwrdm, cpu_logic_state);
-        set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.resume));
+        set_cpu_wakeup_addr(cpu, __pa_symbol(omap_pm_ops.resume));
         omap_pm_ops.scu_prepare(cpu, power_state);
         l2x0_pwrst_prepare(cpu, save_state);
 
@@ -325,7 +325,7 @@ int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
 
         pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
         pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
-        set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.hotplug_restart));
+        set_cpu_wakeup_addr(cpu, __pa_symbol(omap_pm_ops.hotplug_restart));
         omap_pm_ops.scu_prepare(cpu, power_state);
 
         /*
@@ -467,13 +467,13 @@ void __init omap4_mpuss_early_init(void)
         sar_base = omap4_get_sar_ram_base();
 
         if (cpu_is_omap443x())
-                startup_pa = virt_to_phys(omap4_secondary_startup);
+                startup_pa = __pa_symbol(omap4_secondary_startup);
         else if (cpu_is_omap446x())
-                startup_pa = virt_to_phys(omap4460_secondary_startup);
+                startup_pa = __pa_symbol(omap4460_secondary_startup);
         else if ((__boot_cpu_mode & MODE_MASK) == HYP_MODE)
-                startup_pa = virt_to_phys(omap5_secondary_hyp_startup);
+                startup_pa = __pa_symbol(omap5_secondary_hyp_startup);
         else
-                startup_pa = virt_to_phys(omap5_secondary_startup);
+                startup_pa = __pa_symbol(omap5_secondary_startup);
 
         if (cpu_is_omap44xx())
                 writel_relaxed(startup_pa, sar_base +
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index b4de3da6dffa..003353b0b794 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -316,9 +316,9 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
          * A barrier is added to ensure that write buffer is drained
          */
         if (omap_secure_apis_support())
-                omap_auxcoreboot_addr(virt_to_phys(cfg.startup_addr));
+                omap_auxcoreboot_addr(__pa_symbol(cfg.startup_addr));
         else
-                writel_relaxed(virt_to_phys(cfg.startup_addr),
+                writel_relaxed(__pa_symbol(cfg.startup_addr),
                                base + OMAP_AUX_CORE_BOOT_1);
 }
 
diff --git a/arch/arm/mach-prima2/platsmp.c b/arch/arm/mach-prima2/platsmp.c
index 0875b99add18..75ef5d4be554 100644
--- a/arch/arm/mach-prima2/platsmp.c
+++ b/arch/arm/mach-prima2/platsmp.c
@@ -65,7 +65,7 @@ static int sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle)
          * waiting for. This would wake up the secondary core from WFE
          */
 #define SIRFSOC_CPU1_JUMPADDR_OFFSET 0x2bc
-        __raw_writel(virt_to_phys(sirfsoc_secondary_startup),
+        __raw_writel(__pa_symbol(sirfsoc_secondary_startup),
                 clk_base + SIRFSOC_CPU1_JUMPADDR_OFFSET);
 
 #define SIRFSOC_CPU1_WAKEMAGIC_OFFSET 0x2b8
diff --git a/arch/arm/mach-prima2/pm.c b/arch/arm/mach-prima2/pm.c
index 83e94c95e314..b0bcf1ff02dd 100644
--- a/arch/arm/mach-prima2/pm.c
+++ b/arch/arm/mach-prima2/pm.c
@@ -54,7 +54,7 @@ static void sirfsoc_set_sleep_mode(u32 mode)
 
 static int sirfsoc_pre_suspend_power_off(void)
 {
-        u32 wakeup_entry = virt_to_phys(cpu_resume);
+        u32 wakeup_entry = __pa_symbol(cpu_resume);
 
         sirfsoc_rtc_iobrg_writel(wakeup_entry, sirfsoc_pwrc_base +
                 SIRFSOC_PWRC_SCRATCH_PAD1);
diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c
index 9c308de158c6..29630061e700 100644
--- a/arch/arm/mach-pxa/palmz72.c
+++ b/arch/arm/mach-pxa/palmz72.c
@@ -249,7 +249,7 @@ static int palmz72_pm_suspend(void)
         store_ptr = *PALMZ72_SAVE_DWORD;
 
         /* Setting PSPR to a proper value */
-        PSPR = virt_to_phys(&palmz72_resume_info);
+        PSPR = __pa_symbol(&palmz72_resume_info);
 
         return 0;
 }
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index c725baf119e1..ba431fad5c47 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -85,7 +85,7 @@ static void pxa25x_cpu_pm_enter(suspend_state_t state)
 static int pxa25x_cpu_pm_prepare(void)
 {
         /* set resume return address */
-        PSPR = virt_to_phys(cpu_resume);
+        PSPR = __pa_symbol(cpu_resume);
         return 0;
 }
 
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index c0185c5c5a08..9b69be4e9fe3 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -168,7 +168,7 @@ static int pxa27x_cpu_pm_valid(suspend_state_t state)
 static int pxa27x_cpu_pm_prepare(void)
 {
         /* set resume return address */
-        PSPR = virt_to_phys(cpu_resume);
+        PSPR = __pa_symbol(cpu_resume);
         return 0;
 }
 
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index 87acc96388c7..0cc9f124c9ac 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -123,7 +123,7 @@ static void pxa3xx_cpu_pm_suspend(void)
         PSPR = 0x5c014000;
 
         /* overwrite with the resume address */
-        *p = virt_to_phys(cpu_resume);
+        *p = __pa_symbol(cpu_resume);
 
         cpu_suspend(0, pxa3xx_finish_suspend);
 
diff --git a/arch/arm/mach-realview/platsmp-dt.c b/arch/arm/mach-realview/platsmp-dt.c
index 70ca99eb52c6..c242423bf8db 100644
--- a/arch/arm/mach-realview/platsmp-dt.c
+++ b/arch/arm/mach-realview/platsmp-dt.c
@@ -76,7 +76,7 @@ static void __init realview_smp_prepare_cpus(unsigned int max_cpus)
         }
         /* Put the boot address in this magic register */
         regmap_write(map, REALVIEW_SYS_FLAGSSET_OFFSET,
-                     virt_to_phys(versatile_secondary_startup));
+                     __pa_symbol(versatile_secondary_startup));
 }
 
 static const struct smp_operations realview_dt_smp_ops __initconst = {
diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
index 4d827a069d49..3abafdbdd7f4 100644
--- a/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -156,7 +156,7 @@ static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle)
                  */
                 mdelay(1); /* ensure the cpus other than cpu0 to startup */
 
-                writel(virt_to_phys(secondary_startup), sram_base_addr + 8);
+                writel(__pa_symbol(secondary_startup), sram_base_addr + 8);
                 writel(0xDEADBEAF, sram_base_addr + 4);
                 dsb_sev();
         }
@@ -195,7 +195,7 @@ static int __init rockchip_smp_prepare_sram(struct device_node *node)
         }
 
         /* set the boot function for the sram code */
-        rockchip_boot_fn = virt_to_phys(secondary_startup);
+        rockchip_boot_fn = __pa_symbol(secondary_startup);
 
         /* copy the trampoline to sram, that runs during startup of the core */
         memcpy(sram_base_addr, &rockchip_secondary_trampoline, trampoline_sz);
diff --git a/arch/arm/mach-rockchip/pm.c b/arch/arm/mach-rockchip/pm.c
index bee8c8051929..0592534e0b88 100644
--- a/arch/arm/mach-rockchip/pm.c
+++ b/arch/arm/mach-rockchip/pm.c
@@ -62,7 +62,7 @@ static inline u32 rk3288_l2_config(void)
 static void rk3288_config_bootdata(void)
 {
         rkpm_bootdata_cpusp = rk3288_bootram_phy + (SZ_4K - 8);
-        rkpm_bootdata_cpu_code = virt_to_phys(cpu_resume);
+        rkpm_bootdata_cpu_code = __pa_symbol(cpu_resume);
 
         rkpm_bootdata_l2ctlr_f  = 1;
         rkpm_bootdata_l2ctlr = rk3288_l2_config();
diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c
index 895aca225952..f5b5c49b56ac 100644
--- a/arch/arm/mach-s3c24xx/mach-jive.c
+++ b/arch/arm/mach-s3c24xx/mach-jive.c
@@ -484,7 +484,7 @@ static int jive_pm_suspend(void)
          * correct address to resume from. */
 
         __raw_writel(0x2BED, S3C2412_INFORM0);
-        __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1);
+        __raw_writel(__pa_symbol(s3c_cpu_resume), S3C2412_INFORM1);
 
         return 0;
 }
diff --git a/arch/arm/mach-s3c24xx/pm-s3c2410.c b/arch/arm/mach-s3c24xx/pm-s3c2410.c
index 20e481d8a33a..a4588daeddb0 100644
--- a/arch/arm/mach-s3c24xx/pm-s3c2410.c
+++ b/arch/arm/mach-s3c24xx/pm-s3c2410.c
@@ -45,7 +45,7 @@ static void s3c2410_pm_prepare(void)
 {
         /* ensure at least GSTATUS3 has the resume address */
 
-        __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2410_GSTATUS3);
+        __raw_writel(__pa_symbol(s3c_cpu_resume), S3C2410_GSTATUS3);
 
         S3C_PMDBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3));
         S3C_PMDBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4));
diff --git a/arch/arm/mach-s3c24xx/pm-s3c2416.c b/arch/arm/mach-s3c24xx/pm-s3c2416.c
index c0e328e37bd6..b5bbf0d5985c 100644
--- a/arch/arm/mach-s3c24xx/pm-s3c2416.c
+++ b/arch/arm/mach-s3c24xx/pm-s3c2416.c
@@ -48,7 +48,7 @@ static void s3c2416_pm_prepare(void)
          * correct address to resume from.
          */
         __raw_writel(0x2BED, S3C2412_INFORM0);
-        __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1);
+        __raw_writel(__pa_symbol(s3c_cpu_resume), S3C2412_INFORM1);
 }
 
 static int s3c2416_pm_add(struct device *dev, struct subsys_interface *sif)
diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c
index b0be382ff6bb..2f579be8fe67 100644
--- a/arch/arm/mach-s3c64xx/pm.c
+++ b/arch/arm/mach-s3c64xx/pm.c
@@ -304,7 +304,7 @@ static void s3c64xx_pm_prepare(void)
                               wake_irqs, ARRAY_SIZE(wake_irqs));
 
         /* store address of resume. */
-        __raw_writel(virt_to_phys(s3c_cpu_resume), S3C64XX_INFORM0);
+        __raw_writel(__pa_symbol(s3c_cpu_resume), S3C64XX_INFORM0);
 
         /* ensure previous wakeup state is cleared before sleeping */
         __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT);
diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c
index 7d69666de5ba..07cee14a363b 100644
--- a/arch/arm/mach-s5pv210/pm.c
+++ b/arch/arm/mach-s5pv210/pm.c
@@ -69,7 +69,7 @@ static void s5pv210_pm_prepare(void)
         __raw_writel(s5pv210_irqwake_intmask, S5P_WAKEUP_MASK);
 
         /* ensure at least INFORM0 has the resume address */
-        __raw_writel(virt_to_phys(s5pv210_cpu_resume), S5P_INFORM0);
+        __raw_writel(__pa_symbol(s5pv210_cpu_resume), S5P_INFORM0);
 
         tmp = __raw_readl(S5P_SLEEP_CFG);
         tmp &= ~(S5P_SLEEP_CFG_OSC_EN | S5P_SLEEP_CFG_USBOSC_EN);
diff --git a/arch/arm/mach-sa1100/pm.c b/arch/arm/mach-sa1100/pm.c
index 34853d5dfda2..9a7079f565bd 100644
--- a/arch/arm/mach-sa1100/pm.c
+++ b/arch/arm/mach-sa1100/pm.c
@@ -73,7 +73,7 @@ static int sa11x0_pm_enter(suspend_state_t state)
         RCSR = RCSR_HWR | RCSR_SWR | RCSR_WDR | RCSR_SMR;
 
         /* set resume return address */
-        PSPR = virt_to_phys(cpu_resume);
+        PSPR = __pa_symbol(cpu_resume);
 
         /* go zzz */
         cpu_suspend(0, sa1100_finish_suspend);
diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c
index e19266844e16..3ca2c13346f0 100644
--- a/arch/arm/mach-shmobile/platsmp-apmu.c
+++ b/arch/arm/mach-shmobile/platsmp-apmu.c
@@ -190,7 +190,7 @@ static void apmu_parse_dt(void (*fn)(struct resource *res, int cpu, int bit))
 static void __init shmobile_smp_apmu_setup_boot(void)
 {
         /* install boot code shared by all CPUs */
-        shmobile_boot_fn = virt_to_phys(shmobile_smp_boot);
+        shmobile_boot_fn = __pa_symbol(shmobile_smp_boot);
 }
 
 void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus,
@@ -204,7 +204,7 @@ void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus,
 int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         /* For this particular CPU register boot vector */
-        shmobile_smp_hook(cpu, virt_to_phys(secondary_startup), 0);
+        shmobile_smp_hook(cpu, __pa_symbol(secondary_startup), 0);
 
         return apmu_wrap(cpu, apmu_power_on);
 }
@@ -308,7 +308,7 @@ int shmobile_smp_apmu_cpu_kill(unsigned int cpu)
 #if defined(CONFIG_SUSPEND)
 static int shmobile_smp_apmu_do_suspend(unsigned long cpu)
 {
-        shmobile_smp_hook(cpu, virt_to_phys(cpu_resume), 0);
+        shmobile_smp_hook(cpu, __pa_symbol(cpu_resume), 0);
         shmobile_smp_apmu_cpu_shutdown(cpu);
         cpu_do_idle(); /* WFI selects Core Standby */
         return 1;
diff --git a/arch/arm/mach-shmobile/platsmp-scu.c b/arch/arm/mach-shmobile/platsmp-scu.c
index d1ecaf37d142..f1a1efde4beb 100644
--- a/arch/arm/mach-shmobile/platsmp-scu.c
+++ b/arch/arm/mach-shmobile/platsmp-scu.c
@@ -24,7 +24,7 @@ static void __iomem *shmobile_scu_base;
 static int shmobile_scu_cpu_prepare(unsigned int cpu)
 {
         /* For this particular CPU register SCU SMP boot vector */
-        shmobile_smp_hook(cpu, virt_to_phys(shmobile_boot_scu),
+        shmobile_smp_hook(cpu, __pa_symbol(shmobile_boot_scu),
                           shmobile_scu_base_phys);
         return 0;
 }
@@ -33,7 +33,7 @@ void __init shmobile_smp_scu_prepare_cpus(phys_addr_t scu_base_phys,
                                           unsigned int max_cpus)
 {
         /* install boot code shared by all CPUs */
-        shmobile_boot_fn = virt_to_phys(shmobile_smp_boot);
+        shmobile_boot_fn = __pa_symbol(shmobile_smp_boot);
 
         /* enable SCU and cache coherency on booting CPU */
         shmobile_scu_base_phys = scu_base_phys;
diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c
index 07945748b571..0ee76772b507 100644
--- a/arch/arm/mach-socfpga/platsmp.c
+++ b/arch/arm/mach-socfpga/platsmp.c
@@ -40,7 +40,7 @@ static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
 
                 memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
 
-                writel(virt_to_phys(secondary_startup),
+                writel(__pa_symbol(secondary_startup),
                        sys_manager_base_addr + (socfpga_cpu1start_addr & 0x000000ff));
 
                 flush_cache_all();
@@ -63,7 +63,7 @@ static int socfpga_a10_boot_secondary(unsigned int cpu, struct task_struct *idle
                        SOCFPGA_A10_RSTMGR_MODMPURST);
                 memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
 
-                writel(virt_to_phys(secondary_startup),
+                writel(__pa_symbol(secondary_startup),
                        sys_manager_base_addr + (socfpga_cpu1start_addr & 0x00000fff));
 
                 flush_cache_all();
diff --git a/arch/arm/mach-spear/platsmp.c b/arch/arm/mach-spear/platsmp.c
index 8d1e2d551786..39038a03836a 100644
--- a/arch/arm/mach-spear/platsmp.c
+++ b/arch/arm/mach-spear/platsmp.c
@@ -117,7 +117,7 @@ static void __init spear13xx_smp_prepare_cpus(unsigned int max_cpus)
          * (presently it is in SRAM). The BootMonitor waits until it receives a
          * soft interrupt, and then the secondary CPU branches to this address.
          */
-        __raw_writel(virt_to_phys(spear13xx_secondary_startup), SYS_LOCATION);
+        __raw_writel(__pa_symbol(spear13xx_secondary_startup), SYS_LOCATION);
 }
 
 const struct smp_operations spear13xx_smp_ops __initconst = {
diff --git a/arch/arm/mach-sti/platsmp.c b/arch/arm/mach-sti/platsmp.c
index ea5a2277ee46..231f19e17436 100644
--- a/arch/arm/mach-sti/platsmp.c
+++ b/arch/arm/mach-sti/platsmp.c
@@ -103,7 +103,7 @@ static void __init sti_smp_prepare_cpus(unsigned int max_cpus)
         u32 __iomem *cpu_strt_ptr;
         u32 release_phys;
         int cpu;
-        unsigned long entry_pa = virt_to_phys(sti_secondary_startup);
+        unsigned long entry_pa = __pa_symbol(sti_secondary_startup);
 
         np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
 
diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c
index 6642267812c9..8fb5088464db 100644
--- a/arch/arm/mach-sunxi/platsmp.c
+++ b/arch/arm/mach-sunxi/platsmp.c
@@ -80,7 +80,7 @@ static int sun6i_smp_boot_secondary(unsigned int cpu,
         spin_lock(&cpu_lock);
 
         /* Set CPU boot address */
-        writel(virt_to_phys(secondary_startup),
+        writel(__pa_symbol(secondary_startup),
                cpucfg_membase + CPUCFG_PRIVATE0_REG);
 
         /* Assert the CPU core in reset */
@@ -162,7 +162,7 @@ static int sun8i_smp_boot_secondary(unsigned int cpu,
         spin_lock(&cpu_lock);
 
         /* Set CPU boot address */
-        writel(virt_to_phys(secondary_startup),
+        writel(__pa_symbol(secondary_startup),
                cpucfg_membase + CPUCFG_PRIVATE0_REG);
 
         /* Assert the CPU core in reset */
diff --git a/arch/arm/mach-tango/platsmp.c b/arch/arm/mach-tango/platsmp.c
index 98c62a4a8623..2f0c6c050fed 100644
--- a/arch/arm/mach-tango/platsmp.c
+++ b/arch/arm/mach-tango/platsmp.c
@@ -5,7 +5,7 @@
 
 static int tango_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
-        tango_set_aux_boot_addr(virt_to_phys(secondary_startup));
+        tango_set_aux_boot_addr(__pa_symbol(secondary_startup));
         tango_start_aux_core(cpu);
         return 0;
 }
diff --git a/arch/arm/mach-tango/pm.c b/arch/arm/mach-tango/pm.c
index b05c6d6f99d0..406c0814eb6e 100644
--- a/arch/arm/mach-tango/pm.c
+++ b/arch/arm/mach-tango/pm.c
@@ -5,7 +5,7 @@
 
 static int tango_pm_powerdown(unsigned long arg)
 {
-        tango_suspend(virt_to_phys(cpu_resume));
+        tango_suspend(__pa_symbol(cpu_resume));
 
         return -EIO; /* tango_suspend has failed */
 }
diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c
index 6fd9db54887e..dc558892753c 100644
--- a/arch/arm/mach-tegra/reset.c
+++ b/arch/arm/mach-tegra/reset.c
@@ -94,14 +94,14 @@ void __init tegra_cpu_reset_handler_init(void)
         __tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] =
                 *((u32 *)cpu_possible_mask);
         __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] =
-                virt_to_phys((void *)secondary_startup);
+                __pa_symbol((void *)secondary_startup);
 #endif
 
 #ifdef CONFIG_PM_SLEEP
         __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP1] =
                 TEGRA_IRAM_LPx_RESUME_AREA;
         __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP2] =
-                virt_to_phys((void *)tegra_resume);
+                __pa_symbol((void *)tegra_resume);
 #endif
 
         tegra_cpu_reset_handler_enable();
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index e0ee139fdebf..9b124c22035f 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -79,7 +79,7 @@ static int ux500_boot_secondary(unsigned int cpu, struct task_struct *idle)
          * backup ram register at offset 0x1FF0, which is what boot rom code
          * is waiting for. This will wake up the secondary core from WFE.
          */
-        writel(virt_to_phys(secondary_startup),
+        writel(__pa_symbol(secondary_startup),
                backupram + UX500_CPU1_JUMPADDR_OFFSET);
         writel(0xA1FEED01,
                backupram + UX500_CPU1_WAKEMAGIC_OFFSET);
diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c
index 5cedcf572104..ee2a0faafaa1 100644
--- a/arch/arm/mach-vexpress/dcscb.c
+++ b/arch/arm/mach-vexpress/dcscb.c
@@ -166,7 +166,7 @@ static int __init dcscb_init(void)
          * Future entries into the kernel can now go
          * through the cluster entry vectors.
          */
-        vexpress_flags_set(virt_to_phys(mcpm_entry_point));
+        vexpress_flags_set(__pa_symbol(mcpm_entry_point));
 
         return 0;
 }
diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c
index 98e29dee91e8..742499bac6d0 100644
--- a/arch/arm/mach-vexpress/platsmp.c
+++ b/arch/arm/mach-vexpress/platsmp.c
@@ -79,7 +79,7 @@ static void __init vexpress_smp_dt_prepare_cpus(unsigned int max_cpus)
          * until it receives a soft interrupt, and then the
          * secondary CPU branches to this address.
          */
-        vexpress_flags_set(virt_to_phys(versatile_secondary_startup));
+        vexpress_flags_set(__pa_symbol(versatile_secondary_startup));
 }
 
 const struct smp_operations vexpress_smp_dt_ops __initconst = {
diff --git a/arch/arm/mach-vexpress/tc2_pm.c b/arch/arm/mach-vexpress/tc2_pm.c
index 1aa4ccece69f..9b5f3c427086 100644
--- a/arch/arm/mach-vexpress/tc2_pm.c
+++ b/arch/arm/mach-vexpress/tc2_pm.c
@@ -54,7 +54,7 @@ static int tc2_pm_cpu_powerup(unsigned int cpu, unsigned int cluster)
         if (cluster >= TC2_CLUSTERS || cpu >= tc2_nr_cpus[cluster])
                 return -EINVAL;
         ve_spc_set_resume_addr(cluster, cpu,
-                               virt_to_phys(mcpm_entry_point));
+                               __pa_symbol(mcpm_entry_point));
         ve_spc_cpu_wakeup_irq(cluster, cpu, true);
         return 0;
 }
@@ -159,7 +159,7 @@ static int tc2_pm_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
 
 static void tc2_pm_cpu_suspend_prepare(unsigned int cpu, unsigned int cluster)
 {
-        ve_spc_set_resume_addr(cluster, cpu, virt_to_phys(mcpm_entry_point));
+        ve_spc_set_resume_addr(cluster, cpu, __pa_symbol(mcpm_entry_point));
 }
 
 static void tc2_pm_cpu_is_up(unsigned int cpu, unsigned int cluster)
diff --git a/arch/arm/mach-zx/platsmp.c b/arch/arm/mach-zx/platsmp.c
index 0297f92084e0..afb9a82dedc3 100644
--- a/arch/arm/mach-zx/platsmp.c
+++ b/arch/arm/mach-zx/platsmp.c
@@ -76,7 +76,7 @@ void __init zx_smp_prepare_cpus(unsigned int max_cpus)
          * until it receives a soft interrupt, and then the
          * secondary CPU branches to this address.
          */
-        __raw_writel(virt_to_phys(zx_secondary_startup),
+        __raw_writel(__pa_symbol(zx_secondary_startup),
                      aonsysctrl_base + AON_SYS_CTRL_RESERVED1);
 
         iounmap(aonsysctrl_base);
@@ -94,7 +94,7 @@ void __init zx_smp_prepare_cpus(unsigned int max_cpus)
 
         /* Map the first 4 KB IRAM for suspend usage */
         sys_iram = __arm_ioremap_exec(ZX_IRAM_BASE, PAGE_SIZE, false);
-        zx_secondary_startup_pa = virt_to_phys(zx_secondary_startup);
+        zx_secondary_startup_pa = __pa_symbol(zx_secondary_startup);
         fncpy(sys_iram, &zx_resume_jump, zx_suspend_iram_sz);
 }
 
diff --git a/arch/arm/mach-zynq/platsmp.c b/arch/arm/mach-zynq/platsmp.c
index 7cd9865bdeb7..caa6d5fe9078 100644
--- a/arch/arm/mach-zynq/platsmp.c
+++ b/arch/arm/mach-zynq/platsmp.c
@@ -89,7 +89,7 @@ EXPORT_SYMBOL(zynq_cpun_start);
 
 static int zynq_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
-        return zynq_cpun_start(virt_to_phys(secondary_startup), cpu);
+        return zynq_cpun_start(__pa_symbol(secondary_startup), cpu);
 }
 
 /*
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 35e3a56e5d86..c6c4c9c8824b 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -29,6 +29,7 @@ config CPU_ARM720T
         select CPU_COPY_V4WT if MMU
         select CPU_CP15_MMU
         select CPU_PABRT_LEGACY
+        select CPU_THUMB_CAPABLE
         select CPU_TLB_V4WT if MMU
         help
           A 32-bit RISC processor with 8kByte Cache, Write Buffer and
@@ -46,6 +47,7 @@ config CPU_ARM740T
         select CPU_CACHE_V4
         select CPU_CP15_MPU
         select CPU_PABRT_LEGACY
+        select CPU_THUMB_CAPABLE
         help
           A 32-bit RISC processor with 8KB cache or 4KB variants,
           write buffer and MPU(Protection Unit) built around
@@ -79,6 +81,7 @@ config CPU_ARM920T
         select CPU_COPY_V4WB if MMU
         select CPU_CP15_MMU
         select CPU_PABRT_LEGACY
+        select CPU_THUMB_CAPABLE
         select CPU_TLB_V4WBI if MMU
         help
           The ARM920T is licensed to be produced by numerous vendors,
@@ -97,6 +100,7 @@ config CPU_ARM922T
         select CPU_COPY_V4WB if MMU
         select CPU_CP15_MMU
         select CPU_PABRT_LEGACY
+        select CPU_THUMB_CAPABLE
         select CPU_TLB_V4WBI if MMU
         help
           The ARM922T is a version of the ARM920T, but with smaller
@@ -116,6 +120,7 @@ config CPU_ARM925T
         select CPU_COPY_V4WB if MMU
         select CPU_CP15_MMU
         select CPU_PABRT_LEGACY
+        select CPU_THUMB_CAPABLE
         select CPU_TLB_V4WBI if MMU
         help
           The ARM925T is a mix between the ARM920T and ARM926T, but with
@@ -134,6 +139,7 @@ config CPU_ARM926T
         select CPU_COPY_V4WB if MMU
         select CPU_CP15_MMU
         select CPU_PABRT_LEGACY
+        select CPU_THUMB_CAPABLE
         select CPU_TLB_V4WBI if MMU
         help
           This is a variant of the ARM920.  It has slightly different
@@ -170,6 +176,7 @@ config CPU_ARM940T
         select CPU_CACHE_VIVT
         select CPU_CP15_MPU
         select CPU_PABRT_LEGACY
+        select CPU_THUMB_CAPABLE
         help
           ARM940T is a member of the ARM9TDMI family of general-
           purpose microprocessors with MPU and separate 4KB
@@ -188,6 +195,7 @@ config CPU_ARM946E
         select CPU_CACHE_VIVT
         select CPU_CP15_MPU
         select CPU_PABRT_LEGACY
+        select CPU_THUMB_CAPABLE
         help
           ARM946E-S is a member of the ARM9E-S family of high-
           performance, 32-bit system-on-chip processor solutions.
@@ -206,6 +214,7 @@ config CPU_ARM1020
         select CPU_COPY_V4WB if MMU
         select CPU_CP15_MMU
         select CPU_PABRT_LEGACY
+        select CPU_THUMB_CAPABLE
         select CPU_TLB_V4WBI if MMU
         help
           The ARM1020 is the 32K cached version of the ARM10 processor,
@@ -225,6 +234,7 @@ config CPU_ARM1020E
         select CPU_COPY_V4WB if MMU
         select CPU_CP15_MMU
         select CPU_PABRT_LEGACY
+        select CPU_THUMB_CAPABLE
         select CPU_TLB_V4WBI if MMU
 
 # ARM1022E
@@ -236,6 +246,7 @@ config CPU_ARM1022
         select CPU_COPY_V4WB if MMU # can probably do better
         select CPU_CP15_MMU
         select CPU_PABRT_LEGACY
+        select CPU_THUMB_CAPABLE
         select CPU_TLB_V4WBI if MMU
         help
           The ARM1022E is an implementation of the ARMv5TE architecture
@@ -254,6 +265,7 @@ config CPU_ARM1026
         select CPU_COPY_V4WB if MMU # can probably do better
         select CPU_CP15_MMU
         select CPU_PABRT_LEGACY
+        select CPU_THUMB_CAPABLE
         select CPU_TLB_V4WBI if MMU
         help
           The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
@@ -302,6 +314,7 @@ config CPU_XSCALE
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
         select CPU_PABRT_LEGACY
+        select CPU_THUMB_CAPABLE
         select CPU_TLB_V4WBI if MMU
 
 # XScale Core Version 3
@@ -312,6 +325,7 @@ config CPU_XSC3
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
         select CPU_PABRT_LEGACY
+        select CPU_THUMB_CAPABLE
         select CPU_TLB_V4WBI if MMU
         select IO_36
 
@@ -324,6 +338,7 @@ config CPU_MOHAWK
         select CPU_COPY_V4WB if MMU
         select CPU_CP15_MMU
         select CPU_PABRT_LEGACY
+        select CPU_THUMB_CAPABLE
         select CPU_TLB_V4WBI if MMU
 
 # Feroceon
@@ -335,6 +350,7 @@ config CPU_FEROCEON
         select CPU_COPY_FEROCEON if MMU
         select CPU_CP15_MMU
         select CPU_PABRT_LEGACY
+        select CPU_THUMB_CAPABLE
         select CPU_TLB_FEROCEON if MMU
 
 config CPU_FEROCEON_OLD_ID
@@ -367,6 +383,7 @@ config CPU_V6
         select CPU_CP15_MMU
         select CPU_HAS_ASID if MMU
         select CPU_PABRT_V6
+        select CPU_THUMB_CAPABLE
         select CPU_TLB_V6 if MMU
 
 # ARMv6k
@@ -381,6 +398,7 @@ config CPU_V6K
         select CPU_CP15_MMU
         select CPU_HAS_ASID if MMU
         select CPU_PABRT_V6
+        select CPU_THUMB_CAPABLE
         select CPU_TLB_V6 if MMU
 
 # ARMv7
@@ -396,6 +414,7 @@ config CPU_V7
         select CPU_CP15_MPU if !MMU
         select CPU_HAS_ASID if MMU
         select CPU_PABRT_V7
+        select CPU_THUMB_CAPABLE
         select CPU_TLB_V7 if MMU
 
 # ARMv7M
@@ -410,11 +429,17 @@ config CPU_V7M
 
 config CPU_THUMBONLY
         bool
+        select CPU_THUMB_CAPABLE
         # There are no CPUs available with MMU that don't implement an ARM ISA:
         depends on !MMU
         help
           Select this if your CPU doesn't support the 32 bit ARM instructions.
 
+config CPU_THUMB_CAPABLE
+        bool
+        help
+          Select this if your CPU can support Thumb mode.
+
 # Figure out what processor architecture version we should be using.
 # This defines the compiler instruction set which depends on the machine type.
 config CPU_32v3
@@ -655,11 +680,7 @@ config ARCH_DMA_ADDR_T_64BIT
 
 config ARM_THUMB
         bool "Support Thumb user binaries" if !CPU_THUMBONLY
-        depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || \
-                CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || \
-                CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
-                CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || \
-                CPU_V7 || CPU_FEROCEON || CPU_V7M
+        depends on CPU_THUMB_CAPABLE
         default y
         help
           Say Y if you want to include kernel support for running user space
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index e8698241ece9..b3dea80715b4 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -14,6 +14,7 @@ endif
 
 obj-$(CONFIG_ARM_PTDUMP)        += dump.o
 obj-$(CONFIG_MODULES)           += proc-syms.o
+obj-$(CONFIG_DEBUG_VIRTUAL)     += physaddr.o
 
 obj-$(CONFIG_ALIGNMENT_TRAP)    += alignment.o
 obj-$(CONFIG_HIGHMEM)           += highmem.o
diff --git a/arch/arm/mm/cache-uniphier.c b/arch/arm/mm/cache-uniphier.c
index dfe97b409916..f57b080b6fd4 100644
--- a/arch/arm/mm/cache-uniphier.c
+++ b/arch/arm/mm/cache-uniphier.c
@@ -15,6 +15,7 @@
 
 #define pr_fmt(fmt)             "uniphier: " fmt
 
+#include <linux/bitops.h>
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/log2.h>
@@ -71,8 +72,7 @@
  * @ctrl_base: virtual base address of control registers
  * @rev_base: virtual base address of revision registers
  * @op_base: virtual base address of operation registers
- * @way_present_mask: each bit specifies if the way is present
- * @way_locked_mask: each bit specifies if the way is locked
+ * @way_mask: each bit specifies if the way is present
  * @nsets: number of associativity sets
  * @line_size: line size in bytes
  * @range_op_max_size: max size that can be handled by a single range operation
@@ -83,8 +83,7 @@ struct uniphier_cache_data {
         void __iomem *rev_base;
         void __iomem *op_base;
         void __iomem *way_ctrl_base;
-        u32 way_present_mask;
-        u32 way_locked_mask;
+        u32 way_mask;
         u32 nsets;
         u32 line_size;
         u32 range_op_max_size;
@@ -234,17 +233,13 @@ static void __uniphier_cache_enable(struct uniphier_cache_data *data, bool on)
         writel_relaxed(val, data->ctrl_base + UNIPHIER_SSCC);
 }
 
-static void __init __uniphier_cache_set_locked_ways(
-                                        struct uniphier_cache_data *data,
-                                        u32 way_mask)
+static void __init __uniphier_cache_set_active_ways(
+                                        struct uniphier_cache_data *data)
 {
         unsigned int cpu;
 
-        data->way_locked_mask = way_mask & data->way_present_mask;
-
         for_each_possible_cpu(cpu)
-                writel_relaxed(~data->way_locked_mask & data->way_present_mask,
-                               data->way_ctrl_base + 4 * cpu);
+                writel_relaxed(data->way_mask, data->way_ctrl_base + 4 * cpu);
 }
 
 static void uniphier_cache_maint_range(unsigned long start, unsigned long end,
@@ -307,7 +302,7 @@ static void __init uniphier_cache_enable(void)
 
         list_for_each_entry(data, &uniphier_cache_list, list) {
                 __uniphier_cache_enable(data, true);
-                __uniphier_cache_set_locked_ways(data, 0);
+                __uniphier_cache_set_active_ways(data);
         }
 }
 
@@ -382,8 +377,8 @@ static int __init __uniphier_cache_init(struct device_node *np,
                 goto err;
         }
 
-        data->way_present_mask =
-                ((u32)1 << cache_size / data->nsets / data->line_size) - 1;
+        data->way_mask = GENMASK(cache_size / data->nsets / data->line_size - 1,
+                                 0);
 
         data->ctrl_base = of_iomap(np, 0);
         if (!data->ctrl_base) {
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index e309a5e2c935..63eabb06f9f1 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -870,6 +870,9 @@ static int __arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
                                       vma->vm_end - vma->vm_start,
                                       vma->vm_page_prot);
         }
+#else
+        ret = vm_iomap_memory(vma, vma->vm_start,
+                              (vma->vm_end - vma->vm_start));
 #endif  /* CONFIG_MMU */
 
         return ret;
diff --git a/arch/arm/mm/dump.c b/arch/arm/mm/dump.c
index 9fe8e241335c..21192d6eda40 100644
--- a/arch/arm/mm/dump.c
+++ b/arch/arm/mm/dump.c
@@ -18,6 +18,7 @@
 #include <linux/seq_file.h>
 
 #include <asm/fixmap.h>
+#include <asm/memory.h>
 #include <asm/pgtable.h>
 
 struct addr_marker {
@@ -31,8 +32,8 @@ static struct addr_marker address_markers[] = {
         { 0,                    "vmalloc() Area" },
         { VMALLOC_END,          "vmalloc() End" },
         { FIXADDR_START,        "Fixmap Area" },
-        { CONFIG_VECTORS_BASE,  "Vectors" },
-        { CONFIG_VECTORS_BASE + PAGE_SIZE * 2, "Vectors End" },
+        { VECTORS_BASE, "Vectors" },
+        { VECTORS_BASE + PAGE_SIZE * 2, "Vectors End" },
         { -1,                   NULL },
 };
 
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 3cced8455727..f1e6190aa7ea 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -327,6 +327,12 @@ void flush_dcache_page(struct page *page)
         if (page == ZERO_PAGE(0))
                 return;
 
+        if (!cache_ops_need_broadcast() && cache_is_vipt_nonaliasing()) {
+                if (test_bit(PG_dcache_clean, &page->flags))
+                        clear_bit(PG_dcache_clean, &page->flags);
+                return;
+        }
+
         mapping = page_mapping(page);
 
         if (!cache_ops_need_broadcast() &&
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 4be0bee4c357..bf4d3bc41a7a 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -27,6 +27,7 @@
 #include <asm/cp15.h>
 #include <asm/mach-types.h>
 #include <asm/memblock.h>
+#include <asm/memory.h>
 #include <asm/prom.h>
 #include <asm/sections.h>
 #include <asm/setup.h>
@@ -227,41 +228,59 @@ phys_addr_t __init arm_memblock_steal(phys_addr_t size, phys_addr_t align)
         return phys;
 }
 
-void __init arm_memblock_init(const struct machine_desc *mdesc)
+static void __init arm_initrd_init(void)
 {
-        /* Register the kernel text, kernel data and initrd with memblock. */
-#ifdef CONFIG_XIP_KERNEL
-        memblock_reserve(__pa(_sdata), _end - _sdata);
-#else
-        memblock_reserve(__pa(_stext), _end - _stext);
-#endif
 #ifdef CONFIG_BLK_DEV_INITRD
+        phys_addr_t start;
+        unsigned long size;
+
         /* FDT scan will populate initrd_start */
         if (initrd_start && !phys_initrd_size) {
                 phys_initrd_start = __virt_to_phys(initrd_start);
                 phys_initrd_size = initrd_end - initrd_start;
         }
+
         initrd_start = initrd_end = 0;
-        if (phys_initrd_size &&
-            !memblock_is_region_memory(phys_initrd_start, phys_initrd_size)) {
+
+        if (!phys_initrd_size)
+                return;
+
+        /*
+         * Round the memory region to page boundaries as per free_initrd_mem()
+         * This allows us to detect whether the pages overlapping the initrd
+         * are in use, but more importantly, reserves the entire set of pages
+         * as we don't want these pages allocated for other purposes.
+         */
+        start = round_down(phys_initrd_start, PAGE_SIZE);
+        size = phys_initrd_size + (phys_initrd_start - start);
+        size = round_up(size, PAGE_SIZE);
+
+        if (!memblock_is_region_memory(start, size)) {
                 pr_err("INITRD: 0x%08llx+0x%08lx is not a memory region - disabling initrd\n",
-                       (u64)phys_initrd_start, phys_initrd_size);
-                phys_initrd_start = phys_initrd_size = 0;
+                       (u64)start, size);
+                return;
         }
-        if (phys_initrd_size &&
-            memblock_is_region_reserved(phys_initrd_start, phys_initrd_size)) {
+
+        if (memblock_is_region_reserved(start, size)) {
                 pr_err("INITRD: 0x%08llx+0x%08lx overlaps in-use memory region - disabling initrd\n",
-                       (u64)phys_initrd_start, phys_initrd_size);
-                phys_initrd_start = phys_initrd_size = 0;
+                       (u64)start, size);
+                return;
         }
-        if (phys_initrd_size) {
-                memblock_reserve(phys_initrd_start, phys_initrd_size);
 
-                /* Now convert initrd to virtual addresses */
-                initrd_start = __phys_to_virt(phys_initrd_start);
-                initrd_end = initrd_start + phys_initrd_size;
-        }
+        memblock_reserve(start, size);
+
+        /* Now convert initrd to virtual addresses */
+        initrd_start = __phys_to_virt(phys_initrd_start);
+        initrd_end = initrd_start + phys_initrd_size;
 #endif
+}
+
+void __init arm_memblock_init(const struct machine_desc *mdesc)
+{
+        /* Register the kernel text, kernel data and initrd with memblock. */
+        memblock_reserve(__pa(KERNEL_START), KERNEL_END - KERNEL_START);
+
+        arm_initrd_init();
 
         arm_mm_memblock_reserve();
 
@@ -521,8 +540,7 @@ void __init mem_init(void)
                         "      .data : 0x%p" " - 0x%p" "   (%4td kB)\n"
                         "       .bss : 0x%p" " - 0x%p" "   (%4td kB)\n",
 
-                        MLK(UL(CONFIG_VECTORS_BASE), UL(CONFIG_VECTORS_BASE) +
-                                (PAGE_SIZE)),
+                        MLK(VECTORS_BASE, VECTORS_BASE + PAGE_SIZE),
 #ifdef CONFIG_HAVE_TCM
                         MLK(DTCM_OFFSET, (unsigned long) dtcm_end),
                         MLK(ITCM_OFFSET, (unsigned long) itcm_end),
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 4001dd15818d..4e016d7f37b3 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -1152,13 +1152,12 @@ early_param("vmalloc", early_vmalloc);
 
 phys_addr_t arm_lowmem_limit __initdata = 0;
 
-void __init sanity_check_meminfo(void)
+void __init adjust_lowmem_bounds(void)
 {
         phys_addr_t memblock_limit = 0;
-        int highmem = 0;
         u64 vmalloc_limit;
         struct memblock_region *reg;
-        bool should_use_highmem = false;
+        phys_addr_t lowmem_limit = 0;
 
         /*
          * Let's use our own (unoptimized) equivalent of __pa() that is
@@ -1172,43 +1171,18 @@ void __init sanity_check_meminfo(void)
         for_each_memblock(memory, reg) {
                 phys_addr_t block_start = reg->base;
                 phys_addr_t block_end = reg->base + reg->size;
-                phys_addr_t size_limit = reg->size;
 
-                if (reg->base >= vmalloc_limit)
-                        highmem = 1;
-                else
-                        size_limit = vmalloc_limit - reg->base;
-
-
-                if (!IS_ENABLED(CONFIG_HIGHMEM) || cache_is_vipt_aliasing()) {
-
-                        if (highmem) {
-                                pr_notice("Ignoring RAM at %pa-%pa (!CONFIG_HIGHMEM)\n",
-                                          &block_start, &block_end);
-                                memblock_remove(reg->base, reg->size);
-                                should_use_highmem = true;
-                                continue;
-                        }
-
-                        if (reg->size > size_limit) {
-                                phys_addr_t overlap_size = reg->size - size_limit;
-
-                                pr_notice("Truncating RAM at %pa-%pa",
-                                          &block_start, &block_end);
-                                block_end = vmalloc_limit;
-                                pr_cont(" to -%pa", &block_end);
-                                memblock_remove(vmalloc_limit, overlap_size);
-                                should_use_highmem = true;
-                        }
-                }
-
-                if (!highmem) {
-                        if (block_end > arm_lowmem_limit) {
-                                if (reg->size > size_limit)
-                                        arm_lowmem_limit = vmalloc_limit;
-                                else
-                                        arm_lowmem_limit = block_end;
-                        }
+                if (reg->base < vmalloc_limit) {
+                        if (block_end > lowmem_limit)
+                                /*
+                                 * Compare as u64 to ensure vmalloc_limit does
+                                 * not get truncated. block_end should always
+                                 * fit in phys_addr_t so there should be no
+                                 * issue with assignment.
+                                 */
+                                lowmem_limit = min_t(u64,
+                                                         vmalloc_limit,
+                                                         block_end);
 
                         /*
                          * Find the first non-pmd-aligned page, and point
@@ -1227,14 +1201,13 @@ void __init sanity_check_meminfo(void)
                                 if (!IS_ALIGNED(block_start, PMD_SIZE))
                                         memblock_limit = block_start;
                                 else if (!IS_ALIGNED(block_end, PMD_SIZE))
-                                        memblock_limit = arm_lowmem_limit;
+                                        memblock_limit = lowmem_limit;
                         }
 
                 }
         }
 
-        if (should_use_highmem)
-                pr_notice("Consider using a HIGHMEM enabled kernel.\n");
+        arm_lowmem_limit = lowmem_limit;
 
         high_memory = __va(arm_lowmem_limit - 1) + 1;
 
@@ -1248,6 +1221,18 @@ void __init sanity_check_meminfo(void)
         if (!memblock_limit)
                 memblock_limit = arm_lowmem_limit;
 
+        if (!IS_ENABLED(CONFIG_HIGHMEM) || cache_is_vipt_aliasing()) {
+                if (memblock_end_of_DRAM() > arm_lowmem_limit) {
+                        phys_addr_t end = memblock_end_of_DRAM();
+
+                        pr_notice("Ignoring RAM at %pa-%pa\n",
+                                  &memblock_limit, &end);
+                        pr_notice("Consider using a HIGHMEM enabled kernel.\n");
+
+                        memblock_remove(memblock_limit, end - memblock_limit);
+                }
+        }
+
         memblock_set_current_limit(memblock_limit);
 }
 
@@ -1437,11 +1422,7 @@ static void __init kmap_init(void)
 static void __init map_lowmem(void)
 {
         struct memblock_region *reg;
-#ifdef CONFIG_XIP_KERNEL
-        phys_addr_t kernel_x_start = round_down(__pa(_sdata), SECTION_SIZE);
-#else
-        phys_addr_t kernel_x_start = round_down(__pa(_stext), SECTION_SIZE);
-#endif
+        phys_addr_t kernel_x_start = round_down(__pa(KERNEL_START), SECTION_SIZE);
         phys_addr_t kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE);
 
         /* Map all the lowmem memory banks. */
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index 2740967727e2..3b5c7aaf9c76 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -11,6 +11,7 @@
 #include <linux/kernel.h>
 
 #include <asm/cacheflush.h>
+#include <asm/cp15.h>
 #include <asm/sections.h>
 #include <asm/page.h>
 #include <asm/setup.h>
@@ -22,6 +23,8 @@
 
 #include "mm.h"
 
+unsigned long vectors_base;
+
 #ifdef CONFIG_ARM_MPU
 struct mpu_rgn_info mpu_rgn_info;
 
@@ -85,7 +88,7 @@ static unsigned long irbar_read(void)
 }
 
 /* MPU initialisation functions */
-void __init sanity_check_meminfo_mpu(void)
+void __init adjust_lowmem_bounds_mpu(void)
 {
         phys_addr_t phys_offset = PHYS_OFFSET;
         phys_addr_t aligned_region_size, specified_mem_size, rounded_mem_size;
@@ -274,19 +277,64 @@ void __init mpu_setup(void)
         }
 }
 #else
-static void sanity_check_meminfo_mpu(void) {}
+static void adjust_lowmem_bounds_mpu(void) {}
 static void __init mpu_setup(void) {}
 #endif /* CONFIG_ARM_MPU */
 
+#ifdef CONFIG_CPU_CP15
+#ifdef CONFIG_CPU_HIGH_VECTOR
+static unsigned long __init setup_vectors_base(void)
+{
+        unsigned long reg = get_cr();
+
+        set_cr(reg | CR_V);
+        return 0xffff0000;
+}
+#else /* CONFIG_CPU_HIGH_VECTOR */
+/* Write exception base address to VBAR */
+static inline void set_vbar(unsigned long val)
+{
+        asm("mcr p15, 0, %0, c12, c0, 0" : : "r" (val) : "cc");
+}
+
+/*
+ * Security extensions, bits[7:4], permitted values,
+ * 0b0000 - not implemented, 0b0001/0b0010 - implemented
+ */
+static inline bool security_extensions_enabled(void)
+{
+        return !!cpuid_feature_extract(CPUID_EXT_PFR1, 4);
+}
+
+static unsigned long __init setup_vectors_base(void)
+{
+        unsigned long base = 0, reg = get_cr();
+
+        set_cr(reg & ~CR_V);
+        if (security_extensions_enabled()) {
+                if (IS_ENABLED(CONFIG_REMAP_VECTORS_TO_RAM))
+                        base = CONFIG_DRAM_BASE;
+                set_vbar(base);
+        } else if (IS_ENABLED(CONFIG_REMAP_VECTORS_TO_RAM)) {
+                if (CONFIG_DRAM_BASE != 0)
+                        pr_err("Security extensions not enabled, vectors cannot be remapped to RAM, vectors base will be 0x00000000\n");
+        }
+
+        return base;
+}
+#endif /* CONFIG_CPU_HIGH_VECTOR */
+#endif /* CONFIG_CPU_CP15 */
+
 void __init arm_mm_memblock_reserve(void)
 {
 #ifndef CONFIG_CPU_V7M
+        vectors_base = IS_ENABLED(CONFIG_CPU_CP15) ? setup_vectors_base() : 0;
         /*
          * Register the exception vector page.
          * some architectures which the DRAM is the exception vector to trap,
          * alloc_page breaks with error, although it is not NULL, but "0."
          */
-        memblock_reserve(CONFIG_VECTORS_BASE, 2 * PAGE_SIZE);
+        memblock_reserve(vectors_base, 2 * PAGE_SIZE);
 #else /* ifndef CONFIG_CPU_V7M */
         /*
          * There is no dedicated vector page on V7-M. So nothing needs to be
@@ -295,10 +343,10 @@ void __init arm_mm_memblock_reserve(void)
 #endif
 }
 
-void __init sanity_check_meminfo(void)
+void __init adjust_lowmem_bounds(void)
 {
         phys_addr_t end;
-        sanity_check_meminfo_mpu();
+        adjust_lowmem_bounds_mpu();
         end = memblock_end_of_DRAM();
         high_memory = __va(end - 1) + 1;
         memblock_set_current_limit(end);
@@ -310,7 +358,7 @@ void __init sanity_check_meminfo(void)
  */
 void __init paging_init(const struct machine_desc *mdesc)
 {
-        early_trap_init((void *)CONFIG_VECTORS_BASE);
+        early_trap_init((void *)vectors_base);
         mpu_setup();
         bootmem_init();
 }
diff --git a/arch/arm/mm/physaddr.c b/arch/arm/mm/physaddr.c
new file mode 100644
index 000000000000..02e60f495608
--- /dev/null
+++ b/arch/arm/mm/physaddr.c
@@ -0,0 +1,57 @@
+#include <linux/bug.h>
+#include <linux/export.h>
+#include <linux/types.h>
+#include <linux/mmdebug.h>
+#include <linux/mm.h>
+
+#include <asm/sections.h>
+#include <asm/memory.h>
+#include <asm/fixmap.h>
+#include <asm/dma.h>
+
+#include "mm.h"
+
+static inline bool __virt_addr_valid(unsigned long x)
+{
+        /*
+         * high_memory does not get immediately defined, and there
+         * are early callers of __pa() against PAGE_OFFSET
+         */
+        if (!high_memory && x >= PAGE_OFFSET)
+                return true;
+
+        if (high_memory && x >= PAGE_OFFSET && x < (unsigned long)high_memory)
+                return true;
+
+        /*
+         * MAX_DMA_ADDRESS is a virtual address that may not correspond to an
+         * actual physical address. Enough code relies on __pa(MAX_DMA_ADDRESS)
+         * that we just need to work around it and always return true.
+         */
+        if (x == MAX_DMA_ADDRESS)
+                return true;
+
+        return false;
+}
+
+phys_addr_t __virt_to_phys(unsigned long x)
+{
+        WARN(!__virt_addr_valid(x),
+             "virt_to_phys used for non-linear address: %pK (%pS)\n",
+             (void *)x, (void *)x);
+
+        return __virt_to_phys_nodebug(x);
+}
+EXPORT_SYMBOL(__virt_to_phys);
+
+phys_addr_t __phys_addr_symbol(unsigned long x)
+{
+        /* This is bounds checking against the kernel image only.
+         * __pa_symbol should only be used on kernel symbol addresses.
+         */
+        VIRTUAL_BUG_ON(x < (unsigned long)KERNEL_START ||
+                       x > (unsigned long)KERNEL_END);
+
+        return __pa_symbol_nodebug(x);
+}
+EXPORT_SYMBOL(__phys_addr_symbol);
diff --git a/drivers/mtd/devices/lart.c b/drivers/mtd/devices/lart.c
index 82bd00af5cc3..268aae45b514 100644
--- a/drivers/mtd/devices/lart.c
+++ b/drivers/mtd/devices/lart.c
@@ -75,18 +75,18 @@ static char module_name[] = "lart";
 
 /* blob */
 #define NUM_BLOB_BLOCKS         FLASH_NUMBLOCKS_16m_PARAM
-#define BLOB_START                      0x00000000
-#define BLOB_LEN                        (NUM_BLOB_BLOCKS * FLASH_BLOCKSIZE_PARAM)
+#define PART_BLOB_START         0x00000000
+#define PART_BLOB_LEN           (NUM_BLOB_BLOCKS * FLASH_BLOCKSIZE_PARAM)
 
 /* kernel */
 #define NUM_KERNEL_BLOCKS       7
-#define KERNEL_START            (BLOB_START + BLOB_LEN)
-#define KERNEL_LEN                      (NUM_KERNEL_BLOCKS * FLASH_BLOCKSIZE_MAIN)
+#define PART_KERNEL_START       (PART_BLOB_START + PART_BLOB_LEN)
+#define PART_KERNEL_LEN         (NUM_KERNEL_BLOCKS * FLASH_BLOCKSIZE_MAIN)
 
 /* initial ramdisk */
 #define NUM_INITRD_BLOCKS       24
-#define INITRD_START            (KERNEL_START + KERNEL_LEN)
-#define INITRD_LEN                      (NUM_INITRD_BLOCKS * FLASH_BLOCKSIZE_MAIN)
+#define PART_INITRD_START       (PART_KERNEL_START + PART_KERNEL_LEN)
+#define PART_INITRD_LEN         (NUM_INITRD_BLOCKS * FLASH_BLOCKSIZE_MAIN)
 
 /*
  * See section 4.0 in "3 Volt Fast Boot Block Flash Memory" Intel Datasheet
@@ -587,20 +587,20 @@ static struct mtd_partition lart_partitions[] = {
         /* blob */
         {
                 .name   = "blob",
-                .offset = BLOB_START,
-                .size   = BLOB_LEN,
+                .offset = PART_BLOB_START,
+                .size   = PART_BLOB_LEN,
         },
         /* kernel */
         {
                 .name   = "kernel",
-                .offset = KERNEL_START,         /* MTDPART_OFS_APPEND */
-                .size   = KERNEL_LEN,
+                .offset = PART_KERNEL_START,    /* MTDPART_OFS_APPEND */
+                .size   = PART_KERNEL_LEN,
         },
         /* initial ramdisk / file system */
         {
                 .name   = "file system",
-                .offset = INITRD_START,         /* MTDPART_OFS_APPEND */
-                .size   = INITRD_LEN,           /* MTDPART_SIZ_FULL */
+                .offset = PART_INITRD_START,    /* MTDPART_OFS_APPEND */
+                .size   = PART_INITRD_LEN,      /* MTDPART_SIZ_FULL */
         }
 };
 #define NUM_PARTITIONS ARRAY_SIZE(lart_partitions)