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authorArchit Taneja <architt@codeaurora.org>2017-07-12 05:39:55 -0400
committerRob Clark <robdclark@gmail.com>2017-08-01 16:26:01 -0400
commitd4cea38ebb4de90913085391ce4febde1a4ba9aa (patch)
treeb1ccac246dcef4de7063bb1548e5929fa42bd1e8
parentaf1f5f12c21bd9dc08f578d86adc192eec4eb28a (diff)
drm/msm/dsi: Calculate link clock rates with updated dsi->lanes
After the commit mentioned below, we start computing the byte and pixel clocks (dsi_calc_clk_rate) in the DSI bridge's mode_set() op. The calculation involves the number of DSI lanes being used by the downstream bridge/panel. If the downstream bridge/panel tries to change the number of DSI lanes (as done in the ADV7533 driver) in its mode_set() op, then our DSI host driver will not have the correct number of lanes when computing byte/pixel clocks. Fix this by delaying the clock rate calculation in the DSI bridge enable path. In particular, compute the clock rates in msm_dsi_host_get_phy_clk_req(). This fixes the DSI host error interrupts seen when we try to switch between modes that require different number of lanes (4 to 3 lanes, or vice versa) on db410c. The error interrupts occur since the byte/pixel clock rates aren't according to what the DSI video mode timing engine expects. Fixes: b62aa70a98c5 ("drm/msm/dsi: Move PHY operations out of host") Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
-rw-r--r--drivers/gpu/drm/msm/dsi/dsi_host.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 9e9c5696bc03..c7b612c3d771 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -2137,6 +2137,13 @@ void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host,
2137 struct msm_dsi_phy_clk_request *clk_req) 2137 struct msm_dsi_phy_clk_request *clk_req)
2138{ 2138{
2139 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2139 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2140 int ret;
2141
2142 ret = dsi_calc_clk_rate(msm_host);
2143 if (ret) {
2144 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret);
2145 return;
2146 }
2140 2147
2141 clk_req->bitclk_rate = msm_host->byte_clk_rate * 8; 2148 clk_req->bitclk_rate = msm_host->byte_clk_rate * 8;
2142 clk_req->escclk_rate = msm_host->esc_clk_rate; 2149 clk_req->escclk_rate = msm_host->esc_clk_rate;
@@ -2280,7 +2287,6 @@ int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
2280 struct drm_display_mode *mode) 2287 struct drm_display_mode *mode)
2281{ 2288{
2282 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2289 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2283 int ret;
2284 2290
2285 if (msm_host->mode) { 2291 if (msm_host->mode) {
2286 drm_mode_destroy(msm_host->dev, msm_host->mode); 2292 drm_mode_destroy(msm_host->dev, msm_host->mode);
@@ -2293,12 +2299,6 @@ int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
2293 return -ENOMEM; 2299 return -ENOMEM;
2294 } 2300 }
2295 2301
2296 ret = dsi_calc_clk_rate(msm_host);
2297 if (ret) {
2298 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret);
2299 return ret;
2300 }
2301
2302 return 0; 2302 return 0;
2303} 2303}
2304 2304