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authorAndy Gross <andy.gross@linaro.org>2016-11-24 01:24:40 -0500
committerAndy Gross <andy.gross@linaro.org>2016-11-24 01:24:40 -0500
commitd4714a5ab2132e899a531bcd267bd13555244927 (patch)
treedb4bbcf3a5128cb14686c976c442ec02a6ed21a2
parent1001354ca34179f3db924eb66672442a173147dc (diff)
parent4c52ffc708c90b2985f941db5490145530e4df69 (diff)
Merge tag 'qcom-dts-for-4.10-1' into dts-for-4.10-2
Qualcomm Device Tree Changes for v4.10 - v2 * Add EBI2 support to MSM8660 * Add SMSC ethernet support to APQ8060 * Add support for display, pstore, iommu, and hdmi to APQ8064 * Add SDHCI node to MSM8974 Hammerhead * Add WP8548 MangOH board support (MDM9615)
Diffstat
-rw-r--r--Documentation/devicetree/bindings/arm/qcom.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/swir.txt12
-rw-r--r--arch/arm/boot/dts/Makefile3
-rw-r--r--arch/arm/boot/dts/qcom-apq8060-dragonboard.dts119
-rw-r--r--arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts77
-rw-r--r--arch/arm/boot/dts/qcom-apq8064-ifc6410.dts74
-rw-r--r--arch/arm/boot/dts/qcom-apq8064.dtsi321
-rw-r--r--arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts281
-rw-r--r--arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi170
-rw-r--r--arch/arm/boot/dts/qcom-mdm9615.dtsi557
-rw-r--r--arch/arm/boot/dts/qcom-msm8660.dtsi17
-rw-r--r--arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts29
12 files changed, 1658 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/arm/qcom.txt b/Documentation/devicetree/bindings/arm/qcom.txt
index 3e24518c6678..43abf4e0a0a5 100644
--- a/Documentation/devicetree/bindings/arm/qcom.txt
+++ b/Documentation/devicetree/bindings/arm/qcom.txt
@@ -22,6 +22,7 @@ The 'SoC' element must be one of the following strings:
22 msm8916 22 msm8916
23 msm8974 23 msm8974
24 msm8996 24 msm8996
25 mdm9615
25 26
26The 'board' element must be one of the following strings: 27The 'board' element must be one of the following strings:
27 28
diff --git a/Documentation/devicetree/bindings/arm/swir.txt b/Documentation/devicetree/bindings/arm/swir.txt
new file mode 100644
index 000000000000..042be73a95d3
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/swir.txt
@@ -0,0 +1,12 @@
1Sierra Wireless Modules device tree bindings
2--------------------------------------------
3
4Supported Modules :
5 - WP8548 : Includes MDM9615 and PM8018 in a module
6
7Sierra Wireless modules shall have the following properties :
8 Required root node property
9 - compatible: "swir,wp8548" for the WP8548 CF3 Module
10
11Board compatible values:
12 - "swir,mangoh-green-wp8548" for the mangOH green board with the WP8548 module
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index befcd2619902..c7f482d634f0 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -620,7 +620,8 @@ dtb-$(CONFIG_ARCH_QCOM) += \
620 qcom-msm8660-surf.dtb \ 620 qcom-msm8660-surf.dtb \
621 qcom-msm8960-cdp.dtb \ 621 qcom-msm8960-cdp.dtb \
622 qcom-msm8974-lge-nexus5-hammerhead.dtb \ 622 qcom-msm8974-lge-nexus5-hammerhead.dtb \
623 qcom-msm8974-sony-xperia-honami.dtb 623 qcom-msm8974-sony-xperia-honami.dtb \
624 qcom-mdm9615-wp8548-mangoh-green.dtb
624dtb-$(CONFIG_ARCH_REALVIEW) += \ 625dtb-$(CONFIG_ARCH_REALVIEW) += \
625 arm-realview-pb1176.dtb \ 626 arm-realview-pb1176.dtb \
626 arm-realview-pb11mp.dtb \ 627 arm-realview-pb11mp.dtb \
diff --git a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts
index 6c0038398ef2..4b8872cc8bf9 100644
--- a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts
+++ b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts
@@ -51,6 +51,29 @@
51 regulator-boot-on; 51 regulator-boot-on;
52 }; 52 };
53 53
54 /* GPIO controlled ethernet power regulator */
55 dragon_veth: xc622a331mrg {
56 compatible = "regulator-fixed";
57 regulator-name = "XC6222A331MR-G";
58 regulator-min-microvolt = <3300000>;
59 regulator-max-microvolt = <3300000>;
60 vin-supply = <&vph>;
61 gpio = <&pm8058_gpio 40 GPIO_ACTIVE_HIGH>;
62 enable-active-high;
63 pinctrl-names = "default";
64 pinctrl-0 = <&dragon_veth_gpios>;
65 regulator-always-on;
66 };
67
68 /* VDDvario fixed regulator */
69 dragon_vario: nds332p {
70 compatible = "regulator-fixed";
71 regulator-name = "NDS332P";
72 regulator-min-microvolt = <1800000>;
73 regulator-max-microvolt = <1800000>;
74 vin-supply = <&pm8058_s3>;
75 };
76
54 /* This is a levelshifter for SDCC5 */ 77 /* This is a levelshifter for SDCC5 */
55 dragon_vio_txb: txb0104rgyr { 78 dragon_vio_txb: txb0104rgyr {
56 compatible = "regulator-fixed"; 79 compatible = "regulator-fixed";
@@ -167,6 +190,36 @@
167 bias-pull-up; 190 bias-pull-up;
168 }; 191 };
169 }; 192 };
193
194 dragon_ebi2_pins: ebi2 {
195 /*
196 * Pins used by EBI2 on the Dragonboard, actually only
197 * CS2 is used by a real peripheral. CS0 is just
198 * routed to a test point.
199 */
200 mux0 {
201 pins =
202 /* "gpio39", CS1A_N this is not good to mux */
203 "gpio40", /* CS2A_N */
204 "gpio134"; /* CS0_N testpoint TP29 */
205 function = "ebi2cs";
206 };
207 mux1 {
208 pins =
209 /* EBI2_ADDR_7 downto EBI2_ADDR_0 address bus */
210 "gpio123", "gpio124", "gpio125", "gpio126",
211 "gpio127", "gpio128", "gpio129", "gpio130",
212 /* EBI2_DATA_15 downto EBI2_DATA_0 data bus */
213 "gpio135", "gpio136", "gpio137", "gpio138",
214 "gpio139", "gpio140", "gpio141", "gpio142",
215 "gpio143", "gpio144", "gpio145", "gpio146",
216 "gpio147", "gpio148", "gpio149", "gpio150",
217 "gpio151", /* EBI2_OE_N */
218 "gpio153", /* EBI2_ADV */
219 "gpio157"; /* EBI2_WE_N */
220 function = "ebi2";
221 };
222 };
170 }; 223 };
171 224
172 qcom,ssbi@500000 { 225 qcom,ssbi@500000 {
@@ -201,6 +254,15 @@
201 }; 254 };
202 255
203 gpio@150 { 256 gpio@150 {
257 dragon_ethernet_gpios: ethernet-gpios {
258 pinconf {
259 pins = "gpio7";
260 function = "normal";
261 input-enable;
262 bias-disable;
263 power-source = <PM8058_GPIO_S3>;
264 };
265 };
204 dragon_bmp085_gpios: bmp085-gpios { 266 dragon_bmp085_gpios: bmp085-gpios {
205 pinconf { 267 pinconf {
206 pins = "gpio16"; 268 pins = "gpio16";
@@ -238,6 +300,14 @@
238 power-source = <PM8058_GPIO_S3>; 300 power-source = <PM8058_GPIO_S3>;
239 }; 301 };
240 }; 302 };
303 dragon_veth_gpios: veth-gpios {
304 pinconf {
305 pins = "gpio40";
306 function = "normal";
307 bias-disable;
308 drive-push-pull;
309 };
310 };
241 }; 311 };
242 312
243 led@48 { 313 led@48 {
@@ -322,6 +392,55 @@
322 }; 392 };
323 }; 393 };
324 394
395 external-bus@1a100000 {
396 /* The EBI2 will instantiate first, then populate its children */
397 status = "ok";
398 pinctrl-names = "default";
399 pinctrl-0 = <&dragon_ebi2_pins>;
400
401 /*
402 * An on-board SMSC LAN9221 chip for "debug ethernet",
403 * which is actually just an ordinary ethernet on the
404 * EBI2. This has a 25MHz chrystal next to it, so no
405 * clocking is needed.
406 */
407 ethernet-ebi2@2,0 {
408 compatible = "smsc,lan9221", "smsc,lan9115";
409 reg = <2 0x0 0x100>;
410 /*
411 * GPIO7 has interrupt 198 on the PM8058
412 * The second interrupt is the PME interrupt
413 * for network wakeup, connected to the TLMM.
414 */
415 interrupts-extended = <&pmicintc 198 IRQ_TYPE_EDGE_FALLING>,
416 <&tlmm 29 IRQ_TYPE_EDGE_RISING>;
417 reset-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
418 vdd33a-supply = <&dragon_veth>;
419 vddvario-supply = <&dragon_vario>;
420 pinctrl-names = "default";
421 pinctrl-0 = <&dragon_ethernet_gpios>;
422 phy-mode = "mii";
423 reg-io-width = <2>;
424 smsc,force-external-phy;
425 /* IRQ on edge falling = active low */
426 smsc,irq-active-low;
427 smsc,irq-push-pull;
428
429 /*
430 * SLOW chipselect config
431 * Delay 9 cycles (140ns@64MHz) between SMSC
432 * LAN9221 Ethernet controller reads and writes
433 * on CS2.
434 */
435 qcom,xmem-recovery-cycles = <0>;
436 qcom,xmem-write-hold-cycles = <3>;
437 qcom,xmem-write-delta-cycles = <31>;
438 qcom,xmem-read-delta-cycles = <28>;
439 qcom,xmem-write-wait-cycles = <9>;
440 qcom,xmem-read-wait-cycles = <9>;
441 };
442 };
443
325 rpm@104000 { 444 rpm@104000 {
326 /* 445 /*
327 * Set up of the PMIC RPM regulators for this board 446 * Set up of the PMIC RPM regulators for this board
diff --git a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts
index b72e09506448..e39440a86739 100644
--- a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts
@@ -15,6 +15,20 @@
15 stdout-path = "serial0:115200n8"; 15 stdout-path = "serial0:115200n8";
16 }; 16 };
17 17
18 reserved-memory {
19 #address-cells = <1>;
20 #size-cells = <1>;
21 ranges;
22
23 ramoops@88d00000{
24 compatible = "ramoops";
25 reg = <0x88d00000 0x100000>;
26 record-size = <0x00020000>;
27 console-size = <0x00020000>;
28 ftrace-size = <0x00020000>;
29 };
30 };
31
18 ext_3p3v: regulator-fixed@1 { 32 ext_3p3v: regulator-fixed@1 {
19 compatible = "regulator-fixed"; 33 compatible = "regulator-fixed";
20 regulator-min-microvolt = <3300000>; 34 regulator-min-microvolt = <3300000>;
@@ -99,6 +113,7 @@
99 l2 { 113 l2 {
100 regulator-min-microvolt = <1200000>; 114 regulator-min-microvolt = <1200000>;
101 regulator-max-microvolt = <1200000>; 115 regulator-max-microvolt = <1200000>;
116 regulator-always-on;
102 }; 117 };
103 118
104 /* msm_otg-HSUSB_3p3 */ 119 /* msm_otg-HSUSB_3p3 */
@@ -133,13 +148,14 @@
133 regulator-min-microvolt = <3000000>; 148 regulator-min-microvolt = <3000000>;
134 regulator-max-microvolt = <3000000>; 149 regulator-max-microvolt = <3000000>;
135 bias-pull-down; 150 bias-pull-down;
151 regulator-always-on;
136 }; 152 };
137 153
138 /* pwm_power for backlight */ 154 /* pwm_power for backlight */
139 l17 { 155 l17 {
140 regulator-min-microvolt = <3000000>; 156 regulator-min-microvolt = <3000000>;
141 regulator-max-microvolt = <3600000>; 157 regulator-max-microvolt = <3000000>;
142 bias-pull-down; 158 regulator-always-on;
143 }; 159 };
144 160
145 /* camera, qdsp6 */ 161 /* camera, qdsp6 */
@@ -184,6 +200,63 @@
184 }; 200 };
185 }; 201 };
186 202
203 mdp@5100000 {
204 status = "okay";
205 ports {
206 port@1 {
207 mdp_dsi1_out: endpoint {
208 remote-endpoint = <&dsi0_in>;
209 };
210 };
211 };
212 };
213
214 dsi0: mdss_dsi@4700000 {
215 status = "okay";
216 vdda-supply = <&pm8921_l2>;/*VDD_MIPI1 to 4*/
217 vdd-supply = <&pm8921_l8>;
218 vddio-supply = <&pm8921_lvs7>;
219 avdd-supply = <&pm8921_l11>;
220 vcss-supply = <&ext_3p3v>;
221
222 panel@0 {
223 reg = <0>;
224 compatible = "jdi,lt070me05000";
225
226 vddp-supply = <&pm8921_l17>;
227 iovcc-supply = <&pm8921_lvs7>;
228
229 enable-gpios = <&pm8921_gpio 36 GPIO_ACTIVE_HIGH>;
230 reset-gpios = <&tlmm_pinmux 54 GPIO_ACTIVE_LOW>;
231 dcdc-en-gpios = <&pm8921_gpio 23 GPIO_ACTIVE_HIGH>;
232
233 port {
234 panel_in: endpoint {
235 remote-endpoint = <&dsi0_out>;
236 };
237 };
238 };
239 ports {
240 port@0 {
241 dsi0_in: endpoint {
242 remote-endpoint = <&mdp_dsi1_out>;
243 };
244 };
245
246 port@1 {
247 dsi0_out: endpoint {
248 remote-endpoint = <&panel_in>;
249 data-lanes = <0 1 2 3>;
250 };
251 };
252 };
253 };
254
255 dsi-phy@4700200 {
256 status = "okay";
257 vddio-supply = <&pm8921_lvs7>;/*VDD_PLL2_1 to 7*/
258 };
259
187 gsbi@16200000 { 260 gsbi@16200000 {
188 status = "okay"; 261 status = "okay";
189 qcom,mode = <GSBI_PROT_I2C>; 262 qcom,mode = <GSBI_PROT_I2C>;
diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
index 2eeb0904eaa7..3d37cab3b9a9 100644
--- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
@@ -43,6 +43,17 @@
43 }; 43 };
44 }; 44 };
45 45
46 hdmi-out {
47 compatible = "hdmi-connector";
48 type = "d";
49
50 port {
51 hdmi_con: endpoint {
52 remote-endpoint = <&hdmi_out>;
53 };
54 };
55 };
56
46 soc { 57 soc {
47 pinctrl@800000 { 58 pinctrl@800000 {
48 card_detect: card_detect { 59 card_detect: card_detect {
@@ -64,6 +75,25 @@
64 bias-disable; 75 bias-disable;
65 }; 76 };
66 }; 77 };
78
79 hdmi_pinctrl: hdmi-pinctrl {
80 mux {
81 pins = "gpio70", "gpio71", "gpio72";
82 function = "hdmi";
83 };
84
85 pinconf_ddc {
86 pins = "gpio70", "gpio71";
87 bias-pull-up;
88 drive-strength = <2>;
89 };
90
91 pinconf_hpd {
92 pins = "gpio72";
93 bias-pull-down;
94 drive-strength = <16>;
95 };
96 };
67 }; 97 };
68 98
69 rpm@108000 { 99 rpm@108000 {
@@ -329,5 +359,49 @@
329 mmc-pwrseq = <&sdcc4_pwrseq>; 359 mmc-pwrseq = <&sdcc4_pwrseq>;
330 }; 360 };
331 }; 361 };
362
363 hdmi-tx@4a00000 {
364 status = "okay";
365
366 core-vdda-supply = <&pm8921_hdmi_switch>;
367 hdmi-mux-supply = <&ext_3p3v>;
368
369 hpd-gpios = <&tlmm_pinmux 72 GPIO_ACTIVE_HIGH>;
370
371 pinctrl-names = "default";
372 pinctrl-0 = <&hdmi_pinctrl>;
373
374 ports {
375 port@0 {
376 endpoint {
377 remote-endpoint = <&mdp_dtv_out>;
378 };
379 };
380
381 port@1 {
382 endpoint {
383 remote-endpoint = <&hdmi_con>;
384 };
385 };
386 };
387 };
388
389 hdmi-phy@4a00400 {
390 status = "okay";
391
392 core-vdda-supply = <&pm8921_hdmi_switch>;
393 };
394
395 mdp@5100000 {
396 status = "okay";
397
398 ports {
399 port@3 {
400 endpoint {
401 remote-endpoint = <&hdmi_in>;
402 };
403 };
404 };
405 };
332 }; 406 };
333}; 407};
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 1dbe697b2e90..268bd470c865 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -1060,6 +1060,231 @@
1060 reg = <0x1a400000 0x100>; 1060 reg = <0x1a400000 0x100>;
1061 }; 1061 };
1062 1062
1063 gpu: adreno-3xx@4300000 {
1064 compatible = "qcom,adreno-3xx";
1065 reg = <0x04300000 0x20000>;
1066 reg-names = "kgsl_3d0_reg_memory";
1067 interrupts = <GIC_SPI 80 0>;
1068 interrupt-names = "kgsl_3d0_irq";
1069 clock-names =
1070 "core_clk",
1071 "iface_clk",
1072 "mem_clk",
1073 "mem_iface_clk";
1074 clocks =
1075 <&mmcc GFX3D_CLK>,
1076 <&mmcc GFX3D_AHB_CLK>,
1077 <&mmcc GFX3D_AXI_CLK>,
1078 <&mmcc MMSS_IMEM_AHB_CLK>;
1079 qcom,chipid = <0x03020002>;
1080
1081 iommus = <&gfx3d 0
1082 &gfx3d 1
1083 &gfx3d 2
1084 &gfx3d 3
1085 &gfx3d 4
1086 &gfx3d 5
1087 &gfx3d 6
1088 &gfx3d 7
1089 &gfx3d 8
1090 &gfx3d 9
1091 &gfx3d 10
1092 &gfx3d 11
1093 &gfx3d 12
1094 &gfx3d 13
1095 &gfx3d 14
1096 &gfx3d 15
1097 &gfx3d 16
1098 &gfx3d 17
1099 &gfx3d 18
1100 &gfx3d 19
1101 &gfx3d 20
1102 &gfx3d 21
1103 &gfx3d 22
1104 &gfx3d 23
1105 &gfx3d 24
1106 &gfx3d 25
1107 &gfx3d 26
1108 &gfx3d 27
1109 &gfx3d 28
1110 &gfx3d 29
1111 &gfx3d 30
1112 &gfx3d 31
1113 &gfx3d1 0
1114 &gfx3d1 1
1115 &gfx3d1 2
1116 &gfx3d1 3
1117 &gfx3d1 4
1118 &gfx3d1 5
1119 &gfx3d1 6
1120 &gfx3d1 7
1121 &gfx3d1 8
1122 &gfx3d1 9
1123 &gfx3d1 10
1124 &gfx3d1 11
1125 &gfx3d1 12
1126 &gfx3d1 13
1127 &gfx3d1 14
1128 &gfx3d1 15
1129 &gfx3d1 16
1130 &gfx3d1 17
1131 &gfx3d1 18
1132 &gfx3d1 19
1133 &gfx3d1 20
1134 &gfx3d1 21
1135 &gfx3d1 22
1136 &gfx3d1 23
1137 &gfx3d1 24
1138 &gfx3d1 25
1139 &gfx3d1 26
1140 &gfx3d1 27
1141 &gfx3d1 28
1142 &gfx3d1 29
1143 &gfx3d1 30
1144 &gfx3d1 31>;
1145
1146 qcom,gpu-pwrlevels {
1147 compatible = "qcom,gpu-pwrlevels";
1148 qcom,gpu-pwrlevel@0 {
1149 qcom,gpu-freq = <450000000>;
1150 };
1151 qcom,gpu-pwrlevel@1 {
1152 qcom,gpu-freq = <27000000>;
1153 };
1154 };
1155 };
1156
1157 mmss_sfpb: syscon@5700000 {
1158 compatible = "syscon";
1159 reg = <0x5700000 0x70>;
1160 };
1161
1162 dsi0: mdss_dsi@4700000 {
1163 compatible = "qcom,mdss-dsi-ctrl";
1164 label = "MDSS DSI CTRL->0";
1165 #address-cells = <1>;
1166 #size-cells = <0>;
1167 interrupts = <GIC_SPI 82 0>;
1168 reg = <0x04700000 0x200>;
1169 reg-names = "dsi_ctrl";
1170
1171 clocks = <&mmcc DSI_M_AHB_CLK>,
1172 <&mmcc DSI_S_AHB_CLK>,
1173 <&mmcc AMP_AHB_CLK>,
1174 <&mmcc DSI_CLK>,
1175 <&mmcc DSI1_BYTE_CLK>,
1176 <&mmcc DSI_PIXEL_CLK>,
1177 <&mmcc DSI1_ESC_CLK>;
1178 clock-names = "iface_clk", "bus_clk", "core_mmss_clk",
1179 "src_clk", "byte_clk", "pixel_clk",
1180 "core_clk";
1181
1182 assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
1183 <&mmcc DSI1_ESC_SRC>,
1184 <&mmcc DSI_SRC>,
1185 <&mmcc DSI_PIXEL_SRC>;
1186 assigned-clock-parents = <&dsi0_phy 0>,
1187 <&dsi0_phy 0>,
1188 <&dsi0_phy 1>,
1189 <&dsi0_phy 1>;
1190 syscon-sfpb = <&mmss_sfpb>;
1191 phys = <&dsi0_phy>;
1192 ports {
1193 #address-cells = <1>;
1194 #size-cells = <0>;
1195
1196 port@0 {
1197 reg = <0>;
1198 dsi0_in: endpoint {
1199 };
1200 };
1201
1202 port@1 {
1203 reg = <1>;
1204 dsi0_out: endpoint {
1205 };
1206 };
1207 };
1208 };
1209
1210
1211 dsi0_phy: dsi-phy@4700200 {
1212 compatible = "qcom,dsi-phy-28nm-8960";
1213 #clock-cells = <1>;
1214
1215 reg = <0x04700200 0x100>,
1216 <0x04700300 0x200>,
1217 <0x04700500 0x5c>;
1218 reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
1219 clock-names = "iface_clk";
1220 clocks = <&mmcc DSI_M_AHB_CLK>;
1221 };
1222
1223
1224 mdp_port0: iommu@7500000 {
1225 compatible = "qcom,apq8064-iommu";
1226 #iommu-cells = <1>;
1227 clock-names =
1228 "smmu_pclk",
1229 "iommu_clk";
1230 clocks =
1231 <&mmcc SMMU_AHB_CLK>,
1232 <&mmcc MDP_AXI_CLK>;
1233 reg = <0x07500000 0x100000>;
1234 interrupts =
1235 <GIC_SPI 63 0>,
1236 <GIC_SPI 64 0>;
1237 qcom,ncb = <2>;
1238 };
1239
1240 mdp_port1: iommu@7600000 {
1241 compatible = "qcom,apq8064-iommu";
1242 #iommu-cells = <1>;
1243 clock-names =
1244 "smmu_pclk",
1245 "iommu_clk";
1246 clocks =
1247 <&mmcc SMMU_AHB_CLK>,
1248 <&mmcc MDP_AXI_CLK>;
1249 reg = <0x07600000 0x100000>;
1250 interrupts =
1251 <GIC_SPI 61 0>,
1252 <GIC_SPI 62 0>;
1253 qcom,ncb = <2>;
1254 };
1255
1256 gfx3d: iommu@7c00000 {
1257 compatible = "qcom,apq8064-iommu";
1258 #iommu-cells = <1>;
1259 clock-names =
1260 "smmu_pclk",
1261 "iommu_clk";
1262 clocks =
1263 <&mmcc SMMU_AHB_CLK>,
1264 <&mmcc GFX3D_AXI_CLK>;
1265 reg = <0x07c00000 0x100000>;
1266 interrupts =
1267 <GIC_SPI 69 0>,
1268 <GIC_SPI 70 0>;
1269 qcom,ncb = <3>;
1270 };
1271
1272 gfx3d1: iommu@7d00000 {
1273 compatible = "qcom,apq8064-iommu";
1274 #iommu-cells = <1>;
1275 clock-names =
1276 "smmu_pclk",
1277 "iommu_clk";
1278 clocks =
1279 <&mmcc SMMU_AHB_CLK>,
1280 <&mmcc GFX3D_AXI_CLK>;
1281 reg = <0x07d00000 0x100000>;
1282 interrupts =
1283 <GIC_SPI 210 0>,
1284 <GIC_SPI 211 0>;
1285 qcom,ncb = <3>;
1286 };
1287
1063 pcie: pci@1b500000 { 1288 pcie: pci@1b500000 {
1064 compatible = "qcom,pcie-apq8064", "snps,dw-pcie"; 1289 compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
1065 reg = <0x1b500000 0x1000 1290 reg = <0x1b500000 0x1000
@@ -1095,6 +1320,102 @@
1095 reset-names = "axi", "ahb", "por", "pci", "phy"; 1320 reset-names = "axi", "ahb", "por", "pci", "phy";
1096 status = "disabled"; 1321 status = "disabled";
1097 }; 1322 };
1323
1324 hdmi: hdmi-tx@4a00000 {
1325 compatible = "qcom,hdmi-tx-8960";
1326 reg = <0x04a00000 0x2f0>;
1327 reg-names = "core_physical";
1328 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1329 clocks = <&mmcc HDMI_APP_CLK>,
1330 <&mmcc HDMI_M_AHB_CLK>,
1331 <&mmcc HDMI_S_AHB_CLK>;
1332 clock-names = "core_clk",
1333 "master_iface_clk",
1334 "slave_iface_clk";
1335
1336 phys = <&hdmi_phy>;
1337 phy-names = "hdmi-phy";
1338
1339 ports {
1340 #address-cells = <1>;
1341 #size-cells = <0>;
1342
1343 port@0 {
1344 reg = <0>;
1345 hdmi_in: endpoint {
1346 };
1347 };
1348
1349 port@1 {
1350 reg = <1>;
1351 hdmi_out: endpoint {
1352 };
1353 };
1354 };
1355 };
1356
1357 hdmi_phy: hdmi-phy@4a00400 {
1358 compatible = "qcom,hdmi-phy-8960";
1359 reg = <0x4a00400 0x60>,
1360 <0x4a00500 0x100>;
1361 reg-names = "hdmi_phy",
1362 "hdmi_pll";
1363
1364 clocks = <&mmcc HDMI_S_AHB_CLK>;
1365 clock-names = "slave_iface_clk";
1366 };
1367
1368 mdp: mdp@5100000 {
1369 compatible = "qcom,mdp4";
1370 reg = <0x05100000 0xf0000>;
1371 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1372 clocks = <&mmcc MDP_CLK>,
1373 <&mmcc MDP_AHB_CLK>,
1374 <&mmcc MDP_AXI_CLK>,
1375 <&mmcc MDP_LUT_CLK>,
1376 <&mmcc HDMI_TV_CLK>,
1377 <&mmcc MDP_TV_CLK>;
1378 clock-names = "core_clk",
1379 "iface_clk",
1380 "bus_clk",
1381 "lut_clk",
1382 "hdmi_clk",
1383 "tv_clk";
1384
1385 iommus = <&mdp_port0 0
1386 &mdp_port0 2
1387 &mdp_port1 0
1388 &mdp_port1 2>;
1389
1390 ports {
1391 #address-cells = <1>;
1392 #size-cells = <0>;
1393
1394 port@0 {
1395 reg = <0>;
1396 mdp_lvds_out: endpoint {
1397 };
1398 };
1399
1400 port@1 {
1401 reg = <1>;
1402 mdp_dsi1_out: endpoint {
1403 };
1404 };
1405
1406 port@2 {
1407 reg = <2>;
1408 mdp_dsi2_out: endpoint {
1409 };
1410 };
1411
1412 port@3 {
1413 reg = <3>;
1414 mdp_dtv_out: endpoint {
1415 };
1416 };
1417 };
1418 };
1098 }; 1419 };
1099}; 1420};
1100#include "qcom-apq8064-pins.dtsi" 1421#include "qcom-apq8064-pins.dtsi"
diff --git a/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts b/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts
new file mode 100644
index 000000000000..26160c324802
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts
@@ -0,0 +1,281 @@
1/*
2 * Device Tree Source for mangOH Green Board with WP8548 Module
3 *
4 * Copyright (C) 2016 BayLibre, SAS.
5 * Author : Neil Armstrong <narmstrong@baylibre.com>
6 *
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
10 * whole.
11 *
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * Or, alternatively,
23 *
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
31 * conditions:
32 *
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
35 *
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
44 */
45
46#include <dt-bindings/input/input.h>
47
48#include "qcom-mdm9615-wp8548.dtsi"
49#include <dt-bindings/interrupt-controller/irq.h>
50#include <dt-bindings/gpio/gpio.h>
51
52/ {
53 model = "MangOH Green with WP8548 Module";
54 compatible = "swir,mangoh-green-wp8548", "swir,wp8548", "qcom,mdm9615";
55
56 aliases {
57 spi0 = &gsbi3_spi;
58 serial0 = &gsbi4_serial;
59 serial1 = &gsbi5_serial;
60 i2c0 = &gsbi5_i2c;
61 mmc0 = &sdcc1;
62 };
63
64 chosen {
65 stdout-path = "serial1:115200n8";
66 };
67};
68
69&msmgpio {
70 /* MangOH GPIO Mapping :
71 * - 2 : GPIOEXP_INT2
72 * - 7 : IOT1_GPIO2
73 * - 8 : IOT0_GPIO4
74 * - 13: IOT0_GPIO3
75 * - 21: IOT1_GPIO4
76 * - 22: IOT2_GPIO1
77 * - 23: IOT2_GPIO2
78 * - 24: IOT2_GPIO3
79 * - 25: IOT1_GPIO1
80 * - 32: IOT1_GPIO3
81 * - 33: IOT0_GPIO2
82 * - 42: IOT0_GPIO1 and SD Card Detect
83 */
84
85 gpioext1_pins: gpioext1_pins {
86 pins {
87 pins = "gpio2";
88 function = "gpio";
89 input-enable;
90 bias-disable;
91 };
92 };
93
94 sdc_cd_pins: sdc_cd_pins {
95 pins {
96 pins = "gpio42";
97 function = "gpio";
98 drive-strength = <2>;
99 bias-pull-up;
100 };
101 };
102};
103
104&gsbi3_spi {
105 spi@0 {
106 compatible = "swir,mangoh-iotport-spi", "spidev";
107 spi-max-frequency = <24000000>;
108 reg = <0>;
109 };
110};
111
112&gsbi5_i2c {
113 mux@71 {
114 compatible = "nxp,pca9548";
115 #address-cells = <1>;
116 #size-cells = <0>;
117 reg = <0x71>;
118
119 i2c_iot0: i2c@0 {
120 #address-cells = <1>;
121 #size-cells = <0>;
122 reg = <0>;
123 };
124
125 i2c_iot1: i2c@1 {
126 #address-cells = <1>;
127 #size-cells = <0>;
128 reg = <1>;
129 };
130
131 i2c_iot2: i2c@2 {
132 #address-cells = <1>;
133 #size-cells = <0>;
134 reg = <2>;
135 };
136
137 i2c@3 {
138 #address-cells = <1>;
139 #size-cells = <0>;
140 reg = <3>;
141
142 usbhub: hub@8 {
143 compatible = "smsc,usb3503a";
144 reg = <0x8>;
145 connect-gpios = <&gpioext2 1 GPIO_ACTIVE_HIGH>;
146 intn-gpios = <&gpioext2 0 GPIO_ACTIVE_LOW>;
147 initial-mode = <1>;
148 };
149 };
150
151 i2c@4 {
152 #address-cells = <1>;
153 #size-cells = <0>;
154 reg = <4>;
155
156 gpioext0: gpio@3e {
157 /* GPIO Expander 0 Mapping :
158 * - 0: ARDUINO_RESET_Level shift
159 * - 1: BattChrgr_PG_N
160 * - 2: BattGauge_GPIO
161 * - 3: LED_ON (out active high)
162 * - 4: ATmega_reset_GPIO
163 * - 5: X
164 * - 6: PCM_ANALOG_SELECT (out active high)
165 * - 7: X
166 * - 8: Board_rev_res1 (in)
167 * - 9: Board_rev_res2 (in)
168 * - 10: UART_EXP1_ENn (out active low / pull-down)
169 * - 11: UART_EXP1_IN (out pull-down)
170 * - 12: UART_EXP2_IN (out pull-down)
171 * - 13: SDIO_SEL (out pull-down)
172 * - 14: SPI_EXP1_ENn (out active low / pull-down)
173 * - 15: SPI_EXP1_IN (out pull-down)
174 */
175 #gpio-cells = <2>;
176 #interrupt-cells = <2>;
177 compatible = "semtech,sx1509q";
178 reg = <0x3e>;
179 interrupt-parent = <&gpioext1>;
180 interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
181
182 probe-reset;
183
184 gpio-controller;
185 interrupt-controller;
186 };
187 };
188
189 i2c@5 {
190 #address-cells = <1>;
191 #size-cells = <0>;
192 reg = <5>;
193
194 gpioext1: gpio@3f {
195 /* GPIO Expander 1 Mapping :
196 * - 0: GPIOEXP_INT1
197 * - 1: Battery detect
198 * - 2: GPIO_SCF3_RESET
199 * - 3: LED_CARD_DETECT_IOT0 (in)
200 * - 4: LED_CARD_DETECT_IOT1 (in)
201 * - 5: LED_CARD_DETECT_IOT2 (in)
202 * - 6: UIM2_PWM_SELECT
203 * - 7: UIM2_M2_S_SELECT
204 * - 8: TP900
205 * - 9: SENSOR_INT1 (in)
206 * - 10: SENSOR_INT2 (in)
207 * - 11: CARD_DETECT_IOT0 (in pull-up)
208 * - 12: CARD_DETECT_IOT2 (in pull-up)
209 * - 13: CARD_DETECT_IOT1 (in pull-up)
210 * - 14: GPIOEXP_INT3 (in active low / pull-up)
211 * - 15: BattChrgr_INT_N
212 */
213 pinctrl-0 = <&gpioext1_pins>;
214 pinctrl-names = "default";
215
216 #gpio-cells = <2>;
217 #interrupt-cells = <2>;
218 compatible = "semtech,sx1509q";
219 reg = <0x3f>;
220 interrupt-parent = <&msmgpio>;
221 interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
222
223 probe-reset;
224
225 gpio-controller;
226 interrupt-controller;
227 };
228 };
229
230 i2c@6 {
231 #address-cells = <1>;
232 #size-cells = <0>;
233 reg = <6>;
234
235 gpioext2: gpio@70 {
236 /* GPIO Expander 2 Mapping :
237 * - 0: USB_HUB_INTn
238 * - 1: HUB_CONNECT
239 * - 2: GPIO_IOT2_RESET (out active low / pull-up)
240 * - 3: GPIO_IOT1_RESET (out active low / pull-up)
241 * - 4: GPIO_IOT0_RESET (out active low / pull-up)
242 * - 5: TP901
243 * - 6: TP902
244 * - 7: TP903
245 * - 8: UART_EXP2_ENn (out active low / pull-down)
246 * - 9: PCM_EXP1_ENn (out active low)
247 * - 10: PCM_EXP1_SEL (out)
248 * - 11: ARD_FTDI
249 * - 12: TP904
250 * - 13: TP905
251 * - 14: TP906
252 * - 15: RS232_Enable (out active high / pull-up)
253 */
254 #gpio-cells = <2>;
255 #interrupt-cells = <2>;
256 compatible = "semtech,sx1509q";
257 reg = <0x70>;
258 interrupt-parent = <&gpioext1>;
259 interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
260
261 probe-reset;
262
263 gpio-controller;
264 interrupt-controller;
265 };
266 };
267
268 i2c@7 {
269 #address-cells = <1>;
270 #size-cells = <0>;
271 reg = <7>;
272 };
273 };
274};
275
276&sdcc1 {
277 pinctrl-0 = <&sdc_cd_pins>;
278 pinctrl-names = "default";
279 disable-wp;
280 cd-gpios = <&msmgpio 42 GPIO_ACTIVE_LOW>; /* Active low CD */
281};
diff --git a/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi b/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi
new file mode 100644
index 000000000000..7869898e392d
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi
@@ -0,0 +1,170 @@
1/*
2 * Device Tree Source for Sierra Wireless WP8548 Module
3 *
4 * Copyright (C) 2016 BayLibre, SAS.
5 * Author : Neil Armstrong <narmstrong@baylibre.com>
6 *
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
10 * whole.
11 *
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * Or, alternatively,
23 *
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
31 * conditions:
32 *
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
35 *
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
44 */
45
46#include "qcom-mdm9615.dtsi"
47
48/ {
49 model = "Sierra Wireless WP8548 Module";
50 compatible = "swir,wp8548", "qcom,mdm9615";
51
52 memory {
53 reg = <0x48000000 0x7F00000>;
54 };
55};
56
57&msmgpio {
58 pinctrl-0 = <&reset_out_pins>;
59 pinctrl-names = "default";
60
61 gsbi3_pins: gsbi3_pins {
62 mux {
63 pins = "gpio8", "gpio9", "gpio10", "gpio11";
64 function = "gsbi3";
65 drive-strength = <8>;
66 bias-disable;
67 };
68 };
69
70 gsbi4_pins: gsbi4_pins {
71 mux {
72 pins = "gpio12", "gpio13", "gpio14", "gpio15";
73 function = "gsbi4";
74 drive-strength = <8>;
75 bias-disable;
76 };
77 };
78
79 gsbi5_i2c_pins: gsbi5_i2c_pins {
80 pin16 {
81 pins = "gpio16";
82 function = "gsbi5_i2c";
83 drive-strength = <8>;
84 bias-disable;
85 };
86
87 pin17 {
88 pins = "gpio17";
89 function = "gsbi5_i2c";
90 drive-strength = <2>;
91 bias-disable;
92 };
93 };
94
95 gsbi5_uart_pins: gsbi5_uart_pins {
96 mux {
97 pins = "gpio18", "gpio19";
98 function = "gsbi5_uart";
99 drive-strength = <8>;
100 bias-disable;
101 };
102 };
103
104 reset_out_pins: reset_out_pins {
105 pins {
106 pins = "gpio66";
107 function = "gpio";
108 drive-strength = <2>;
109 bias-pull-up;
110 output-high;
111 };
112 };
113};
114
115&pmicgpio {
116 usb_vbus_5v_pins: usb_vbus_5v_pins {
117 pins = "gpio4";
118 function = "normal";
119 output-high;
120 bias-disable;
121 qcom,drive-strength = <1>;
122 power-source = <2>;
123 };
124};
125
126&gsbi3 {
127 status = "ok";
128 qcom,mode = <GSBI_PROT_SPI>;
129};
130
131&gsbi3_spi {
132 status = "ok";
133 pinctrl-0 = <&gsbi3_pins>;
134 pinctrl-names = "default";
135 assigned-clocks = <&gcc GSBI3_QUP_CLK>;
136 assigned-clock-rates = <24000000>;
137};
138
139&gsbi4 {
140 status = "ok";
141 qcom,mode = <GSBI_PROT_UART_W_FC>;
142};
143
144&gsbi4_serial {
145 status = "ok";
146 pinctrl-0 = <&gsbi4_pins>;
147 pinctrl-names = "default";
148};
149
150&gsbi5 {
151 status = "ok";
152 qcom,mode = <GSBI_PROT_I2C_UART>;
153};
154
155&gsbi5_i2c {
156 status = "ok";
157 clock-frequency = <200000>;
158 pinctrl-0 = <&gsbi5_i2c_pins>;
159 pinctrl-names = "default";
160};
161
162&gsbi5_serial {
163 status = "ok";
164 pinctrl-0 = <&gsbi5_uart_pins>;
165 pinctrl-names = "default";
166};
167
168&sdcc1 {
169 status = "ok";
170};
diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi
new file mode 100644
index 000000000000..5ae4ec59e6ea
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi
@@ -0,0 +1,557 @@
1/*
2 * Device Tree Source for Qualcomm MDM9615 SoC
3 *
4 * Copyright (C) 2016 BayLibre, SAS.
5 * Author : Neil Armstrong <narmstrong@baylibre.com>
6 *
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
10 * whole.
11 *
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * Or, alternatively,
23 *
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
31 * conditions:
32 *
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
35 *
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
44 */
45
46/dts-v1/;
47
48/include/ "skeleton.dtsi"
49
50#include <dt-bindings/interrupt-controller/arm-gic.h>
51#include <dt-bindings/clock/qcom,gcc-mdm9615.h>
52#include <dt-bindings/reset/qcom,gcc-mdm9615.h>
53#include <dt-bindings/mfd/qcom-rpm.h>
54#include <dt-bindings/soc/qcom,gsbi.h>
55
56/ {
57 model = "Qualcomm MDM9615";
58 compatible = "qcom,mdm9615";
59 interrupt-parent = <&intc>;
60
61 cpus {
62 #address-cells = <1>;
63 #size-cells = <0>;
64
65 cpu0: cpu@0 {
66 compatible = "arm,cortex-a5";
67 device_type = "cpu";
68 next-level-cache = <&L2>;
69 };
70 };
71
72 cpu-pmu {
73 compatible = "arm,cortex-a5-pmu";
74 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
75 };
76
77 clocks {
78 cxo_board {
79 compatible = "fixed-clock";
80 #clock-cells = <0>;
81 clock-frequency = <19200000>;
82 };
83 };
84
85 regulators {
86 vsdcc_fixed: vsdcc-regulator {
87 compatible = "regulator-fixed";
88 regulator-name = "SDCC Power";
89 regulator-min-microvolt = <2700000>;
90 regulator-max-microvolt = <2700000>;
91 regulator-always-on;
92 };
93 };
94
95 soc: soc {
96 #address-cells = <1>;
97 #size-cells = <1>;
98 ranges;
99 compatible = "simple-bus";
100
101 L2: l2-cache@2040000 {
102 compatible = "arm,pl310-cache";
103 reg = <0x02040000 0x1000>;
104 arm,data-latency = <2 2 0>;
105 cache-unified;
106 cache-level = <2>;
107 };
108
109 intc: interrupt-controller@2000000 {
110 compatible = "qcom,msm-qgic2";
111 interrupt-controller;
112 #interrupt-cells = <3>;
113 reg = <0x02000000 0x1000>,
114 <0x02002000 0x1000>;
115 };
116
117 timer@200a000 {
118 compatible = "qcom,kpss-timer", "qcom,msm-timer";
119 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>,
120 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>,
121 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>;
122 reg = <0x0200a000 0x100>;
123 clock-frequency = <27000000>,
124 <32768>;
125 cpu-offset = <0x80000>;
126 };
127
128 msmgpio: pinctrl@800000 {
129 compatible = "qcom,mdm9615-pinctrl";
130 gpio-controller;
131 #gpio-cells = <2>;
132 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
133 interrupt-controller;
134 #interrupt-cells = <2>;
135 reg = <0x800000 0x4000>;
136 };
137
138 gcc: clock-controller@900000 {
139 compatible = "qcom,gcc-mdm9615";
140 #clock-cells = <1>;
141 #reset-cells = <1>;
142 reg = <0x900000 0x4000>;
143 };
144
145 lcc: clock-controller@28000000 {
146 compatible = "qcom,lcc-mdm9615";
147 reg = <0x28000000 0x1000>;
148 #clock-cells = <1>;
149 #reset-cells = <1>;
150 };
151
152 l2cc: clock-controller@2011000 {
153 compatible = "syscon";
154 reg = <0x02011000 0x1000>;
155 };
156
157 rng@1a500000 {
158 compatible = "qcom,prng";
159 reg = <0x1a500000 0x200>;
160 clocks = <&gcc PRNG_CLK>;
161 clock-names = "core";
162 assigned-clocks = <&gcc PRNG_CLK>;
163 assigned-clock-rates = <32000000>;
164 };
165
166 gsbi2: gsbi@16100000 {
167 compatible = "qcom,gsbi-v1.0.0";
168 cell-index = <2>;
169 reg = <0x16100000 0x100>;
170 clocks = <&gcc GSBI2_H_CLK>;
171 clock-names = "iface";
172 status = "disabled";
173 #address-cells = <1>;
174 #size-cells = <1>;
175 ranges;
176
177 gsbi2_i2c: i2c@16180000 {
178 compatible = "qcom,i2c-qup-v1.1.1";
179 #address-cells = <1>;
180 #size-cells = <0>;
181 reg = <0x16180000 0x1000>;
182 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
183
184 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
185 clock-names = "core", "iface";
186 status = "disabled";
187 };
188 };
189
190 gsbi3: gsbi@16200000 {
191 compatible = "qcom,gsbi-v1.0.0";
192 cell-index = <3>;
193 reg = <0x16200000 0x100>;
194 clocks = <&gcc GSBI3_H_CLK>;
195 clock-names = "iface";
196 status = "disabled";
197 #address-cells = <1>;
198 #size-cells = <1>;
199 ranges;
200
201 gsbi3_spi: spi@16280000 {
202 compatible = "qcom,spi-qup-v1.1.1";
203 #address-cells = <1>;
204 #size-cells = <0>;
205 reg = <0x16280000 0x1000>;
206 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
207 spi-max-frequency = <24000000>;
208
209 clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>;
210 clock-names = "core", "iface";
211 status = "disabled";
212 };
213 };
214
215 gsbi4: gsbi@16300000 {
216 compatible = "qcom,gsbi-v1.0.0";
217 cell-index = <4>;
218 reg = <0x16300000 0x100>;
219 clocks = <&gcc GSBI4_H_CLK>;
220 clock-names = "iface";
221 status = "disabled";
222 #address-cells = <1>;
223 #size-cells = <1>;
224 ranges;
225
226 syscon-tcsr = <&tcsr>;
227
228 gsbi4_serial: serial@16340000 {
229 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
230 reg = <0x16340000 0x1000>,
231 <0x16300000 0x1000>;
232 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
234 clock-names = "core", "iface";
235 status = "disabled";
236 };
237 };
238
239 gsbi5: gsbi@16400000 {
240 compatible = "qcom,gsbi-v1.0.0";
241 cell-index = <5>;
242 reg = <0x16400000 0x100>;
243 clocks = <&gcc GSBI5_H_CLK>;
244 clock-names = "iface";
245 status = "disabled";
246 #address-cells = <1>;
247 #size-cells = <1>;
248 ranges;
249
250 syscon-tcsr = <&tcsr>;
251
252 gsbi5_i2c: i2c@16480000 {
253 compatible = "qcom,i2c-qup-v1.1.1";
254 #address-cells = <1>;
255 #size-cells = <0>;
256 reg = <0x16480000 0x1000>;
257 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
258
259 /* QUP clock is not initialized, set rate */
260 assigned-clocks = <&gcc GSBI5_QUP_CLK>;
261 assigned-clock-rates = <24000000>;
262
263 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
264 clock-names = "core", "iface";
265 status = "disabled";
266 };
267
268 gsbi5_serial: serial@16440000 {
269 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
270 reg = <0x16440000 0x1000>,
271 <0x16400000 0x1000>;
272 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
273 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
274 clock-names = "core", "iface";
275 status = "disabled";
276 };
277 };
278
279 qcom,ssbi@500000 {
280 compatible = "qcom,ssbi";
281 reg = <0x500000 0x1000>;
282 qcom,controller-type = "pmic-arbiter";
283
284 pmicintc: pmic@0 {
285 compatible = "qcom,pm8018", "qcom,pm8921";
286 interrupts = <GIC_PPI 226 IRQ_TYPE_LEVEL_HIGH>;
287 #interrupt-cells = <2>;
288 interrupt-controller;
289 #address-cells = <1>;
290 #size-cells = <0>;
291
292 pwrkey@1c {
293 compatible = "qcom,pm8018-pwrkey", "qcom,pm8921-pwrkey";
294 reg = <0x1c>;
295 interrupt-parent = <&pmicintc>;
296 interrupts = <50 IRQ_TYPE_EDGE_RISING>,
297 <51 IRQ_TYPE_EDGE_RISING>;
298 debounce = <15625>;
299 pull-up;
300 };
301
302 pmicmpp: mpp@50 {
303 compatible = "qcom,pm8018-mpp", "qcom,ssbi-mpp";
304 interrupt-parent = <&pmicintc>;
305 interrupts = <24 IRQ_TYPE_NONE>,
306 <25 IRQ_TYPE_NONE>,
307 <26 IRQ_TYPE_NONE>,
308 <27 IRQ_TYPE_NONE>,
309 <28 IRQ_TYPE_NONE>,
310 <29 IRQ_TYPE_NONE>;
311 reg = <0x50>;
312 gpio-controller;
313 #gpio-cells = <2>;
314 };
315
316 rtc@11d {
317 compatible = "qcom,pm8018-rtc", "qcom,pm8921-rtc";
318 interrupt-parent = <&pmicintc>;
319 interrupts = <39 IRQ_TYPE_EDGE_RISING>;
320 reg = <0x11d>;
321 allow-set-time;
322 };
323
324 pmicgpio: gpio@150 {
325 compatible = "qcom,pm8018-gpio", "qcom,ssbi-gpio";
326 interrupt-parent = <&pmicintc>;
327 interrupts = <24 IRQ_TYPE_NONE>,
328 <25 IRQ_TYPE_NONE>,
329 <26 IRQ_TYPE_NONE>,
330 <27 IRQ_TYPE_NONE>,
331 <28 IRQ_TYPE_NONE>,
332 <29 IRQ_TYPE_NONE>;
333 gpio-controller;
334 #gpio-cells = <2>;
335 };
336 };
337 };
338
339 sdcc1bam: dma@12182000{
340 compatible = "qcom,bam-v1.3.0";
341 reg = <0x12182000 0x8000>;
342 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
343 clocks = <&gcc SDC1_H_CLK>;
344 clock-names = "bam_clk";
345 #dma-cells = <1>;
346 qcom,ee = <0>;
347 };
348
349 sdcc2bam: dma@12142000{
350 compatible = "qcom,bam-v1.3.0";
351 reg = <0x12142000 0x8000>;
352 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&gcc SDC2_H_CLK>;
354 clock-names = "bam_clk";
355 #dma-cells = <1>;
356 qcom,ee = <0>;
357 };
358
359 amba {
360 compatible = "arm,amba-bus";
361 #address-cells = <1>;
362 #size-cells = <1>;
363 ranges;
364 sdcc1: sdcc@12180000 {
365 status = "disabled";
366 compatible = "arm,pl18x", "arm,primecell";
367 arm,primecell-periphid = <0x00051180>;
368 reg = <0x12180000 0x2000>;
369 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
370 interrupt-names = "cmd_irq";
371 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
372 clock-names = "mclk", "apb_pclk";
373 bus-width = <8>;
374 max-frequency = <48000000>;
375 cap-sd-highspeed;
376 cap-mmc-highspeed;
377 vmmc-supply = <&vsdcc_fixed>;
378 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
379 dma-names = "tx", "rx";
380 assigned-clocks = <&gcc SDC1_CLK>;
381 assigned-clock-rates = <400000>;
382 };
383
384 sdcc2: sdcc@12140000 {
385 compatible = "arm,pl18x", "arm,primecell";
386 arm,primecell-periphid = <0x00051180>;
387 status = "disabled";
388 reg = <0x12140000 0x2000>;
389 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
390 interrupt-names = "cmd_irq";
391 clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
392 clock-names = "mclk", "apb_pclk";
393 bus-width = <4>;
394 cap-sd-highspeed;
395 cap-mmc-highspeed;
396 max-frequency = <48000000>;
397 no-1-8-v;
398 vmmc-supply = <&vsdcc_fixed>;
399 dmas = <&sdcc2bam 2>, <&sdcc2bam 1>;
400 dma-names = "tx", "rx";
401 assigned-clocks = <&gcc SDC2_CLK>;
402 assigned-clock-rates = <400000>;
403 };
404 };
405
406 tcsr: syscon@1a400000 {
407 compatible = "qcom,tcsr-mdm9615", "syscon";
408 reg = <0x1a400000 0x100>;
409 };
410
411 rpm: rpm@108000 {
412 compatible = "qcom,rpm-mdm9615";
413 reg = <0x108000 0x1000>;
414
415 qcom,ipc = <&l2cc 0x8 2>;
416
417 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
418 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
419 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
420 interrupt-names = "ack", "err", "wakeup";
421
422 regulators {
423 compatible = "qcom,rpm-pm8018-regulators";
424
425 vin_lvs1-supply = <&pm8018_s3>;
426
427 vdd_l7-supply = <&pm8018_s4>;
428 vdd_l8-supply = <&pm8018_s3>;
429 vdd_l9_l10_l11_l12-supply = <&pm8018_s5>;
430
431 /* Buck SMPS */
432 pm8018_s1: s1 {
433 regulator-min-microvolt = <500000>;
434 regulator-max-microvolt = <1150000>;
435 qcom,switch-mode-frequency = <1600000>;
436 bias-pull-down;
437 };
438
439 pm8018_s2: s2 {
440 regulator-min-microvolt = <1225000>;
441 regulator-max-microvolt = <1300000>;
442 qcom,switch-mode-frequency = <1600000>;
443 bias-pull-down;
444 };
445
446 pm8018_s3: s3 {
447 regulator-always-on;
448 regulator-min-microvolt = <1800000>;
449 regulator-max-microvolt = <1800000>;
450 qcom,switch-mode-frequency = <1600000>;
451 bias-pull-down;
452 };
453
454 pm8018_s4: s4 {
455 regulator-min-microvolt = <2100000>;
456 regulator-max-microvolt = <2200000>;
457 qcom,switch-mode-frequency = <1600000>;
458 bias-pull-down;
459 };
460
461 pm8018_s5: s5 {
462 regulator-always-on;
463 regulator-min-microvolt = <1350000>;
464 regulator-max-microvolt = <1350000>;
465 qcom,switch-mode-frequency = <1600000>;
466 bias-pull-down;
467 };
468
469 /* PMOS LDO */
470 pm8018_l2: l2 {
471 regulator-always-on;
472 regulator-min-microvolt = <1800000>;
473 regulator-max-microvolt = <1800000>;
474 bias-pull-down;
475 };
476
477 pm8018_l3: l3 {
478 regulator-always-on;
479 regulator-min-microvolt = <1800000>;
480 regulator-max-microvolt = <1800000>;
481 bias-pull-down;
482 };
483
484 pm8018_l4: l4 {
485 regulator-min-microvolt = <3300000>;
486 regulator-max-microvolt = <3300000>;
487 bias-pull-down;
488 };
489
490 pm8018_l5: l5 {
491 regulator-min-microvolt = <2850000>;
492 regulator-max-microvolt = <2850000>;
493 bias-pull-down;
494 };
495
496 pm8018_l6: l6 {
497 regulator-min-microvolt = <1800000>;
498 regulator-max-microvolt = <2850000>;
499 bias-pull-down;
500 };
501
502 pm8018_l7: l7 {
503 regulator-min-microvolt = <1850000>;
504 regulator-max-microvolt = <1900000>;
505 bias-pull-down;
506 };
507
508 pm8018_l8: l8 {
509 regulator-min-microvolt = <1200000>;
510 regulator-max-microvolt = <1200000>;
511 bias-pull-down;
512 };
513
514 pm8018_l9: l9 {
515 regulator-min-microvolt = <750000>;
516 regulator-max-microvolt = <1150000>;
517 bias-pull-down;
518 };
519
520 pm8018_l10: l10 {
521 regulator-min-microvolt = <1050000>;
522 regulator-max-microvolt = <1050000>;
523 bias-pull-down;
524 };
525
526 pm8018_l11: l11 {
527 regulator-min-microvolt = <1050000>;
528 regulator-max-microvolt = <1050000>;
529 bias-pull-down;
530 };
531
532 pm8018_l12: l12 {
533 regulator-min-microvolt = <1050000>;
534 regulator-max-microvolt = <1050000>;
535 bias-pull-down;
536 };
537
538 pm8018_l13: l13 {
539 regulator-min-microvolt = <1850000>;
540 regulator-max-microvolt = <2950000>;
541 bias-pull-down;
542 };
543
544 pm8018_l14: l14 {
545 regulator-min-microvolt = <2850000>;
546 regulator-max-microvolt = <2850000>;
547 bias-pull-down;
548 };
549
550 /* Low Voltage Switch */
551 pm8018_lvs1: lvs1 {
552 bias-pull-down;
553 };
554 };
555 };
556 };
557};
diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi
index 8c65e0d82559..4d828f810746 100644
--- a/arch/arm/boot/dts/qcom-msm8660.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
@@ -141,6 +141,23 @@
141 }; 141 };
142 }; 142 };
143 143
144 external-bus@1a100000 {
145 compatible = "qcom,msm8660-ebi2";
146 #address-cells = <2>;
147 #size-cells = <1>;
148 ranges = <0 0x0 0x1a800000 0x00800000>,
149 <1 0x0 0x1b000000 0x00800000>,
150 <2 0x0 0x1b800000 0x00800000>,
151 <3 0x0 0x1d000000 0x08000000>,
152 <4 0x0 0x1c800000 0x00800000>,
153 <5 0x0 0x1c000000 0x00800000>;
154 reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
155 reg-names = "ebi2", "xmem";
156 clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;
157 clock-names = "ebi2x", "ebi2";
158 status = "disabled";
159 };
160
144 qcom,ssbi@500000 { 161 qcom,ssbi@500000 {
145 compatible = "qcom,ssbi"; 162 compatible = "qcom,ssbi";
146 reg = <0x500000 0x1000>; 163 reg = <0x500000 0x1000>;
diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts
index c0fb4a698c56..382bcc3231a9 100644
--- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts
+++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts
@@ -224,6 +224,35 @@
224 status = "ok"; 224 status = "ok";
225 }; 225 };
226 226
227 pinctrl@fd510000 {
228 sdhc1_pin_a: sdhc1-pin-active {
229 clk {
230 pins = "sdc1_clk";
231 drive-strength = <16>;
232 bias-disable;
233 };
234
235 cmd-data {
236 pins = "sdc1_cmd", "sdc1_data";
237 drive-strength = <10>;
238 bias-pull-up;
239 };
240 };
241 };
242
243 sdhci@f9824900 {
244 status = "ok";
245
246 vmmc-supply = <&pm8941_l20>;
247 vqmmc-supply = <&pm8941_s3>;
248
249 bus-width = <8>;
250 non-removable;
251
252 pinctrl-names = "default";
253 pinctrl-0 = <&sdhc1_pin_a>;
254 };
255
227 gpio-keys { 256 gpio-keys {
228 compatible = "gpio-keys"; 257 compatible = "gpio-keys";
229 input-name = "gpio-keys"; 258 input-name = "gpio-keys";
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-18 18:18:15 -0400