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authorStephane Viau <sviau@codeaurora.org>2015-09-15 08:41:47 -0400
committerRob Clark <robdclark@gmail.com>2015-10-22 15:39:55 -0400
commitd40325b43750eb4a8a81240e36fe38e9ccbcc9eb (patch)
tree10902990c370d1f2fedb26832702b57810c329d4
parent5e921b19268d87a0c64f3181c0d3ea9df9eea972 (diff)
drm/msm/mdp5: Avoid printing error messages for optional clocks
The current behavior is to try to get optional clocks and print a dev_err message in case of failure. This looks rather confusing and may increase with the amount of optional clocks. We may need a cleaner way to handle per-device clocks but in the meantime, let's reduce the amount of dev_err messages during the probe. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
-rw-r--r--Documentation/devicetree/bindings/drm/msm/mdp.txt3
-rw-r--r--drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c27
2 files changed, 18 insertions, 12 deletions
diff --git a/Documentation/devicetree/bindings/drm/msm/mdp.txt b/Documentation/devicetree/bindings/drm/msm/mdp.txt
index 1a0598e5279d..0833edaba4c3 100644
--- a/Documentation/devicetree/bindings/drm/msm/mdp.txt
+++ b/Documentation/devicetree/bindings/drm/msm/mdp.txt
@@ -11,13 +11,14 @@ Required properties:
11- clock-names: the following clocks are required: 11- clock-names: the following clocks are required:
12 * "core_clk" 12 * "core_clk"
13 * "iface_clk" 13 * "iface_clk"
14 * "lut_clk"
15 * "src_clk" 14 * "src_clk"
16 * "hdmi_clk" 15 * "hdmi_clk"
17 * "mpd_clk" 16 * "mpd_clk"
18 17
19Optional properties: 18Optional properties:
20- gpus: phandle for gpu device 19- gpus: phandle for gpu device
20- clock-names: the following clocks are optional:
21 * "lut_clk"
21 22
22Example: 23Example:
23 24
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
index 7dbdced1fa3c..34c4ad54c269 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
@@ -452,15 +452,19 @@ static void read_hw_revision(struct mdp5_kms *mdp5_kms,
452} 452}
453 453
454static int get_clk(struct platform_device *pdev, struct clk **clkp, 454static int get_clk(struct platform_device *pdev, struct clk **clkp,
455 const char *name) 455 const char *name, bool mandatory)
456{ 456{
457 struct device *dev = &pdev->dev; 457 struct device *dev = &pdev->dev;
458 struct clk *clk = devm_clk_get(dev, name); 458 struct clk *clk = devm_clk_get(dev, name);
459 if (IS_ERR(clk)) { 459 if (IS_ERR(clk) && mandatory) {
460 dev_err(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk)); 460 dev_err(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk));
461 return PTR_ERR(clk); 461 return PTR_ERR(clk);
462 } 462 }
463 *clkp = clk; 463 if (IS_ERR(clk))
464 DBG("skipping %s", name);
465 else
466 *clkp = clk;
467
464 return 0; 468 return 0;
465} 469}
466 470
@@ -514,25 +518,26 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev)
514 goto fail; 518 goto fail;
515 } 519 }
516 520
517 ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus_clk"); 521 /* mandatory clocks: */
522 ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus_clk", true);
518 if (ret) 523 if (ret)
519 goto fail; 524 goto fail;
520 ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface_clk"); 525 ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface_clk", true);
521 if (ret) 526 if (ret)
522 goto fail; 527 goto fail;
523 ret = get_clk(pdev, &mdp5_kms->src_clk, "core_clk_src"); 528 ret = get_clk(pdev, &mdp5_kms->src_clk, "core_clk_src", true);
524 if (ret) 529 if (ret)
525 goto fail; 530 goto fail;
526 ret = get_clk(pdev, &mdp5_kms->core_clk, "core_clk"); 531 ret = get_clk(pdev, &mdp5_kms->core_clk, "core_clk", true);
527 if (ret) 532 if (ret)
528 goto fail; 533 goto fail;
529 ret = get_clk(pdev, &mdp5_kms->lut_clk, "lut_clk"); 534 ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync_clk", true);
530 if (ret)
531 DBG("failed to get (optional) lut_clk clock");
532 ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync_clk");
533 if (ret) 535 if (ret)
534 goto fail; 536 goto fail;
535 537
538 /* optional clocks: */
539 get_clk(pdev, &mdp5_kms->lut_clk, "lut_clk", false);
540
536 /* we need to set a default rate before enabling. Set a safe 541 /* we need to set a default rate before enabling. Set a safe
537 * rate first, then figure out hw revision, and then set a 542 * rate first, then figure out hw revision, and then set a
538 * more optimal rate: 543 * more optimal rate: