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authorRex Zhu <Rex.Zhu@amd.com>2017-09-19 23:22:56 -0400
committerAlex Deucher <alexander.deucher@amd.com>2017-09-26 15:14:26 -0400
commitd3f8c0abf45866d0e474181e147594d3da15834d (patch)
tree3c3765eb9cd2bd64d61b71c54346595df9c7bb95
parente9c7577c09b5062a4f1464b8ef4472c14bdfd2e7 (diff)
drm/amd/powerplay: refine interface in struct pp_smumgr_func
unify to use struct hwmgr as function parameter in smumgr. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat
-rw-r--r--drivers/gpu/drm/amd/powerplay/amd_powerplay.c12
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c8
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c90
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c2
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c26
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c60
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c137
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c24
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c12
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c148
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c18
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c16
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/smumgr.h110
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c140
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.h4
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c14
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c292
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c59
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c130
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c57
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c76
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c97
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c122
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c130
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h8
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c212
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h36
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c89
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c70
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c64
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c194
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h16
32 files changed, 1225 insertions, 1248 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 2634d792404a..c37ea9543ca3 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -83,7 +83,7 @@ static int pp_sw_init(void *handle)
83 if (smumgr->smumgr_funcs->smu_init == NULL) 83 if (smumgr->smumgr_funcs->smu_init == NULL)
84 return -EINVAL; 84 return -EINVAL;
85 85
86 ret = smumgr->smumgr_funcs->smu_init(smumgr); 86 ret = smumgr->smumgr_funcs->smu_init(pp_handle->hwmgr);
87 87
88 pr_info("amdgpu: powerplay sw initialized\n"); 88 pr_info("amdgpu: powerplay sw initialized\n");
89 } 89 }
@@ -103,7 +103,7 @@ static int pp_sw_fini(void *handle)
103 if (smumgr->smumgr_funcs->smu_fini == NULL) 103 if (smumgr->smumgr_funcs->smu_fini == NULL)
104 return -EINVAL; 104 return -EINVAL;
105 105
106 ret = smumgr->smumgr_funcs->smu_fini(smumgr); 106 ret = smumgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
107 } 107 }
108 return ret; 108 return ret;
109} 109}
@@ -122,9 +122,9 @@ static int pp_hw_init(void *handle)
122 if (smumgr->smumgr_funcs->start_smu == NULL) 122 if (smumgr->smumgr_funcs->start_smu == NULL)
123 return -EINVAL; 123 return -EINVAL;
124 124
125 if(smumgr->smumgr_funcs->start_smu(smumgr)) { 125 if(smumgr->smumgr_funcs->start_smu(pp_handle->hwmgr)) {
126 pr_err("smc start failed\n"); 126 pr_err("smc start failed\n");
127 smumgr->smumgr_funcs->smu_fini(smumgr); 127 smumgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
128 return -EINVAL;; 128 return -EINVAL;;
129 } 129 }
130 if (ret == PP_DPM_DISABLED) 130 if (ret == PP_DPM_DISABLED)
@@ -246,10 +246,10 @@ static int pp_resume(void *handle)
246 if (smumgr->smumgr_funcs->start_smu == NULL) 246 if (smumgr->smumgr_funcs->start_smu == NULL)
247 return -EINVAL; 247 return -EINVAL;
248 248
249 ret = smumgr->smumgr_funcs->start_smu(smumgr); 249 ret = smumgr->smumgr_funcs->start_smu(pp_handle->hwmgr);
250 if (ret) { 250 if (ret) {
251 pr_err("smc start failed\n"); 251 pr_err("smc start failed\n");
252 smumgr->smumgr_funcs->smu_fini(smumgr); 252 smumgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
253 return ret; 253 return ret;
254 } 254 }
255 255
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
index 576b61eb6b8f..44de0874629f 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
@@ -113,12 +113,12 @@ int cz_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
113 PHM_PlatformCaps_UVDDPM)) { 113 PHM_PlatformCaps_UVDDPM)) {
114 cz_hwmgr->dpm_flags |= DPMFlags_UVD_Enabled; 114 cz_hwmgr->dpm_flags |= DPMFlags_UVD_Enabled;
115 dpm_features |= UVD_DPM_MASK; 115 dpm_features |= UVD_DPM_MASK;
116 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 116 smum_send_msg_to_smc_with_parameter(hwmgr,
117 PPSMC_MSG_EnableAllSmuFeatures, dpm_features); 117 PPSMC_MSG_EnableAllSmuFeatures, dpm_features);
118 } else { 118 } else {
119 dpm_features |= UVD_DPM_MASK; 119 dpm_features |= UVD_DPM_MASK;
120 cz_hwmgr->dpm_flags &= ~DPMFlags_UVD_Enabled; 120 cz_hwmgr->dpm_flags &= ~DPMFlags_UVD_Enabled;
121 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 121 smum_send_msg_to_smc_with_parameter(hwmgr,
122 PPSMC_MSG_DisableAllSmuFeatures, dpm_features); 122 PPSMC_MSG_DisableAllSmuFeatures, dpm_features);
123 } 123 }
124 return 0; 124 return 0;
@@ -134,12 +134,12 @@ int cz_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
134 PHM_PlatformCaps_VCEDPM)) { 134 PHM_PlatformCaps_VCEDPM)) {
135 cz_hwmgr->dpm_flags |= DPMFlags_VCE_Enabled; 135 cz_hwmgr->dpm_flags |= DPMFlags_VCE_Enabled;
136 dpm_features |= VCE_DPM_MASK; 136 dpm_features |= VCE_DPM_MASK;
137 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 137 smum_send_msg_to_smc_with_parameter(hwmgr,
138 PPSMC_MSG_EnableAllSmuFeatures, dpm_features); 138 PPSMC_MSG_EnableAllSmuFeatures, dpm_features);
139 } else { 139 } else {
140 dpm_features |= VCE_DPM_MASK; 140 dpm_features |= VCE_DPM_MASK;
141 cz_hwmgr->dpm_flags &= ~DPMFlags_VCE_Enabled; 141 cz_hwmgr->dpm_flags &= ~DPMFlags_VCE_Enabled;
142 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 142 smum_send_msg_to_smc_with_parameter(hwmgr,
143 PPSMC_MSG_DisableAllSmuFeatures, dpm_features); 143 PPSMC_MSG_DisableAllSmuFeatures, dpm_features);
144 } 144 }
145 145
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
index 045fdb3da056..73bb99d62a44 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
@@ -162,8 +162,8 @@ static uint32_t cz_get_max_sclk_level(struct pp_hwmgr *hwmgr)
162 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); 162 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
163 163
164 if (cz_hwmgr->max_sclk_level == 0) { 164 if (cz_hwmgr->max_sclk_level == 0) {
165 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxSclkLevel); 165 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxSclkLevel);
166 cz_hwmgr->max_sclk_level = smum_get_argument(hwmgr->smumgr) + 1; 166 cz_hwmgr->max_sclk_level = smum_get_argument(hwmgr) + 1;
167 } 167 }
168 168
169 return cz_hwmgr->max_sclk_level; 169 return cz_hwmgr->max_sclk_level;
@@ -462,7 +462,7 @@ static int cz_upload_pptable_to_smu(struct pp_hwmgr *hwmgr)
462 if (!hwmgr->need_pp_table_upload) 462 if (!hwmgr->need_pp_table_upload)
463 return 0; 463 return 0;
464 464
465 ret = smum_download_powerplay_table(hwmgr->smumgr, &table); 465 ret = smum_download_powerplay_table(hwmgr, &table);
466 466
467 PP_ASSERT_WITH_CODE((0 == ret && NULL != table), 467 PP_ASSERT_WITH_CODE((0 == ret && NULL != table),
468 "Fail to get clock table from SMU!", return -EINVAL;); 468 "Fail to get clock table from SMU!", return -EINVAL;);
@@ -554,7 +554,7 @@ static int cz_upload_pptable_to_smu(struct pp_hwmgr *hwmgr)
554 (uint8_t)dividers.pll_post_divider; 554 (uint8_t)dividers.pll_post_divider;
555 555
556 } 556 }
557 ret = smum_upload_powerplay_table(hwmgr->smumgr); 557 ret = smum_upload_powerplay_table(hwmgr);
558 558
559 return ret; 559 return ret;
560} 560}
@@ -598,8 +598,8 @@ static int cz_init_uvd_limit(struct pp_hwmgr *hwmgr)
598 cz_hwmgr->uvd_dpm.soft_min_clk = 0; 598 cz_hwmgr->uvd_dpm.soft_min_clk = 0;
599 cz_hwmgr->uvd_dpm.hard_min_clk = 0; 599 cz_hwmgr->uvd_dpm.hard_min_clk = 0;
600 600
601 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxUvdLevel); 601 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxUvdLevel);
602 level = smum_get_argument(hwmgr->smumgr); 602 level = smum_get_argument(hwmgr);
603 603
604 if (level < table->count) 604 if (level < table->count)
605 clock = table->entries[level].vclk; 605 clock = table->entries[level].vclk;
@@ -625,8 +625,8 @@ static int cz_init_vce_limit(struct pp_hwmgr *hwmgr)
625 cz_hwmgr->vce_dpm.soft_min_clk = 0; 625 cz_hwmgr->vce_dpm.soft_min_clk = 0;
626 cz_hwmgr->vce_dpm.hard_min_clk = 0; 626 cz_hwmgr->vce_dpm.hard_min_clk = 0;
627 627
628 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxEclkLevel); 628 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxEclkLevel);
629 level = smum_get_argument(hwmgr->smumgr); 629 level = smum_get_argument(hwmgr);
630 630
631 if (level < table->count) 631 if (level < table->count)
632 clock = table->entries[level].ecclk; 632 clock = table->entries[level].ecclk;
@@ -652,8 +652,8 @@ static int cz_init_acp_limit(struct pp_hwmgr *hwmgr)
652 cz_hwmgr->acp_dpm.soft_min_clk = 0; 652 cz_hwmgr->acp_dpm.soft_min_clk = 0;
653 cz_hwmgr->acp_dpm.hard_min_clk = 0; 653 cz_hwmgr->acp_dpm.hard_min_clk = 0;
654 654
655 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxAclkLevel); 655 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxAclkLevel);
656 level = smum_get_argument(hwmgr->smumgr); 656 level = smum_get_argument(hwmgr);
657 657
658 if (level < table->count) 658 if (level < table->count)
659 clock = table->entries[level].acpclk; 659 clock = table->entries[level].acpclk;
@@ -709,7 +709,7 @@ static int cz_update_sclk_limit(struct pp_hwmgr *hwmgr)
709 if (cz_hwmgr->sclk_dpm.hard_min_clk != clock) { 709 if (cz_hwmgr->sclk_dpm.hard_min_clk != clock) {
710 cz_hwmgr->sclk_dpm.hard_min_clk = clock; 710 cz_hwmgr->sclk_dpm.hard_min_clk = clock;
711 711
712 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 712 smum_send_msg_to_smc_with_parameter(hwmgr,
713 PPSMC_MSG_SetSclkHardMin, 713 PPSMC_MSG_SetSclkHardMin,
714 cz_get_sclk_level(hwmgr, 714 cz_get_sclk_level(hwmgr,
715 cz_hwmgr->sclk_dpm.hard_min_clk, 715 cz_hwmgr->sclk_dpm.hard_min_clk,
@@ -735,7 +735,7 @@ static int cz_update_sclk_limit(struct pp_hwmgr *hwmgr)
735 735
736 if (cz_hwmgr->sclk_dpm.soft_min_clk != clock) { 736 if (cz_hwmgr->sclk_dpm.soft_min_clk != clock) {
737 cz_hwmgr->sclk_dpm.soft_min_clk = clock; 737 cz_hwmgr->sclk_dpm.soft_min_clk = clock;
738 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 738 smum_send_msg_to_smc_with_parameter(hwmgr,
739 PPSMC_MSG_SetSclkSoftMin, 739 PPSMC_MSG_SetSclkSoftMin,
740 cz_get_sclk_level(hwmgr, 740 cz_get_sclk_level(hwmgr,
741 cz_hwmgr->sclk_dpm.soft_min_clk, 741 cz_hwmgr->sclk_dpm.soft_min_clk,
@@ -746,7 +746,7 @@ static int cz_update_sclk_limit(struct pp_hwmgr *hwmgr)
746 PHM_PlatformCaps_StablePState) && 746 PHM_PlatformCaps_StablePState) &&
747 cz_hwmgr->sclk_dpm.soft_max_clk != clock) { 747 cz_hwmgr->sclk_dpm.soft_max_clk != clock) {
748 cz_hwmgr->sclk_dpm.soft_max_clk = clock; 748 cz_hwmgr->sclk_dpm.soft_max_clk = clock;
749 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 749 smum_send_msg_to_smc_with_parameter(hwmgr,
750 PPSMC_MSG_SetSclkSoftMax, 750 PPSMC_MSG_SetSclkSoftMax,
751 cz_get_sclk_level(hwmgr, 751 cz_get_sclk_level(hwmgr,
752 cz_hwmgr->sclk_dpm.soft_max_clk, 752 cz_hwmgr->sclk_dpm.soft_max_clk,
@@ -766,7 +766,7 @@ static int cz_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr)
766 766
767 PP_DBG_LOG("Setting Deep Sleep Clock: %d\n", clks); 767 PP_DBG_LOG("Setting Deep Sleep Clock: %d\n", clks);
768 768
769 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 769 smum_send_msg_to_smc_with_parameter(hwmgr,
770 PPSMC_MSG_SetMinDeepSleepSclk, 770 PPSMC_MSG_SetMinDeepSleepSclk,
771 clks); 771 clks);
772 } 772 }
@@ -779,7 +779,7 @@ static int cz_set_watermark_threshold(struct pp_hwmgr *hwmgr)
779 struct cz_hwmgr *cz_hwmgr = 779 struct cz_hwmgr *cz_hwmgr =
780 (struct cz_hwmgr *)(hwmgr->backend); 780 (struct cz_hwmgr *)(hwmgr->backend);
781 781
782 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 782 smum_send_msg_to_smc_with_parameter(hwmgr,
783 PPSMC_MSG_SetWatermarkFrequency, 783 PPSMC_MSG_SetWatermarkFrequency,
784 cz_hwmgr->sclk_dpm.soft_max_clk); 784 cz_hwmgr->sclk_dpm.soft_max_clk);
785 785
@@ -794,13 +794,13 @@ static int cz_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, b
794 if (enable) { 794 if (enable) {
795 PP_DBG_LOG("enable Low Memory PState.\n"); 795 PP_DBG_LOG("enable Low Memory PState.\n");
796 796
797 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 797 return smum_send_msg_to_smc_with_parameter(hwmgr,
798 PPSMC_MSG_EnableLowMemoryPstate, 798 PPSMC_MSG_EnableLowMemoryPstate,
799 (lock ? 1 : 0)); 799 (lock ? 1 : 0));
800 } else { 800 } else {
801 PP_DBG_LOG("disable Low Memory PState.\n"); 801 PP_DBG_LOG("disable Low Memory PState.\n");
802 802
803 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 803 return smum_send_msg_to_smc_with_parameter(hwmgr,
804 PPSMC_MSG_DisableLowMemoryPstate, 804 PPSMC_MSG_DisableLowMemoryPstate,
805 (lock ? 1 : 0)); 805 (lock ? 1 : 0));
806 } 806 }
@@ -820,7 +820,7 @@ static int cz_disable_nb_dpm(struct pp_hwmgr *hwmgr)
820 cz_nbdpm_pstate_enable_disable(hwmgr, true, true); 820 cz_nbdpm_pstate_enable_disable(hwmgr, true, true);
821 dpm_features |= NB_DPM_MASK; 821 dpm_features |= NB_DPM_MASK;
822 ret = smum_send_msg_to_smc_with_parameter( 822 ret = smum_send_msg_to_smc_with_parameter(
823 hwmgr->smumgr, 823 hwmgr,
824 PPSMC_MSG_DisableAllSmuFeatures, 824 PPSMC_MSG_DisableAllSmuFeatures,
825 dpm_features); 825 dpm_features);
826 if (ret == 0) 826 if (ret == 0)
@@ -841,7 +841,7 @@ static int cz_enable_nb_dpm(struct pp_hwmgr *hwmgr)
841 PP_DBG_LOG("enabling ALL SMU features.\n"); 841 PP_DBG_LOG("enabling ALL SMU features.\n");
842 dpm_features |= NB_DPM_MASK; 842 dpm_features |= NB_DPM_MASK;
843 ret = smum_send_msg_to_smc_with_parameter( 843 ret = smum_send_msg_to_smc_with_parameter(
844 hwmgr->smumgr, 844 hwmgr,
845 PPSMC_MSG_EnableAllSmuFeatures, 845 PPSMC_MSG_EnableAllSmuFeatures,
846 dpm_features); 846 dpm_features);
847 if (ret == 0) 847 if (ret == 0)
@@ -968,7 +968,7 @@ static int cz_start_dpm(struct pp_hwmgr *hwmgr)
968 cz_hwmgr->dpm_flags |= DPMFlags_SCLK_Enabled; 968 cz_hwmgr->dpm_flags |= DPMFlags_SCLK_Enabled;
969 dpm_features |= SCLK_DPM_MASK; 969 dpm_features |= SCLK_DPM_MASK;
970 970
971 ret = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 971 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
972 PPSMC_MSG_EnableAllSmuFeatures, 972 PPSMC_MSG_EnableAllSmuFeatures,
973 dpm_features); 973 dpm_features);
974 974
@@ -984,7 +984,7 @@ static int cz_stop_dpm(struct pp_hwmgr *hwmgr)
984 if (cz_hwmgr->dpm_flags & DPMFlags_SCLK_Enabled) { 984 if (cz_hwmgr->dpm_flags & DPMFlags_SCLK_Enabled) {
985 dpm_features |= SCLK_DPM_MASK; 985 dpm_features |= SCLK_DPM_MASK;
986 cz_hwmgr->dpm_flags &= ~DPMFlags_SCLK_Enabled; 986 cz_hwmgr->dpm_flags &= ~DPMFlags_SCLK_Enabled;
987 ret = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 987 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
988 PPSMC_MSG_DisableAllSmuFeatures, 988 PPSMC_MSG_DisableAllSmuFeatures,
989 dpm_features); 989 dpm_features);
990 } 990 }
@@ -998,13 +998,13 @@ static int cz_program_bootup_state(struct pp_hwmgr *hwmgr)
998 cz_hwmgr->sclk_dpm.soft_min_clk = cz_hwmgr->sys_info.bootup_engine_clock; 998 cz_hwmgr->sclk_dpm.soft_min_clk = cz_hwmgr->sys_info.bootup_engine_clock;
999 cz_hwmgr->sclk_dpm.soft_max_clk = cz_hwmgr->sys_info.bootup_engine_clock; 999 cz_hwmgr->sclk_dpm.soft_max_clk = cz_hwmgr->sys_info.bootup_engine_clock;
1000 1000
1001 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 1001 smum_send_msg_to_smc_with_parameter(hwmgr,
1002 PPSMC_MSG_SetSclkSoftMin, 1002 PPSMC_MSG_SetSclkSoftMin,
1003 cz_get_sclk_level(hwmgr, 1003 cz_get_sclk_level(hwmgr,
1004 cz_hwmgr->sclk_dpm.soft_min_clk, 1004 cz_hwmgr->sclk_dpm.soft_min_clk,
1005 PPSMC_MSG_SetSclkSoftMin)); 1005 PPSMC_MSG_SetSclkSoftMin));
1006 1006
1007 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 1007 smum_send_msg_to_smc_with_parameter(hwmgr,
1008 PPSMC_MSG_SetSclkSoftMax, 1008 PPSMC_MSG_SetSclkSoftMax,
1009 cz_get_sclk_level(hwmgr, 1009 cz_get_sclk_level(hwmgr,
1010 cz_hwmgr->sclk_dpm.soft_max_clk, 1010 cz_hwmgr->sclk_dpm.soft_max_clk,
@@ -1026,9 +1026,9 @@ static bool cz_dpm_check_smu_features(struct pp_hwmgr *hwmgr,
1026 int result; 1026 int result;
1027 unsigned long features; 1027 unsigned long features;
1028 1028
1029 result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_GetFeatureStatus, 0); 1029 result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetFeatureStatus, 0);
1030 if (result == 0) { 1030 if (result == 0) {
1031 features = smum_get_argument(hwmgr->smumgr); 1031 features = smum_get_argument(hwmgr);
1032 if (features & check_feature) 1032 if (features & check_feature)
1033 return true; 1033 return true;
1034 } 1034 }
@@ -1178,13 +1178,13 @@ static int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr)
1178{ 1178{
1179 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); 1179 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1180 1180
1181 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 1181 smum_send_msg_to_smc_with_parameter(hwmgr,
1182 PPSMC_MSG_SetSclkSoftMin, 1182 PPSMC_MSG_SetSclkSoftMin,
1183 cz_get_sclk_level(hwmgr, 1183 cz_get_sclk_level(hwmgr,
1184 cz_hwmgr->sclk_dpm.soft_max_clk, 1184 cz_hwmgr->sclk_dpm.soft_max_clk,
1185 PPSMC_MSG_SetSclkSoftMin)); 1185 PPSMC_MSG_SetSclkSoftMin));
1186 1186
1187 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 1187 smum_send_msg_to_smc_with_parameter(hwmgr,
1188 PPSMC_MSG_SetSclkSoftMax, 1188 PPSMC_MSG_SetSclkSoftMax,
1189 cz_get_sclk_level(hwmgr, 1189 cz_get_sclk_level(hwmgr,
1190 cz_hwmgr->sclk_dpm.soft_max_clk, 1190 cz_hwmgr->sclk_dpm.soft_max_clk,
@@ -1216,13 +1216,13 @@ static int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
1216 cz_hwmgr->sclk_dpm.soft_max_clk = clock; 1216 cz_hwmgr->sclk_dpm.soft_max_clk = clock;
1217 cz_hwmgr->sclk_dpm.hard_max_clk = clock; 1217 cz_hwmgr->sclk_dpm.hard_max_clk = clock;
1218 1218
1219 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 1219 smum_send_msg_to_smc_with_parameter(hwmgr,
1220 PPSMC_MSG_SetSclkSoftMin, 1220 PPSMC_MSG_SetSclkSoftMin,
1221 cz_get_sclk_level(hwmgr, 1221 cz_get_sclk_level(hwmgr,
1222 cz_hwmgr->sclk_dpm.soft_min_clk, 1222 cz_hwmgr->sclk_dpm.soft_min_clk,
1223 PPSMC_MSG_SetSclkSoftMin)); 1223 PPSMC_MSG_SetSclkSoftMin));
1224 1224
1225 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 1225 smum_send_msg_to_smc_with_parameter(hwmgr,
1226 PPSMC_MSG_SetSclkSoftMax, 1226 PPSMC_MSG_SetSclkSoftMax,
1227 cz_get_sclk_level(hwmgr, 1227 cz_get_sclk_level(hwmgr,
1228 cz_hwmgr->sclk_dpm.soft_max_clk, 1228 cz_hwmgr->sclk_dpm.soft_max_clk,
@@ -1235,13 +1235,13 @@ static int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr)
1235{ 1235{
1236 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); 1236 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1237 1237
1238 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 1238 smum_send_msg_to_smc_with_parameter(hwmgr,
1239 PPSMC_MSG_SetSclkSoftMax, 1239 PPSMC_MSG_SetSclkSoftMax,
1240 cz_get_sclk_level(hwmgr, 1240 cz_get_sclk_level(hwmgr,
1241 cz_hwmgr->sclk_dpm.soft_min_clk, 1241 cz_hwmgr->sclk_dpm.soft_min_clk,
1242 PPSMC_MSG_SetSclkSoftMax)); 1242 PPSMC_MSG_SetSclkSoftMax));
1243 1243
1244 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 1244 smum_send_msg_to_smc_with_parameter(hwmgr,
1245 PPSMC_MSG_SetSclkSoftMin, 1245 PPSMC_MSG_SetSclkSoftMin,
1246 cz_get_sclk_level(hwmgr, 1246 cz_get_sclk_level(hwmgr,
1247 cz_hwmgr->sclk_dpm.soft_min_clk, 1247 cz_hwmgr->sclk_dpm.soft_min_clk,
@@ -1281,7 +1281,7 @@ int cz_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr)
1281{ 1281{
1282 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1282 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1283 PHM_PlatformCaps_UVDPowerGating)) 1283 PHM_PlatformCaps_UVDPowerGating))
1284 return smum_send_msg_to_smc(hwmgr->smumgr, 1284 return smum_send_msg_to_smc(hwmgr,
1285 PPSMC_MSG_UVDPowerOFF); 1285 PPSMC_MSG_UVDPowerOFF);
1286 return 0; 1286 return 0;
1287} 1287}
@@ -1293,11 +1293,11 @@ int cz_dpm_powerup_uvd(struct pp_hwmgr *hwmgr)
1293 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1293 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1294 PHM_PlatformCaps_UVDDynamicPowerGating)) { 1294 PHM_PlatformCaps_UVDDynamicPowerGating)) {
1295 return smum_send_msg_to_smc_with_parameter( 1295 return smum_send_msg_to_smc_with_parameter(
1296 hwmgr->smumgr, 1296 hwmgr,
1297 PPSMC_MSG_UVDPowerON, 1); 1297 PPSMC_MSG_UVDPowerON, 1);
1298 } else { 1298 } else {
1299 return smum_send_msg_to_smc_with_parameter( 1299 return smum_send_msg_to_smc_with_parameter(
1300 hwmgr->smumgr, 1300 hwmgr,
1301 PPSMC_MSG_UVDPowerON, 0); 1301 PPSMC_MSG_UVDPowerON, 0);
1302 } 1302 }
1303 } 1303 }
@@ -1319,7 +1319,7 @@ int cz_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
1319 cz_hwmgr->uvd_dpm.hard_min_clk = 1319 cz_hwmgr->uvd_dpm.hard_min_clk =
1320 ptable->entries[ptable->count - 1].vclk; 1320 ptable->entries[ptable->count - 1].vclk;
1321 1321
1322 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 1322 smum_send_msg_to_smc_with_parameter(hwmgr,
1323 PPSMC_MSG_SetUvdHardMin, 1323 PPSMC_MSG_SetUvdHardMin,
1324 cz_get_uvd_level(hwmgr, 1324 cz_get_uvd_level(hwmgr,
1325 cz_hwmgr->uvd_dpm.hard_min_clk, 1325 cz_hwmgr->uvd_dpm.hard_min_clk,
@@ -1349,7 +1349,7 @@ int cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr)
1349 cz_hwmgr->vce_dpm.hard_min_clk = 1349 cz_hwmgr->vce_dpm.hard_min_clk =
1350 ptable->entries[ptable->count - 1].ecclk; 1350 ptable->entries[ptable->count - 1].ecclk;
1351 1351
1352 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 1352 smum_send_msg_to_smc_with_parameter(hwmgr,
1353 PPSMC_MSG_SetEclkHardMin, 1353 PPSMC_MSG_SetEclkHardMin,
1354 cz_get_eclk_level(hwmgr, 1354 cz_get_eclk_level(hwmgr,
1355 cz_hwmgr->vce_dpm.hard_min_clk, 1355 cz_hwmgr->vce_dpm.hard_min_clk,
@@ -1357,15 +1357,15 @@ int cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr)
1357 } else { 1357 } else {
1358 /*Program HardMin based on the vce_arbiter.ecclk */ 1358 /*Program HardMin based on the vce_arbiter.ecclk */
1359 if (hwmgr->vce_arbiter.ecclk == 0) { 1359 if (hwmgr->vce_arbiter.ecclk == 0) {
1360 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 1360 smum_send_msg_to_smc_with_parameter(hwmgr,
1361 PPSMC_MSG_SetEclkHardMin, 0); 1361 PPSMC_MSG_SetEclkHardMin, 0);
1362 /* disable ECLK DPM 0. Otherwise VCE could hang if 1362 /* disable ECLK DPM 0. Otherwise VCE could hang if
1363 * switching SCLK from DPM 0 to 6/7 */ 1363 * switching SCLK from DPM 0 to 6/7 */
1364 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 1364 smum_send_msg_to_smc_with_parameter(hwmgr,
1365 PPSMC_MSG_SetEclkSoftMin, 1); 1365 PPSMC_MSG_SetEclkSoftMin, 1);
1366 } else { 1366 } else {
1367 cz_hwmgr->vce_dpm.hard_min_clk = hwmgr->vce_arbiter.ecclk; 1367 cz_hwmgr->vce_dpm.hard_min_clk = hwmgr->vce_arbiter.ecclk;
1368 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 1368 smum_send_msg_to_smc_with_parameter(hwmgr,
1369 PPSMC_MSG_SetEclkHardMin, 1369 PPSMC_MSG_SetEclkHardMin,
1370 cz_get_eclk_level(hwmgr, 1370 cz_get_eclk_level(hwmgr,
1371 cz_hwmgr->vce_dpm.hard_min_clk, 1371 cz_hwmgr->vce_dpm.hard_min_clk,
@@ -1379,7 +1379,7 @@ int cz_dpm_powerdown_vce(struct pp_hwmgr *hwmgr)
1379{ 1379{
1380 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1380 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1381 PHM_PlatformCaps_VCEPowerGating)) 1381 PHM_PlatformCaps_VCEPowerGating))
1382 return smum_send_msg_to_smc(hwmgr->smumgr, 1382 return smum_send_msg_to_smc(hwmgr,
1383 PPSMC_MSG_VCEPowerOFF); 1383 PPSMC_MSG_VCEPowerOFF);
1384 return 0; 1384 return 0;
1385} 1385}
@@ -1388,7 +1388,7 @@ int cz_dpm_powerup_vce(struct pp_hwmgr *hwmgr)
1388{ 1388{
1389 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1389 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1390 PHM_PlatformCaps_VCEPowerGating)) 1390 PHM_PlatformCaps_VCEPowerGating))
1391 return smum_send_msg_to_smc(hwmgr->smumgr, 1391 return smum_send_msg_to_smc(hwmgr,
1392 PPSMC_MSG_VCEPowerON); 1392 PPSMC_MSG_VCEPowerON);
1393 return 0; 1393 return 0;
1394} 1394}
@@ -1538,7 +1538,7 @@ static void cz_hw_print_display_cfg(
1538 PP_DBG_LOG("SetDisplaySizePowerParams data: 0x%X\n", 1538 PP_DBG_LOG("SetDisplaySizePowerParams data: 0x%X\n",
1539 data); 1539 data);
1540 1540
1541 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 1541 smum_send_msg_to_smc_with_parameter(hwmgr,
1542 PPSMC_MSG_SetDisplaySizePowerParams, 1542 PPSMC_MSG_SetDisplaySizePowerParams,
1543 data); 1543 data);
1544 } 1544 }
@@ -1603,10 +1603,10 @@ static int cz_force_clock_level(struct pp_hwmgr *hwmgr,
1603 1603
1604 switch (type) { 1604 switch (type) {
1605 case PP_SCLK: 1605 case PP_SCLK:
1606 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 1606 smum_send_msg_to_smc_with_parameter(hwmgr,
1607 PPSMC_MSG_SetSclkSoftMin, 1607 PPSMC_MSG_SetSclkSoftMin,
1608 mask); 1608 mask);
1609 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 1609 smum_send_msg_to_smc_with_parameter(hwmgr,
1610 PPSMC_MSG_SetSclkSoftMax, 1610 PPSMC_MSG_SetSclkSoftMax,
1611 mask); 1611 mask);
1612 break; 1612 break;
@@ -1848,7 +1848,7 @@ static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx,
1848 *((uint32_t *)value) = 0; 1848 *((uint32_t *)value) = 0;
1849 return 0; 1849 return 0;
1850 case AMDGPU_PP_SENSOR_GPU_LOAD: 1850 case AMDGPU_PP_SENSOR_GPU_LOAD:
1851 result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetAverageGraphicsActivity); 1851 result = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetAverageGraphicsActivity);
1852 if (0 == result) { 1852 if (0 == result) {
1853 activity_percent = cgs_read_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0); 1853 activity_percent = cgs_read_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0);
1854 activity_percent = activity_percent > 100 ? 100 : activity_percent; 1854 activity_percent = activity_percent > 100 ? 100 : activity_percent;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 3f7cf559c81f..16101c392c3b 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -818,7 +818,7 @@ void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr)
818 for (i = 0; i < vddc_table->count; i++) { 818 for (i = 0; i < vddc_table->count; i++) {
819 if (req_vddc <= vddc_table->entries[i].vddc) { 819 if (req_vddc <= vddc_table->entries[i].vddc) {
820 req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE); 820 req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE);
821 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 821 smum_send_msg_to_smc_with_parameter(hwmgr,
822 PPSMC_MSG_VddC_Request, req_volt); 822 PPSMC_MSG_VddC_Request, req_volt);
823 return; 823 return;
824 } 824 }
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
index 603035a5a4db..9186b0788fac 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
@@ -174,33 +174,33 @@ static int rv_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input)
174 ((hwmgr->uvd_arbiter.dclk_soft_min / 100) != rv_data->dclk_soft_min)) { 174 ((hwmgr->uvd_arbiter.dclk_soft_min / 100) != rv_data->dclk_soft_min)) {
175 rv_data->vclk_soft_min = hwmgr->uvd_arbiter.vclk_soft_min / 100; 175 rv_data->vclk_soft_min = hwmgr->uvd_arbiter.vclk_soft_min / 100;
176 rv_data->dclk_soft_min = hwmgr->uvd_arbiter.dclk_soft_min / 100; 176 rv_data->dclk_soft_min = hwmgr->uvd_arbiter.dclk_soft_min / 100;
177 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 177 smum_send_msg_to_smc_with_parameter(hwmgr,
178 PPSMC_MSG_SetSoftMinVcn, 178 PPSMC_MSG_SetSoftMinVcn,
179 (rv_data->vclk_soft_min << 16) | rv_data->vclk_soft_min); 179 (rv_data->vclk_soft_min << 16) | rv_data->vclk_soft_min);
180 } 180 }
181 181
182 if((hwmgr->gfx_arbiter.sclk_hard_min != 0) && 182 if((hwmgr->gfx_arbiter.sclk_hard_min != 0) &&
183 ((hwmgr->gfx_arbiter.sclk_hard_min / 100) != rv_data->soc_actual_hard_min_freq)) { 183 ((hwmgr->gfx_arbiter.sclk_hard_min / 100) != rv_data->soc_actual_hard_min_freq)) {
184 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 184 smum_send_msg_to_smc_with_parameter(hwmgr,
185 PPSMC_MSG_SetHardMinSocclkByFreq, 185 PPSMC_MSG_SetHardMinSocclkByFreq,
186 hwmgr->gfx_arbiter.sclk_hard_min / 100); 186 hwmgr->gfx_arbiter.sclk_hard_min / 100);
187 rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->soc_actual_hard_min_freq); 187 rv_read_arg_from_smc(hwmgr, &rv_data->soc_actual_hard_min_freq);
188 } 188 }
189 189
190 if ((hwmgr->gfx_arbiter.gfxclk != 0) && 190 if ((hwmgr->gfx_arbiter.gfxclk != 0) &&
191 (rv_data->gfx_actual_soft_min_freq != (hwmgr->gfx_arbiter.gfxclk))) { 191 (rv_data->gfx_actual_soft_min_freq != (hwmgr->gfx_arbiter.gfxclk))) {
192 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 192 smum_send_msg_to_smc_with_parameter(hwmgr,
193 PPSMC_MSG_SetMinVideoGfxclkFreq, 193 PPSMC_MSG_SetMinVideoGfxclkFreq,
194 hwmgr->gfx_arbiter.gfxclk / 100); 194 hwmgr->gfx_arbiter.gfxclk / 100);
195 rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->gfx_actual_soft_min_freq); 195 rv_read_arg_from_smc(hwmgr, &rv_data->gfx_actual_soft_min_freq);
196 } 196 }
197 197
198 if ((hwmgr->gfx_arbiter.fclk != 0) && 198 if ((hwmgr->gfx_arbiter.fclk != 0) &&
199 (rv_data->fabric_actual_soft_min_freq != (hwmgr->gfx_arbiter.fclk / 100))) { 199 (rv_data->fabric_actual_soft_min_freq != (hwmgr->gfx_arbiter.fclk / 100))) {
200 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 200 smum_send_msg_to_smc_with_parameter(hwmgr,
201 PPSMC_MSG_SetMinVideoFclkFreq, 201 PPSMC_MSG_SetMinVideoFclkFreq,
202 hwmgr->gfx_arbiter.fclk / 100); 202 hwmgr->gfx_arbiter.fclk / 100);
203 rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->fabric_actual_soft_min_freq); 203 rv_read_arg_from_smc(hwmgr, &rv_data->fabric_actual_soft_min_freq);
204 } 204 }
205 205
206 return 0; 206 return 0;
@@ -212,7 +212,7 @@ static int rv_set_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock)
212 212
213 if (rv_data->need_min_deep_sleep_dcefclk && rv_data->deep_sleep_dcefclk != clock/100) { 213 if (rv_data->need_min_deep_sleep_dcefclk && rv_data->deep_sleep_dcefclk != clock/100) {
214 rv_data->deep_sleep_dcefclk = clock/100; 214 rv_data->deep_sleep_dcefclk = clock/100;
215 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 215 smum_send_msg_to_smc_with_parameter(hwmgr,
216 PPSMC_MSG_SetMinDeepSleepDcefclk, 216 PPSMC_MSG_SetMinDeepSleepDcefclk,
217 rv_data->deep_sleep_dcefclk); 217 rv_data->deep_sleep_dcefclk);
218 } 218 }
@@ -225,7 +225,7 @@ static int rv_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count)
225 225
226 if (rv_data->num_active_display != count) { 226 if (rv_data->num_active_display != count) {
227 rv_data->num_active_display = count; 227 rv_data->num_active_display = count;
228 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 228 smum_send_msg_to_smc_with_parameter(hwmgr,
229 PPSMC_MSG_SetDisplayCount, 229 PPSMC_MSG_SetDisplayCount,
230 rv_data->num_active_display); 230 rv_data->num_active_display);
231 } 231 }
@@ -277,7 +277,7 @@ static int rv_disable_gfx_off(struct pp_hwmgr *hwmgr)
277 struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend); 277 struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
278 278
279 if (rv_data->gfx_off_controled_by_driver) 279 if (rv_data->gfx_off_controled_by_driver)
280 smum_send_msg_to_smc(hwmgr->smumgr, 280 smum_send_msg_to_smc(hwmgr,
281 PPSMC_MSG_DisableGfxOff); 281 PPSMC_MSG_DisableGfxOff);
282 282
283 return 0; 283 return 0;
@@ -293,7 +293,7 @@ static int rv_enable_gfx_off(struct pp_hwmgr *hwmgr)
293 struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend); 293 struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
294 294
295 if (rv_data->gfx_off_controled_by_driver) 295 if (rv_data->gfx_off_controled_by_driver)
296 smum_send_msg_to_smc(hwmgr->smumgr, 296 smum_send_msg_to_smc(hwmgr,
297 PPSMC_MSG_EnableGfxOff); 297 PPSMC_MSG_EnableGfxOff);
298 298
299 return 0; 299 return 0;
@@ -383,7 +383,7 @@ static int rv_populate_clock_table(struct pp_hwmgr *hwmgr)
383 DpmClocks_t *table = &(rv_data->clock_table); 383 DpmClocks_t *table = &(rv_data->clock_table);
384 struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info); 384 struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info);
385 385
386 result = rv_copy_table_from_smc(hwmgr->smumgr, (uint8_t *)table, CLOCKTABLE); 386 result = rv_copy_table_from_smc(hwmgr, (uint8_t *)table, CLOCKTABLE);
387 387
388 PP_ASSERT_WITH_CODE((0 == result), 388 PP_ASSERT_WITH_CODE((0 == result),
389 "Attempt to copy clock table from smc failed", 389 "Attempt to copy clock table from smc failed",
@@ -799,7 +799,7 @@ int rv_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
799 return -EINVAL; 799 return -EINVAL;
800 } 800 }
801 801
802 result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, msg, 802 result = smum_send_msg_to_smc_with_parameter(hwmgr, msg,
803 clk_freq); 803 clk_freq);
804 804
805 return result; 805 return result;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
index 48f60dedac2b..69a0678ace98 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
@@ -27,21 +27,21 @@
27 27
28static int smu7_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) 28static int smu7_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
29{ 29{
30 return smum_send_msg_to_smc(hwmgr->smumgr, enable ? 30 return smum_send_msg_to_smc(hwmgr, enable ?
31 PPSMC_MSG_UVDDPM_Enable : 31 PPSMC_MSG_UVDDPM_Enable :
32 PPSMC_MSG_UVDDPM_Disable); 32 PPSMC_MSG_UVDDPM_Disable);
33} 33}
34 34
35static int smu7_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) 35static int smu7_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
36{ 36{
37 return smum_send_msg_to_smc(hwmgr->smumgr, enable ? 37 return smum_send_msg_to_smc(hwmgr, enable ?
38 PPSMC_MSG_VCEDPM_Enable : 38 PPSMC_MSG_VCEDPM_Enable :
39 PPSMC_MSG_VCEDPM_Disable); 39 PPSMC_MSG_VCEDPM_Disable);
40} 40}
41 41
42static int smu7_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable) 42static int smu7_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
43{ 43{
44 return smum_send_msg_to_smc(hwmgr->smumgr, enable ? 44 return smum_send_msg_to_smc(hwmgr, enable ?
45 PPSMC_MSG_SAMUDPM_Enable : 45 PPSMC_MSG_SAMUDPM_Enable :
46 PPSMC_MSG_SAMUDPM_Disable); 46 PPSMC_MSG_SAMUDPM_Disable);
47} 47}
@@ -70,7 +70,7 @@ static int smu7_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
70int smu7_powerdown_uvd(struct pp_hwmgr *hwmgr) 70int smu7_powerdown_uvd(struct pp_hwmgr *hwmgr)
71{ 71{
72 if (phm_cf_want_uvd_power_gating(hwmgr)) 72 if (phm_cf_want_uvd_power_gating(hwmgr))
73 return smum_send_msg_to_smc(hwmgr->smumgr, 73 return smum_send_msg_to_smc(hwmgr,
74 PPSMC_MSG_UVDPowerOFF); 74 PPSMC_MSG_UVDPowerOFF);
75 return 0; 75 return 0;
76} 76}
@@ -80,10 +80,10 @@ static int smu7_powerup_uvd(struct pp_hwmgr *hwmgr)
80 if (phm_cf_want_uvd_power_gating(hwmgr)) { 80 if (phm_cf_want_uvd_power_gating(hwmgr)) {
81 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 81 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
82 PHM_PlatformCaps_UVDDynamicPowerGating)) { 82 PHM_PlatformCaps_UVDDynamicPowerGating)) {
83 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 83 return smum_send_msg_to_smc_with_parameter(hwmgr,
84 PPSMC_MSG_UVDPowerON, 1); 84 PPSMC_MSG_UVDPowerON, 1);
85 } else { 85 } else {
86 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 86 return smum_send_msg_to_smc_with_parameter(hwmgr,
87 PPSMC_MSG_UVDPowerON, 0); 87 PPSMC_MSG_UVDPowerON, 0);
88 } 88 }
89 } 89 }
@@ -94,7 +94,7 @@ static int smu7_powerup_uvd(struct pp_hwmgr *hwmgr)
94static int smu7_powerdown_vce(struct pp_hwmgr *hwmgr) 94static int smu7_powerdown_vce(struct pp_hwmgr *hwmgr)
95{ 95{
96 if (phm_cf_want_vce_power_gating(hwmgr)) 96 if (phm_cf_want_vce_power_gating(hwmgr))
97 return smum_send_msg_to_smc(hwmgr->smumgr, 97 return smum_send_msg_to_smc(hwmgr,
98 PPSMC_MSG_VCEPowerOFF); 98 PPSMC_MSG_VCEPowerOFF);
99 return 0; 99 return 0;
100} 100}
@@ -102,7 +102,7 @@ static int smu7_powerdown_vce(struct pp_hwmgr *hwmgr)
102static int smu7_powerup_vce(struct pp_hwmgr *hwmgr) 102static int smu7_powerup_vce(struct pp_hwmgr *hwmgr)
103{ 103{
104 if (phm_cf_want_vce_power_gating(hwmgr)) 104 if (phm_cf_want_vce_power_gating(hwmgr))
105 return smum_send_msg_to_smc(hwmgr->smumgr, 105 return smum_send_msg_to_smc(hwmgr,
106 PPSMC_MSG_VCEPowerON); 106 PPSMC_MSG_VCEPowerON);
107 return 0; 107 return 0;
108} 108}
@@ -111,7 +111,7 @@ static int smu7_powerdown_samu(struct pp_hwmgr *hwmgr)
111{ 111{
112 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 112 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
113 PHM_PlatformCaps_SamuPowerGating)) 113 PHM_PlatformCaps_SamuPowerGating))
114 return smum_send_msg_to_smc(hwmgr->smumgr, 114 return smum_send_msg_to_smc(hwmgr,
115 PPSMC_MSG_SAMPowerOFF); 115 PPSMC_MSG_SAMPowerOFF);
116 return 0; 116 return 0;
117} 117}
@@ -120,7 +120,7 @@ static int smu7_powerup_samu(struct pp_hwmgr *hwmgr)
120{ 120{
121 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 121 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
122 PHM_PlatformCaps_SamuPowerGating)) 122 PHM_PlatformCaps_SamuPowerGating))
123 return smum_send_msg_to_smc(hwmgr->smumgr, 123 return smum_send_msg_to_smc(hwmgr,
124 PPSMC_MSG_SAMPowerON); 124 PPSMC_MSG_SAMPowerON);
125 return 0; 125 return 0;
126} 126}
@@ -235,7 +235,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
235 value = CG_GFX_CGCG_MASK; 235 value = CG_GFX_CGCG_MASK;
236 236
237 if (smum_send_msg_to_smc_with_parameter( 237 if (smum_send_msg_to_smc_with_parameter(
238 hwmgr->smumgr, msg, value)) 238 hwmgr, msg, value))
239 return -EINVAL; 239 return -EINVAL;
240 } 240 }
241 if (PP_STATE_SUPPORT_LS & *msg_id) { 241 if (PP_STATE_SUPPORT_LS & *msg_id) {
@@ -245,7 +245,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
245 value = CG_GFX_CGLS_MASK; 245 value = CG_GFX_CGLS_MASK;
246 246
247 if (smum_send_msg_to_smc_with_parameter( 247 if (smum_send_msg_to_smc_with_parameter(
248 hwmgr->smumgr, msg, value)) 248 hwmgr, msg, value))
249 return -EINVAL; 249 return -EINVAL;
250 } 250 }
251 break; 251 break;
@@ -258,7 +258,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
258 value = CG_GFX_3DCG_MASK; 258 value = CG_GFX_3DCG_MASK;
259 259
260 if (smum_send_msg_to_smc_with_parameter( 260 if (smum_send_msg_to_smc_with_parameter(
261 hwmgr->smumgr, msg, value)) 261 hwmgr, msg, value))
262 return -EINVAL; 262 return -EINVAL;
263 } 263 }
264 264
@@ -269,7 +269,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
269 value = CG_GFX_3DLS_MASK; 269 value = CG_GFX_3DLS_MASK;
270 270
271 if (smum_send_msg_to_smc_with_parameter( 271 if (smum_send_msg_to_smc_with_parameter(
272 hwmgr->smumgr, msg, value)) 272 hwmgr, msg, value))
273 return -EINVAL; 273 return -EINVAL;
274 } 274 }
275 break; 275 break;
@@ -282,7 +282,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
282 value = CG_GFX_RLC_LS_MASK; 282 value = CG_GFX_RLC_LS_MASK;
283 283
284 if (smum_send_msg_to_smc_with_parameter( 284 if (smum_send_msg_to_smc_with_parameter(
285 hwmgr->smumgr, msg, value)) 285 hwmgr, msg, value))
286 return -EINVAL; 286 return -EINVAL;
287 } 287 }
288 break; 288 break;
@@ -295,7 +295,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
295 value = CG_GFX_CP_LS_MASK; 295 value = CG_GFX_CP_LS_MASK;
296 296
297 if (smum_send_msg_to_smc_with_parameter( 297 if (smum_send_msg_to_smc_with_parameter(
298 hwmgr->smumgr, msg, value)) 298 hwmgr, msg, value))
299 return -EINVAL; 299 return -EINVAL;
300 } 300 }
301 break; 301 break;
@@ -309,7 +309,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
309 CG_GFX_OTHERS_MGCG_MASK); 309 CG_GFX_OTHERS_MGCG_MASK);
310 310
311 if (smum_send_msg_to_smc_with_parameter( 311 if (smum_send_msg_to_smc_with_parameter(
312 hwmgr->smumgr, msg, value)) 312 hwmgr, msg, value))
313 return -EINVAL; 313 return -EINVAL;
314 } 314 }
315 break; 315 break;
@@ -329,7 +329,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
329 value = CG_SYS_BIF_MGCG_MASK; 329 value = CG_SYS_BIF_MGCG_MASK;
330 330
331 if (smum_send_msg_to_smc_with_parameter( 331 if (smum_send_msg_to_smc_with_parameter(
332 hwmgr->smumgr, msg, value)) 332 hwmgr, msg, value))
333 return -EINVAL; 333 return -EINVAL;
334 } 334 }
335 if (PP_STATE_SUPPORT_LS & *msg_id) { 335 if (PP_STATE_SUPPORT_LS & *msg_id) {
@@ -339,7 +339,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
339 value = CG_SYS_BIF_MGLS_MASK; 339 value = CG_SYS_BIF_MGLS_MASK;
340 340
341 if (smum_send_msg_to_smc_with_parameter( 341 if (smum_send_msg_to_smc_with_parameter(
342 hwmgr->smumgr, msg, value)) 342 hwmgr, msg, value))
343 return -EINVAL; 343 return -EINVAL;
344 } 344 }
345 break; 345 break;
@@ -352,7 +352,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
352 value = CG_SYS_MC_MGCG_MASK; 352 value = CG_SYS_MC_MGCG_MASK;
353 353
354 if (smum_send_msg_to_smc_with_parameter( 354 if (smum_send_msg_to_smc_with_parameter(
355 hwmgr->smumgr, msg, value)) 355 hwmgr, msg, value))
356 return -EINVAL; 356 return -EINVAL;
357 } 357 }
358 358
@@ -363,7 +363,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
363 value = CG_SYS_MC_MGLS_MASK; 363 value = CG_SYS_MC_MGLS_MASK;
364 364
365 if (smum_send_msg_to_smc_with_parameter( 365 if (smum_send_msg_to_smc_with_parameter(
366 hwmgr->smumgr, msg, value)) 366 hwmgr, msg, value))
367 return -EINVAL; 367 return -EINVAL;
368 } 368 }
369 break; 369 break;
@@ -376,7 +376,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
376 value = CG_SYS_DRM_MGCG_MASK; 376 value = CG_SYS_DRM_MGCG_MASK;
377 377
378 if (smum_send_msg_to_smc_with_parameter( 378 if (smum_send_msg_to_smc_with_parameter(
379 hwmgr->smumgr, msg, value)) 379 hwmgr, msg, value))
380 return -EINVAL; 380 return -EINVAL;
381 } 381 }
382 if (PP_STATE_SUPPORT_LS & *msg_id) { 382 if (PP_STATE_SUPPORT_LS & *msg_id) {
@@ -386,7 +386,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
386 value = CG_SYS_DRM_MGLS_MASK; 386 value = CG_SYS_DRM_MGLS_MASK;
387 387
388 if (smum_send_msg_to_smc_with_parameter( 388 if (smum_send_msg_to_smc_with_parameter(
389 hwmgr->smumgr, msg, value)) 389 hwmgr, msg, value))
390 return -EINVAL; 390 return -EINVAL;
391 } 391 }
392 break; 392 break;
@@ -399,7 +399,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
399 value = CG_SYS_HDP_MGCG_MASK; 399 value = CG_SYS_HDP_MGCG_MASK;
400 400
401 if (smum_send_msg_to_smc_with_parameter( 401 if (smum_send_msg_to_smc_with_parameter(
402 hwmgr->smumgr, msg, value)) 402 hwmgr, msg, value))
403 return -EINVAL; 403 return -EINVAL;
404 } 404 }
405 405
@@ -410,7 +410,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
410 value = CG_SYS_HDP_MGLS_MASK; 410 value = CG_SYS_HDP_MGLS_MASK;
411 411
412 if (smum_send_msg_to_smc_with_parameter( 412 if (smum_send_msg_to_smc_with_parameter(
413 hwmgr->smumgr, msg, value)) 413 hwmgr, msg, value))
414 return -EINVAL; 414 return -EINVAL;
415 } 415 }
416 break; 416 break;
@@ -423,7 +423,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
423 value = CG_SYS_SDMA_MGCG_MASK; 423 value = CG_SYS_SDMA_MGCG_MASK;
424 424
425 if (smum_send_msg_to_smc_with_parameter( 425 if (smum_send_msg_to_smc_with_parameter(
426 hwmgr->smumgr, msg, value)) 426 hwmgr, msg, value))
427 return -EINVAL; 427 return -EINVAL;
428 } 428 }
429 429
@@ -434,7 +434,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
434 value = CG_SYS_SDMA_MGLS_MASK; 434 value = CG_SYS_SDMA_MGLS_MASK;
435 435
436 if (smum_send_msg_to_smc_with_parameter( 436 if (smum_send_msg_to_smc_with_parameter(
437 hwmgr->smumgr, msg, value)) 437 hwmgr, msg, value))
438 return -EINVAL; 438 return -EINVAL;
439 } 439 }
440 break; 440 break;
@@ -447,7 +447,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
447 value = CG_SYS_ROM_MASK; 447 value = CG_SYS_ROM_MASK;
448 448
449 if (smum_send_msg_to_smc_with_parameter( 449 if (smum_send_msg_to_smc_with_parameter(
450 hwmgr->smumgr, msg, value)) 450 hwmgr, msg, value))
451 return -EINVAL; 451 return -EINVAL;
452 } 452 }
453 break; 453 break;
@@ -487,9 +487,9 @@ int smu7_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable)
487 active_cus = sys_info.value; 487 active_cus = sys_info.value;
488 488
489 if (enable) 489 if (enable)
490 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 490 return smum_send_msg_to_smc_with_parameter(hwmgr,
491 PPSMC_MSG_GFX_CU_PG_ENABLE, active_cus); 491 PPSMC_MSG_GFX_CU_PG_ENABLE, active_cus);
492 else 492 else
493 return smum_send_msg_to_smc(hwmgr->smumgr, 493 return smum_send_msg_to_smc(hwmgr,
494 PPSMC_MSG_GFX_CU_PG_DISABLE); 494 PPSMC_MSG_GFX_CU_PG_DISABLE);
495} 495}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 4c603e53a171..bc2f227559cd 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -164,7 +164,7 @@ static int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
164static int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr) 164static int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
165{ 165{
166 if (hwmgr->feature_mask & PP_SMC_VOLTAGE_CONTROL_MASK) 166 if (hwmgr->feature_mask & PP_SMC_VOLTAGE_CONTROL_MASK)
167 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable); 167 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Enable);
168 168
169 return 0; 169 return 0;
170} 170}
@@ -301,28 +301,28 @@ static int smu7_construct_voltage_tables(struct pp_hwmgr *hwmgr)
301 "Failed to retrieve SVI2 VDDC table from dependancy table.", return result;); 301 "Failed to retrieve SVI2 VDDC table from dependancy table.", return result;);
302 } 302 }
303 303
304 tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_VDDC); 304 tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDC);
305 PP_ASSERT_WITH_CODE( 305 PP_ASSERT_WITH_CODE(
306 (data->vddc_voltage_table.count <= tmp), 306 (data->vddc_voltage_table.count <= tmp),
307 "Too many voltage values for VDDC. Trimming to fit state table.", 307 "Too many voltage values for VDDC. Trimming to fit state table.",
308 phm_trim_voltage_table_to_fit_state_table(tmp, 308 phm_trim_voltage_table_to_fit_state_table(tmp,
309 &(data->vddc_voltage_table))); 309 &(data->vddc_voltage_table)));
310 310
311 tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_VDDGFX); 311 tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX);
312 PP_ASSERT_WITH_CODE( 312 PP_ASSERT_WITH_CODE(
313 (data->vddgfx_voltage_table.count <= tmp), 313 (data->vddgfx_voltage_table.count <= tmp),
314 "Too many voltage values for VDDC. Trimming to fit state table.", 314 "Too many voltage values for VDDC. Trimming to fit state table.",
315 phm_trim_voltage_table_to_fit_state_table(tmp, 315 phm_trim_voltage_table_to_fit_state_table(tmp,
316 &(data->vddgfx_voltage_table))); 316 &(data->vddgfx_voltage_table)));
317 317
318 tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_VDDCI); 318 tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDCI);
319 PP_ASSERT_WITH_CODE( 319 PP_ASSERT_WITH_CODE(
320 (data->vddci_voltage_table.count <= tmp), 320 (data->vddci_voltage_table.count <= tmp),
321 "Too many voltage values for VDDCI. Trimming to fit state table.", 321 "Too many voltage values for VDDCI. Trimming to fit state table.",
322 phm_trim_voltage_table_to_fit_state_table(tmp, 322 phm_trim_voltage_table_to_fit_state_table(tmp,
323 &(data->vddci_voltage_table))); 323 &(data->vddci_voltage_table)));
324 324
325 tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_MVDD); 325 tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_MVDD);
326 PP_ASSERT_WITH_CODE( 326 PP_ASSERT_WITH_CODE(
327 (data->mvdd_voltage_table.count <= tmp), 327 (data->mvdd_voltage_table.count <= tmp),
328 "Too many voltage values for MVDD. Trimming to fit state table.", 328 "Too many voltage values for MVDD. Trimming to fit state table.",
@@ -471,7 +471,7 @@ static int smu7_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
471 471
472static int smu7_reset_to_default(struct pp_hwmgr *hwmgr) 472static int smu7_reset_to_default(struct pp_hwmgr *hwmgr)
473{ 473{
474 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ResetToDefaults); 474 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ResetToDefaults);
475} 475}
476 476
477/** 477/**
@@ -529,7 +529,7 @@ static int smu7_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
529 data->pcie_gen_performance = data->pcie_gen_power_saving; 529 data->pcie_gen_performance = data->pcie_gen_power_saving;
530 data->pcie_lane_performance = data->pcie_lane_power_saving; 530 data->pcie_lane_performance = data->pcie_lane_power_saving;
531 } 531 }
532 tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_LINK); 532 tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_LINK);
533 phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table, 533 phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
534 tmp, 534 tmp,
535 MAX_REGULAR_DPM_NUMBER); 535 MAX_REGULAR_DPM_NUMBER);
@@ -610,27 +610,27 @@ static int smu7_reset_dpm_tables(struct pp_hwmgr *hwmgr)
610 610
611 phm_reset_single_dpm_table( 611 phm_reset_single_dpm_table(
612 &data->dpm_table.sclk_table, 612 &data->dpm_table.sclk_table,
613 smum_get_mac_definition(hwmgr->smumgr, 613 smum_get_mac_definition(hwmgr,
614 SMU_MAX_LEVELS_GRAPHICS), 614 SMU_MAX_LEVELS_GRAPHICS),
615 MAX_REGULAR_DPM_NUMBER); 615 MAX_REGULAR_DPM_NUMBER);
616 phm_reset_single_dpm_table( 616 phm_reset_single_dpm_table(
617 &data->dpm_table.mclk_table, 617 &data->dpm_table.mclk_table,
618 smum_get_mac_definition(hwmgr->smumgr, 618 smum_get_mac_definition(hwmgr,
619 SMU_MAX_LEVELS_MEMORY), MAX_REGULAR_DPM_NUMBER); 619 SMU_MAX_LEVELS_MEMORY), MAX_REGULAR_DPM_NUMBER);
620 620
621 phm_reset_single_dpm_table( 621 phm_reset_single_dpm_table(
622 &data->dpm_table.vddc_table, 622 &data->dpm_table.vddc_table,
623 smum_get_mac_definition(hwmgr->smumgr, 623 smum_get_mac_definition(hwmgr,
624 SMU_MAX_LEVELS_VDDC), 624 SMU_MAX_LEVELS_VDDC),
625 MAX_REGULAR_DPM_NUMBER); 625 MAX_REGULAR_DPM_NUMBER);
626 phm_reset_single_dpm_table( 626 phm_reset_single_dpm_table(
627 &data->dpm_table.vddci_table, 627 &data->dpm_table.vddci_table,
628 smum_get_mac_definition(hwmgr->smumgr, 628 smum_get_mac_definition(hwmgr,
629 SMU_MAX_LEVELS_VDDCI), MAX_REGULAR_DPM_NUMBER); 629 SMU_MAX_LEVELS_VDDCI), MAX_REGULAR_DPM_NUMBER);
630 630
631 phm_reset_single_dpm_table( 631 phm_reset_single_dpm_table(
632 &data->dpm_table.mvdd_table, 632 &data->dpm_table.mvdd_table,
633 smum_get_mac_definition(hwmgr->smumgr, 633 smum_get_mac_definition(hwmgr,
634 SMU_MAX_LEVELS_MVDD), 634 SMU_MAX_LEVELS_MVDD),
635 MAX_REGULAR_DPM_NUMBER); 635 MAX_REGULAR_DPM_NUMBER);
636 return 0; 636 return 0;
@@ -840,7 +840,7 @@ static int smu7_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
840 840
841 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 841 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
842 PHM_PlatformCaps_RegulatorHot)) 842 PHM_PlatformCaps_RegulatorHot))
843 return smum_send_msg_to_smc(hwmgr->smumgr, 843 return smum_send_msg_to_smc(hwmgr,
844 PPSMC_MSG_EnableVRHotGPIOInterrupt); 844 PPSMC_MSG_EnableVRHotGPIOInterrupt);
845 845
846 return 0; 846 return 0;
@@ -858,7 +858,7 @@ static int smu7_enable_ulv(struct pp_hwmgr *hwmgr)
858 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 858 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
859 859
860 if (data->ulv_supported) 860 if (data->ulv_supported)
861 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV); 861 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableULV);
862 862
863 return 0; 863 return 0;
864} 864}
@@ -868,7 +868,7 @@ static int smu7_disable_ulv(struct pp_hwmgr *hwmgr)
868 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 868 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
869 869
870 if (data->ulv_supported) 870 if (data->ulv_supported)
871 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DisableULV); 871 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableULV);
872 872
873 return 0; 873 return 0;
874} 874}
@@ -877,12 +877,12 @@ static int smu7_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
877{ 877{
878 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 878 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
879 PHM_PlatformCaps_SclkDeepSleep)) { 879 PHM_PlatformCaps_SclkDeepSleep)) {
880 if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON)) 880 if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MASTER_DeepSleep_ON))
881 PP_ASSERT_WITH_CODE(false, 881 PP_ASSERT_WITH_CODE(false,
882 "Attempt to enable Master Deep Sleep switch failed!", 882 "Attempt to enable Master Deep Sleep switch failed!",
883 return -EINVAL); 883 return -EINVAL);
884 } else { 884 } else {
885 if (smum_send_msg_to_smc(hwmgr->smumgr, 885 if (smum_send_msg_to_smc(hwmgr,
886 PPSMC_MSG_MASTER_DeepSleep_OFF)) { 886 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
887 PP_ASSERT_WITH_CODE(false, 887 PP_ASSERT_WITH_CODE(false,
888 "Attempt to disable Master Deep Sleep switch failed!", 888 "Attempt to disable Master Deep Sleep switch failed!",
@@ -897,7 +897,7 @@ static int smu7_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
897{ 897{
898 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 898 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
899 PHM_PlatformCaps_SclkDeepSleep)) { 899 PHM_PlatformCaps_SclkDeepSleep)) {
900 if (smum_send_msg_to_smc(hwmgr->smumgr, 900 if (smum_send_msg_to_smc(hwmgr,
901 PPSMC_MSG_MASTER_DeepSleep_OFF)) { 901 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
902 PP_ASSERT_WITH_CODE(false, 902 PP_ASSERT_WITH_CODE(false,
903 "Attempt to disable Master Deep Sleep switch failed!", 903 "Attempt to disable Master Deep Sleep switch failed!",
@@ -913,12 +913,12 @@ static int smu7_disable_handshake_uvd(struct pp_hwmgr *hwmgr)
913 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 913 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
914 uint32_t soft_register_value = 0; 914 uint32_t soft_register_value = 0;
915 uint32_t handshake_disables_offset = data->soft_regs_start 915 uint32_t handshake_disables_offset = data->soft_regs_start
916 + smum_get_offsetof(hwmgr->smumgr, 916 + smum_get_offsetof(hwmgr,
917 SMU_SoftRegisters, HandshakeDisables); 917 SMU_SoftRegisters, HandshakeDisables);
918 918
919 soft_register_value = cgs_read_ind_register(hwmgr->device, 919 soft_register_value = cgs_read_ind_register(hwmgr->device,
920 CGS_IND_REG__SMC, handshake_disables_offset); 920 CGS_IND_REG__SMC, handshake_disables_offset);
921 soft_register_value |= smum_get_mac_definition(hwmgr->smumgr, 921 soft_register_value |= smum_get_mac_definition(hwmgr,
922 SMU_UVD_MCLK_HANDSHAKE_DISABLE); 922 SMU_UVD_MCLK_HANDSHAKE_DISABLE);
923 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 923 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
924 handshake_disables_offset, soft_register_value); 924 handshake_disables_offset, soft_register_value);
@@ -932,7 +932,7 @@ static int smu7_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
932 /* enable SCLK dpm */ 932 /* enable SCLK dpm */
933 if (!data->sclk_dpm_key_disabled) 933 if (!data->sclk_dpm_key_disabled)
934 PP_ASSERT_WITH_CODE( 934 PP_ASSERT_WITH_CODE(
935 (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)), 935 (0 == smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Enable)),
936 "Failed to enable SCLK DPM during DPM Start Function!", 936 "Failed to enable SCLK DPM during DPM Start Function!",
937 return -EINVAL); 937 return -EINVAL);
938 938
@@ -941,7 +941,7 @@ static int smu7_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
941 if (!(hwmgr->feature_mask & PP_UVD_HANDSHAKE_MASK)) 941 if (!(hwmgr->feature_mask & PP_UVD_HANDSHAKE_MASK))
942 smu7_disable_handshake_uvd(hwmgr); 942 smu7_disable_handshake_uvd(hwmgr);
943 PP_ASSERT_WITH_CODE( 943 PP_ASSERT_WITH_CODE(
944 (0 == smum_send_msg_to_smc(hwmgr->smumgr, 944 (0 == smum_send_msg_to_smc(hwmgr,
945 PPSMC_MSG_MCLKDPM_Enable)), 945 PPSMC_MSG_MCLKDPM_Enable)),
946 "Failed to enable MCLK DPM during DPM Start Function!", 946 "Failed to enable MCLK DPM during DPM Start Function!",
947 return -EINVAL); 947 return -EINVAL);
@@ -989,7 +989,7 @@ static int smu7_start_dpm(struct pp_hwmgr *hwmgr)
989 989
990 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 990 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
991 data->soft_regs_start + 991 data->soft_regs_start +
992 smum_get_offsetof(hwmgr->smumgr, SMU_SoftRegisters, 992 smum_get_offsetof(hwmgr, SMU_SoftRegisters,
993 VoltageChangeTimeout), 0x1000); 993 VoltageChangeTimeout), 0x1000);
994 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, 994 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
995 SWRST_COMMAND_1, RESETLC, 0x0); 995 SWRST_COMMAND_1, RESETLC, 0x0);
@@ -1006,7 +1006,7 @@ static int smu7_start_dpm(struct pp_hwmgr *hwmgr)
1006 /* enable PCIE dpm */ 1006 /* enable PCIE dpm */
1007 if (0 == data->pcie_dpm_key_disabled) { 1007 if (0 == data->pcie_dpm_key_disabled) {
1008 PP_ASSERT_WITH_CODE( 1008 PP_ASSERT_WITH_CODE(
1009 (0 == smum_send_msg_to_smc(hwmgr->smumgr, 1009 (0 == smum_send_msg_to_smc(hwmgr,
1010 PPSMC_MSG_PCIeDPM_Enable)), 1010 PPSMC_MSG_PCIeDPM_Enable)),
1011 "Failed to enable pcie DPM during DPM Start Function!", 1011 "Failed to enable pcie DPM during DPM Start Function!",
1012 return -EINVAL); 1012 return -EINVAL);
@@ -1014,7 +1014,7 @@ static int smu7_start_dpm(struct pp_hwmgr *hwmgr)
1014 1014
1015 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1015 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1016 PHM_PlatformCaps_Falcon_QuickTransition)) { 1016 PHM_PlatformCaps_Falcon_QuickTransition)) {
1017 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr, 1017 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr,
1018 PPSMC_MSG_EnableACDCGPIOInterrupt)), 1018 PPSMC_MSG_EnableACDCGPIOInterrupt)),
1019 "Failed to enable AC DC GPIO Interrupt!", 1019 "Failed to enable AC DC GPIO Interrupt!",
1020 ); 1020 );
@@ -1032,7 +1032,7 @@ static int smu7_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
1032 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), 1032 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
1033 "Trying to disable SCLK DPM when DPM is disabled", 1033 "Trying to disable SCLK DPM when DPM is disabled",
1034 return 0); 1034 return 0);
1035 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Disable); 1035 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Disable);
1036 } 1036 }
1037 1037
1038 /* disable MCLK dpm */ 1038 /* disable MCLK dpm */
@@ -1040,7 +1040,7 @@ static int smu7_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
1040 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), 1040 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
1041 "Trying to disable MCLK DPM when DPM is disabled", 1041 "Trying to disable MCLK DPM when DPM is disabled",
1042 return 0); 1042 return 0);
1043 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MCLKDPM_Disable); 1043 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_Disable);
1044 } 1044 }
1045 1045
1046 return 0; 1046 return 0;
@@ -1060,7 +1060,7 @@ static int smu7_stop_dpm(struct pp_hwmgr *hwmgr)
1060 /* disable PCIE dpm */ 1060 /* disable PCIE dpm */
1061 if (!data->pcie_dpm_key_disabled) { 1061 if (!data->pcie_dpm_key_disabled) {
1062 PP_ASSERT_WITH_CODE( 1062 PP_ASSERT_WITH_CODE(
1063 (smum_send_msg_to_smc(hwmgr->smumgr, 1063 (smum_send_msg_to_smc(hwmgr,
1064 PPSMC_MSG_PCIeDPM_Disable) == 0), 1064 PPSMC_MSG_PCIeDPM_Disable) == 0),
1065 "Failed to disable pcie DPM during DPM Stop Function!", 1065 "Failed to disable pcie DPM during DPM Stop Function!",
1066 return -EINVAL); 1066 return -EINVAL);
@@ -1072,7 +1072,7 @@ static int smu7_stop_dpm(struct pp_hwmgr *hwmgr)
1072 "Trying to disable voltage DPM when DPM is disabled", 1072 "Trying to disable voltage DPM when DPM is disabled",
1073 return 0); 1073 return 0);
1074 1074
1075 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Disable); 1075 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Disable);
1076 1076
1077 return 0; 1077 return 0;
1078} 1078}
@@ -1226,7 +1226,7 @@ static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
1226 PP_ASSERT_WITH_CODE((0 == tmp_result), 1226 PP_ASSERT_WITH_CODE((0 == tmp_result),
1227 "Failed to enable VR hot GPIO interrupt!", result = tmp_result); 1227 "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
1228 1228
1229 smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_NoDisplay); 1229 smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_NoDisplay);
1230 1230
1231 tmp_result = smu7_enable_sclk_control(hwmgr); 1231 tmp_result = smu7_enable_sclk_control(hwmgr);
1232 PP_ASSERT_WITH_CODE((0 == tmp_result), 1232 PP_ASSERT_WITH_CODE((0 == tmp_result),
@@ -1692,7 +1692,7 @@ static int phm_add_voltage(struct pp_hwmgr *hwmgr,
1692 PP_ASSERT_WITH_CODE((0 != look_up_table->count), 1692 PP_ASSERT_WITH_CODE((0 != look_up_table->count),
1693 "Lookup Table empty.", return -EINVAL); 1693 "Lookup Table empty.", return -EINVAL);
1694 1694
1695 i = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_VDDGFX); 1695 i = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX);
1696 PP_ASSERT_WITH_CODE((i >= look_up_table->count), 1696 PP_ASSERT_WITH_CODE((i >= look_up_table->count),
1697 "Lookup Table is full.", return -EINVAL); 1697 "Lookup Table is full.", return -EINVAL);
1698 1698
@@ -2423,7 +2423,7 @@ static int smu7_force_dpm_highest(struct pp_hwmgr *hwmgr)
2423 level++; 2423 level++;
2424 2424
2425 if (level) 2425 if (level)
2426 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 2426 smum_send_msg_to_smc_with_parameter(hwmgr,
2427 PPSMC_MSG_PCIeDPM_ForceLevel, level); 2427 PPSMC_MSG_PCIeDPM_ForceLevel, level);
2428 } 2428 }
2429 } 2429 }
@@ -2436,7 +2436,7 @@ static int smu7_force_dpm_highest(struct pp_hwmgr *hwmgr)
2436 level++; 2436 level++;
2437 2437
2438 if (level) 2438 if (level)
2439 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 2439 smum_send_msg_to_smc_with_parameter(hwmgr,
2440 PPSMC_MSG_SCLKDPM_SetEnabledMask, 2440 PPSMC_MSG_SCLKDPM_SetEnabledMask,
2441 (1 << level)); 2441 (1 << level));
2442 } 2442 }
@@ -2450,7 +2450,7 @@ static int smu7_force_dpm_highest(struct pp_hwmgr *hwmgr)
2450 level++; 2450 level++;
2451 2451
2452 if (level) 2452 if (level)
2453 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 2453 smum_send_msg_to_smc_with_parameter(hwmgr,
2454 PPSMC_MSG_MCLKDPM_SetEnabledMask, 2454 PPSMC_MSG_MCLKDPM_SetEnabledMask,
2455 (1 << level)); 2455 (1 << level));
2456 } 2456 }
@@ -2469,14 +2469,14 @@ static int smu7_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
2469 2469
2470 if (!data->sclk_dpm_key_disabled) { 2470 if (!data->sclk_dpm_key_disabled) {
2471 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) 2471 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
2472 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 2472 smum_send_msg_to_smc_with_parameter(hwmgr,
2473 PPSMC_MSG_SCLKDPM_SetEnabledMask, 2473 PPSMC_MSG_SCLKDPM_SetEnabledMask,
2474 data->dpm_level_enable_mask.sclk_dpm_enable_mask); 2474 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
2475 } 2475 }
2476 2476
2477 if (!data->mclk_dpm_key_disabled) { 2477 if (!data->mclk_dpm_key_disabled) {
2478 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) 2478 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
2479 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 2479 smum_send_msg_to_smc_with_parameter(hwmgr,
2480 PPSMC_MSG_MCLKDPM_SetEnabledMask, 2480 PPSMC_MSG_MCLKDPM_SetEnabledMask,
2481 data->dpm_level_enable_mask.mclk_dpm_enable_mask); 2481 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
2482 } 2482 }
@@ -2492,7 +2492,7 @@ static int smu7_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
2492 return -EINVAL; 2492 return -EINVAL;
2493 2493
2494 if (!data->pcie_dpm_key_disabled) { 2494 if (!data->pcie_dpm_key_disabled) {
2495 smum_send_msg_to_smc(hwmgr->smumgr, 2495 smum_send_msg_to_smc(hwmgr,
2496 PPSMC_MSG_PCIeDPM_UnForceLevel); 2496 PPSMC_MSG_PCIeDPM_UnForceLevel);
2497 } 2497 }
2498 2498
@@ -2509,7 +2509,7 @@ static int smu7_force_dpm_lowest(struct pp_hwmgr *hwmgr)
2509 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { 2509 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
2510 level = phm_get_lowest_enabled_level(hwmgr, 2510 level = phm_get_lowest_enabled_level(hwmgr,
2511 data->dpm_level_enable_mask.sclk_dpm_enable_mask); 2511 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
2512 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 2512 smum_send_msg_to_smc_with_parameter(hwmgr,
2513 PPSMC_MSG_SCLKDPM_SetEnabledMask, 2513 PPSMC_MSG_SCLKDPM_SetEnabledMask,
2514 (1 << level)); 2514 (1 << level));
2515 2515
@@ -2519,7 +2519,7 @@ static int smu7_force_dpm_lowest(struct pp_hwmgr *hwmgr)
2519 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) { 2519 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
2520 level = phm_get_lowest_enabled_level(hwmgr, 2520 level = phm_get_lowest_enabled_level(hwmgr,
2521 data->dpm_level_enable_mask.mclk_dpm_enable_mask); 2521 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
2522 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 2522 smum_send_msg_to_smc_with_parameter(hwmgr,
2523 PPSMC_MSG_MCLKDPM_SetEnabledMask, 2523 PPSMC_MSG_MCLKDPM_SetEnabledMask,
2524 (1 << level)); 2524 (1 << level));
2525 } 2525 }
@@ -2529,7 +2529,7 @@ static int smu7_force_dpm_lowest(struct pp_hwmgr *hwmgr)
2529 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) { 2529 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
2530 level = phm_get_lowest_enabled_level(hwmgr, 2530 level = phm_get_lowest_enabled_level(hwmgr,
2531 data->dpm_level_enable_mask.pcie_dpm_enable_mask); 2531 data->dpm_level_enable_mask.pcie_dpm_enable_mask);
2532 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 2532 smum_send_msg_to_smc_with_parameter(hwmgr,
2533 PPSMC_MSG_PCIeDPM_ForceLevel, 2533 PPSMC_MSG_PCIeDPM_ForceLevel,
2534 (level)); 2534 (level));
2535 } 2535 }
@@ -3005,7 +3005,7 @@ static int smu7_get_pp_table_entry_callback_func_v1(struct pp_hwmgr *hwmgr,
3005 [smu7_power_state->performance_level_count++]); 3005 [smu7_power_state->performance_level_count++]);
3006 3006
3007 PP_ASSERT_WITH_CODE( 3007 PP_ASSERT_WITH_CODE(
3008 (smu7_power_state->performance_level_count < smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_GRAPHICS)), 3008 (smu7_power_state->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHICS)),
3009 "Performance levels exceeds SMC limit!", 3009 "Performance levels exceeds SMC limit!",
3010 return -EINVAL); 3010 return -EINVAL);
3011 3011
@@ -3169,7 +3169,7 @@ static int smu7_get_pp_table_entry_callback_func_v0(struct pp_hwmgr *hwmgr,
3169 data->highest_mclk = memory_clock; 3169 data->highest_mclk = memory_clock;
3170 3170
3171 PP_ASSERT_WITH_CODE( 3171 PP_ASSERT_WITH_CODE(
3172 (ps->performance_level_count < smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_GRAPHICS)), 3172 (ps->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHICS)),
3173 "Performance levels exceeds SMC limit!", 3173 "Performance levels exceeds SMC limit!",
3174 return -EINVAL); 3174 return -EINVAL);
3175 3175
@@ -3315,14 +3315,14 @@ static int smu7_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3315static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr, 3315static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr,
3316 struct pp_gpu_power *query) 3316 struct pp_gpu_power *query)
3317{ 3317{
3318 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr, 3318 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
3319 PPSMC_MSG_PmStatusLogStart), 3319 PPSMC_MSG_PmStatusLogStart),
3320 "Failed to start pm status log!", 3320 "Failed to start pm status log!",
3321 return -1); 3321 return -1);
3322 3322
3323 msleep_interruptible(20); 3323 msleep_interruptible(20);
3324 3324
3325 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr, 3325 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
3326 PPSMC_MSG_PmStatusLogSample), 3326 PPSMC_MSG_PmStatusLogSample),
3327 "Failed to sample pm status log!", 3327 "Failed to sample pm status log!",
3328 return -1); 3328 return -1);
@@ -3356,19 +3356,19 @@ static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx,
3356 3356
3357 switch (idx) { 3357 switch (idx) {
3358 case AMDGPU_PP_SENSOR_GFX_SCLK: 3358 case AMDGPU_PP_SENSOR_GFX_SCLK:
3359 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency); 3359 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency);
3360 sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); 3360 sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3361 *((uint32_t *)value) = sclk; 3361 *((uint32_t *)value) = sclk;
3362 *size = 4; 3362 *size = 4;
3363 return 0; 3363 return 0;
3364 case AMDGPU_PP_SENSOR_GFX_MCLK: 3364 case AMDGPU_PP_SENSOR_GFX_MCLK:
3365 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency); 3365 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency);
3366 mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); 3366 mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3367 *((uint32_t *)value) = mclk; 3367 *((uint32_t *)value) = mclk;
3368 *size = 4; 3368 *size = 4;
3369 return 0; 3369 return 0;
3370 case AMDGPU_PP_SENSOR_GPU_LOAD: 3370 case AMDGPU_PP_SENSOR_GPU_LOAD:
3371 offset = data->soft_regs_start + smum_get_offsetof(hwmgr->smumgr, 3371 offset = data->soft_regs_start + smum_get_offsetof(hwmgr,
3372 SMU_SoftRegisters, 3372 SMU_SoftRegisters,
3373 AverageGraphicsActivity); 3373 AverageGraphicsActivity);
3374 3374
@@ -3535,7 +3535,7 @@ static int smu7_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
3535 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), 3535 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
3536 "Trying to freeze SCLK DPM when DPM is disabled", 3536 "Trying to freeze SCLK DPM when DPM is disabled",
3537 ); 3537 );
3538 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, 3538 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
3539 PPSMC_MSG_SCLKDPM_FreezeLevel), 3539 PPSMC_MSG_SCLKDPM_FreezeLevel),
3540 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!", 3540 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
3541 return -EINVAL); 3541 return -EINVAL);
@@ -3547,7 +3547,7 @@ static int smu7_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
3547 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), 3547 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
3548 "Trying to freeze MCLK DPM when DPM is disabled", 3548 "Trying to freeze MCLK DPM when DPM is disabled",
3549 ); 3549 );
3550 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, 3550 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
3551 PPSMC_MSG_MCLKDPM_FreezeLevel), 3551 PPSMC_MSG_MCLKDPM_FreezeLevel),
3552 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!", 3552 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
3553 return -EINVAL); 3553 return -EINVAL);
@@ -3765,7 +3765,7 @@ static int smu7_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
3765 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), 3765 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
3766 "Trying to Unfreeze SCLK DPM when DPM is disabled", 3766 "Trying to Unfreeze SCLK DPM when DPM is disabled",
3767 ); 3767 );
3768 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, 3768 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
3769 PPSMC_MSG_SCLKDPM_UnfreezeLevel), 3769 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
3770 "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!", 3770 "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
3771 return -EINVAL); 3771 return -EINVAL);
@@ -3777,7 +3777,7 @@ static int smu7_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
3777 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), 3777 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
3778 "Trying to Unfreeze MCLK DPM when DPM is disabled", 3778 "Trying to Unfreeze MCLK DPM when DPM is disabled",
3779 ); 3779 );
3780 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, 3780 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
3781 PPSMC_MSG_SCLKDPM_UnfreezeLevel), 3781 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
3782 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!", 3782 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
3783 return -EINVAL); 3783 return -EINVAL);
@@ -3828,9 +3828,9 @@ static int smu7_notify_smc_display(struct pp_hwmgr *hwmgr)
3828 int ret = 0; 3828 int ret = 0;
3829 3829
3830 if (hwmgr->feature_mask & PP_VBI_TIME_SUPPORT_MASK) { 3830 if (hwmgr->feature_mask & PP_VBI_TIME_SUPPORT_MASK) {
3831 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 3831 smum_send_msg_to_smc_with_parameter(hwmgr,
3832 (PPSMC_Msg)PPSMC_MSG_SetVBITimeout, data->frame_time_x2); 3832 (PPSMC_Msg)PPSMC_MSG_SetVBITimeout, data->frame_time_x2);
3833 ret = (smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_HasDisplay) == 0) ? 0 : -EINVAL; 3833 ret = (smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_HasDisplay) == 0) ? 0 : -EINVAL;
3834 } 3834 }
3835 return ret; 3835 return ret;
3836} 3836}
@@ -3905,7 +3905,7 @@ static int smu7_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_f
3905 hwmgr->thermal_controller. 3905 hwmgr->thermal_controller.
3906 advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm; 3906 advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
3907 3907
3908 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 3908 return smum_send_msg_to_smc_with_parameter(hwmgr,
3909 PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm); 3909 PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
3910} 3910}
3911 3911
@@ -3914,7 +3914,7 @@ smu7_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
3914{ 3914{
3915 PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay; 3915 PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
3916 3916
3917 return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ? 0 : -1; 3917 return (smum_send_msg_to_smc(hwmgr, msg) == 0) ? 0 : -1;
3918} 3918}
3919 3919
3920static int 3920static int
@@ -3977,12 +3977,12 @@ static int smu7_program_display_gap(struct pp_hwmgr *hwmgr)
3977 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2); 3977 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
3978 3978
3979 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 3979 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3980 data->soft_regs_start + smum_get_offsetof(hwmgr->smumgr, 3980 data->soft_regs_start + smum_get_offsetof(hwmgr,
3981 SMU_SoftRegisters, 3981 SMU_SoftRegisters,
3982 PreVBlankGap), 0x64); 3982 PreVBlankGap), 0x64);
3983 3983
3984 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 3984 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3985 data->soft_regs_start + smum_get_offsetof(hwmgr->smumgr, 3985 data->soft_regs_start + smum_get_offsetof(hwmgr,
3986 SMU_SoftRegisters, 3986 SMU_SoftRegisters,
3987 VBlankTimeout), 3987 VBlankTimeout),
3988 (frame_time_in_us - pre_vbi_time_in_us)); 3988 (frame_time_in_us - pre_vbi_time_in_us));
@@ -4007,7 +4007,7 @@ static int smu7_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_f
4007 hwmgr->thermal_controller. 4007 hwmgr->thermal_controller.
4008 advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm; 4008 advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
4009 4009
4010 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 4010 return smum_send_msg_to_smc_with_parameter(hwmgr,
4011 PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm); 4011 PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
4012} 4012}
4013 4013
@@ -4257,13 +4257,13 @@ static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
4257 switch (type) { 4257 switch (type) {
4258 case PP_SCLK: 4258 case PP_SCLK:
4259 if (!data->sclk_dpm_key_disabled) 4259 if (!data->sclk_dpm_key_disabled)
4260 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 4260 smum_send_msg_to_smc_with_parameter(hwmgr,
4261 PPSMC_MSG_SCLKDPM_SetEnabledMask, 4261 PPSMC_MSG_SCLKDPM_SetEnabledMask,
4262 data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask); 4262 data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
4263 break; 4263 break;
4264 case PP_MCLK: 4264 case PP_MCLK:
4265 if (!data->mclk_dpm_key_disabled) 4265 if (!data->mclk_dpm_key_disabled)
4266 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 4266 smum_send_msg_to_smc_with_parameter(hwmgr,
4267 PPSMC_MSG_MCLKDPM_SetEnabledMask, 4267 PPSMC_MSG_MCLKDPM_SetEnabledMask,
4268 data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask); 4268 data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
4269 break; 4269 break;
@@ -4276,7 +4276,7 @@ static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
4276 level++; 4276 level++;
4277 4277
4278 if (!data->pcie_dpm_key_disabled) 4278 if (!data->pcie_dpm_key_disabled)
4279 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 4279 smum_send_msg_to_smc_with_parameter(hwmgr,
4280 PPSMC_MSG_PCIeDPM_ForceLevel, 4280 PPSMC_MSG_PCIeDPM_ForceLevel,
4281 level); 4281 level);
4282 break; 4282 break;
@@ -4300,7 +4300,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
4300 4300
4301 switch (type) { 4301 switch (type) {
4302 case PP_SCLK: 4302 case PP_SCLK:
4303 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency); 4303 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency);
4304 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); 4304 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4305 4305
4306 for (i = 0; i < sclk_table->count; i++) { 4306 for (i = 0; i < sclk_table->count; i++) {
@@ -4316,7 +4316,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
4316 (i == now) ? "*" : ""); 4316 (i == now) ? "*" : "");
4317 break; 4317 break;
4318 case PP_MCLK: 4318 case PP_MCLK:
4319 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency); 4319 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency);
4320 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); 4320 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4321 4321
4322 for (i = 0; i < mclk_table->count; i++) { 4322 for (i = 0; i < mclk_table->count; i++) {
@@ -4602,7 +4602,7 @@ static int smu7_set_power_profile_state(struct pp_hwmgr *hwmgr,
4602 4602
4603 if (sclk_mask) { 4603 if (sclk_mask) {
4604 if (!data->sclk_dpm_key_disabled) 4604 if (!data->sclk_dpm_key_disabled)
4605 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 4605 smum_send_msg_to_smc_with_parameter(hwmgr,
4606 PPSMC_MSG_SCLKDPM_SetEnabledMask, 4606 PPSMC_MSG_SCLKDPM_SetEnabledMask,
4607 data->dpm_level_enable_mask. 4607 data->dpm_level_enable_mask.
4608 sclk_dpm_enable_mask & 4608 sclk_dpm_enable_mask &
@@ -4611,7 +4611,7 @@ static int smu7_set_power_profile_state(struct pp_hwmgr *hwmgr,
4611 4611
4612 if (mclk_mask) { 4612 if (mclk_mask) {
4613 if (!data->mclk_dpm_key_disabled) 4613 if (!data->mclk_dpm_key_disabled)
4614 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 4614 smum_send_msg_to_smc_with_parameter(hwmgr,
4615 PPSMC_MSG_MCLKDPM_SetEnabledMask, 4615 PPSMC_MSG_MCLKDPM_SetEnabledMask,
4616 data->dpm_level_enable_mask. 4616 data->dpm_level_enable_mask.
4617 mclk_dpm_enable_mask & 4617 mclk_dpm_enable_mask &
@@ -4623,8 +4623,7 @@ static int smu7_set_power_profile_state(struct pp_hwmgr *hwmgr,
4623 4623
4624static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable) 4624static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
4625{ 4625{
4626 struct pp_smumgr *smumgr = (struct pp_smumgr *)(hwmgr->smumgr); 4626 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend);
4627 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
4628 4627
4629 if (smu_data == NULL) 4628 if (smu_data == NULL)
4630 return -EINVAL; 4629 return -EINVAL;
@@ -4636,13 +4635,13 @@ static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
4636 if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, 4635 if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
4637 CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) 4636 CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON))
4638 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc( 4637 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
4639 hwmgr->smumgr, PPSMC_MSG_EnableAvfs), 4638 hwmgr, PPSMC_MSG_EnableAvfs),
4640 "Failed to enable AVFS!", 4639 "Failed to enable AVFS!",
4641 return -EINVAL); 4640 return -EINVAL);
4642 } else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, 4641 } else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
4643 CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) 4642 CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON))
4644 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc( 4643 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
4645 hwmgr->smumgr, PPSMC_MSG_DisableAvfs), 4644 hwmgr, PPSMC_MSG_DisableAvfs),
4646 "Failed to disable AVFS!", 4645 "Failed to disable AVFS!",
4647 return -EINVAL); 4646 return -EINVAL);
4648 4647
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
index 0fbaeb19a542..a20d67a78b70 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
@@ -660,7 +660,7 @@ static int smu7_enable_didt(struct pp_hwmgr *hwmgr, const bool enable)
660 didt_block |= block_en << TCP_Enable_SHIFT; 660 didt_block |= block_en << TCP_Enable_SHIFT;
661 661
662 if (enable) 662 if (enable)
663 result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_Didt_Block_Function, didt_block); 663 result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_Didt_Block_Function, didt_block);
664 664
665 return result; 665 return result;
666} 666}
@@ -781,7 +781,7 @@ int smu7_enable_didt_config(struct pp_hwmgr *hwmgr)
781 PP_ASSERT_WITH_CODE((result == 0), "EnableDiDt failed.", return result); 781 PP_ASSERT_WITH_CODE((result == 0), "EnableDiDt failed.", return result);
782 782
783 if (hwmgr->chip_id == CHIP_POLARIS11) { 783 if (hwmgr->chip_id == CHIP_POLARIS11) {
784 result = smum_send_msg_to_smc(hwmgr->smumgr, 784 result = smum_send_msg_to_smc(hwmgr,
785 (uint16_t)(PPSMC_MSG_EnableDpmDidt)); 785 (uint16_t)(PPSMC_MSG_EnableDpmDidt));
786 PP_ASSERT_WITH_CODE((0 == result), 786 PP_ASSERT_WITH_CODE((0 == result),
787 "Failed to enable DPM DIDT.", return result); 787 "Failed to enable DPM DIDT.", return result);
@@ -809,7 +809,7 @@ int smu7_disable_didt_config(struct pp_hwmgr *hwmgr)
809 "Post DIDT enable clock gating failed.", 809 "Post DIDT enable clock gating failed.",
810 return result); 810 return result);
811 if (hwmgr->chip_id == CHIP_POLARIS11) { 811 if (hwmgr->chip_id == CHIP_POLARIS11) {
812 result = smum_send_msg_to_smc(hwmgr->smumgr, 812 result = smum_send_msg_to_smc(hwmgr,
813 (uint16_t)(PPSMC_MSG_DisableDpmDidt)); 813 (uint16_t)(PPSMC_MSG_DisableDpmDidt));
814 PP_ASSERT_WITH_CODE((0 == result), 814 PP_ASSERT_WITH_CODE((0 == result),
815 "Failed to disable DPM DIDT.", return result); 815 "Failed to disable DPM DIDT.", return result);
@@ -827,7 +827,7 @@ int smu7_enable_smc_cac(struct pp_hwmgr *hwmgr)
827 827
828 if (PP_CAP(PHM_PlatformCaps_CAC)) { 828 if (PP_CAP(PHM_PlatformCaps_CAC)) {
829 int smc_result; 829 int smc_result;
830 smc_result = smum_send_msg_to_smc(hwmgr->smumgr, 830 smc_result = smum_send_msg_to_smc(hwmgr,
831 (uint16_t)(PPSMC_MSG_EnableCac)); 831 (uint16_t)(PPSMC_MSG_EnableCac));
832 PP_ASSERT_WITH_CODE((0 == smc_result), 832 PP_ASSERT_WITH_CODE((0 == smc_result),
833 "Failed to enable CAC in SMC.", result = -1); 833 "Failed to enable CAC in SMC.", result = -1);
@@ -843,7 +843,7 @@ int smu7_disable_smc_cac(struct pp_hwmgr *hwmgr)
843 int result = 0; 843 int result = 0;
844 844
845 if (PP_CAP(PHM_PlatformCaps_CAC) && data->cac_enabled) { 845 if (PP_CAP(PHM_PlatformCaps_CAC) && data->cac_enabled) {
846 int smc_result = smum_send_msg_to_smc(hwmgr->smumgr, 846 int smc_result = smum_send_msg_to_smc(hwmgr,
847 (uint16_t)(PPSMC_MSG_DisableCac)); 847 (uint16_t)(PPSMC_MSG_DisableCac));
848 PP_ASSERT_WITH_CODE((smc_result == 0), 848 PP_ASSERT_WITH_CODE((smc_result == 0),
849 "Failed to disable CAC in SMC.", result = -1); 849 "Failed to disable CAC in SMC.", result = -1);
@@ -859,7 +859,7 @@ int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
859 859
860 if (data->power_containment_features & 860 if (data->power_containment_features &
861 POWERCONTAINMENT_FEATURE_PkgPwrLimit) 861 POWERCONTAINMENT_FEATURE_PkgPwrLimit)
862 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 862 return smum_send_msg_to_smc_with_parameter(hwmgr,
863 PPSMC_MSG_PkgPwrSetLimit, n); 863 PPSMC_MSG_PkgPwrSetLimit, n);
864 return 0; 864 return 0;
865} 865}
@@ -867,7 +867,7 @@ int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
867static int smu7_set_overdriver_target_tdp(struct pp_hwmgr *hwmgr, 867static int smu7_set_overdriver_target_tdp(struct pp_hwmgr *hwmgr,
868 uint32_t target_tdp) 868 uint32_t target_tdp)
869{ 869{
870 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 870 return smum_send_msg_to_smc_with_parameter(hwmgr,
871 PPSMC_MSG_OverDriveSetTargetTdp, target_tdp); 871 PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
872} 872}
873 873
@@ -888,7 +888,7 @@ int smu7_enable_power_containment(struct pp_hwmgr *hwmgr)
888 888
889 if (PP_CAP(PHM_PlatformCaps_PowerContainment)) { 889 if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
890 if (data->enable_tdc_limit_feature) { 890 if (data->enable_tdc_limit_feature) {
891 smc_result = smum_send_msg_to_smc(hwmgr->smumgr, 891 smc_result = smum_send_msg_to_smc(hwmgr,
892 (uint16_t)(PPSMC_MSG_TDCLimitEnable)); 892 (uint16_t)(PPSMC_MSG_TDCLimitEnable));
893 PP_ASSERT_WITH_CODE((0 == smc_result), 893 PP_ASSERT_WITH_CODE((0 == smc_result),
894 "Failed to enable TDCLimit in SMC.", result = -1;); 894 "Failed to enable TDCLimit in SMC.", result = -1;);
@@ -898,7 +898,7 @@ int smu7_enable_power_containment(struct pp_hwmgr *hwmgr)
898 } 898 }
899 899
900 if (data->enable_pkg_pwr_tracking_feature) { 900 if (data->enable_pkg_pwr_tracking_feature) {
901 smc_result = smum_send_msg_to_smc(hwmgr->smumgr, 901 smc_result = smum_send_msg_to_smc(hwmgr,
902 (uint16_t)(PPSMC_MSG_PkgPwrLimitEnable)); 902 (uint16_t)(PPSMC_MSG_PkgPwrLimitEnable));
903 PP_ASSERT_WITH_CODE((0 == smc_result), 903 PP_ASSERT_WITH_CODE((0 == smc_result),
904 "Failed to enable PkgPwrTracking in SMC.", result = -1;); 904 "Failed to enable PkgPwrTracking in SMC.", result = -1;);
@@ -927,7 +927,7 @@ int smu7_disable_power_containment(struct pp_hwmgr *hwmgr)
927 927
928 if (data->power_containment_features & 928 if (data->power_containment_features &
929 POWERCONTAINMENT_FEATURE_TDCLimit) { 929 POWERCONTAINMENT_FEATURE_TDCLimit) {
930 smc_result = smum_send_msg_to_smc(hwmgr->smumgr, 930 smc_result = smum_send_msg_to_smc(hwmgr,
931 (uint16_t)(PPSMC_MSG_TDCLimitDisable)); 931 (uint16_t)(PPSMC_MSG_TDCLimitDisable));
932 PP_ASSERT_WITH_CODE((smc_result == 0), 932 PP_ASSERT_WITH_CODE((smc_result == 0),
933 "Failed to disable TDCLimit in SMC.", 933 "Failed to disable TDCLimit in SMC.",
@@ -936,7 +936,7 @@ int smu7_disable_power_containment(struct pp_hwmgr *hwmgr)
936 936
937 if (data->power_containment_features & 937 if (data->power_containment_features &
938 POWERCONTAINMENT_FEATURE_DTE) { 938 POWERCONTAINMENT_FEATURE_DTE) {
939 smc_result = smum_send_msg_to_smc(hwmgr->smumgr, 939 smc_result = smum_send_msg_to_smc(hwmgr,
940 (uint16_t)(PPSMC_MSG_DisableDTE)); 940 (uint16_t)(PPSMC_MSG_DisableDTE));
941 PP_ASSERT_WITH_CODE((smc_result == 0), 941 PP_ASSERT_WITH_CODE((smc_result == 0),
942 "Failed to disable DTE in SMC.", 942 "Failed to disable DTE in SMC.",
@@ -945,7 +945,7 @@ int smu7_disable_power_containment(struct pp_hwmgr *hwmgr)
945 945
946 if (data->power_containment_features & 946 if (data->power_containment_features &
947 POWERCONTAINMENT_FEATURE_PkgPwrLimit) { 947 POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
948 smc_result = smum_send_msg_to_smc(hwmgr->smumgr, 948 smc_result = smum_send_msg_to_smc(hwmgr,
949 (uint16_t)(PPSMC_MSG_PkgPwrLimitDisable)); 949 (uint16_t)(PPSMC_MSG_PkgPwrLimitDisable));
950 PP_ASSERT_WITH_CODE((smc_result == 0), 950 PP_ASSERT_WITH_CODE((smc_result == 0),
951 "Failed to disable PkgPwrTracking in SMC.", 951 "Failed to disable PkgPwrTracking in SMC.",
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
index 10e12b2b4385..d7aa643cdb51 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
@@ -152,7 +152,7 @@ int smu7_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
152 152
153 if (PP_CAP(PHM_PlatformCaps_ODFuzzyFanControlSupport)) { 153 if (PP_CAP(PHM_PlatformCaps_ODFuzzyFanControlSupport)) {
154 cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_FUZZY); 154 cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_FUZZY);
155 result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StartFanControl); 155 result = smum_send_msg_to_smc(hwmgr, PPSMC_StartFanControl);
156 156
157 if (PP_CAP(PHM_PlatformCaps_FanSpeedInTableIsRPM)) 157 if (PP_CAP(PHM_PlatformCaps_FanSpeedInTableIsRPM))
158 hwmgr->hwmgr_func->set_max_fan_rpm_output(hwmgr, 158 hwmgr->hwmgr_func->set_max_fan_rpm_output(hwmgr,
@@ -165,12 +165,12 @@ int smu7_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
165 165
166 } else { 166 } else {
167 cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_TABLE); 167 cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_TABLE);
168 result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StartFanControl); 168 result = smum_send_msg_to_smc(hwmgr, PPSMC_StartFanControl);
169 } 169 }
170 170
171 if (!result && hwmgr->thermal_controller. 171 if (!result && hwmgr->thermal_controller.
172 advanceFanControlParameters.ucTargetTemperature) 172 advanceFanControlParameters.ucTargetTemperature)
173 result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 173 result = smum_send_msg_to_smc_with_parameter(hwmgr,
174 PPSMC_MSG_SetFanTemperatureTarget, 174 PPSMC_MSG_SetFanTemperatureTarget,
175 hwmgr->thermal_controller. 175 hwmgr->thermal_controller.
176 advanceFanControlParameters.ucTargetTemperature); 176 advanceFanControlParameters.ucTargetTemperature);
@@ -183,7 +183,7 @@ int smu7_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
183int smu7_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr) 183int smu7_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)
184{ 184{
185 hwmgr->fan_ctrl_enabled = false; 185 hwmgr->fan_ctrl_enabled = false;
186 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StopFanControl); 186 return smum_send_msg_to_smc(hwmgr, PPSMC_StopFanControl);
187} 187}
188 188
189/** 189/**
@@ -371,7 +371,7 @@ static void smu7_thermal_enable_alert(struct pp_hwmgr *hwmgr)
371 CG_THERMAL_INT, THERM_INT_MASK, alert); 371 CG_THERMAL_INT, THERM_INT_MASK, alert);
372 372
373 /* send message to SMU to enable internal thermal interrupts */ 373 /* send message to SMU to enable internal thermal interrupts */
374 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Thermal_Cntl_Enable); 374 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Thermal_Cntl_Enable);
375} 375}
376 376
377/** 377/**
@@ -389,7 +389,7 @@ int smu7_thermal_disable_alert(struct pp_hwmgr *hwmgr)
389 CG_THERMAL_INT, THERM_INT_MASK, alert); 389 CG_THERMAL_INT, THERM_INT_MASK, alert);
390 390
391 /* send message to SMU to disable internal thermal interrupts */ 391 /* send message to SMU to disable internal thermal interrupts */
392 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Thermal_Cntl_Disable); 392 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Thermal_Cntl_Disable);
393} 393}
394 394
395/** 395/**
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 439cb371c56a..a59d282797f5 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -425,8 +425,8 @@ static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
425 if (data->registry_data.vr0hot_enabled) 425 if (data->registry_data.vr0hot_enabled)
426 data->smu_features[GNLD_VR0HOT].supported = true; 426 data->smu_features[GNLD_VR0HOT].supported = true;
427 427
428 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetSmuVersion); 428 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);
429 vega10_read_arg_from_smc(hwmgr->smumgr, &(data->smu_version)); 429 vega10_read_arg_from_smc(hwmgr, &(data->smu_version));
430 /* ACG firmware has major version 5 */ 430 /* ACG firmware has major version 5 */
431 if ((data->smu_version & 0xff000000) == 0x5000000) 431 if ((data->smu_version & 0xff000000) == 0x5000000)
432 data->smu_features[GNLD_ACG].supported = true; 432 data->smu_features[GNLD_ACG].supported = true;
@@ -922,7 +922,7 @@ static bool vega10_is_dpm_running(struct pp_hwmgr *hwmgr)
922{ 922{
923 uint32_t features_enabled; 923 uint32_t features_enabled;
924 924
925 if (!vega10_get_smc_features(hwmgr->smumgr, &features_enabled)) { 925 if (!vega10_get_smc_features(hwmgr, &features_enabled)) {
926 if (features_enabled & SMC_DPM_FEATURES) 926 if (features_enabled & SMC_DPM_FEATURES)
927 return true; 927 return true;
928 } 928 }
@@ -2272,21 +2272,21 @@ static int vega10_acg_enable(struct pp_hwmgr *hwmgr)
2272 uint32_t agc_btc_response; 2272 uint32_t agc_btc_response;
2273 2273
2274 if (data->smu_features[GNLD_ACG].supported) { 2274 if (data->smu_features[GNLD_ACG].supported) {
2275 if (0 == vega10_enable_smc_features(hwmgr->smumgr, true, 2275 if (0 == vega10_enable_smc_features(hwmgr, true,
2276 data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_bitmap)) 2276 data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_bitmap))
2277 data->smu_features[GNLD_DPM_PREFETCHER].enabled = true; 2277 data->smu_features[GNLD_DPM_PREFETCHER].enabled = true;
2278 2278
2279 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_InitializeAcg); 2279 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_InitializeAcg);
2280 2280
2281 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_RunAcgBtc); 2281 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgBtc);
2282 vega10_read_arg_from_smc(hwmgr->smumgr, &agc_btc_response); 2282 vega10_read_arg_from_smc(hwmgr, &agc_btc_response);
2283 2283
2284 if (1 == agc_btc_response) { 2284 if (1 == agc_btc_response) {
2285 if (1 == data->acg_loop_state) 2285 if (1 == data->acg_loop_state)
2286 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_RunAcgInClosedLoop); 2286 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInClosedLoop);
2287 else if (2 == data->acg_loop_state) 2287 else if (2 == data->acg_loop_state)
2288 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_RunAcgInOpenLoop); 2288 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInOpenLoop);
2289 if (0 == vega10_enable_smc_features(hwmgr->smumgr, true, 2289 if (0 == vega10_enable_smc_features(hwmgr, true,
2290 data->smu_features[GNLD_ACG].smu_feature_bitmap)) 2290 data->smu_features[GNLD_ACG].smu_feature_bitmap))
2291 data->smu_features[GNLD_ACG].enabled = true; 2291 data->smu_features[GNLD_ACG].enabled = true;
2292 } else { 2292 } else {
@@ -2305,7 +2305,7 @@ static int vega10_acg_disable(struct pp_hwmgr *hwmgr)
2305 2305
2306 if (data->smu_features[GNLD_ACG].supported && 2306 if (data->smu_features[GNLD_ACG].supported &&
2307 data->smu_features[GNLD_ACG].enabled) 2307 data->smu_features[GNLD_ACG].enabled)
2308 if (!vega10_enable_smc_features(hwmgr->smumgr, false, 2308 if (!vega10_enable_smc_features(hwmgr, false,
2309 data->smu_features[GNLD_ACG].smu_feature_bitmap)) 2309 data->smu_features[GNLD_ACG].smu_feature_bitmap))
2310 data->smu_features[GNLD_ACG].enabled = false; 2310 data->smu_features[GNLD_ACG].enabled = false;
2311 2311
@@ -2355,14 +2355,14 @@ static int vega10_avfs_enable(struct pp_hwmgr *hwmgr, bool enable)
2355 2355
2356 if (data->smu_features[GNLD_AVFS].supported) { 2356 if (data->smu_features[GNLD_AVFS].supported) {
2357 if (enable) { 2357 if (enable) {
2358 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, 2358 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2359 true, 2359 true,
2360 data->smu_features[GNLD_AVFS].smu_feature_bitmap), 2360 data->smu_features[GNLD_AVFS].smu_feature_bitmap),
2361 "[avfs_control] Attempt to Enable AVFS feature Failed!", 2361 "[avfs_control] Attempt to Enable AVFS feature Failed!",
2362 return -1); 2362 return -1);
2363 data->smu_features[GNLD_AVFS].enabled = true; 2363 data->smu_features[GNLD_AVFS].enabled = true;
2364 } else { 2364 } else {
2365 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, 2365 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2366 false, 2366 false,
2367 data->smu_features[GNLD_AVFS].smu_feature_id), 2367 data->smu_features[GNLD_AVFS].smu_feature_id),
2368 "[avfs_control] Attempt to Disable AVFS feature Failed!", 2368 "[avfs_control] Attempt to Disable AVFS feature Failed!",
@@ -2385,11 +2385,11 @@ static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr)
2385 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); 2385 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
2386 AvfsFuseOverride_t *avfs_fuse_table = &(data->smc_state_table.avfs_fuse_override_table); 2386 AvfsFuseOverride_t *avfs_fuse_table = &(data->smc_state_table.avfs_fuse_override_table);
2387 2387
2388 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ReadSerialNumTop32); 2388 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32);
2389 vega10_read_arg_from_smc(hwmgr->smumgr, &top32); 2389 vega10_read_arg_from_smc(hwmgr, &top32);
2390 2390
2391 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ReadSerialNumBottom32); 2391 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32);
2392 vega10_read_arg_from_smc(hwmgr->smumgr, &bottom32); 2392 vega10_read_arg_from_smc(hwmgr, &bottom32);
2393 2393
2394 serial_number = ((uint64_t)bottom32 << 32) | top32; 2394 serial_number = ((uint64_t)bottom32 << 32) | top32;
2395 2395
@@ -2403,7 +2403,7 @@ static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr)
2403 avfs_fuse_table->VFT2_b = fuse.VFT2_b; 2403 avfs_fuse_table->VFT2_b = fuse.VFT2_b;
2404 avfs_fuse_table->VFT2_m1 = fuse.VFT2_m1; 2404 avfs_fuse_table->VFT2_m1 = fuse.VFT2_m1;
2405 avfs_fuse_table->VFT2_m2 = fuse.VFT2_m2; 2405 avfs_fuse_table->VFT2_m2 = fuse.VFT2_m2;
2406 result = vega10_copy_table_to_smc(hwmgr->smumgr, 2406 result = vega10_copy_table_to_smc(hwmgr,
2407 (uint8_t *)avfs_fuse_table, AVFSFUSETABLE); 2407 (uint8_t *)avfs_fuse_table, AVFSFUSETABLE);
2408 PP_ASSERT_WITH_CODE(!result, 2408 PP_ASSERT_WITH_CODE(!result,
2409 "Failed to upload FuseOVerride!", 2409 "Failed to upload FuseOVerride!",
@@ -2542,14 +2542,14 @@ static int vega10_init_smc_table(struct pp_hwmgr *hwmgr)
2542 data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk; 2542 data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
2543 data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk; 2543 data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
2544 if (0 != boot_up_values.usVddc) { 2544 if (0 != boot_up_values.usVddc) {
2545 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 2545 smum_send_msg_to_smc_with_parameter(hwmgr,
2546 PPSMC_MSG_SetFloorSocVoltage, 2546 PPSMC_MSG_SetFloorSocVoltage,
2547 (boot_up_values.usVddc * 4)); 2547 (boot_up_values.usVddc * 4));
2548 data->vbios_boot_state.bsoc_vddc_lock = true; 2548 data->vbios_boot_state.bsoc_vddc_lock = true;
2549 } else { 2549 } else {
2550 data->vbios_boot_state.bsoc_vddc_lock = false; 2550 data->vbios_boot_state.bsoc_vddc_lock = false;
2551 } 2551 }
2552 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 2552 smum_send_msg_to_smc_with_parameter(hwmgr,
2553 PPSMC_MSG_SetMinDeepSleepDcefclk, 2553 PPSMC_MSG_SetMinDeepSleepDcefclk,
2554 (uint32_t)(data->vbios_boot_state.dcef_clock / 100)); 2554 (uint32_t)(data->vbios_boot_state.dcef_clock / 100));
2555 } 2555 }
@@ -2575,7 +2575,7 @@ static int vega10_init_smc_table(struct pp_hwmgr *hwmgr)
2575 2575
2576 vega10_populate_and_upload_avfs_fuse_override(hwmgr); 2576 vega10_populate_and_upload_avfs_fuse_override(hwmgr);
2577 2577
2578 result = vega10_copy_table_to_smc(hwmgr->smumgr, 2578 result = vega10_copy_table_to_smc(hwmgr,
2579 (uint8_t *)pp_table, PPTABLE); 2579 (uint8_t *)pp_table, PPTABLE);
2580 PP_ASSERT_WITH_CODE(!result, 2580 PP_ASSERT_WITH_CODE(!result,
2581 "Failed to upload PPtable!", return result); 2581 "Failed to upload PPtable!", return result);
@@ -2598,7 +2598,7 @@ static int vega10_enable_thermal_protection(struct pp_hwmgr *hwmgr)
2598 pr_info("THERMAL Feature Already enabled!"); 2598 pr_info("THERMAL Feature Already enabled!");
2599 2599
2600 PP_ASSERT_WITH_CODE( 2600 PP_ASSERT_WITH_CODE(
2601 !vega10_enable_smc_features(hwmgr->smumgr, 2601 !vega10_enable_smc_features(hwmgr,
2602 true, 2602 true,
2603 data->smu_features[GNLD_THERMAL].smu_feature_bitmap), 2603 data->smu_features[GNLD_THERMAL].smu_feature_bitmap),
2604 "Enable THERMAL Feature Failed!", 2604 "Enable THERMAL Feature Failed!",
@@ -2618,7 +2618,7 @@ static int vega10_disable_thermal_protection(struct pp_hwmgr *hwmgr)
2618 pr_info("THERMAL Feature Already disabled!"); 2618 pr_info("THERMAL Feature Already disabled!");
2619 2619
2620 PP_ASSERT_WITH_CODE( 2620 PP_ASSERT_WITH_CODE(
2621 !vega10_enable_smc_features(hwmgr->smumgr, 2621 !vega10_enable_smc_features(hwmgr,
2622 false, 2622 false,
2623 data->smu_features[GNLD_THERMAL].smu_feature_bitmap), 2623 data->smu_features[GNLD_THERMAL].smu_feature_bitmap),
2624 "disable THERMAL Feature Failed!", 2624 "disable THERMAL Feature Failed!",
@@ -2637,7 +2637,7 @@ static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr)
2637 if (PP_CAP(PHM_PlatformCaps_RegulatorHot)) { 2637 if (PP_CAP(PHM_PlatformCaps_RegulatorHot)) {
2638 if (data->smu_features[GNLD_VR0HOT].supported) { 2638 if (data->smu_features[GNLD_VR0HOT].supported) {
2639 PP_ASSERT_WITH_CODE( 2639 PP_ASSERT_WITH_CODE(
2640 !vega10_enable_smc_features(hwmgr->smumgr, 2640 !vega10_enable_smc_features(hwmgr,
2641 true, 2641 true,
2642 data->smu_features[GNLD_VR0HOT].smu_feature_bitmap), 2642 data->smu_features[GNLD_VR0HOT].smu_feature_bitmap),
2643 "Attempt to Enable VR0 Hot feature Failed!", 2643 "Attempt to Enable VR0 Hot feature Failed!",
@@ -2646,7 +2646,7 @@ static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr)
2646 } else { 2646 } else {
2647 if (data->smu_features[GNLD_VR1HOT].supported) { 2647 if (data->smu_features[GNLD_VR1HOT].supported) {
2648 PP_ASSERT_WITH_CODE( 2648 PP_ASSERT_WITH_CODE(
2649 !vega10_enable_smc_features(hwmgr->smumgr, 2649 !vega10_enable_smc_features(hwmgr,
2650 true, 2650 true,
2651 data->smu_features[GNLD_VR1HOT].smu_feature_bitmap), 2651 data->smu_features[GNLD_VR1HOT].smu_feature_bitmap),
2652 "Attempt to Enable VR0 Hot feature Failed!", 2652 "Attempt to Enable VR0 Hot feature Failed!",
@@ -2664,7 +2664,7 @@ static int vega10_enable_ulv(struct pp_hwmgr *hwmgr)
2664 (struct vega10_hwmgr *)(hwmgr->backend); 2664 (struct vega10_hwmgr *)(hwmgr->backend);
2665 2665
2666 if (data->registry_data.ulv_support) { 2666 if (data->registry_data.ulv_support) {
2667 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, 2667 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2668 true, data->smu_features[GNLD_ULV].smu_feature_bitmap), 2668 true, data->smu_features[GNLD_ULV].smu_feature_bitmap),
2669 "Enable ULV Feature Failed!", 2669 "Enable ULV Feature Failed!",
2670 return -1); 2670 return -1);
@@ -2680,7 +2680,7 @@ static int vega10_disable_ulv(struct pp_hwmgr *hwmgr)
2680 (struct vega10_hwmgr *)(hwmgr->backend); 2680 (struct vega10_hwmgr *)(hwmgr->backend);
2681 2681
2682 if (data->registry_data.ulv_support) { 2682 if (data->registry_data.ulv_support) {
2683 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, 2683 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2684 false, data->smu_features[GNLD_ULV].smu_feature_bitmap), 2684 false, data->smu_features[GNLD_ULV].smu_feature_bitmap),
2685 "disable ULV Feature Failed!", 2685 "disable ULV Feature Failed!",
2686 return -EINVAL); 2686 return -EINVAL);
@@ -2696,7 +2696,7 @@ static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2696 (struct vega10_hwmgr *)(hwmgr->backend); 2696 (struct vega10_hwmgr *)(hwmgr->backend);
2697 2697
2698 if (data->smu_features[GNLD_DS_GFXCLK].supported) { 2698 if (data->smu_features[GNLD_DS_GFXCLK].supported) {
2699 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, 2699 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2700 true, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap), 2700 true, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap),
2701 "Attempt to Enable DS_GFXCLK Feature Failed!", 2701 "Attempt to Enable DS_GFXCLK Feature Failed!",
2702 return -EINVAL); 2702 return -EINVAL);
@@ -2704,7 +2704,7 @@ static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2704 } 2704 }
2705 2705
2706 if (data->smu_features[GNLD_DS_SOCCLK].supported) { 2706 if (data->smu_features[GNLD_DS_SOCCLK].supported) {
2707 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, 2707 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2708 true, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap), 2708 true, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap),
2709 "Attempt to Enable DS_SOCCLK Feature Failed!", 2709 "Attempt to Enable DS_SOCCLK Feature Failed!",
2710 return -EINVAL); 2710 return -EINVAL);
@@ -2712,7 +2712,7 @@ static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2712 } 2712 }
2713 2713
2714 if (data->smu_features[GNLD_DS_LCLK].supported) { 2714 if (data->smu_features[GNLD_DS_LCLK].supported) {
2715 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, 2715 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2716 true, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap), 2716 true, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap),
2717 "Attempt to Enable DS_LCLK Feature Failed!", 2717 "Attempt to Enable DS_LCLK Feature Failed!",
2718 return -EINVAL); 2718 return -EINVAL);
@@ -2720,7 +2720,7 @@ static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2720 } 2720 }
2721 2721
2722 if (data->smu_features[GNLD_DS_DCEFCLK].supported) { 2722 if (data->smu_features[GNLD_DS_DCEFCLK].supported) {
2723 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, 2723 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2724 true, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap), 2724 true, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap),
2725 "Attempt to Enable DS_DCEFCLK Feature Failed!", 2725 "Attempt to Enable DS_DCEFCLK Feature Failed!",
2726 return -EINVAL); 2726 return -EINVAL);
@@ -2736,7 +2736,7 @@ static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2736 (struct vega10_hwmgr *)(hwmgr->backend); 2736 (struct vega10_hwmgr *)(hwmgr->backend);
2737 2737
2738 if (data->smu_features[GNLD_DS_GFXCLK].supported) { 2738 if (data->smu_features[GNLD_DS_GFXCLK].supported) {
2739 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, 2739 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2740 false, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap), 2740 false, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap),
2741 "Attempt to disable DS_GFXCLK Feature Failed!", 2741 "Attempt to disable DS_GFXCLK Feature Failed!",
2742 return -EINVAL); 2742 return -EINVAL);
@@ -2744,7 +2744,7 @@ static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2744 } 2744 }
2745 2745
2746 if (data->smu_features[GNLD_DS_SOCCLK].supported) { 2746 if (data->smu_features[GNLD_DS_SOCCLK].supported) {
2747 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, 2747 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2748 false, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap), 2748 false, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap),
2749 "Attempt to disable DS_ Feature Failed!", 2749 "Attempt to disable DS_ Feature Failed!",
2750 return -EINVAL); 2750 return -EINVAL);
@@ -2752,7 +2752,7 @@ static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2752 } 2752 }
2753 2753
2754 if (data->smu_features[GNLD_DS_LCLK].supported) { 2754 if (data->smu_features[GNLD_DS_LCLK].supported) {
2755 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, 2755 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2756 false, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap), 2756 false, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap),
2757 "Attempt to disable DS_LCLK Feature Failed!", 2757 "Attempt to disable DS_LCLK Feature Failed!",
2758 return -EINVAL); 2758 return -EINVAL);
@@ -2760,7 +2760,7 @@ static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2760 } 2760 }
2761 2761
2762 if (data->smu_features[GNLD_DS_DCEFCLK].supported) { 2762 if (data->smu_features[GNLD_DS_DCEFCLK].supported) {
2763 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, 2763 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2764 false, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap), 2764 false, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap),
2765 "Attempt to disable DS_DCEFCLK Feature Failed!", 2765 "Attempt to disable DS_DCEFCLK Feature Failed!",
2766 return -EINVAL); 2766 return -EINVAL);
@@ -2778,7 +2778,7 @@ static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
2778 2778
2779 2779
2780 if(data->smu_features[GNLD_LED_DISPLAY].supported == true){ 2780 if(data->smu_features[GNLD_LED_DISPLAY].supported == true){
2781 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, 2781 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2782 false, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap), 2782 false, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap),
2783 "Attempt to disable LED DPM feature failed!", return -EINVAL); 2783 "Attempt to disable LED DPM feature failed!", return -EINVAL);
2784 data->smu_features[GNLD_LED_DISPLAY].enabled = false; 2784 data->smu_features[GNLD_LED_DISPLAY].enabled = false;
@@ -2796,7 +2796,7 @@ static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
2796 } 2796 }
2797 } 2797 }
2798 2798
2799 vega10_enable_smc_features(hwmgr->smumgr, false, feature_mask); 2799 vega10_enable_smc_features(hwmgr, false, feature_mask);
2800 2800
2801 return 0; 2801 return 0;
2802} 2802}
@@ -2826,7 +2826,7 @@ static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
2826 } 2826 }
2827 } 2827 }
2828 2828
2829 if (vega10_enable_smc_features(hwmgr->smumgr, 2829 if (vega10_enable_smc_features(hwmgr,
2830 true, feature_mask)) { 2830 true, feature_mask)) {
2831 for (i = 0; i < GNLD_DPM_MAX; i++) { 2831 for (i = 0; i < GNLD_DPM_MAX; i++) {
2832 if (data->smu_features[i].smu_feature_bitmap & 2832 if (data->smu_features[i].smu_feature_bitmap &
@@ -2836,21 +2836,21 @@ static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
2836 } 2836 }
2837 2837
2838 if(data->smu_features[GNLD_LED_DISPLAY].supported == true){ 2838 if(data->smu_features[GNLD_LED_DISPLAY].supported == true){
2839 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, 2839 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2840 true, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap), 2840 true, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap),
2841 "Attempt to Enable LED DPM feature Failed!", return -EINVAL); 2841 "Attempt to Enable LED DPM feature Failed!", return -EINVAL);
2842 data->smu_features[GNLD_LED_DISPLAY].enabled = true; 2842 data->smu_features[GNLD_LED_DISPLAY].enabled = true;
2843 } 2843 }
2844 2844
2845 if (data->vbios_boot_state.bsoc_vddc_lock) { 2845 if (data->vbios_boot_state.bsoc_vddc_lock) {
2846 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 2846 smum_send_msg_to_smc_with_parameter(hwmgr,
2847 PPSMC_MSG_SetFloorSocVoltage, 0); 2847 PPSMC_MSG_SetFloorSocVoltage, 0);
2848 data->vbios_boot_state.bsoc_vddc_lock = false; 2848 data->vbios_boot_state.bsoc_vddc_lock = false;
2849 } 2849 }
2850 2850
2851 if (PP_CAP(PHM_PlatformCaps_Falcon_QuickTransition)) { 2851 if (PP_CAP(PHM_PlatformCaps_Falcon_QuickTransition)) {
2852 if (data->smu_features[GNLD_ACDC].supported) { 2852 if (data->smu_features[GNLD_ACDC].supported) {
2853 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, 2853 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2854 true, data->smu_features[GNLD_ACDC].smu_feature_bitmap), 2854 true, data->smu_features[GNLD_ACDC].smu_feature_bitmap),
2855 "Attempt to Enable DS_GFXCLK Feature Failed!", 2855 "Attempt to Enable DS_GFXCLK Feature Failed!",
2856 return -1); 2856 return -1);
@@ -2867,13 +2867,13 @@ static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
2867 (struct vega10_hwmgr *)(hwmgr->backend); 2867 (struct vega10_hwmgr *)(hwmgr->backend);
2868 int tmp_result, result = 0; 2868 int tmp_result, result = 0;
2869 2869
2870 tmp_result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 2870 tmp_result = smum_send_msg_to_smc_with_parameter(hwmgr,
2871 PPSMC_MSG_ConfigureTelemetry, data->config_telemetry); 2871 PPSMC_MSG_ConfigureTelemetry, data->config_telemetry);
2872 PP_ASSERT_WITH_CODE(!tmp_result, 2872 PP_ASSERT_WITH_CODE(!tmp_result,
2873 "Failed to configure telemetry!", 2873 "Failed to configure telemetry!",
2874 return tmp_result); 2874 return tmp_result);
2875 2875
2876 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 2876 smum_send_msg_to_smc_with_parameter(hwmgr,
2877 PPSMC_MSG_NumOfDisplays, 0); 2877 PPSMC_MSG_NumOfDisplays, 0);
2878 2878
2879 tmp_result = (!vega10_is_dpm_running(hwmgr)) ? 0 : -1; 2879 tmp_result = (!vega10_is_dpm_running(hwmgr)) ? 0 : -1;
@@ -3674,7 +3674,7 @@ static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr)
3674 if (data->smc_state_table.gfx_boot_level != 3674 if (data->smc_state_table.gfx_boot_level !=
3675 data->dpm_table.gfx_table.dpm_state.soft_min_level) { 3675 data->dpm_table.gfx_table.dpm_state.soft_min_level) {
3676 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter( 3676 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
3677 hwmgr->smumgr, 3677 hwmgr,
3678 PPSMC_MSG_SetSoftMinGfxclkByIndex, 3678 PPSMC_MSG_SetSoftMinGfxclkByIndex,
3679 data->smc_state_table.gfx_boot_level), 3679 data->smc_state_table.gfx_boot_level),
3680 "Failed to set soft min sclk index!", 3680 "Failed to set soft min sclk index!",
@@ -3690,14 +3690,14 @@ static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr)
3690 if (data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1) { 3690 if (data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1) {
3691 socclk_idx = vega10_get_soc_index_for_max_uclk(hwmgr); 3691 socclk_idx = vega10_get_soc_index_for_max_uclk(hwmgr);
3692 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter( 3692 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
3693 hwmgr->smumgr, 3693 hwmgr,
3694 PPSMC_MSG_SetSoftMinSocclkByIndex, 3694 PPSMC_MSG_SetSoftMinSocclkByIndex,
3695 socclk_idx), 3695 socclk_idx),
3696 "Failed to set soft min uclk index!", 3696 "Failed to set soft min uclk index!",
3697 return -EINVAL); 3697 return -EINVAL);
3698 } else { 3698 } else {
3699 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter( 3699 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
3700 hwmgr->smumgr, 3700 hwmgr,
3701 PPSMC_MSG_SetSoftMinUclkByIndex, 3701 PPSMC_MSG_SetSoftMinUclkByIndex,
3702 data->smc_state_table.mem_boot_level), 3702 data->smc_state_table.mem_boot_level),
3703 "Failed to set soft min uclk index!", 3703 "Failed to set soft min uclk index!",
@@ -3722,7 +3722,7 @@ static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
3722 if (data->smc_state_table.gfx_max_level != 3722 if (data->smc_state_table.gfx_max_level !=
3723 data->dpm_table.gfx_table.dpm_state.soft_max_level) { 3723 data->dpm_table.gfx_table.dpm_state.soft_max_level) {
3724 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter( 3724 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
3725 hwmgr->smumgr, 3725 hwmgr,
3726 PPSMC_MSG_SetSoftMaxGfxclkByIndex, 3726 PPSMC_MSG_SetSoftMaxGfxclkByIndex,
3727 data->smc_state_table.gfx_max_level), 3727 data->smc_state_table.gfx_max_level),
3728 "Failed to set soft max sclk index!", 3728 "Failed to set soft max sclk index!",
@@ -3736,7 +3736,7 @@ static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
3736 if (data->smc_state_table.mem_max_level != 3736 if (data->smc_state_table.mem_max_level !=
3737 data->dpm_table.mem_table.dpm_state.soft_max_level) { 3737 data->dpm_table.mem_table.dpm_state.soft_max_level) {
3738 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter( 3738 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
3739 hwmgr->smumgr, 3739 hwmgr,
3740 PPSMC_MSG_SetSoftMaxUclkByIndex, 3740 PPSMC_MSG_SetSoftMaxUclkByIndex,
3741 data->smc_state_table.mem_max_level), 3741 data->smc_state_table.mem_max_level),
3742 "Failed to set soft max mclk index!", 3742 "Failed to set soft max mclk index!",
@@ -3795,7 +3795,7 @@ int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
3795 (struct vega10_hwmgr *)(hwmgr->backend); 3795 (struct vega10_hwmgr *)(hwmgr->backend);
3796 3796
3797 if (data->smu_features[GNLD_DPM_VCE].supported) { 3797 if (data->smu_features[GNLD_DPM_VCE].supported) {
3798 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, 3798 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
3799 enable, 3799 enable,
3800 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap), 3800 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap),
3801 "Attempt to Enable/Disable DPM VCE Failed!", 3801 "Attempt to Enable/Disable DPM VCE Failed!",
@@ -3825,7 +3825,7 @@ static int vega10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
3825 cpu_to_le32(low_sclk_interrupt_threshold); 3825 cpu_to_le32(low_sclk_interrupt_threshold);
3826 3826
3827 /* This message will also enable SmcToHost Interrupt */ 3827 /* This message will also enable SmcToHost Interrupt */
3828 result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 3828 result = smum_send_msg_to_smc_with_parameter(hwmgr,
3829 PPSMC_MSG_SetLowGfxclkInterruptThreshold, 3829 PPSMC_MSG_SetLowGfxclkInterruptThreshold,
3830 (uint32_t)low_sclk_interrupt_threshold); 3830 (uint32_t)low_sclk_interrupt_threshold);
3831 } 3831 }
@@ -3861,7 +3861,7 @@ static int vega10_set_power_state_tasks(struct pp_hwmgr *hwmgr,
3861 "Failed to update SCLK threshold!", 3861 "Failed to update SCLK threshold!",
3862 result = tmp_result); 3862 result = tmp_result);
3863 3863
3864 result = vega10_copy_table_to_smc(hwmgr->smumgr, 3864 result = vega10_copy_table_to_smc(hwmgr,
3865 (uint8_t *)pp_table, PPTABLE); 3865 (uint8_t *)pp_table, PPTABLE);
3866 PP_ASSERT_WITH_CODE(!result, 3866 PP_ASSERT_WITH_CODE(!result,
3867 "Failed to upload PPtable!", return result); 3867 "Failed to upload PPtable!", return result);
@@ -3921,12 +3921,12 @@ static int vega10_get_gpu_power(struct pp_hwmgr *hwmgr,
3921{ 3921{
3922 uint32_t value; 3922 uint32_t value;
3923 3923
3924 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr, 3924 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
3925 PPSMC_MSG_GetCurrPkgPwr), 3925 PPSMC_MSG_GetCurrPkgPwr),
3926 "Failed to get current package power!", 3926 "Failed to get current package power!",
3927 return -EINVAL); 3927 return -EINVAL);
3928 3928
3929 vega10_read_arg_from_smc(hwmgr->smumgr, &value); 3929 vega10_read_arg_from_smc(hwmgr, &value);
3930 /* power value is an integer */ 3930 /* power value is an integer */
3931 query->average_gpu_power = value << 8; 3931 query->average_gpu_power = value << 8;
3932 3932
@@ -3943,25 +3943,25 @@ static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
3943 3943
3944 switch (idx) { 3944 switch (idx) {
3945 case AMDGPU_PP_SENSOR_GFX_SCLK: 3945 case AMDGPU_PP_SENSOR_GFX_SCLK:
3946 ret = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetCurrentGfxclkIndex); 3946 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex);
3947 if (!ret) { 3947 if (!ret) {
3948 vega10_read_arg_from_smc(hwmgr->smumgr, &sclk_idx); 3948 vega10_read_arg_from_smc(hwmgr, &sclk_idx);
3949 *((uint32_t *)value) = dpm_table->gfx_table.dpm_levels[sclk_idx].value; 3949 *((uint32_t *)value) = dpm_table->gfx_table.dpm_levels[sclk_idx].value;
3950 *size = 4; 3950 *size = 4;
3951 } 3951 }
3952 break; 3952 break;
3953 case AMDGPU_PP_SENSOR_GFX_MCLK: 3953 case AMDGPU_PP_SENSOR_GFX_MCLK:
3954 ret = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetCurrentUclkIndex); 3954 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex);
3955 if (!ret) { 3955 if (!ret) {
3956 vega10_read_arg_from_smc(hwmgr->smumgr, &mclk_idx); 3956 vega10_read_arg_from_smc(hwmgr, &mclk_idx);
3957 *((uint32_t *)value) = dpm_table->mem_table.dpm_levels[mclk_idx].value; 3957 *((uint32_t *)value) = dpm_table->mem_table.dpm_levels[mclk_idx].value;
3958 *size = 4; 3958 *size = 4;
3959 } 3959 }
3960 break; 3960 break;
3961 case AMDGPU_PP_SENSOR_GPU_LOAD: 3961 case AMDGPU_PP_SENSOR_GPU_LOAD:
3962 ret = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_GetAverageGfxActivity, 0); 3962 ret = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0);
3963 if (!ret) { 3963 if (!ret) {
3964 vega10_read_arg_from_smc(hwmgr->smumgr, &activity_percent); 3964 vega10_read_arg_from_smc(hwmgr, &activity_percent);
3965 *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent; 3965 *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent;
3966 *size = 4; 3966 *size = 4;
3967 } 3967 }
@@ -3996,7 +3996,7 @@ static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
3996static int vega10_notify_smc_display_change(struct pp_hwmgr *hwmgr, 3996static int vega10_notify_smc_display_change(struct pp_hwmgr *hwmgr,
3997 bool has_disp) 3997 bool has_disp)
3998{ 3998{
3999 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 3999 return smum_send_msg_to_smc_with_parameter(hwmgr,
4000 PPSMC_MSG_SetUclkFastSwitch, 4000 PPSMC_MSG_SetUclkFastSwitch,
4001 has_disp ? 0 : 1); 4001 has_disp ? 0 : 1);
4002} 4002}
@@ -4031,7 +4031,7 @@ int vega10_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
4031 4031
4032 if (!result) { 4032 if (!result) {
4033 clk_request = (clk_freq << 16) | clk_select; 4033 clk_request = (clk_freq << 16) | clk_select;
4034 result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 4034 result = smum_send_msg_to_smc_with_parameter(hwmgr,
4035 PPSMC_MSG_RequestDisplayClockByFreq, 4035 PPSMC_MSG_RequestDisplayClockByFreq,
4036 clk_request); 4036 clk_request);
4037 } 4037 }
@@ -4101,7 +4101,7 @@ static int vega10_notify_smc_display_config_after_ps_adjustment(
4101 clock_req.clock_freq_in_khz = dpm_table->dpm_levels[i].value; 4101 clock_req.clock_freq_in_khz = dpm_table->dpm_levels[i].value;
4102 if (!vega10_display_clock_voltage_request(hwmgr, &clock_req)) { 4102 if (!vega10_display_clock_voltage_request(hwmgr, &clock_req)) {
4103 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter( 4103 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
4104 hwmgr->smumgr, PPSMC_MSG_SetMinDeepSleepDcefclk, 4104 hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
4105 min_clocks.dcefClockInSR /100), 4105 min_clocks.dcefClockInSR /100),
4106 "Attempt to set divider for DCEFCLK Failed!",); 4106 "Attempt to set divider for DCEFCLK Failed!",);
4107 } else { 4107 } else {
@@ -4113,7 +4113,7 @@ static int vega10_notify_smc_display_config_after_ps_adjustment(
4113 4113
4114 if (min_clocks.memoryClock != 0) { 4114 if (min_clocks.memoryClock != 0) {
4115 idx = vega10_get_uclk_index(hwmgr, mclk_table, min_clocks.memoryClock); 4115 idx = vega10_get_uclk_index(hwmgr, mclk_table, min_clocks.memoryClock);
4116 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetSoftMinUclkByIndex, idx); 4116 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetSoftMinUclkByIndex, idx);
4117 data->dpm_table.mem_table.dpm_state.soft_min_level= idx; 4117 data->dpm_table.mem_table.dpm_state.soft_min_level= idx;
4118 } 4118 }
4119 4119
@@ -4596,11 +4596,11 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
4596 if (data->registry_data.sclk_dpm_key_disabled) 4596 if (data->registry_data.sclk_dpm_key_disabled)
4597 break; 4597 break;
4598 4598
4599 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr, 4599 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
4600 PPSMC_MSG_GetCurrentGfxclkIndex), 4600 PPSMC_MSG_GetCurrentGfxclkIndex),
4601 "Attempt to get current sclk index Failed!", 4601 "Attempt to get current sclk index Failed!",
4602 return -1); 4602 return -1);
4603 PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr->smumgr, 4603 PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr,
4604 &now), 4604 &now),
4605 "Attempt to read sclk index Failed!", 4605 "Attempt to read sclk index Failed!",
4606 return -1); 4606 return -1);
@@ -4614,11 +4614,11 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
4614 if (data->registry_data.mclk_dpm_key_disabled) 4614 if (data->registry_data.mclk_dpm_key_disabled)
4615 break; 4615 break;
4616 4616
4617 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr, 4617 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
4618 PPSMC_MSG_GetCurrentUclkIndex), 4618 PPSMC_MSG_GetCurrentUclkIndex),
4619 "Attempt to get current mclk index Failed!", 4619 "Attempt to get current mclk index Failed!",
4620 return -1); 4620 return -1);
4621 PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr->smumgr, 4621 PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr,
4622 &now), 4622 &now),
4623 "Attempt to read mclk index Failed!", 4623 "Attempt to read mclk index Failed!",
4624 return -1); 4624 return -1);
@@ -4629,11 +4629,11 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
4629 (i == now) ? "*" : ""); 4629 (i == now) ? "*" : "");
4630 break; 4630 break;
4631 case PP_PCIE: 4631 case PP_PCIE:
4632 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr, 4632 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
4633 PPSMC_MSG_GetCurrentLinkIndex), 4633 PPSMC_MSG_GetCurrentLinkIndex),
4634 "Attempt to get current mclk index Failed!", 4634 "Attempt to get current mclk index Failed!",
4635 return -1); 4635 return -1);
4636 PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr->smumgr, 4636 PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr,
4637 &now), 4637 &now),
4638 "Attempt to read mclk index Failed!", 4638 "Attempt to read mclk index Failed!",
4639 return -1); 4639 return -1);
@@ -4661,7 +4661,7 @@ static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4661 4661
4662 if ((data->water_marks_bitmap & WaterMarksExist) && 4662 if ((data->water_marks_bitmap & WaterMarksExist) &&
4663 !(data->water_marks_bitmap & WaterMarksLoaded)) { 4663 !(data->water_marks_bitmap & WaterMarksLoaded)) {
4664 result = vega10_copy_table_to_smc(hwmgr->smumgr, 4664 result = vega10_copy_table_to_smc(hwmgr,
4665 (uint8_t *)wm_table, WMTABLE); 4665 (uint8_t *)wm_table, WMTABLE);
4666 PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return EINVAL); 4666 PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return EINVAL);
4667 data->water_marks_bitmap |= WaterMarksLoaded; 4667 data->water_marks_bitmap |= WaterMarksLoaded;
@@ -4670,7 +4670,7 @@ static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4670 if (data->water_marks_bitmap & WaterMarksLoaded) { 4670 if (data->water_marks_bitmap & WaterMarksLoaded) {
4671 cgs_get_active_displays_info(hwmgr->device, &info); 4671 cgs_get_active_displays_info(hwmgr->device, &info);
4672 num_turned_on_displays = info.display_count; 4672 num_turned_on_displays = info.display_count;
4673 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 4673 smum_send_msg_to_smc_with_parameter(hwmgr,
4674 PPSMC_MSG_NumOfDisplays, num_turned_on_displays); 4674 PPSMC_MSG_NumOfDisplays, num_turned_on_displays);
4675 } 4675 }
4676 4676
@@ -4683,7 +4683,7 @@ int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
4683 (struct vega10_hwmgr *)(hwmgr->backend); 4683 (struct vega10_hwmgr *)(hwmgr->backend);
4684 4684
4685 if (data->smu_features[GNLD_DPM_UVD].supported) { 4685 if (data->smu_features[GNLD_DPM_UVD].supported) {
4686 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, 4686 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
4687 enable, 4687 enable,
4688 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap), 4688 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap),
4689 "Attempt to Enable/Disable DPM UVD Failed!", 4689 "Attempt to Enable/Disable DPM UVD Failed!",
@@ -4870,7 +4870,7 @@ static int vega10_set_power_profile_state(struct pp_hwmgr *hwmgr,
4870 if (!data->registry_data.sclk_dpm_key_disabled) 4870 if (!data->registry_data.sclk_dpm_key_disabled)
4871 PP_ASSERT_WITH_CODE( 4871 PP_ASSERT_WITH_CODE(
4872 !smum_send_msg_to_smc_with_parameter( 4872 !smum_send_msg_to_smc_with_parameter(
4873 hwmgr->smumgr, 4873 hwmgr,
4874 PPSMC_MSG_SetSoftMinGfxclkByIndex, 4874 PPSMC_MSG_SetSoftMinGfxclkByIndex,
4875 sclk_idx), 4875 sclk_idx),
4876 "Failed to set soft min sclk index!", 4876 "Failed to set soft min sclk index!",
@@ -4881,7 +4881,7 @@ static int vega10_set_power_profile_state(struct pp_hwmgr *hwmgr,
4881 if (!data->registry_data.mclk_dpm_key_disabled) 4881 if (!data->registry_data.mclk_dpm_key_disabled)
4882 PP_ASSERT_WITH_CODE( 4882 PP_ASSERT_WITH_CODE(
4883 !smum_send_msg_to_smc_with_parameter( 4883 !smum_send_msg_to_smc_with_parameter(
4884 hwmgr->smumgr, 4884 hwmgr,
4885 PPSMC_MSG_SetSoftMinUclkByIndex, 4885 PPSMC_MSG_SetSoftMinUclkByIndex,
4886 mclk_idx), 4886 mclk_idx),
4887 "Failed to set soft min mclk index!", 4887 "Failed to set soft min mclk index!",
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
index 0090ff1bf416..d2f695692f77 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
@@ -926,7 +926,7 @@ static void vega10_didt_set_mask(struct pp_hwmgr *hwmgr, const bool enable)
926 926
927 if (enable) { 927 if (enable) {
928 /* For Vega10, SMC does not support any mask yet. */ 928 /* For Vega10, SMC does not support any mask yet. */
929 result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_ConfigureGfxDidt, didt_block_info); 929 result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ConfigureGfxDidt, didt_block_info);
930 PP_ASSERT((0 == result), "[EnableDiDtConfig] SMC Configure Gfx Didt Failed!"); 930 PP_ASSERT((0 == result), "[EnableDiDtConfig] SMC Configure Gfx Didt Failed!");
931 } 931 }
932} 932}
@@ -1243,7 +1243,7 @@ int vega10_enable_didt_config(struct pp_hwmgr *hwmgr)
1243 } 1243 }
1244 1244
1245 if (0 == result) { 1245 if (0 == result) {
1246 PP_ASSERT_WITH_CODE((!vega10_enable_smc_features(hwmgr->smumgr, true, data->smu_features[GNLD_DIDT].smu_feature_bitmap)), 1246 PP_ASSERT_WITH_CODE((!vega10_enable_smc_features(hwmgr, true, data->smu_features[GNLD_DIDT].smu_feature_bitmap)),
1247 "[EnableDiDtConfig] Attempt to Enable DiDt feature Failed!", return result); 1247 "[EnableDiDtConfig] Attempt to Enable DiDt feature Failed!", return result);
1248 data->smu_features[GNLD_DIDT].enabled = true; 1248 data->smu_features[GNLD_DIDT].enabled = true;
1249 } 1249 }
@@ -1290,7 +1290,7 @@ int vega10_disable_didt_config(struct pp_hwmgr *hwmgr)
1290 } 1290 }
1291 1291
1292 if (0 == result) { 1292 if (0 == result) {
1293 PP_ASSERT_WITH_CODE((0 != vega10_enable_smc_features(hwmgr->smumgr, false, data->smu_features[GNLD_DIDT].smu_feature_bitmap)), 1293 PP_ASSERT_WITH_CODE((0 != vega10_enable_smc_features(hwmgr, false, data->smu_features[GNLD_DIDT].smu_feature_bitmap)),
1294 "[DisableDiDtConfig] Attempt to Disable DiDt feature Failed!", return result); 1294 "[DisableDiDtConfig] Attempt to Disable DiDt feature Failed!", return result);
1295 data->smu_features[GNLD_DIDT].enabled = false; 1295 data->smu_features[GNLD_DIDT].enabled = false;
1296 } 1296 }
@@ -1344,7 +1344,7 @@ int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
1344 (struct vega10_hwmgr *)(hwmgr->backend); 1344 (struct vega10_hwmgr *)(hwmgr->backend);
1345 1345
1346 if (data->registry_data.enable_pkg_pwr_tracking_feature) 1346 if (data->registry_data.enable_pkg_pwr_tracking_feature)
1347 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 1347 return smum_send_msg_to_smc_with_parameter(hwmgr,
1348 PPSMC_MSG_SetPptLimit, n); 1348 PPSMC_MSG_SetPptLimit, n);
1349 1349
1350 return 0; 1350 return 0;
@@ -1363,13 +1363,13 @@ int vega10_enable_power_containment(struct pp_hwmgr *hwmgr)
1363 1363
1364 if (PP_CAP(PHM_PlatformCaps_PowerContainment)) { 1364 if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
1365 if (data->smu_features[GNLD_PPT].supported) 1365 if (data->smu_features[GNLD_PPT].supported)
1366 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, 1366 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
1367 true, data->smu_features[GNLD_PPT].smu_feature_bitmap), 1367 true, data->smu_features[GNLD_PPT].smu_feature_bitmap),
1368 "Attempt to enable PPT feature Failed!", 1368 "Attempt to enable PPT feature Failed!",
1369 data->smu_features[GNLD_PPT].supported = false); 1369 data->smu_features[GNLD_PPT].supported = false);
1370 1370
1371 if (data->smu_features[GNLD_TDC].supported) 1371 if (data->smu_features[GNLD_TDC].supported)
1372 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, 1372 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
1373 true, data->smu_features[GNLD_TDC].smu_feature_bitmap), 1373 true, data->smu_features[GNLD_TDC].smu_feature_bitmap),
1374 "Attempt to enable PPT feature Failed!", 1374 "Attempt to enable PPT feature Failed!",
1375 data->smu_features[GNLD_TDC].supported = false); 1375 data->smu_features[GNLD_TDC].supported = false);
@@ -1390,13 +1390,13 @@ int vega10_disable_power_containment(struct pp_hwmgr *hwmgr)
1390 1390
1391 if (PP_CAP(PHM_PlatformCaps_PowerContainment)) { 1391 if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
1392 if (data->smu_features[GNLD_PPT].supported) 1392 if (data->smu_features[GNLD_PPT].supported)
1393 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, 1393 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
1394 false, data->smu_features[GNLD_PPT].smu_feature_bitmap), 1394 false, data->smu_features[GNLD_PPT].smu_feature_bitmap),
1395 "Attempt to disable PPT feature Failed!", 1395 "Attempt to disable PPT feature Failed!",
1396 data->smu_features[GNLD_PPT].supported = false); 1396 data->smu_features[GNLD_PPT].supported = false);
1397 1397
1398 if (data->smu_features[GNLD_TDC].supported) 1398 if (data->smu_features[GNLD_TDC].supported)
1399 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, 1399 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
1400 false, data->smu_features[GNLD_TDC].smu_feature_bitmap), 1400 false, data->smu_features[GNLD_TDC].smu_feature_bitmap),
1401 "Attempt to disable PPT feature Failed!", 1401 "Attempt to disable PPT feature Failed!",
1402 data->smu_features[GNLD_TDC].supported = false); 1402 data->smu_features[GNLD_TDC].supported = false);
@@ -1408,7 +1408,7 @@ int vega10_disable_power_containment(struct pp_hwmgr *hwmgr)
1408static int vega10_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr, 1408static int vega10_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr,
1409 uint32_t adjust_percent) 1409 uint32_t adjust_percent)
1410{ 1410{
1411 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 1411 return smum_send_msg_to_smc_with_parameter(hwmgr,
1412 PPSMC_MSG_OverDriveSetPercentage, adjust_percent); 1412 PPSMC_MSG_OverDriveSetPercentage, adjust_percent);
1413} 1413}
1414 1414
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
index ce873e40a8fd..1feefac49ea9 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
@@ -31,11 +31,11 @@
31 31
32static int vega10_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm) 32static int vega10_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm)
33{ 33{
34 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr, 34 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
35 PPSMC_MSG_GetCurrentRpm), 35 PPSMC_MSG_GetCurrentRpm),
36 "Attempt to get current RPM from SMC Failed!", 36 "Attempt to get current RPM from SMC Failed!",
37 return -1); 37 return -1);
38 PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr->smumgr, 38 PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr,
39 current_rpm), 39 current_rpm),
40 "Attempt to read current RPM from SMC Failed!", 40 "Attempt to read current RPM from SMC Failed!",
41 return -1); 41 return -1);
@@ -199,7 +199,7 @@ static int vega10_enable_fan_control_feature(struct pp_hwmgr *hwmgr)
199 199
200 if (data->smu_features[GNLD_FAN_CONTROL].supported) { 200 if (data->smu_features[GNLD_FAN_CONTROL].supported) {
201 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features( 201 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
202 hwmgr->smumgr, true, 202 hwmgr, true,
203 data->smu_features[GNLD_FAN_CONTROL]. 203 data->smu_features[GNLD_FAN_CONTROL].
204 smu_feature_bitmap), 204 smu_feature_bitmap),
205 "Attempt to Enable FAN CONTROL feature Failed!", 205 "Attempt to Enable FAN CONTROL feature Failed!",
@@ -216,7 +216,7 @@ static int vega10_disable_fan_control_feature(struct pp_hwmgr *hwmgr)
216 216
217 if (data->smu_features[GNLD_FAN_CONTROL].supported) { 217 if (data->smu_features[GNLD_FAN_CONTROL].supported) {
218 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features( 218 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
219 hwmgr->smumgr, false, 219 hwmgr, false,
220 data->smu_features[GNLD_FAN_CONTROL]. 220 data->smu_features[GNLD_FAN_CONTROL].
221 smu_feature_bitmap), 221 smu_feature_bitmap),
222 "Attempt to Enable FAN CONTROL feature Failed!", 222 "Attempt to Enable FAN CONTROL feature Failed!",
@@ -458,7 +458,7 @@ static int vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr)
458 if (data->smu_features[GNLD_FW_CTF].enabled) 458 if (data->smu_features[GNLD_FW_CTF].enabled)
459 printk("[Thermal_EnableAlert] FW CTF Already Enabled!\n"); 459 printk("[Thermal_EnableAlert] FW CTF Already Enabled!\n");
460 460
461 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, 461 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
462 true, 462 true,
463 data->smu_features[GNLD_FW_CTF].smu_feature_bitmap), 463 data->smu_features[GNLD_FW_CTF].smu_feature_bitmap),
464 "Attempt to Enable FW CTF feature Failed!", 464 "Attempt to Enable FW CTF feature Failed!",
@@ -490,7 +490,7 @@ int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr)
490 printk("[Thermal_EnableAlert] FW CTF Already disabled!\n"); 490 printk("[Thermal_EnableAlert] FW CTF Already disabled!\n");
491 491
492 492
493 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, 493 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
494 false, 494 false,
495 data->smu_features[GNLD_FW_CTF].smu_feature_bitmap), 495 data->smu_features[GNLD_FW_CTF].smu_feature_bitmap),
496 "Attempt to disable FW CTF feature Failed!", 496 "Attempt to disable FW CTF feature Failed!",
@@ -546,7 +546,7 @@ int vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
546 table->FanTargetTemperature = hwmgr->thermal_controller. 546 table->FanTargetTemperature = hwmgr->thermal_controller.
547 advanceFanControlParameters.usTMax; 547 advanceFanControlParameters.usTMax;
548 548
549 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 549 smum_send_msg_to_smc_with_parameter(hwmgr,
550 PPSMC_MSG_SetFanTemperatureTarget, 550 PPSMC_MSG_SetFanTemperatureTarget,
551 (uint32_t)table->FanTargetTemperature); 551 (uint32_t)table->FanTargetTemperature);
552 552
@@ -575,7 +575,7 @@ int vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
575 table->FanStartTemp = hwmgr->thermal_controller. 575 table->FanStartTemp = hwmgr->thermal_controller.
576 advanceFanControlParameters.usZeroRPMStartTemperature; 576 advanceFanControlParameters.usZeroRPMStartTemperature;
577 577
578 ret = vega10_copy_table_to_smc(hwmgr->smumgr, 578 ret = vega10_copy_table_to_smc(hwmgr,
579 (uint8_t *)(&(data->smc_state_table.pp_table)), PPTABLE); 579 (uint8_t *)(&(data->smc_state_table.pp_table)), PPTABLE);
580 if (ret) 580 if (ret)
581 pr_info("Failed to update Fan Control Table in PPTable!"); 581 pr_info("Failed to update Fan Control Table in PPTable!");
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
index f807dd639aed..58581e1bbf50 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
@@ -103,21 +103,21 @@ enum SMU_MAC_DEFINITION {
103 103
104 104
105struct pp_smumgr_func { 105struct pp_smumgr_func {
106 int (*smu_init)(struct pp_smumgr *smumgr); 106 int (*smu_init)(struct pp_hwmgr *hwmgr);
107 int (*smu_fini)(struct pp_smumgr *smumgr); 107 int (*smu_fini)(struct pp_hwmgr *hwmgr);
108 int (*start_smu)(struct pp_smumgr *smumgr); 108 int (*start_smu)(struct pp_hwmgr *hwmgr);
109 int (*check_fw_load_finish)(struct pp_smumgr *smumgr, 109 int (*check_fw_load_finish)(struct pp_hwmgr *hwmgr,
110 uint32_t firmware); 110 uint32_t firmware);
111 int (*request_smu_load_fw)(struct pp_smumgr *smumgr); 111 int (*request_smu_load_fw)(struct pp_hwmgr *hwmgr);
112 int (*request_smu_load_specific_fw)(struct pp_smumgr *smumgr, 112 int (*request_smu_load_specific_fw)(struct pp_hwmgr *hwmgr,
113 uint32_t firmware); 113 uint32_t firmware);
114 int (*get_argument)(struct pp_smumgr *smumgr); 114 int (*get_argument)(struct pp_hwmgr *hwmgr);
115 int (*send_msg_to_smc)(struct pp_smumgr *smumgr, uint16_t msg); 115 int (*send_msg_to_smc)(struct pp_hwmgr *hwmgr, uint16_t msg);
116 int (*send_msg_to_smc_with_parameter)(struct pp_smumgr *smumgr, 116 int (*send_msg_to_smc_with_parameter)(struct pp_hwmgr *hwmgr,
117 uint16_t msg, uint32_t parameter); 117 uint16_t msg, uint32_t parameter);
118 int (*download_pptable_settings)(struct pp_smumgr *smumgr, 118 int (*download_pptable_settings)(struct pp_hwmgr *hwmgr,
119 void **table); 119 void **table);
120 int (*upload_pptable_settings)(struct pp_smumgr *smumgr); 120 int (*upload_pptable_settings)(struct pp_hwmgr *hwmgr);
121 int (*update_smc_table)(struct pp_hwmgr *hwmgr, uint32_t type); 121 int (*update_smc_table)(struct pp_hwmgr *hwmgr, uint32_t type);
122 int (*process_firmware_header)(struct pp_hwmgr *hwmgr); 122 int (*process_firmware_header)(struct pp_hwmgr *hwmgr);
123 int (*update_sclk_threshold)(struct pp_hwmgr *hwmgr); 123 int (*update_sclk_threshold)(struct pp_hwmgr *hwmgr);
@@ -132,7 +132,7 @@ struct pp_smumgr_func {
132 bool (*is_dpm_running)(struct pp_hwmgr *hwmgr); 132 bool (*is_dpm_running)(struct pp_hwmgr *hwmgr);
133 int (*populate_requested_graphic_levels)(struct pp_hwmgr *hwmgr, 133 int (*populate_requested_graphic_levels)(struct pp_hwmgr *hwmgr,
134 struct amd_pp_profile *request); 134 struct amd_pp_profile *request);
135 bool (*is_hw_avfs_present)(struct pp_smumgr *smumgr); 135 bool (*is_hw_avfs_present)(struct pp_hwmgr *hwmgr);
136}; 136};
137 137
138struct pp_smumgr { 138struct pp_smumgr {
@@ -148,30 +148,30 @@ struct pp_smumgr {
148 148
149extern int smum_early_init(struct pp_instance *handle); 149extern int smum_early_init(struct pp_instance *handle);
150 150
151extern int smum_get_argument(struct pp_smumgr *smumgr); 151extern int smum_get_argument(struct pp_hwmgr *hwmgr);
152 152
153extern int smum_download_powerplay_table(struct pp_smumgr *smumgr, void **table); 153extern int smum_download_powerplay_table(struct pp_hwmgr *hwmgr, void **table);
154 154
155extern int smum_upload_powerplay_table(struct pp_smumgr *smumgr); 155extern int smum_upload_powerplay_table(struct pp_hwmgr *hwmgr);
156 156
157extern int smum_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg); 157extern int smum_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg);
158 158
159extern int smum_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, 159extern int smum_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
160 uint16_t msg, uint32_t parameter); 160 uint16_t msg, uint32_t parameter);
161 161
162extern int smum_wait_on_register(struct pp_smumgr *smumgr, 162extern int smum_wait_on_register(struct pp_hwmgr *hwmgr,
163 uint32_t index, uint32_t value, uint32_t mask); 163 uint32_t index, uint32_t value, uint32_t mask);
164 164
165extern int smum_wait_for_register_unequal(struct pp_smumgr *smumgr, 165extern int smum_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
166 uint32_t index, uint32_t value, uint32_t mask); 166 uint32_t index, uint32_t value, uint32_t mask);
167 167
168extern int smum_wait_on_indirect_register(struct pp_smumgr *smumgr, 168extern int smum_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
169 uint32_t indirect_port, uint32_t index, 169 uint32_t indirect_port, uint32_t index,
170 uint32_t value, uint32_t mask); 170 uint32_t value, uint32_t mask);
171 171
172 172
173extern void smum_wait_for_indirect_register_unequal( 173extern void smum_wait_for_indirect_register_unequal(
174 struct pp_smumgr *smumgr, 174 struct pp_hwmgr *hwmgr,
175 uint32_t indirect_port, uint32_t index, 175 uint32_t indirect_port, uint32_t index,
176 uint32_t value, uint32_t mask); 176 uint32_t value, uint32_t mask);
177 177
@@ -181,7 +181,7 @@ extern int smu_allocate_memory(void *device, uint32_t size,
181 void **kptr, void *handle); 181 void **kptr, void *handle);
182 182
183extern int smu_free_memory(void *device, void *handle); 183extern int smu_free_memory(void *device, void *handle);
184extern int vega10_smum_init(struct pp_smumgr *smumgr); 184extern int vega10_smum_init(struct pp_hwmgr *hwmgr);
185 185
186extern int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr); 186extern int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr);
187 187
@@ -193,44 +193,44 @@ extern int smum_init_smc_table(struct pp_hwmgr *hwmgr);
193extern int smum_populate_all_graphic_levels(struct pp_hwmgr *hwmgr); 193extern int smum_populate_all_graphic_levels(struct pp_hwmgr *hwmgr);
194extern int smum_populate_all_memory_levels(struct pp_hwmgr *hwmgr); 194extern int smum_populate_all_memory_levels(struct pp_hwmgr *hwmgr);
195extern int smum_initialize_mc_reg_table(struct pp_hwmgr *hwmgr); 195extern int smum_initialize_mc_reg_table(struct pp_hwmgr *hwmgr);
196extern uint32_t smum_get_offsetof(struct pp_smumgr *smumgr, 196extern uint32_t smum_get_offsetof(struct pp_hwmgr *hwmgr,
197 uint32_t type, uint32_t member); 197 uint32_t type, uint32_t member);
198extern uint32_t smum_get_mac_definition(struct pp_smumgr *smumgr, uint32_t value); 198extern uint32_t smum_get_mac_definition(struct pp_hwmgr *hwmgr, uint32_t value);
199 199
200extern bool smum_is_dpm_running(struct pp_hwmgr *hwmgr); 200extern bool smum_is_dpm_running(struct pp_hwmgr *hwmgr);
201 201
202extern int smum_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr, 202extern int smum_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
203 struct amd_pp_profile *request); 203 struct amd_pp_profile *request);
204 204
205extern bool smum_is_hw_avfs_present(struct pp_smumgr *smumgr); 205extern bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr);
206 206
207#define SMUM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 207#define SMUM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
208 208
209#define SMUM_FIELD_MASK(reg, field) reg##__##field##_MASK 209#define SMUM_FIELD_MASK(reg, field) reg##__##field##_MASK
210 210
211#define SMUM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, \ 211#define SMUM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, \
212 port, index, value, mask) \ 212 port, index, value, mask) \
213 smum_wait_on_indirect_register(smumgr, \ 213 smum_wait_on_indirect_register(hwmgr, \
214 mm##port##_INDEX, index, value, mask) 214 mm##port##_INDEX, index, value, mask)
215 215
216#define SMUM_WAIT_INDIRECT_REGISTER(smumgr, port, reg, value, mask) \ 216#define SMUM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
217 SMUM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, port, ix##reg, value, mask) 217 SMUM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
218 218
219#define SMUM_WAIT_INDIRECT_FIELD(smumgr, port, reg, field, fieldval) \ 219#define SMUM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
220 SMUM_WAIT_INDIRECT_REGISTER(smumgr, port, reg, (fieldval) << SMUM_FIELD_SHIFT(reg, field), \ 220 SMUM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) << SMUM_FIELD_SHIFT(reg, field), \
221 SMUM_FIELD_MASK(reg, field) ) 221 SMUM_FIELD_MASK(reg, field) )
222 222
223#define SMUM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, \ 223#define SMUM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \
224 index, value, mask) \ 224 index, value, mask) \
225 smum_wait_for_register_unequal(smumgr, \ 225 smum_wait_for_register_unequal(hwmgr, \
226 index, value, mask) 226 index, value, mask)
227 227
228#define SMUM_WAIT_REGISTER_UNEQUAL(smumgr, reg, value, mask) \ 228#define SMUM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask) \
229 SMUM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, \ 229 SMUM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \
230 mm##reg, value, mask) 230 mm##reg, value, mask)
231 231
232#define SMUM_WAIT_FIELD_UNEQUAL(smumgr, reg, field, fieldval) \ 232#define SMUM_WAIT_FIELD_UNEQUAL(hwmgr, reg, field, fieldval) \
233 SMUM_WAIT_REGISTER_UNEQUAL(smumgr, reg, \ 233 SMUM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, \
234 (fieldval) << SMUM_FIELD_SHIFT(reg, field), \ 234 (fieldval) << SMUM_FIELD_SHIFT(reg, field), \
235 SMUM_FIELD_MASK(reg, field)) 235 SMUM_FIELD_MASK(reg, field))
236 236
@@ -250,22 +250,22 @@ extern bool smum_is_hw_avfs_present(struct pp_smumgr *smumgr);
250 SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ 250 SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
251 reg, field) 251 reg, field)
252 252
253#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, \ 253#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, \
254 port, index, value, mask) \ 254 port, index, value, mask) \
255 smum_wait_on_indirect_register(smumgr, \ 255 smum_wait_on_indirect_register(hwmgr, \
256 mm##port##_INDEX_0, index, value, mask) 256 mm##port##_INDEX_0, index, value, mask)
257 257
258#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, \ 258#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \
259 port, index, value, mask) \ 259 port, index, value, mask) \
260 smum_wait_for_indirect_register_unequal(smumgr, \ 260 smum_wait_for_indirect_register_unequal(hwmgr, \
261 mm##port##_INDEX_0, index, value, mask) 261 mm##port##_INDEX_0, index, value, mask)
262 262
263 263
264#define SMUM_WAIT_VFPF_INDIRECT_REGISTER(smumgr, port, reg, value, mask) \ 264#define SMUM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
265 SMUM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, port, ix##reg, value, mask) 265 SMUM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
266 266
267#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, value, mask) \ 267#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \
268 SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, port, ix##reg, value, mask) 268 SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
269 269
270 270
271/*Operations on named fields.*/ 271/*Operations on named fields.*/
@@ -290,25 +290,25 @@ extern bool smum_is_hw_avfs_present(struct pp_smumgr *smumgr);
290 reg, field, fieldval)) 290 reg, field, fieldval))
291 291
292 292
293#define SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, port, reg, field, fieldval) \ 293#define SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
294 SMUM_WAIT_VFPF_INDIRECT_REGISTER(smumgr, port, reg, \ 294 SMUM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, \
295 (fieldval) << SMUM_FIELD_SHIFT(reg, field), \ 295 (fieldval) << SMUM_FIELD_SHIFT(reg, field), \
296 SMUM_FIELD_MASK(reg, field)) 296 SMUM_FIELD_MASK(reg, field))
297 297
298#define SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, port, reg, field, fieldval) \ 298#define SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
299 SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, \ 299 SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, \
300 (fieldval) << SMUM_FIELD_SHIFT(reg, field), \ 300 (fieldval) << SMUM_FIELD_SHIFT(reg, field), \
301 SMUM_FIELD_MASK(reg, field)) 301 SMUM_FIELD_MASK(reg, field))
302 302
303#define SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, port, index, value, mask) \ 303#define SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask) \
304 smum_wait_for_indirect_register_unequal(smumgr, \ 304 smum_wait_for_indirect_register_unequal(hwmgr, \
305 mm##port##_INDEX, index, value, mask) 305 mm##port##_INDEX, index, value, mask)
306 306
307#define SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, value, mask) \ 307#define SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \
308 SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, port, ix##reg, value, mask) 308 SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
309 309
310#define SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(smumgr, port, reg, field, fieldval) \ 310#define SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
311 SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, (fieldval) << SMUM_FIELD_SHIFT(reg, field), \ 311 SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, (fieldval) << SMUM_FIELD_SHIFT(reg, field), \
312 SMUM_FIELD_MASK(reg, field) ) 312 SMUM_FIELD_MASK(reg, field) )
313 313
314#endif 314#endif
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c
index b7a239190785..2710a6fa3df0 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c
@@ -94,7 +94,7 @@ static const struct ci_pt_defaults defaults_saturn_xt = {
94}; 94};
95 95
96 96
97static int ci_set_smc_sram_address(struct pp_smumgr *smumgr, 97static int ci_set_smc_sram_address(struct pp_hwmgr *hwmgr,
98 uint32_t smc_addr, uint32_t limit) 98 uint32_t smc_addr, uint32_t limit)
99{ 99{
100 if ((0 != (3 & smc_addr)) 100 if ((0 != (3 & smc_addr))
@@ -103,12 +103,12 @@ static int ci_set_smc_sram_address(struct pp_smumgr *smumgr,
103 return -EINVAL; 103 return -EINVAL;
104 } 104 }
105 105
106 cgs_write_register(smumgr->device, mmSMC_IND_INDEX_0, smc_addr); 106 cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, smc_addr);
107 SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0); 107 SMUM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
108 return 0; 108 return 0;
109} 109}
110 110
111static int ci_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, 111static int ci_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address,
112 const uint8_t *src, uint32_t byte_count, uint32_t limit) 112 const uint8_t *src, uint32_t byte_count, uint32_t limit)
113{ 113{
114 int result; 114 int result;
@@ -129,12 +129,12 @@ static int ci_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_add
129 /* Bytes are written into the SMC address space with the MSB first. */ 129 /* Bytes are written into the SMC address space with the MSB first. */
130 data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3]; 130 data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3];
131 131
132 result = ci_set_smc_sram_address(smumgr, addr, limit); 132 result = ci_set_smc_sram_address(hwmgr, addr, limit);
133 133
134 if (0 != result) 134 if (0 != result)
135 return result; 135 return result;
136 136
137 cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, data); 137 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data);
138 138
139 src += 4; 139 src += 4;
140 byte_count -= 4; 140 byte_count -= 4;
@@ -145,13 +145,13 @@ static int ci_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_add
145 145
146 data = 0; 146 data = 0;
147 147
148 result = ci_set_smc_sram_address(smumgr, addr, limit); 148 result = ci_set_smc_sram_address(hwmgr, addr, limit);
149 149
150 if (0 != result) 150 if (0 != result)
151 return result; 151 return result;
152 152
153 153
154 original_data = cgs_read_register(smumgr->device, mmSMC_IND_DATA_0); 154 original_data = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_0);
155 155
156 extra_shift = 8 * (4 - byte_count); 156 extra_shift = 8 * (4 - byte_count);
157 157
@@ -165,61 +165,61 @@ static int ci_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_add
165 165
166 data |= (original_data & ~((~0UL) << extra_shift)); 166 data |= (original_data & ~((~0UL) << extra_shift));
167 167
168 result = ci_set_smc_sram_address(smumgr, addr, limit); 168 result = ci_set_smc_sram_address(hwmgr, addr, limit);
169 169
170 if (0 != result) 170 if (0 != result)
171 return result; 171 return result;
172 172
173 cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, data); 173 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data);
174 } 174 }
175 175
176 return 0; 176 return 0;
177} 177}
178 178
179 179
180static int ci_program_jump_on_start(struct pp_smumgr *smumgr) 180static int ci_program_jump_on_start(struct pp_hwmgr *hwmgr)
181{ 181{
182 static const unsigned char data[4] = { 0xE0, 0x00, 0x80, 0x40 }; 182 static const unsigned char data[4] = { 0xE0, 0x00, 0x80, 0x40 };
183 183
184 ci_copy_bytes_to_smc(smumgr, 0x0, data, 4, sizeof(data)+1); 184 ci_copy_bytes_to_smc(hwmgr, 0x0, data, 4, sizeof(data)+1);
185 185
186 return 0; 186 return 0;
187} 187}
188 188
189bool ci_is_smc_ram_running(struct pp_smumgr *smumgr) 189bool ci_is_smc_ram_running(struct pp_hwmgr *hwmgr)
190{ 190{
191 return ((0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, 191 return ((0 == SMUM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
192 CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) 192 CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable))
193 && (0x20100 <= cgs_read_ind_register(smumgr->device, 193 && (0x20100 <= cgs_read_ind_register(hwmgr->device,
194 CGS_IND_REG__SMC, ixSMC_PC_C))); 194 CGS_IND_REG__SMC, ixSMC_PC_C)));
195} 195}
196 196
197static int ci_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, 197static int ci_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr,
198 uint32_t *value, uint32_t limit) 198 uint32_t *value, uint32_t limit)
199{ 199{
200 int result; 200 int result;
201 201
202 result = ci_set_smc_sram_address(smumgr, smc_addr, limit); 202 result = ci_set_smc_sram_address(hwmgr, smc_addr, limit);
203 203
204 if (result) 204 if (result)
205 return result; 205 return result;
206 206
207 *value = cgs_read_register(smumgr->device, mmSMC_IND_DATA_0); 207 *value = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_0);
208 return 0; 208 return 0;
209} 209}
210 210
211int ci_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg) 211int ci_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
212{ 212{
213 int ret; 213 int ret;
214 214
215 if (!ci_is_smc_ram_running(smumgr)) 215 if (!ci_is_smc_ram_running(hwmgr))
216 return -EINVAL; 216 return -EINVAL;
217 217
218 cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg); 218 cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, msg);
219 219
220 SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0); 220 SMUM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
221 221
222 ret = SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP); 222 ret = SMUM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP);
223 223
224 if (ret != 1) 224 if (ret != 1)
225 pr_info("\n failed to send message %x ret is %d\n", msg, ret); 225 pr_info("\n failed to send message %x ret is %d\n", msg, ret);
@@ -227,11 +227,11 @@ int ci_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
227 return 0; 227 return 0;
228} 228}
229 229
230int ci_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, 230int ci_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
231 uint16_t msg, uint32_t parameter) 231 uint16_t msg, uint32_t parameter)
232{ 232{
233 cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter); 233 cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, parameter);
234 return ci_send_msg_to_smc(smumgr, msg); 234 return ci_send_msg_to_smc(hwmgr, msg);
235} 235}
236 236
237static void ci_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) 237static void ci_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
@@ -510,7 +510,7 @@ int ci_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
510 data->dpm_level_enable_mask.sclk_dpm_enable_mask = 510 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
511 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); 511 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
512 512
513 result = ci_copy_bytes_to_smc(hwmgr->smumgr, array, 513 result = ci_copy_bytes_to_smc(hwmgr, array,
514 (u8 *)levels, array_size, 514 (u8 *)levels, array_size,
515 SMC_RAM_END); 515 SMC_RAM_END);
516 516
@@ -553,7 +553,7 @@ static int ci_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
553 const struct ci_pt_defaults *defaults = smu_data->power_tune_defaults; 553 const struct ci_pt_defaults *defaults = smu_data->power_tune_defaults;
554 uint32_t temp; 554 uint32_t temp;
555 555
556 if (ci_read_smc_sram_dword(hwmgr->smumgr, 556 if (ci_read_smc_sram_dword(hwmgr,
557 fuse_table_offset + 557 fuse_table_offset +
558 offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl), 558 offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl),
559 (uint32_t *)&temp, SMC_RAM_END)) 559 (uint32_t *)&temp, SMC_RAM_END))
@@ -686,7 +686,7 @@ static int ci_populate_pm_fuses(struct pp_hwmgr *hwmgr)
686 686
687 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 687 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
688 PHM_PlatformCaps_PowerContainment)) { 688 PHM_PlatformCaps_PowerContainment)) {
689 if (ci_read_smc_sram_dword(hwmgr->smumgr, 689 if (ci_read_smc_sram_dword(hwmgr,
690 SMU7_FIRMWARE_HEADER_LOCATION + 690 SMU7_FIRMWARE_HEADER_LOCATION +
691 offsetof(SMU7_Firmware_Header, PmFuseTable), 691 offsetof(SMU7_Firmware_Header, PmFuseTable),
692 &pm_fuse_table_offset, SMC_RAM_END)) { 692 &pm_fuse_table_offset, SMC_RAM_END)) {
@@ -713,7 +713,7 @@ static int ci_populate_pm_fuses(struct pp_hwmgr *hwmgr)
713 if (ret) 713 if (ret)
714 return ret; 714 return ret;
715 715
716 ret = ci_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset, 716 ret = ci_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
717 (uint8_t *)&smu_data->power_tune_table, 717 (uint8_t *)&smu_data->power_tune_table,
718 sizeof(struct SMU7_Discrete_PmFuses), SMC_RAM_END); 718 sizeof(struct SMU7_Discrete_PmFuses), SMC_RAM_END);
719 } 719 }
@@ -1343,7 +1343,7 @@ int ci_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1343 data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); 1343 data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1344 smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH; 1344 smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1345 1345
1346 result = ci_copy_bytes_to_smc(hwmgr->smumgr, 1346 result = ci_copy_bytes_to_smc(hwmgr,
1347 level_array_address, (uint8_t *)levels, (uint32_t)level_array_size, 1347 level_array_address, (uint8_t *)levels, (uint32_t)level_array_size,
1348 SMC_RAM_END); 1348 SMC_RAM_END);
1349 1349
@@ -1705,7 +1705,7 @@ static int ci_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1705 1705
1706 if (0 == result) { 1706 if (0 == result) {
1707 result = ci_copy_bytes_to_smc( 1707 result = ci_copy_bytes_to_smc(
1708 hwmgr->smumgr, 1708 hwmgr,
1709 smu_data->arb_table_start, 1709 smu_data->arb_table_start,
1710 (uint8_t *)&arb_regs, 1710 (uint8_t *)&arb_regs,
1711 sizeof(SMU7_Discrete_MCArbDramTimingTable), 1711 sizeof(SMU7_Discrete_MCArbDramTimingTable),
@@ -1756,10 +1756,10 @@ static int ci_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1756 return result; 1756 return result;
1757} 1757}
1758 1758
1759static int ci_populate_mc_reg_address(struct pp_smumgr *smumgr, 1759static int ci_populate_mc_reg_address(struct pp_hwmgr *hwmgr,
1760 SMU7_Discrete_MCRegisters *mc_reg_table) 1760 SMU7_Discrete_MCRegisters *mc_reg_table)
1761{ 1761{
1762 const struct ci_smumgr *smu_data = (struct ci_smumgr *)smumgr->backend; 1762 const struct ci_smumgr *smu_data = (struct ci_smumgr *)hwmgr->smumgr->backend;
1763 1763
1764 uint32_t i, j; 1764 uint32_t i, j;
1765 1765
@@ -1796,12 +1796,12 @@ static void ci_convert_mc_registers(
1796} 1796}
1797 1797
1798static int ci_convert_mc_reg_table_entry_to_smc( 1798static int ci_convert_mc_reg_table_entry_to_smc(
1799 struct pp_smumgr *smumgr, 1799 struct pp_hwmgr *hwmgr,
1800 const uint32_t memory_clock, 1800 const uint32_t memory_clock,
1801 SMU7_Discrete_MCRegisterSet *mc_reg_table_data 1801 SMU7_Discrete_MCRegisterSet *mc_reg_table_data
1802 ) 1802 )
1803{ 1803{
1804 struct ci_smumgr *smu_data = (struct ci_smumgr *)(smumgr->backend); 1804 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend);
1805 uint32_t i = 0; 1805 uint32_t i = 0;
1806 1806
1807 for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) { 1807 for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) {
@@ -1831,7 +1831,7 @@ static int ci_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
1831 1831
1832 for (i = 0; i < data->dpm_table.mclk_table.count; i++) { 1832 for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
1833 res = ci_convert_mc_reg_table_entry_to_smc( 1833 res = ci_convert_mc_reg_table_entry_to_smc(
1834 hwmgr->smumgr, 1834 hwmgr,
1835 data->dpm_table.mclk_table.dpm_levels[i].value, 1835 data->dpm_table.mclk_table.dpm_levels[i].value,
1836 &mc_regs->data[i] 1836 &mc_regs->data[i]
1837 ); 1837 );
@@ -1845,8 +1845,7 @@ static int ci_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
1845 1845
1846static int ci_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr) 1846static int ci_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
1847{ 1847{
1848 struct pp_smumgr *smumgr = hwmgr->smumgr; 1848 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend);
1849 struct ci_smumgr *smu_data = (struct ci_smumgr *)(smumgr->backend);
1850 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1849 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1851 uint32_t address; 1850 uint32_t address;
1852 int32_t result; 1851 int32_t result;
@@ -1864,7 +1863,7 @@ static int ci_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
1864 1863
1865 address = smu_data->mc_reg_table_start + (uint32_t)offsetof(SMU7_Discrete_MCRegisters, data[0]); 1864 address = smu_data->mc_reg_table_start + (uint32_t)offsetof(SMU7_Discrete_MCRegisters, data[0]);
1866 1865
1867 return ci_copy_bytes_to_smc(hwmgr->smumgr, address, 1866 return ci_copy_bytes_to_smc(hwmgr, address,
1868 (uint8_t *)&smu_data->mc_regs.data[0], 1867 (uint8_t *)&smu_data->mc_regs.data[0],
1869 sizeof(SMU7_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count, 1868 sizeof(SMU7_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count,
1870 SMC_RAM_END); 1869 SMC_RAM_END);
@@ -1873,11 +1872,10 @@ static int ci_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
1873static int ci_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr) 1872static int ci_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
1874{ 1873{
1875 int result; 1874 int result;
1876 struct pp_smumgr *smumgr = hwmgr->smumgr; 1875 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend);
1877 struct ci_smumgr *smu_data = (struct ci_smumgr *)(smumgr->backend);
1878 1876
1879 memset(&smu_data->mc_regs, 0x00, sizeof(SMU7_Discrete_MCRegisters)); 1877 memset(&smu_data->mc_regs, 0x00, sizeof(SMU7_Discrete_MCRegisters));
1880 result = ci_populate_mc_reg_address(smumgr, &(smu_data->mc_regs)); 1878 result = ci_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs));
1881 PP_ASSERT_WITH_CODE(0 == result, 1879 PP_ASSERT_WITH_CODE(0 == result,
1882 "Failed to initialize MCRegTable for the MC register addresses!", return result;); 1880 "Failed to initialize MCRegTable for the MC register addresses!", return result;);
1883 1881
@@ -1885,7 +1883,7 @@ static int ci_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
1885 PP_ASSERT_WITH_CODE(0 == result, 1883 PP_ASSERT_WITH_CODE(0 == result,
1886 "Failed to initialize MCRegTable for driver state!", return result;); 1884 "Failed to initialize MCRegTable for driver state!", return result;);
1887 1885
1888 return ci_copy_bytes_to_smc(smumgr, smu_data->mc_reg_table_start, 1886 return ci_copy_bytes_to_smc(hwmgr, smu_data->mc_reg_table_start,
1889 (uint8_t *)&smu_data->mc_regs, sizeof(SMU7_Discrete_MCRegisters), SMC_RAM_END); 1887 (uint8_t *)&smu_data->mc_regs, sizeof(SMU7_Discrete_MCRegisters), SMC_RAM_END);
1890} 1888}
1891 1889
@@ -1930,17 +1928,17 @@ static int ci_populate_smc_svi2_config(struct pp_hwmgr *hwmgr,
1930 return 0; 1928 return 0;
1931} 1929}
1932 1930
1933static int ci_start_smc(struct pp_smumgr *smumgr) 1931static int ci_start_smc(struct pp_hwmgr *hwmgr)
1934{ 1932{
1935 /* set smc instruct start point at 0x0 */ 1933 /* set smc instruct start point at 0x0 */
1936 ci_program_jump_on_start(smumgr); 1934 ci_program_jump_on_start(hwmgr);
1937 1935
1938 /* enable smc clock */ 1936 /* enable smc clock */
1939 SMUM_WRITE_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); 1937 SMUM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
1940 1938
1941 SMUM_WRITE_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 0); 1939 SMUM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 0);
1942 1940
1943 SMUM_WAIT_INDIRECT_FIELD(smumgr, SMC_IND, FIRMWARE_FLAGS, 1941 SMUM_WAIT_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS,
1944 INTERRUPTS_ENABLED, 1); 1942 INTERRUPTS_ENABLED, 1);
1945 1943
1946 return 0; 1944 return 0;
@@ -2105,7 +2103,7 @@ int ci_init_smc_table(struct pp_hwmgr *hwmgr)
2105 table->BootMVdd = PP_HOST_TO_SMC_US(table->BootMVdd * VOLTAGE_SCALE); 2103 table->BootMVdd = PP_HOST_TO_SMC_US(table->BootMVdd * VOLTAGE_SCALE);
2106 2104
2107 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */ 2105 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2108 result = ci_copy_bytes_to_smc(hwmgr->smumgr, smu_data->dpm_table_start + 2106 result = ci_copy_bytes_to_smc(hwmgr, smu_data->dpm_table_start +
2109 offsetof(SMU7_Discrete_DpmTable, SystemFlags), 2107 offsetof(SMU7_Discrete_DpmTable, SystemFlags),
2110 (uint8_t *)&(table->SystemFlags), 2108 (uint8_t *)&(table->SystemFlags),
2111 sizeof(SMU7_Discrete_DpmTable)-3 * sizeof(SMU7_PIDController), 2109 sizeof(SMU7_Discrete_DpmTable)-3 * sizeof(SMU7_PIDController),
@@ -2122,7 +2120,7 @@ int ci_init_smc_table(struct pp_hwmgr *hwmgr)
2122 PP_ASSERT_WITH_CODE(0 == result, 2120 PP_ASSERT_WITH_CODE(0 == result,
2123 "Failed to populate PM fuses to SMC memory!", return result); 2121 "Failed to populate PM fuses to SMC memory!", return result);
2124 2122
2125 ci_start_smc(hwmgr->smumgr); 2123 ci_start_smc(hwmgr);
2126 2124
2127 return 0; 2125 return 0;
2128} 2126}
@@ -2197,7 +2195,7 @@ int ci_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
2197 2195
2198 fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_MULT_THERMAL_CTRL, TEMP_SEL); 2196 fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_MULT_THERMAL_CTRL, TEMP_SEL);
2199 2197
2200 res = ci_copy_bytes_to_smc(hwmgr->smumgr, ci_data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), SMC_RAM_END); 2198 res = ci_copy_bytes_to_smc(hwmgr, ci_data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), SMC_RAM_END);
2201 2199
2202 return 0; 2200 return 0;
2203} 2201}
@@ -2233,7 +2231,7 @@ int ci_update_sclk_threshold(struct pp_hwmgr *hwmgr)
2233 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold); 2231 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
2234 2232
2235 result = ci_copy_bytes_to_smc( 2233 result = ci_copy_bytes_to_smc(
2236 hwmgr->smumgr, 2234 hwmgr,
2237 smu_data->dpm_table_start + 2235 smu_data->dpm_table_start +
2238 offsetof(SMU7_Discrete_DpmTable, 2236 offsetof(SMU7_Discrete_DpmTable,
2239 LowSclkInterruptT), 2237 LowSclkInterruptT),
@@ -2303,7 +2301,7 @@ uint32_t ci_get_mac_definition(uint32_t value)
2303 return 0; 2301 return 0;
2304} 2302}
2305 2303
2306static int ci_load_smc_ucode(struct pp_smumgr *smumgr) 2304static int ci_load_smc_ucode(struct pp_hwmgr *hwmgr)
2307{ 2305{
2308 uint32_t byte_count, start_addr; 2306 uint32_t byte_count, start_addr;
2309 uint8_t *src; 2307 uint8_t *src;
@@ -2311,9 +2309,9 @@ static int ci_load_smc_ucode(struct pp_smumgr *smumgr)
2311 2309
2312 struct cgs_firmware_info info = {0}; 2310 struct cgs_firmware_info info = {0};
2313 2311
2314 cgs_get_firmware_info(smumgr->device, CGS_UCODE_ID_SMU, &info); 2312 cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU, &info);
2315 2313
2316 smumgr->is_kicker = info.is_kicker; 2314 hwmgr->smumgr->is_kicker = info.is_kicker;
2317 byte_count = info.image_size; 2315 byte_count = info.image_size;
2318 src = (uint8_t *)info.kptr; 2316 src = (uint8_t *)info.kptr;
2319 start_addr = info.ucode_start_address; 2317 start_addr = info.ucode_start_address;
@@ -2323,15 +2321,15 @@ static int ci_load_smc_ucode(struct pp_smumgr *smumgr)
2323 return -EINVAL; 2321 return -EINVAL;
2324 } 2322 }
2325 2323
2326 cgs_write_register(smumgr->device, mmSMC_IND_INDEX_0, start_addr); 2324 cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, start_addr);
2327 SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1); 2325 SMUM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1);
2328 2326
2329 for (; byte_count >= 4; byte_count -= 4) { 2327 for (; byte_count >= 4; byte_count -= 4) {
2330 data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3]; 2328 data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
2331 cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, data); 2329 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data);
2332 src += 4; 2330 src += 4;
2333 } 2331 }
2334 SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0); 2332 SMUM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
2335 2333
2336 if (0 != byte_count) { 2334 if (0 != byte_count) {
2337 pr_err("SMC size must be dividable by 4\n"); 2335 pr_err("SMC size must be dividable by 4\n");
@@ -2343,18 +2341,18 @@ static int ci_load_smc_ucode(struct pp_smumgr *smumgr)
2343 2341
2344static int ci_upload_firmware(struct pp_hwmgr *hwmgr) 2342static int ci_upload_firmware(struct pp_hwmgr *hwmgr)
2345{ 2343{
2346 if (ci_is_smc_ram_running(hwmgr->smumgr)) { 2344 if (ci_is_smc_ram_running(hwmgr)) {
2347 pr_info("smc is running, no need to load smc firmware\n"); 2345 pr_info("smc is running, no need to load smc firmware\n");
2348 return 0; 2346 return 0;
2349 } 2347 }
2350 SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr->smumgr, SMC_IND, RCU_UC_EVENTS, 2348 SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS,
2351 boot_seq_done, 1); 2349 boot_seq_done, 1);
2352 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_MISC_CNTL, 2350 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_MISC_CNTL,
2353 pre_fetcher_en, 1); 2351 pre_fetcher_en, 1);
2354 2352
2355 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 1); 2353 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 1);
2356 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 1); 2354 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 1);
2357 return ci_load_smc_ucode(hwmgr->smumgr); 2355 return ci_load_smc_ucode(hwmgr);
2358} 2356}
2359 2357
2360int ci_process_firmware_header(struct pp_hwmgr *hwmgr) 2358int ci_process_firmware_header(struct pp_hwmgr *hwmgr)
@@ -2369,7 +2367,7 @@ int ci_process_firmware_header(struct pp_hwmgr *hwmgr)
2369 if (ci_upload_firmware(hwmgr)) 2367 if (ci_upload_firmware(hwmgr))
2370 return -EINVAL; 2368 return -EINVAL;
2371 2369
2372 result = ci_read_smc_sram_dword(hwmgr->smumgr, 2370 result = ci_read_smc_sram_dword(hwmgr,
2373 SMU7_FIRMWARE_HEADER_LOCATION + 2371 SMU7_FIRMWARE_HEADER_LOCATION +
2374 offsetof(SMU7_Firmware_Header, DpmTable), 2372 offsetof(SMU7_Firmware_Header, DpmTable),
2375 &tmp, SMC_RAM_END); 2373 &tmp, SMC_RAM_END);
@@ -2379,7 +2377,7 @@ int ci_process_firmware_header(struct pp_hwmgr *hwmgr)
2379 2377
2380 error |= (0 != result); 2378 error |= (0 != result);
2381 2379
2382 result = ci_read_smc_sram_dword(hwmgr->smumgr, 2380 result = ci_read_smc_sram_dword(hwmgr,
2383 SMU7_FIRMWARE_HEADER_LOCATION + 2381 SMU7_FIRMWARE_HEADER_LOCATION +
2384 offsetof(SMU7_Firmware_Header, SoftRegisters), 2382 offsetof(SMU7_Firmware_Header, SoftRegisters),
2385 &tmp, SMC_RAM_END); 2383 &tmp, SMC_RAM_END);
@@ -2391,7 +2389,7 @@ int ci_process_firmware_header(struct pp_hwmgr *hwmgr)
2391 2389
2392 error |= (0 != result); 2390 error |= (0 != result);
2393 2391
2394 result = ci_read_smc_sram_dword(hwmgr->smumgr, 2392 result = ci_read_smc_sram_dword(hwmgr,
2395 SMU7_FIRMWARE_HEADER_LOCATION + 2393 SMU7_FIRMWARE_HEADER_LOCATION +
2396 offsetof(SMU7_Firmware_Header, mcRegisterTable), 2394 offsetof(SMU7_Firmware_Header, mcRegisterTable),
2397 &tmp, SMC_RAM_END); 2395 &tmp, SMC_RAM_END);
@@ -2399,7 +2397,7 @@ int ci_process_firmware_header(struct pp_hwmgr *hwmgr)
2399 if (0 == result) 2397 if (0 == result)
2400 ci_data->mc_reg_table_start = tmp; 2398 ci_data->mc_reg_table_start = tmp;
2401 2399
2402 result = ci_read_smc_sram_dword(hwmgr->smumgr, 2400 result = ci_read_smc_sram_dword(hwmgr,
2403 SMU7_FIRMWARE_HEADER_LOCATION + 2401 SMU7_FIRMWARE_HEADER_LOCATION +
2404 offsetof(SMU7_Firmware_Header, FanTable), 2402 offsetof(SMU7_Firmware_Header, FanTable),
2405 &tmp, SMC_RAM_END); 2403 &tmp, SMC_RAM_END);
@@ -2409,7 +2407,7 @@ int ci_process_firmware_header(struct pp_hwmgr *hwmgr)
2409 2407
2410 error |= (0 != result); 2408 error |= (0 != result);
2411 2409
2412 result = ci_read_smc_sram_dword(hwmgr->smumgr, 2410 result = ci_read_smc_sram_dword(hwmgr,
2413 SMU7_FIRMWARE_HEADER_LOCATION + 2411 SMU7_FIRMWARE_HEADER_LOCATION +
2414 offsetof(SMU7_Firmware_Header, mcArbDramTimingTable), 2412 offsetof(SMU7_Firmware_Header, mcArbDramTimingTable),
2415 &tmp, SMC_RAM_END); 2413 &tmp, SMC_RAM_END);
@@ -2419,7 +2417,7 @@ int ci_process_firmware_header(struct pp_hwmgr *hwmgr)
2419 2417
2420 error |= (0 != result); 2418 error |= (0 != result);
2421 2419
2422 result = ci_read_smc_sram_dword(hwmgr->smumgr, 2420 result = ci_read_smc_sram_dword(hwmgr,
2423 SMU7_FIRMWARE_HEADER_LOCATION + 2421 SMU7_FIRMWARE_HEADER_LOCATION +
2424 offsetof(SMU7_Firmware_Header, Version), 2422 offsetof(SMU7_Firmware_Header, Version),
2425 &tmp, SMC_RAM_END); 2423 &tmp, SMC_RAM_END);
@@ -2726,7 +2724,7 @@ int ci_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
2726 2724
2727bool ci_is_dpm_running(struct pp_hwmgr *hwmgr) 2725bool ci_is_dpm_running(struct pp_hwmgr *hwmgr)
2728{ 2726{
2729 return ci_is_smc_ram_running(hwmgr->smumgr); 2727 return ci_is_smc_ram_running(hwmgr);
2730} 2728}
2731 2729
2732int ci_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr, 2730int ci_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
@@ -2750,6 +2748,6 @@ int ci_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
2750 levels[i].DownH = request->down_hyst; 2748 levels[i].DownH = request->down_hyst;
2751 } 2749 }
2752 2750
2753 return ci_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels, 2751 return ci_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
2754 array_size, SMC_RAM_END); 2752 array_size, SMC_RAM_END);
2755} 2753}
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.h b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.h
index 05b36b800942..cc4176d2d25f 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.h
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.h
@@ -30,9 +30,9 @@ struct pp_smumgr;
30struct pp_hwmgr; 30struct pp_hwmgr;
31struct amd_pp_profile; 31struct amd_pp_profile;
32 32
33int ci_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, 33int ci_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
34 uint16_t msg, uint32_t parameter); 34 uint16_t msg, uint32_t parameter);
35int ci_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg); 35int ci_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg);
36int ci_populate_all_graphic_levels(struct pp_hwmgr *hwmgr); 36int ci_populate_all_graphic_levels(struct pp_hwmgr *hwmgr);
37int ci_populate_all_memory_levels(struct pp_hwmgr *hwmgr); 37int ci_populate_all_memory_levels(struct pp_hwmgr *hwmgr);
38int ci_init_smc_table(struct pp_hwmgr *hwmgr); 38int ci_init_smc_table(struct pp_hwmgr *hwmgr);
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
index 62f6bdae6612..d2e24e3a963d 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
@@ -30,7 +30,7 @@
30#include "cgs_common.h" 30#include "cgs_common.h"
31#include "ci_smc.h" 31#include "ci_smc.h"
32 32
33static int ci_smu_init(struct pp_smumgr *smumgr) 33static int ci_smu_init(struct pp_hwmgr *hwmgr)
34{ 34{
35 int i; 35 int i;
36 struct ci_smumgr *ci_priv = NULL; 36 struct ci_smumgr *ci_priv = NULL;
@@ -43,20 +43,20 @@ static int ci_smu_init(struct pp_smumgr *smumgr)
43 for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) 43 for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++)
44 ci_priv->activity_target[i] = 30; 44 ci_priv->activity_target[i] = 30;
45 45
46 smumgr->backend = ci_priv; 46 hwmgr->smumgr->backend = ci_priv;
47 47
48 return 0; 48 return 0;
49} 49}
50 50
51static int ci_smu_fini(struct pp_smumgr *smumgr) 51static int ci_smu_fini(struct pp_hwmgr *hwmgr)
52{ 52{
53 kfree(smumgr->backend); 53 kfree(hwmgr->smumgr->backend);
54 smumgr->backend = NULL; 54 hwmgr->smumgr->backend = NULL;
55 cgs_rel_firmware(smumgr->device, CGS_UCODE_ID_SMU); 55 cgs_rel_firmware(hwmgr->device, CGS_UCODE_ID_SMU);
56 return 0; 56 return 0;
57} 57}
58 58
59static int ci_start_smu(struct pp_smumgr *smumgr) 59static int ci_start_smu(struct pp_hwmgr *hwmgr)
60{ 60{
61 return 0; 61 return 0;
62} 62}
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
index 652aaa43e95c..a6fa0e86a8fd 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
@@ -52,53 +52,52 @@ static const enum cz_scratch_entry firmware_list[] = {
52 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, 52 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G,
53}; 53};
54 54
55static int cz_smum_get_argument(struct pp_smumgr *smumgr) 55static int cz_smum_get_argument(struct pp_hwmgr *hwmgr)
56{ 56{
57 if (smumgr == NULL || smumgr->device == NULL) 57 if (hwmgr == NULL || hwmgr->device == NULL)
58 return -EINVAL; 58 return -EINVAL;
59 59
60 return cgs_read_register(smumgr->device, 60 return cgs_read_register(hwmgr->device,
61 mmSMU_MP1_SRBM2P_ARG_0); 61 mmSMU_MP1_SRBM2P_ARG_0);
62} 62}
63 63
64static int cz_send_msg_to_smc_async(struct pp_smumgr *smumgr, 64static int cz_send_msg_to_smc_async(struct pp_hwmgr *hwmgr, uint16_t msg)
65 uint16_t msg)
66{ 65{
67 int result = 0; 66 int result = 0;
68 67
69 if (smumgr == NULL || smumgr->device == NULL) 68 if (hwmgr == NULL || hwmgr->device == NULL)
70 return -EINVAL; 69 return -EINVAL;
71 70
72 result = SMUM_WAIT_FIELD_UNEQUAL(smumgr, 71 result = SMUM_WAIT_FIELD_UNEQUAL(hwmgr,
73 SMU_MP1_SRBM2P_RESP_0, CONTENT, 0); 72 SMU_MP1_SRBM2P_RESP_0, CONTENT, 0);
74 if (result != 0) { 73 if (result != 0) {
75 pr_err("cz_send_msg_to_smc_async (0x%04x) failed\n", msg); 74 pr_err("cz_send_msg_to_smc_async (0x%04x) failed\n", msg);
76 return result; 75 return result;
77 } 76 }
78 77
79 cgs_write_register(smumgr->device, mmSMU_MP1_SRBM2P_RESP_0, 0); 78 cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_RESP_0, 0);
80 cgs_write_register(smumgr->device, mmSMU_MP1_SRBM2P_MSG_0, msg); 79 cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_MSG_0, msg);
81 80
82 return 0; 81 return 0;
83} 82}
84 83
85/* Send a message to the SMC, and wait for its response.*/ 84/* Send a message to the SMC, and wait for its response.*/
86static int cz_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg) 85static int cz_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
87{ 86{
88 int result = 0; 87 int result = 0;
89 88
90 result = cz_send_msg_to_smc_async(smumgr, msg); 89 result = cz_send_msg_to_smc_async(hwmgr, msg);
91 if (result != 0) 90 if (result != 0)
92 return result; 91 return result;
93 92
94 return SMUM_WAIT_FIELD_UNEQUAL(smumgr, 93 return SMUM_WAIT_FIELD_UNEQUAL(hwmgr,
95 SMU_MP1_SRBM2P_RESP_0, CONTENT, 0); 94 SMU_MP1_SRBM2P_RESP_0, CONTENT, 0);
96} 95}
97 96
98static int cz_set_smc_sram_address(struct pp_smumgr *smumgr, 97static int cz_set_smc_sram_address(struct pp_hwmgr *hwmgr,
99 uint32_t smc_address, uint32_t limit) 98 uint32_t smc_address, uint32_t limit)
100{ 99{
101 if (smumgr == NULL || smumgr->device == NULL) 100 if (hwmgr == NULL || hwmgr->device == NULL)
102 return -EINVAL; 101 return -EINVAL;
103 102
104 if (0 != (3 & smc_address)) { 103 if (0 != (3 & smc_address)) {
@@ -111,39 +110,39 @@ static int cz_set_smc_sram_address(struct pp_smumgr *smumgr,
111 return -EINVAL; 110 return -EINVAL;
112 } 111 }
113 112
114 cgs_write_register(smumgr->device, mmMP0PUB_IND_INDEX_0, 113 cgs_write_register(hwmgr->device, mmMP0PUB_IND_INDEX_0,
115 SMN_MP1_SRAM_START_ADDR + smc_address); 114 SMN_MP1_SRAM_START_ADDR + smc_address);
116 115
117 return 0; 116 return 0;
118} 117}
119 118
120static int cz_write_smc_sram_dword(struct pp_smumgr *smumgr, 119static int cz_write_smc_sram_dword(struct pp_hwmgr *hwmgr,
121 uint32_t smc_address, uint32_t value, uint32_t limit) 120 uint32_t smc_address, uint32_t value, uint32_t limit)
122{ 121{
123 int result; 122 int result;
124 123
125 if (smumgr == NULL || smumgr->device == NULL) 124 if (hwmgr == NULL || hwmgr->device == NULL)
126 return -EINVAL; 125 return -EINVAL;
127 126
128 result = cz_set_smc_sram_address(smumgr, smc_address, limit); 127 result = cz_set_smc_sram_address(hwmgr, smc_address, limit);
129 if (!result) 128 if (!result)
130 cgs_write_register(smumgr->device, mmMP0PUB_IND_DATA_0, value); 129 cgs_write_register(hwmgr->device, mmMP0PUB_IND_DATA_0, value);
131 130
132 return result; 131 return result;
133} 132}
134 133
135static int cz_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, 134static int cz_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
136 uint16_t msg, uint32_t parameter) 135 uint16_t msg, uint32_t parameter)
137{ 136{
138 if (smumgr == NULL || smumgr->device == NULL) 137 if (hwmgr == NULL || hwmgr->device == NULL)
139 return -EINVAL; 138 return -EINVAL;
140 139
141 cgs_write_register(smumgr->device, mmSMU_MP1_SRBM2P_ARG_0, parameter); 140 cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0, parameter);
142 141
143 return cz_send_msg_to_smc(smumgr, msg); 142 return cz_send_msg_to_smc(hwmgr, msg);
144} 143}
145 144
146static int cz_check_fw_load_finish(struct pp_smumgr *smumgr, 145static int cz_check_fw_load_finish(struct pp_hwmgr *hwmgr,
147 uint32_t firmware) 146 uint32_t firmware)
148{ 147{
149 int i; 148 int i;
@@ -151,19 +150,19 @@ static int cz_check_fw_load_finish(struct pp_smumgr *smumgr,
151 SMU8_FIRMWARE_HEADER_LOCATION + 150 SMU8_FIRMWARE_HEADER_LOCATION +
152 offsetof(struct SMU8_Firmware_Header, UcodeLoadStatus); 151 offsetof(struct SMU8_Firmware_Header, UcodeLoadStatus);
153 152
154 if (smumgr == NULL || smumgr->device == NULL) 153 if (hwmgr == NULL || hwmgr->device == NULL)
155 return -EINVAL; 154 return -EINVAL;
156 155
157 cgs_write_register(smumgr->device, mmMP0PUB_IND_INDEX, index); 156 cgs_write_register(hwmgr->device, mmMP0PUB_IND_INDEX, index);
158 157
159 for (i = 0; i < smumgr->usec_timeout; i++) { 158 for (i = 0; i < hwmgr->usec_timeout; i++) {
160 if (firmware == 159 if (firmware ==
161 (cgs_read_register(smumgr->device, mmMP0PUB_IND_DATA) & firmware)) 160 (cgs_read_register(hwmgr->device, mmMP0PUB_IND_DATA) & firmware))
162 break; 161 break;
163 udelay(1); 162 udelay(1);
164 } 163 }
165 164
166 if (i >= smumgr->usec_timeout) { 165 if (i >= hwmgr->usec_timeout) {
167 pr_err("SMU check loaded firmware failed.\n"); 166 pr_err("SMU check loaded firmware failed.\n");
168 return -EINVAL; 167 return -EINVAL;
169 } 168 }
@@ -171,7 +170,7 @@ static int cz_check_fw_load_finish(struct pp_smumgr *smumgr,
171 return 0; 170 return 0;
172} 171}
173 172
174static int cz_load_mec_firmware(struct pp_smumgr *smumgr) 173static int cz_load_mec_firmware(struct pp_hwmgr *hwmgr)
175{ 174{
176 uint32_t reg_data; 175 uint32_t reg_data;
177 uint32_t tmp; 176 uint32_t tmp;
@@ -179,44 +178,44 @@ static int cz_load_mec_firmware(struct pp_smumgr *smumgr)
179 struct cgs_firmware_info info = {0}; 178 struct cgs_firmware_info info = {0};
180 struct cz_smumgr *cz_smu; 179 struct cz_smumgr *cz_smu;
181 180
182 if (smumgr == NULL || smumgr->device == NULL) 181 if (hwmgr == NULL || hwmgr->device == NULL)
183 return -EINVAL; 182 return -EINVAL;
184 183
185 cz_smu = (struct cz_smumgr *)smumgr->backend; 184 cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend;
186 ret = cgs_get_firmware_info(smumgr->device, 185 ret = cgs_get_firmware_info(hwmgr->device,
187 CGS_UCODE_ID_CP_MEC, &info); 186 CGS_UCODE_ID_CP_MEC, &info);
188 187
189 if (ret) 188 if (ret)
190 return -EINVAL; 189 return -EINVAL;
191 190
192 /* Disable MEC parsing/prefetching */ 191 /* Disable MEC parsing/prefetching */
193 tmp = cgs_read_register(smumgr->device, 192 tmp = cgs_read_register(hwmgr->device,
194 mmCP_MEC_CNTL); 193 mmCP_MEC_CNTL);
195 tmp = SMUM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1); 194 tmp = SMUM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);
196 tmp = SMUM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1); 195 tmp = SMUM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);
197 cgs_write_register(smumgr->device, mmCP_MEC_CNTL, tmp); 196 cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, tmp);
198 197
199 tmp = cgs_read_register(smumgr->device, 198 tmp = cgs_read_register(hwmgr->device,
200 mmCP_CPC_IC_BASE_CNTL); 199 mmCP_CPC_IC_BASE_CNTL);
201 200
202 tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 201 tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
203 tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ATC, 0); 202 tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ATC, 0);
204 tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 203 tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
205 tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, MTYPE, 1); 204 tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, MTYPE, 1);
206 cgs_write_register(smumgr->device, mmCP_CPC_IC_BASE_CNTL, tmp); 205 cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_CNTL, tmp);
207 206
208 reg_data = smu_lower_32_bits(info.mc_addr) & 207 reg_data = smu_lower_32_bits(info.mc_addr) &
209 SMUM_FIELD_MASK(CP_CPC_IC_BASE_LO, IC_BASE_LO); 208 SMUM_FIELD_MASK(CP_CPC_IC_BASE_LO, IC_BASE_LO);
210 cgs_write_register(smumgr->device, mmCP_CPC_IC_BASE_LO, reg_data); 209 cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_LO, reg_data);
211 210
212 reg_data = smu_upper_32_bits(info.mc_addr) & 211 reg_data = smu_upper_32_bits(info.mc_addr) &
213 SMUM_FIELD_MASK(CP_CPC_IC_BASE_HI, IC_BASE_HI); 212 SMUM_FIELD_MASK(CP_CPC_IC_BASE_HI, IC_BASE_HI);
214 cgs_write_register(smumgr->device, mmCP_CPC_IC_BASE_HI, reg_data); 213 cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_HI, reg_data);
215 214
216 return 0; 215 return 0;
217} 216}
218 217
219static uint8_t cz_translate_firmware_enum_to_arg(struct pp_smumgr *smumgr, 218static uint8_t cz_translate_firmware_enum_to_arg(struct pp_hwmgr *hwmgr,
220 enum cz_scratch_entry firmware_enum) 219 enum cz_scratch_entry firmware_enum)
221{ 220{
222 uint8_t ret = 0; 221 uint8_t ret = 0;
@@ -226,7 +225,7 @@ static uint8_t cz_translate_firmware_enum_to_arg(struct pp_smumgr *smumgr,
226 ret = UCODE_ID_SDMA0; 225 ret = UCODE_ID_SDMA0;
227 break; 226 break;
228 case CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1: 227 case CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1:
229 if (smumgr->chip_id == CHIP_STONEY) 228 if (hwmgr->chip_id == CHIP_STONEY)
230 ret = UCODE_ID_SDMA0; 229 ret = UCODE_ID_SDMA0;
231 else 230 else
232 ret = UCODE_ID_SDMA1; 231 ret = UCODE_ID_SDMA1;
@@ -244,7 +243,7 @@ static uint8_t cz_translate_firmware_enum_to_arg(struct pp_smumgr *smumgr,
244 ret = UCODE_ID_CP_MEC_JT1; 243 ret = UCODE_ID_CP_MEC_JT1;
245 break; 244 break;
246 case CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2: 245 case CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2:
247 if (smumgr->chip_id == CHIP_STONEY) 246 if (hwmgr->chip_id == CHIP_STONEY)
248 ret = UCODE_ID_CP_MEC_JT1; 247 ret = UCODE_ID_CP_MEC_JT1;
249 else 248 else
250 ret = UCODE_ID_CP_MEC_JT2; 249 ret = UCODE_ID_CP_MEC_JT2;
@@ -326,17 +325,17 @@ static enum cgs_ucode_id cz_convert_fw_type_to_cgs(uint32_t fw_type)
326} 325}
327 326
328static int cz_smu_populate_single_scratch_task( 327static int cz_smu_populate_single_scratch_task(
329 struct pp_smumgr *smumgr, 328 struct pp_hwmgr *hwmgr,
330 enum cz_scratch_entry fw_enum, 329 enum cz_scratch_entry fw_enum,
331 uint8_t type, bool is_last) 330 uint8_t type, bool is_last)
332{ 331{
333 uint8_t i; 332 uint8_t i;
334 struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; 333 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend;
335 struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr; 334 struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
336 struct SMU_Task *task = &toc->tasks[cz_smu->toc_entry_used_count++]; 335 struct SMU_Task *task = &toc->tasks[cz_smu->toc_entry_used_count++];
337 336
338 task->type = type; 337 task->type = type;
339 task->arg = cz_translate_firmware_enum_to_arg(smumgr, fw_enum); 338 task->arg = cz_translate_firmware_enum_to_arg(hwmgr, fw_enum);
340 task->next = is_last ? END_OF_TASK_LIST : cz_smu->toc_entry_used_count; 339 task->next = is_last ? END_OF_TASK_LIST : cz_smu->toc_entry_used_count;
341 340
342 for (i = 0; i < cz_smu->scratch_buffer_length; i++) 341 for (i = 0; i < cz_smu->scratch_buffer_length; i++)
@@ -363,17 +362,17 @@ static int cz_smu_populate_single_scratch_task(
363} 362}
364 363
365static int cz_smu_populate_single_ucode_load_task( 364static int cz_smu_populate_single_ucode_load_task(
366 struct pp_smumgr *smumgr, 365 struct pp_hwmgr *hwmgr,
367 enum cz_scratch_entry fw_enum, 366 enum cz_scratch_entry fw_enum,
368 bool is_last) 367 bool is_last)
369{ 368{
370 uint8_t i; 369 uint8_t i;
371 struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; 370 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend;
372 struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr; 371 struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
373 struct SMU_Task *task = &toc->tasks[cz_smu->toc_entry_used_count++]; 372 struct SMU_Task *task = &toc->tasks[cz_smu->toc_entry_used_count++];
374 373
375 task->type = TASK_TYPE_UCODE_LOAD; 374 task->type = TASK_TYPE_UCODE_LOAD;
376 task->arg = cz_translate_firmware_enum_to_arg(smumgr, fw_enum); 375 task->arg = cz_translate_firmware_enum_to_arg(hwmgr, fw_enum);
377 task->next = is_last ? END_OF_TASK_LIST : cz_smu->toc_entry_used_count; 376 task->next = is_last ? END_OF_TASK_LIST : cz_smu->toc_entry_used_count;
378 377
379 for (i = 0; i < cz_smu->driver_buffer_length; i++) 378 for (i = 0; i < cz_smu->driver_buffer_length; i++)
@@ -392,22 +391,22 @@ static int cz_smu_populate_single_ucode_load_task(
392 return 0; 391 return 0;
393} 392}
394 393
395static int cz_smu_construct_toc_for_rlc_aram_save(struct pp_smumgr *smumgr) 394static int cz_smu_construct_toc_for_rlc_aram_save(struct pp_hwmgr *hwmgr)
396{ 395{
397 struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; 396 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend;
398 397
399 cz_smu->toc_entry_aram = cz_smu->toc_entry_used_count; 398 cz_smu->toc_entry_aram = cz_smu->toc_entry_used_count;
400 cz_smu_populate_single_scratch_task(smumgr, 399 cz_smu_populate_single_scratch_task(hwmgr,
401 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM, 400 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
402 TASK_TYPE_UCODE_SAVE, true); 401 TASK_TYPE_UCODE_SAVE, true);
403 402
404 return 0; 403 return 0;
405} 404}
406 405
407static int cz_smu_initialize_toc_empty_job_list(struct pp_smumgr *smumgr) 406static int cz_smu_initialize_toc_empty_job_list(struct pp_hwmgr *hwmgr)
408{ 407{
409 int i; 408 int i;
410 struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; 409 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend;
411 struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr; 410 struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
412 411
413 for (i = 0; i < NUM_JOBLIST_ENTRIES; i++) 412 for (i = 0; i < NUM_JOBLIST_ENTRIES; i++)
@@ -416,17 +415,17 @@ static int cz_smu_initialize_toc_empty_job_list(struct pp_smumgr *smumgr)
416 return 0; 415 return 0;
417} 416}
418 417
419static int cz_smu_construct_toc_for_vddgfx_enter(struct pp_smumgr *smumgr) 418static int cz_smu_construct_toc_for_vddgfx_enter(struct pp_hwmgr *hwmgr)
420{ 419{
421 struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; 420 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend;
422 struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr; 421 struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
423 422
424 toc->JobList[JOB_GFX_SAVE] = (uint8_t)cz_smu->toc_entry_used_count; 423 toc->JobList[JOB_GFX_SAVE] = (uint8_t)cz_smu->toc_entry_used_count;
425 cz_smu_populate_single_scratch_task(smumgr, 424 cz_smu_populate_single_scratch_task(hwmgr,
426 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH, 425 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
427 TASK_TYPE_UCODE_SAVE, false); 426 TASK_TYPE_UCODE_SAVE, false);
428 427
429 cz_smu_populate_single_scratch_task(smumgr, 428 cz_smu_populate_single_scratch_task(hwmgr,
430 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM, 429 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
431 TASK_TYPE_UCODE_SAVE, true); 430 TASK_TYPE_UCODE_SAVE, true);
432 431
@@ -434,121 +433,120 @@ static int cz_smu_construct_toc_for_vddgfx_enter(struct pp_smumgr *smumgr)
434} 433}
435 434
436 435
437static int cz_smu_construct_toc_for_vddgfx_exit(struct pp_smumgr *smumgr) 436static int cz_smu_construct_toc_for_vddgfx_exit(struct pp_hwmgr *hwmgr)
438{ 437{
439 struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; 438 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend;
440 struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr; 439 struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
441 440
442 toc->JobList[JOB_GFX_RESTORE] = (uint8_t)cz_smu->toc_entry_used_count; 441 toc->JobList[JOB_GFX_RESTORE] = (uint8_t)cz_smu->toc_entry_used_count;
443 442
444 cz_smu_populate_single_ucode_load_task(smumgr, 443 cz_smu_populate_single_ucode_load_task(hwmgr,
445 CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, false); 444 CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, false);
446 cz_smu_populate_single_ucode_load_task(smumgr, 445 cz_smu_populate_single_ucode_load_task(hwmgr,
447 CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP, false); 446 CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP, false);
448 cz_smu_populate_single_ucode_load_task(smumgr, 447 cz_smu_populate_single_ucode_load_task(hwmgr,
449 CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false); 448 CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false);
450 cz_smu_populate_single_ucode_load_task(smumgr, 449 cz_smu_populate_single_ucode_load_task(hwmgr,
451 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false); 450 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
452 451
453 if (smumgr->chip_id == CHIP_STONEY) 452 if (hwmgr->chip_id == CHIP_STONEY)
454 cz_smu_populate_single_ucode_load_task(smumgr, 453 cz_smu_populate_single_ucode_load_task(hwmgr,
455 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false); 454 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
456 else 455 else
457 cz_smu_populate_single_ucode_load_task(smumgr, 456 cz_smu_populate_single_ucode_load_task(hwmgr,
458 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false); 457 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false);
459 458
460 cz_smu_populate_single_ucode_load_task(smumgr, 459 cz_smu_populate_single_ucode_load_task(hwmgr,
461 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, false); 460 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, false);
462 461
463 /* populate scratch */ 462 /* populate scratch */
464 cz_smu_populate_single_scratch_task(smumgr, 463 cz_smu_populate_single_scratch_task(hwmgr,
465 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH, 464 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
466 TASK_TYPE_UCODE_LOAD, false); 465 TASK_TYPE_UCODE_LOAD, false);
467 466
468 cz_smu_populate_single_scratch_task(smumgr, 467 cz_smu_populate_single_scratch_task(hwmgr,
469 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM, 468 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
470 TASK_TYPE_UCODE_LOAD, false); 469 TASK_TYPE_UCODE_LOAD, false);
471 470
472 cz_smu_populate_single_scratch_task(smumgr, 471 cz_smu_populate_single_scratch_task(hwmgr,
473 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM, 472 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
474 TASK_TYPE_UCODE_LOAD, true); 473 TASK_TYPE_UCODE_LOAD, true);
475 474
476 return 0; 475 return 0;
477} 476}
478 477
479static int cz_smu_construct_toc_for_power_profiling( 478static int cz_smu_construct_toc_for_power_profiling(struct pp_hwmgr *hwmgr)
480 struct pp_smumgr *smumgr)
481{ 479{
482 struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; 480 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend;
483 481
484 cz_smu->toc_entry_power_profiling_index = cz_smu->toc_entry_used_count; 482 cz_smu->toc_entry_power_profiling_index = cz_smu->toc_entry_used_count;
485 483
486 cz_smu_populate_single_scratch_task(smumgr, 484 cz_smu_populate_single_scratch_task(hwmgr,
487 CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING, 485 CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING,
488 TASK_TYPE_INITIALIZE, true); 486 TASK_TYPE_INITIALIZE, true);
489 return 0; 487 return 0;
490} 488}
491 489
492static int cz_smu_construct_toc_for_bootup(struct pp_smumgr *smumgr) 490static int cz_smu_construct_toc_for_bootup(struct pp_hwmgr *hwmgr)
493{ 491{
494 struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; 492 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend;
495 493
496 cz_smu->toc_entry_initialize_index = cz_smu->toc_entry_used_count; 494 cz_smu->toc_entry_initialize_index = cz_smu->toc_entry_used_count;
497 495
498 cz_smu_populate_single_ucode_load_task(smumgr, 496 cz_smu_populate_single_ucode_load_task(hwmgr,
499 CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0, false); 497 CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0, false);
500 if (smumgr->chip_id != CHIP_STONEY) 498 if (hwmgr->chip_id != CHIP_STONEY)
501 cz_smu_populate_single_ucode_load_task(smumgr, 499 cz_smu_populate_single_ucode_load_task(hwmgr,
502 CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1, false); 500 CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1, false);
503 cz_smu_populate_single_ucode_load_task(smumgr, 501 cz_smu_populate_single_ucode_load_task(hwmgr,
504 CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, false); 502 CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, false);
505 cz_smu_populate_single_ucode_load_task(smumgr, 503 cz_smu_populate_single_ucode_load_task(hwmgr,
506 CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP, false); 504 CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP, false);
507 cz_smu_populate_single_ucode_load_task(smumgr, 505 cz_smu_populate_single_ucode_load_task(hwmgr,
508 CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false); 506 CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false);
509 cz_smu_populate_single_ucode_load_task(smumgr, 507 cz_smu_populate_single_ucode_load_task(hwmgr,
510 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false); 508 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
511 if (smumgr->chip_id != CHIP_STONEY) 509 if (hwmgr->chip_id != CHIP_STONEY)
512 cz_smu_populate_single_ucode_load_task(smumgr, 510 cz_smu_populate_single_ucode_load_task(hwmgr,
513 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false); 511 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false);
514 cz_smu_populate_single_ucode_load_task(smumgr, 512 cz_smu_populate_single_ucode_load_task(hwmgr,
515 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, true); 513 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, true);
516 514
517 return 0; 515 return 0;
518} 516}
519 517
520static int cz_smu_construct_toc_for_clock_table(struct pp_smumgr *smumgr) 518static int cz_smu_construct_toc_for_clock_table(struct pp_hwmgr *hwmgr)
521{ 519{
522 struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; 520 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend;
523 521
524 cz_smu->toc_entry_clock_table = cz_smu->toc_entry_used_count; 522 cz_smu->toc_entry_clock_table = cz_smu->toc_entry_used_count;
525 523
526 cz_smu_populate_single_scratch_task(smumgr, 524 cz_smu_populate_single_scratch_task(hwmgr,
527 CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE, 525 CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE,
528 TASK_TYPE_INITIALIZE, true); 526 TASK_TYPE_INITIALIZE, true);
529 527
530 return 0; 528 return 0;
531} 529}
532 530
533static int cz_smu_construct_toc(struct pp_smumgr *smumgr) 531static int cz_smu_construct_toc(struct pp_hwmgr *hwmgr)
534{ 532{
535 struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; 533 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend;
536 534
537 cz_smu->toc_entry_used_count = 0; 535 cz_smu->toc_entry_used_count = 0;
538 cz_smu_initialize_toc_empty_job_list(smumgr); 536 cz_smu_initialize_toc_empty_job_list(hwmgr);
539 cz_smu_construct_toc_for_rlc_aram_save(smumgr); 537 cz_smu_construct_toc_for_rlc_aram_save(hwmgr);
540 cz_smu_construct_toc_for_vddgfx_enter(smumgr); 538 cz_smu_construct_toc_for_vddgfx_enter(hwmgr);
541 cz_smu_construct_toc_for_vddgfx_exit(smumgr); 539 cz_smu_construct_toc_for_vddgfx_exit(hwmgr);
542 cz_smu_construct_toc_for_power_profiling(smumgr); 540 cz_smu_construct_toc_for_power_profiling(hwmgr);
543 cz_smu_construct_toc_for_bootup(smumgr); 541 cz_smu_construct_toc_for_bootup(hwmgr);
544 cz_smu_construct_toc_for_clock_table(smumgr); 542 cz_smu_construct_toc_for_clock_table(hwmgr);
545 543
546 return 0; 544 return 0;
547} 545}
548 546
549static int cz_smu_populate_firmware_entries(struct pp_smumgr *smumgr) 547static int cz_smu_populate_firmware_entries(struct pp_hwmgr *hwmgr)
550{ 548{
551 struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; 549 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend;
552 uint32_t firmware_type; 550 uint32_t firmware_type;
553 uint32_t i; 551 uint32_t i;
554 int ret; 552 int ret;
@@ -559,12 +557,12 @@ static int cz_smu_populate_firmware_entries(struct pp_smumgr *smumgr)
559 557
560 for (i = 0; i < ARRAY_SIZE(firmware_list); i++) { 558 for (i = 0; i < ARRAY_SIZE(firmware_list); i++) {
561 559
562 firmware_type = cz_translate_firmware_enum_to_arg(smumgr, 560 firmware_type = cz_translate_firmware_enum_to_arg(hwmgr,
563 firmware_list[i]); 561 firmware_list[i]);
564 562
565 ucode_id = cz_convert_fw_type_to_cgs(firmware_type); 563 ucode_id = cz_convert_fw_type_to_cgs(firmware_type);
566 564
567 ret = cgs_get_firmware_info(smumgr->device, 565 ret = cgs_get_firmware_info(hwmgr->device,
568 ucode_id, &info); 566 ucode_id, &info);
569 567
570 if (ret == 0) { 568 if (ret == 0) {
@@ -585,12 +583,12 @@ static int cz_smu_populate_firmware_entries(struct pp_smumgr *smumgr)
585} 583}
586 584
587static int cz_smu_populate_single_scratch_entry( 585static int cz_smu_populate_single_scratch_entry(
588 struct pp_smumgr *smumgr, 586 struct pp_hwmgr *hwmgr,
589 enum cz_scratch_entry scratch_type, 587 enum cz_scratch_entry scratch_type,
590 uint32_t ulsize_byte, 588 uint32_t ulsize_byte,
591 struct cz_buffer_entry *entry) 589 struct cz_buffer_entry *entry)
592{ 590{
593 struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; 591 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend;
594 long long mc_addr = 592 long long mc_addr =
595 ((long long)(cz_smu->smu_buffer.mc_addr_high) << 32) 593 ((long long)(cz_smu->smu_buffer.mc_addr_high) << 32)
596 | cz_smu->smu_buffer.mc_addr_low; 594 | cz_smu->smu_buffer.mc_addr_low;
@@ -611,9 +609,9 @@ static int cz_smu_populate_single_scratch_entry(
611 return 0; 609 return 0;
612} 610}
613 611
614static int cz_download_pptable_settings(struct pp_smumgr *smumgr, void **table) 612static int cz_download_pptable_settings(struct pp_hwmgr *hwmgr, void **table)
615{ 613{
616 struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; 614 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend;
617 unsigned long i; 615 unsigned long i;
618 616
619 for (i = 0; i < cz_smu->scratch_buffer_length; i++) { 617 for (i = 0; i < cz_smu->scratch_buffer_length; i++) {
@@ -624,25 +622,25 @@ static int cz_download_pptable_settings(struct pp_smumgr *smumgr, void **table)
624 622
625 *table = (struct SMU8_Fusion_ClkTable *)cz_smu->scratch_buffer[i].kaddr; 623 *table = (struct SMU8_Fusion_ClkTable *)cz_smu->scratch_buffer[i].kaddr;
626 624
627 cz_send_msg_to_smc_with_parameter(smumgr, 625 cz_send_msg_to_smc_with_parameter(hwmgr,
628 PPSMC_MSG_SetClkTableAddrHi, 626 PPSMC_MSG_SetClkTableAddrHi,
629 cz_smu->scratch_buffer[i].mc_addr_high); 627 cz_smu->scratch_buffer[i].mc_addr_high);
630 628
631 cz_send_msg_to_smc_with_parameter(smumgr, 629 cz_send_msg_to_smc_with_parameter(hwmgr,
632 PPSMC_MSG_SetClkTableAddrLo, 630 PPSMC_MSG_SetClkTableAddrLo,
633 cz_smu->scratch_buffer[i].mc_addr_low); 631 cz_smu->scratch_buffer[i].mc_addr_low);
634 632
635 cz_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_ExecuteJob, 633 cz_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ExecuteJob,
636 cz_smu->toc_entry_clock_table); 634 cz_smu->toc_entry_clock_table);
637 635
638 cz_send_msg_to_smc(smumgr, PPSMC_MSG_ClkTableXferToDram); 636 cz_send_msg_to_smc(hwmgr, PPSMC_MSG_ClkTableXferToDram);
639 637
640 return 0; 638 return 0;
641} 639}
642 640
643static int cz_upload_pptable_settings(struct pp_smumgr *smumgr) 641static int cz_upload_pptable_settings(struct pp_hwmgr *hwmgr)
644{ 642{
645 struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; 643 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend;
646 unsigned long i; 644 unsigned long i;
647 645
648 for (i = 0; i < cz_smu->scratch_buffer_length; i++) { 646 for (i = 0; i < cz_smu->scratch_buffer_length; i++) {
@@ -651,63 +649,63 @@ static int cz_upload_pptable_settings(struct pp_smumgr *smumgr)
651 break; 649 break;
652 } 650 }
653 651
654 cz_send_msg_to_smc_with_parameter(smumgr, 652 cz_send_msg_to_smc_with_parameter(hwmgr,
655 PPSMC_MSG_SetClkTableAddrHi, 653 PPSMC_MSG_SetClkTableAddrHi,
656 cz_smu->scratch_buffer[i].mc_addr_high); 654 cz_smu->scratch_buffer[i].mc_addr_high);
657 655
658 cz_send_msg_to_smc_with_parameter(smumgr, 656 cz_send_msg_to_smc_with_parameter(hwmgr,
659 PPSMC_MSG_SetClkTableAddrLo, 657 PPSMC_MSG_SetClkTableAddrLo,
660 cz_smu->scratch_buffer[i].mc_addr_low); 658 cz_smu->scratch_buffer[i].mc_addr_low);
661 659
662 cz_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_ExecuteJob, 660 cz_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ExecuteJob,
663 cz_smu->toc_entry_clock_table); 661 cz_smu->toc_entry_clock_table);
664 662
665 cz_send_msg_to_smc(smumgr, PPSMC_MSG_ClkTableXferToSmu); 663 cz_send_msg_to_smc(hwmgr, PPSMC_MSG_ClkTableXferToSmu);
666 664
667 return 0; 665 return 0;
668} 666}
669 667
670static int cz_request_smu_load_fw(struct pp_smumgr *smumgr) 668static int cz_request_smu_load_fw(struct pp_hwmgr *hwmgr)
671{ 669{
672 struct cz_smumgr *cz_smu = (struct cz_smumgr *)(smumgr->backend); 670 struct cz_smumgr *cz_smu = (struct cz_smumgr *)(hwmgr->smumgr->backend);
673 uint32_t smc_address; 671 uint32_t smc_address;
674 672
675 if (!smumgr->reload_fw) { 673 if (!hwmgr->smumgr->reload_fw) {
676 pr_info("skip reloading...\n"); 674 pr_info("skip reloading...\n");
677 return 0; 675 return 0;
678 } 676 }
679 677
680 cz_smu_populate_firmware_entries(smumgr); 678 cz_smu_populate_firmware_entries(hwmgr);
681 679
682 cz_smu_construct_toc(smumgr); 680 cz_smu_construct_toc(hwmgr);
683 681
684 smc_address = SMU8_FIRMWARE_HEADER_LOCATION + 682 smc_address = SMU8_FIRMWARE_HEADER_LOCATION +
685 offsetof(struct SMU8_Firmware_Header, UcodeLoadStatus); 683 offsetof(struct SMU8_Firmware_Header, UcodeLoadStatus);
686 684
687 cz_write_smc_sram_dword(smumgr, smc_address, 0, smc_address+4); 685 cz_write_smc_sram_dword(hwmgr, smc_address, 0, smc_address+4);
688 686
689 cz_send_msg_to_smc_with_parameter(smumgr, 687 cz_send_msg_to_smc_with_parameter(hwmgr,
690 PPSMC_MSG_DriverDramAddrHi, 688 PPSMC_MSG_DriverDramAddrHi,
691 cz_smu->toc_buffer.mc_addr_high); 689 cz_smu->toc_buffer.mc_addr_high);
692 690
693 cz_send_msg_to_smc_with_parameter(smumgr, 691 cz_send_msg_to_smc_with_parameter(hwmgr,
694 PPSMC_MSG_DriverDramAddrLo, 692 PPSMC_MSG_DriverDramAddrLo,
695 cz_smu->toc_buffer.mc_addr_low); 693 cz_smu->toc_buffer.mc_addr_low);
696 694
697 cz_send_msg_to_smc(smumgr, PPSMC_MSG_InitJobs); 695 cz_send_msg_to_smc(hwmgr, PPSMC_MSG_InitJobs);
698 696
699 cz_send_msg_to_smc_with_parameter(smumgr, 697 cz_send_msg_to_smc_with_parameter(hwmgr,
700 PPSMC_MSG_ExecuteJob, 698 PPSMC_MSG_ExecuteJob,
701 cz_smu->toc_entry_aram); 699 cz_smu->toc_entry_aram);
702 cz_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_ExecuteJob, 700 cz_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ExecuteJob,
703 cz_smu->toc_entry_power_profiling_index); 701 cz_smu->toc_entry_power_profiling_index);
704 702
705 return cz_send_msg_to_smc_with_parameter(smumgr, 703 return cz_send_msg_to_smc_with_parameter(hwmgr,
706 PPSMC_MSG_ExecuteJob, 704 PPSMC_MSG_ExecuteJob,
707 cz_smu->toc_entry_initialize_index); 705 cz_smu->toc_entry_initialize_index);
708} 706}
709 707
710static int cz_start_smu(struct pp_smumgr *smumgr) 708static int cz_start_smu(struct pp_hwmgr *hwmgr)
711{ 709{
712 int ret = 0; 710 int ret = 0;
713 uint32_t fw_to_check = 0; 711 uint32_t fw_to_check = 0;
@@ -721,23 +719,23 @@ static int cz_start_smu(struct pp_smumgr *smumgr)
721 UCODE_ID_CP_MEC_JT1_MASK | 719 UCODE_ID_CP_MEC_JT1_MASK |
722 UCODE_ID_CP_MEC_JT2_MASK; 720 UCODE_ID_CP_MEC_JT2_MASK;
723 721
724 if (smumgr->chip_id == CHIP_STONEY) 722 if (hwmgr->chip_id == CHIP_STONEY)
725 fw_to_check &= ~(UCODE_ID_SDMA1_MASK | UCODE_ID_CP_MEC_JT2_MASK); 723 fw_to_check &= ~(UCODE_ID_SDMA1_MASK | UCODE_ID_CP_MEC_JT2_MASK);
726 724
727 ret = cz_request_smu_load_fw(smumgr); 725 ret = cz_request_smu_load_fw(hwmgr);
728 if (ret) 726 if (ret)
729 pr_err("SMU firmware load failed\n"); 727 pr_err("SMU firmware load failed\n");
730 728
731 cz_check_fw_load_finish(smumgr, fw_to_check); 729 cz_check_fw_load_finish(hwmgr, fw_to_check);
732 730
733 ret = cz_load_mec_firmware(smumgr); 731 ret = cz_load_mec_firmware(hwmgr);
734 if (ret) 732 if (ret)
735 pr_err("Mec Firmware load failed\n"); 733 pr_err("Mec Firmware load failed\n");
736 734
737 return ret; 735 return ret;
738} 736}
739 737
740static int cz_smu_init(struct pp_smumgr *smumgr) 738static int cz_smu_init(struct pp_hwmgr *hwmgr)
741{ 739{
742 uint64_t mc_addr = 0; 740 uint64_t mc_addr = 0;
743 int ret = 0; 741 int ret = 0;
@@ -747,7 +745,7 @@ static int cz_smu_init(struct pp_smumgr *smumgr)
747 if (cz_smu == NULL) 745 if (cz_smu == NULL)
748 return -ENOMEM; 746 return -ENOMEM;
749 747
750 smumgr->backend = cz_smu; 748 hwmgr->smumgr->backend = cz_smu;
751 749
752 cz_smu->toc_buffer.data_size = 4096; 750 cz_smu->toc_buffer.data_size = 4096;
753 cz_smu->smu_buffer.data_size = 751 cz_smu->smu_buffer.data_size =
@@ -757,7 +755,7 @@ static int cz_smu_init(struct pp_smumgr *smumgr)
757 ALIGN(sizeof(struct SMU8_MultimediaPowerLogData), 32) + 755 ALIGN(sizeof(struct SMU8_MultimediaPowerLogData), 32) +
758 ALIGN(sizeof(struct SMU8_Fusion_ClkTable), 32); 756 ALIGN(sizeof(struct SMU8_Fusion_ClkTable), 32);
759 757
760 ret = smu_allocate_memory(smumgr->device, 758 ret = smu_allocate_memory(hwmgr->device,
761 cz_smu->toc_buffer.data_size, 759 cz_smu->toc_buffer.data_size,
762 CGS_GPU_MEM_TYPE__GART_CACHEABLE, 760 CGS_GPU_MEM_TYPE__GART_CACHEABLE,
763 PAGE_SIZE, 761 PAGE_SIZE,
@@ -770,7 +768,7 @@ static int cz_smu_init(struct pp_smumgr *smumgr)
770 cz_smu->toc_buffer.mc_addr_high = smu_upper_32_bits(mc_addr); 768 cz_smu->toc_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
771 cz_smu->toc_buffer.mc_addr_low = smu_lower_32_bits(mc_addr); 769 cz_smu->toc_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
772 770
773 ret = smu_allocate_memory(smumgr->device, 771 ret = smu_allocate_memory(hwmgr->device,
774 cz_smu->smu_buffer.data_size, 772 cz_smu->smu_buffer.data_size,
775 CGS_GPU_MEM_TYPE__GART_CACHEABLE, 773 CGS_GPU_MEM_TYPE__GART_CACHEABLE,
776 PAGE_SIZE, 774 PAGE_SIZE,
@@ -783,7 +781,7 @@ static int cz_smu_init(struct pp_smumgr *smumgr)
783 cz_smu->smu_buffer.mc_addr_high = smu_upper_32_bits(mc_addr); 781 cz_smu->smu_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
784 cz_smu->smu_buffer.mc_addr_low = smu_lower_32_bits(mc_addr); 782 cz_smu->smu_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
785 783
786 if (0 != cz_smu_populate_single_scratch_entry(smumgr, 784 if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
787 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH, 785 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
788 UCODE_ID_RLC_SCRATCH_SIZE_BYTE, 786 UCODE_ID_RLC_SCRATCH_SIZE_BYTE,
789 &cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) { 787 &cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
@@ -791,14 +789,14 @@ static int cz_smu_init(struct pp_smumgr *smumgr)
791 return -1; 789 return -1;
792 } 790 }
793 791
794 if (0 != cz_smu_populate_single_scratch_entry(smumgr, 792 if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
795 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM, 793 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
796 UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE, 794 UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE,
797 &cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) { 795 &cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
798 pr_err("Error when Populate Firmware Entry.\n"); 796 pr_err("Error when Populate Firmware Entry.\n");
799 return -1; 797 return -1;
800 } 798 }
801 if (0 != cz_smu_populate_single_scratch_entry(smumgr, 799 if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
802 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM, 800 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
803 UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE, 801 UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE,
804 &cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) { 802 &cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
@@ -806,7 +804,7 @@ static int cz_smu_init(struct pp_smumgr *smumgr)
806 return -1; 804 return -1;
807 } 805 }
808 806
809 if (0 != cz_smu_populate_single_scratch_entry(smumgr, 807 if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
810 CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING, 808 CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING,
811 sizeof(struct SMU8_MultimediaPowerLogData), 809 sizeof(struct SMU8_MultimediaPowerLogData),
812 &cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) { 810 &cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
@@ -814,7 +812,7 @@ static int cz_smu_init(struct pp_smumgr *smumgr)
814 return -1; 812 return -1;
815 } 813 }
816 814
817 if (0 != cz_smu_populate_single_scratch_entry(smumgr, 815 if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
818 CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE, 816 CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE,
819 sizeof(struct SMU8_Fusion_ClkTable), 817 sizeof(struct SMU8_Fusion_ClkTable),
820 &cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) { 818 &cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
@@ -825,18 +823,18 @@ static int cz_smu_init(struct pp_smumgr *smumgr)
825 return 0; 823 return 0;
826} 824}
827 825
828static int cz_smu_fini(struct pp_smumgr *smumgr) 826static int cz_smu_fini(struct pp_hwmgr *hwmgr)
829{ 827{
830 struct cz_smumgr *cz_smu; 828 struct cz_smumgr *cz_smu;
831 829
832 if (smumgr == NULL || smumgr->device == NULL) 830 if (hwmgr == NULL || hwmgr->device == NULL)
833 return -EINVAL; 831 return -EINVAL;
834 832
835 cz_smu = (struct cz_smumgr *)smumgr->backend; 833 cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend;
836 if (cz_smu) { 834 if (cz_smu) {
837 cgs_free_gpu_mem(smumgr->device, 835 cgs_free_gpu_mem(hwmgr->device,
838 cz_smu->toc_buffer.handle); 836 cz_smu->toc_buffer.handle);
839 cgs_free_gpu_mem(smumgr->device, 837 cgs_free_gpu_mem(hwmgr->device,
840 cz_smu->smu_buffer.handle); 838 cz_smu->smu_buffer.handle);
841 kfree(cz_smu); 839 kfree(cz_smu);
842 } 840 }
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
index 9f612dd395ac..843ed7a665f6 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
@@ -338,7 +338,7 @@ static int fiji_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
338 const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults; 338 const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults;
339 uint32_t temp; 339 uint32_t temp;
340 340
341 if (smu7_read_smc_sram_dword(hwmgr->smumgr, 341 if (smu7_read_smc_sram_dword(hwmgr,
342 fuse_table_offset + 342 fuse_table_offset +
343 offsetof(SMU73_Discrete_PmFuses, TdcWaterfallCtl), 343 offsetof(SMU73_Discrete_PmFuses, TdcWaterfallCtl),
344 (uint32_t *)&temp, SMC_RAM_END)) 344 (uint32_t *)&temp, SMC_RAM_END))
@@ -425,7 +425,7 @@ static int fiji_populate_pm_fuses(struct pp_hwmgr *hwmgr)
425 425
426 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 426 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
427 PHM_PlatformCaps_PowerContainment)) { 427 PHM_PlatformCaps_PowerContainment)) {
428 if (smu7_read_smc_sram_dword(hwmgr->smumgr, 428 if (smu7_read_smc_sram_dword(hwmgr,
429 SMU7_FIRMWARE_HEADER_LOCATION + 429 SMU7_FIRMWARE_HEADER_LOCATION +
430 offsetof(SMU73_Firmware_Header, PmFuseTable), 430 offsetof(SMU73_Firmware_Header, PmFuseTable),
431 &pm_fuse_table_offset, SMC_RAM_END)) 431 &pm_fuse_table_offset, SMC_RAM_END))
@@ -473,7 +473,7 @@ static int fiji_populate_pm_fuses(struct pp_hwmgr *hwmgr)
473 "Attempt to populate BapmVddCBaseLeakage Hi and Lo " 473 "Attempt to populate BapmVddCBaseLeakage Hi and Lo "
474 "Sidd Failed!", return -EINVAL); 474 "Sidd Failed!", return -EINVAL);
475 475
476 if (smu7_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset, 476 if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
477 (uint8_t *)&smu_data->power_tune_table, 477 (uint8_t *)&smu_data->power_tune_table,
478 sizeof(struct SMU73_Discrete_PmFuses), SMC_RAM_END)) 478 sizeof(struct SMU73_Discrete_PmFuses), SMC_RAM_END))
479 PP_ASSERT_WITH_CODE(false, 479 PP_ASSERT_WITH_CODE(false,
@@ -848,7 +848,7 @@ int fiji_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
848 levels[1].pcieDpmLevel = mid_pcie_level_enabled; 848 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
849 } 849 }
850 /* level count will send to smc once at init smc table and never change */ 850 /* level count will send to smc once at init smc table and never change */
851 result = smu7_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels, 851 result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
852 (uint32_t)array_size, SMC_RAM_END); 852 (uint32_t)array_size, SMC_RAM_END);
853 853
854 return result; 854 return result;
@@ -1032,7 +1032,7 @@ int fiji_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1032 PPSMC_DISPLAY_WATERMARK_HIGH; 1032 PPSMC_DISPLAY_WATERMARK_HIGH;
1033 1033
1034 /* level count will send to smc once at init smc table and never change */ 1034 /* level count will send to smc once at init smc table and never change */
1035 result = smu7_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels, 1035 result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
1036 (uint32_t)array_size, SMC_RAM_END); 1036 (uint32_t)array_size, SMC_RAM_END);
1037 1037
1038 return result; 1038 return result;
@@ -1359,7 +1359,7 @@ static int fiji_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1359 1359
1360 if (!result) 1360 if (!result)
1361 result = smu7_copy_bytes_to_smc( 1361 result = smu7_copy_bytes_to_smc(
1362 hwmgr->smumgr, 1362 hwmgr,
1363 smu_data->smu7_data.arb_table_start, 1363 smu_data->smu7_data.arb_table_start,
1364 (uint8_t *)&arb_regs, 1364 (uint8_t *)&arb_regs,
1365 sizeof(SMU73_Discrete_MCArbDramTimingTable), 1365 sizeof(SMU73_Discrete_MCArbDramTimingTable),
@@ -1683,9 +1683,9 @@ static int fiji_populate_vr_config(struct pp_hwmgr *hwmgr,
1683 return 0; 1683 return 0;
1684} 1684}
1685 1685
1686static int fiji_init_arb_table_index(struct pp_smumgr *smumgr) 1686static int fiji_init_arb_table_index(struct pp_hwmgr *hwmgr)
1687{ 1687{
1688 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(smumgr->backend); 1688 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
1689 uint32_t tmp; 1689 uint32_t tmp;
1690 int result; 1690 int result;
1691 1691
@@ -1697,7 +1697,7 @@ static int fiji_init_arb_table_index(struct pp_smumgr *smumgr)
1697 * In reality this field should not be in that structure 1697 * In reality this field should not be in that structure
1698 * but in a soft register. 1698 * but in a soft register.
1699 */ 1699 */
1700 result = smu7_read_smc_sram_dword(smumgr, 1700 result = smu7_read_smc_sram_dword(hwmgr,
1701 smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END); 1701 smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
1702 1702
1703 if (result) 1703 if (result)
@@ -1706,7 +1706,7 @@ static int fiji_init_arb_table_index(struct pp_smumgr *smumgr)
1706 tmp &= 0x00FFFFFF; 1706 tmp &= 0x00FFFFFF;
1707 tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24; 1707 tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
1708 1708
1709 return smu7_write_smc_sram_dword(smumgr, 1709 return smu7_write_smc_sram_dword(hwmgr,
1710 smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END); 1710 smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END);
1711} 1711}
1712 1712
@@ -1771,7 +1771,7 @@ static int fiji_setup_dpm_led_config(struct pp_hwmgr *hwmgr)
1771 } 1771 }
1772 } 1772 }
1773 if (mask) 1773 if (mask)
1774 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 1774 smum_send_msg_to_smc_with_parameter(hwmgr,
1775 PPSMC_MSG_LedConfig, 1775 PPSMC_MSG_LedConfig,
1776 mask); 1776 mask);
1777 return 0; 1777 return 0;
@@ -1974,7 +1974,7 @@ int fiji_init_smc_table(struct pp_hwmgr *hwmgr)
1974 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime); 1974 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
1975 1975
1976 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */ 1976 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
1977 result = smu7_copy_bytes_to_smc(hwmgr->smumgr, 1977 result = smu7_copy_bytes_to_smc(hwmgr,
1978 smu_data->smu7_data.dpm_table_start + 1978 smu_data->smu7_data.dpm_table_start +
1979 offsetof(SMU73_Discrete_DpmTable, SystemFlags), 1979 offsetof(SMU73_Discrete_DpmTable, SystemFlags),
1980 (uint8_t *)&(table->SystemFlags), 1980 (uint8_t *)&(table->SystemFlags),
@@ -1983,7 +1983,7 @@ int fiji_init_smc_table(struct pp_hwmgr *hwmgr)
1983 PP_ASSERT_WITH_CODE(0 == result, 1983 PP_ASSERT_WITH_CODE(0 == result,
1984 "Failed to upload dpm data to SMC memory!", return result); 1984 "Failed to upload dpm data to SMC memory!", return result);
1985 1985
1986 result = fiji_init_arb_table_index(hwmgr->smumgr); 1986 result = fiji_init_arb_table_index(hwmgr);
1987 PP_ASSERT_WITH_CODE(0 == result, 1987 PP_ASSERT_WITH_CODE(0 == result,
1988 "Failed to upload arb data to SMC memory!", return result); 1988 "Failed to upload arb data to SMC memory!", return result);
1989 1989
@@ -2093,20 +2093,20 @@ int fiji_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
2093 hwmgr->device, CGS_IND_REG__SMC, 2093 hwmgr->device, CGS_IND_REG__SMC,
2094 CG_MULT_THERMAL_CTRL, TEMP_SEL); 2094 CG_MULT_THERMAL_CTRL, TEMP_SEL);
2095 2095
2096 res = smu7_copy_bytes_to_smc(hwmgr->smumgr, smu_data->smu7_data.fan_table_start, 2096 res = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.fan_table_start,
2097 (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), 2097 (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table),
2098 SMC_RAM_END); 2098 SMC_RAM_END);
2099 2099
2100 if (!res && hwmgr->thermal_controller. 2100 if (!res && hwmgr->thermal_controller.
2101 advanceFanControlParameters.ucMinimumPWMLimit) 2101 advanceFanControlParameters.ucMinimumPWMLimit)
2102 res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 2102 res = smum_send_msg_to_smc_with_parameter(hwmgr,
2103 PPSMC_MSG_SetFanMinPwm, 2103 PPSMC_MSG_SetFanMinPwm,
2104 hwmgr->thermal_controller. 2104 hwmgr->thermal_controller.
2105 advanceFanControlParameters.ucMinimumPWMLimit); 2105 advanceFanControlParameters.ucMinimumPWMLimit);
2106 2106
2107 if (!res && hwmgr->thermal_controller. 2107 if (!res && hwmgr->thermal_controller.
2108 advanceFanControlParameters.ulMinFanSCLKAcousticLimit) 2108 advanceFanControlParameters.ulMinFanSCLKAcousticLimit)
2109 res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 2109 res = smum_send_msg_to_smc_with_parameter(hwmgr,
2110 PPSMC_MSG_SetFanSclkTarget, 2110 PPSMC_MSG_SetFanSclkTarget,
2111 hwmgr->thermal_controller. 2111 hwmgr->thermal_controller.
2112 advanceFanControlParameters.ulMinFanSCLKAcousticLimit); 2112 advanceFanControlParameters.ulMinFanSCLKAcousticLimit);
@@ -2122,13 +2122,12 @@ int fiji_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
2122int fiji_thermal_avfs_enable(struct pp_hwmgr *hwmgr) 2122int fiji_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
2123{ 2123{
2124 int ret; 2124 int ret;
2125 struct pp_smumgr *smumgr = (struct pp_smumgr *)(hwmgr->smumgr); 2125 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend);
2126 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
2127 2126
2128 if (smu_data->avfs.avfs_btc_status != AVFS_BTC_ENABLEAVFS) 2127 if (smu_data->avfs.avfs_btc_status != AVFS_BTC_ENABLEAVFS)
2129 return 0; 2128 return 0;
2130 2129
2131 ret = smum_send_msg_to_smc(smumgr, PPSMC_MSG_EnableAvfs); 2130 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAvfs);
2132 2131
2133 if (!ret) 2132 if (!ret)
2134 /* If this param is not changed, this function could fire unnecessarily */ 2133 /* If this param is not changed, this function could fire unnecessarily */
@@ -2168,7 +2167,7 @@ int fiji_update_sclk_threshold(struct pp_hwmgr *hwmgr)
2168 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold); 2167 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
2169 2168
2170 result = smu7_copy_bytes_to_smc( 2169 result = smu7_copy_bytes_to_smc(
2171 hwmgr->smumgr, 2170 hwmgr,
2172 smu_data->smu7_data.dpm_table_start + 2171 smu_data->smu7_data.dpm_table_start +
2173 offsetof(SMU73_Discrete_DpmTable, 2172 offsetof(SMU73_Discrete_DpmTable,
2174 LowSclkInterruptThreshold), 2173 LowSclkInterruptThreshold),
@@ -2269,7 +2268,7 @@ static int fiji_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
2269 PHM_PlatformCaps_UVDDPM) || 2268 PHM_PlatformCaps_UVDDPM) ||
2270 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 2269 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2271 PHM_PlatformCaps_StablePState)) 2270 PHM_PlatformCaps_StablePState))
2272 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 2271 smum_send_msg_to_smc_with_parameter(hwmgr,
2273 PPSMC_MSG_UVDDPM_SetEnabledMask, 2272 PPSMC_MSG_UVDDPM_SetEnabledMask,
2274 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel)); 2273 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel));
2275 return 0; 2274 return 0;
@@ -2301,7 +2300,7 @@ static int fiji_update_vce_smc_table(struct pp_hwmgr *hwmgr)
2301 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value); 2300 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
2302 2301
2303 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) 2302 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
2304 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 2303 smum_send_msg_to_smc_with_parameter(hwmgr,
2305 PPSMC_MSG_VCEDPM_SetEnabledMask, 2304 PPSMC_MSG_VCEDPM_SetEnabledMask,
2306 (uint32_t)1 << smu_data->smc_state_table.VceBootLevel); 2305 (uint32_t)1 << smu_data->smc_state_table.VceBootLevel);
2307 return 0; 2306 return 0;
@@ -2328,7 +2327,7 @@ static int fiji_update_samu_smc_table(struct pp_hwmgr *hwmgr)
2328 2327
2329 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 2328 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2330 PHM_PlatformCaps_StablePState)) 2329 PHM_PlatformCaps_StablePState))
2331 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 2330 smum_send_msg_to_smc_with_parameter(hwmgr,
2332 PPSMC_MSG_SAMUDPM_SetEnabledMask, 2331 PPSMC_MSG_SAMUDPM_SetEnabledMask,
2333 (uint32_t)(1 << smu_data->smc_state_table.SamuBootLevel)); 2332 (uint32_t)(1 << smu_data->smc_state_table.SamuBootLevel));
2334 return 0; 2333 return 0;
@@ -2367,7 +2366,7 @@ int fiji_process_firmware_header(struct pp_hwmgr *hwmgr)
2367 int result; 2366 int result;
2368 bool error = false; 2367 bool error = false;
2369 2368
2370 result = smu7_read_smc_sram_dword(hwmgr->smumgr, 2369 result = smu7_read_smc_sram_dword(hwmgr,
2371 SMU7_FIRMWARE_HEADER_LOCATION + 2370 SMU7_FIRMWARE_HEADER_LOCATION +
2372 offsetof(SMU73_Firmware_Header, DpmTable), 2371 offsetof(SMU73_Firmware_Header, DpmTable),
2373 &tmp, SMC_RAM_END); 2372 &tmp, SMC_RAM_END);
@@ -2377,7 +2376,7 @@ int fiji_process_firmware_header(struct pp_hwmgr *hwmgr)
2377 2376
2378 error |= (0 != result); 2377 error |= (0 != result);
2379 2378
2380 result = smu7_read_smc_sram_dword(hwmgr->smumgr, 2379 result = smu7_read_smc_sram_dword(hwmgr,
2381 SMU7_FIRMWARE_HEADER_LOCATION + 2380 SMU7_FIRMWARE_HEADER_LOCATION +
2382 offsetof(SMU73_Firmware_Header, SoftRegisters), 2381 offsetof(SMU73_Firmware_Header, SoftRegisters),
2383 &tmp, SMC_RAM_END); 2382 &tmp, SMC_RAM_END);
@@ -2389,7 +2388,7 @@ int fiji_process_firmware_header(struct pp_hwmgr *hwmgr)
2389 2388
2390 error |= (0 != result); 2389 error |= (0 != result);
2391 2390
2392 result = smu7_read_smc_sram_dword(hwmgr->smumgr, 2391 result = smu7_read_smc_sram_dword(hwmgr,
2393 SMU7_FIRMWARE_HEADER_LOCATION + 2392 SMU7_FIRMWARE_HEADER_LOCATION +
2394 offsetof(SMU73_Firmware_Header, mcRegisterTable), 2393 offsetof(SMU73_Firmware_Header, mcRegisterTable),
2395 &tmp, SMC_RAM_END); 2394 &tmp, SMC_RAM_END);
@@ -2397,7 +2396,7 @@ int fiji_process_firmware_header(struct pp_hwmgr *hwmgr)
2397 if (!result) 2396 if (!result)
2398 smu_data->smu7_data.mc_reg_table_start = tmp; 2397 smu_data->smu7_data.mc_reg_table_start = tmp;
2399 2398
2400 result = smu7_read_smc_sram_dword(hwmgr->smumgr, 2399 result = smu7_read_smc_sram_dword(hwmgr,
2401 SMU7_FIRMWARE_HEADER_LOCATION + 2400 SMU7_FIRMWARE_HEADER_LOCATION +
2402 offsetof(SMU73_Firmware_Header, FanTable), 2401 offsetof(SMU73_Firmware_Header, FanTable),
2403 &tmp, SMC_RAM_END); 2402 &tmp, SMC_RAM_END);
@@ -2407,7 +2406,7 @@ int fiji_process_firmware_header(struct pp_hwmgr *hwmgr)
2407 2406
2408 error |= (0 != result); 2407 error |= (0 != result);
2409 2408
2410 result = smu7_read_smc_sram_dword(hwmgr->smumgr, 2409 result = smu7_read_smc_sram_dword(hwmgr,
2411 SMU7_FIRMWARE_HEADER_LOCATION + 2410 SMU7_FIRMWARE_HEADER_LOCATION +
2412 offsetof(SMU73_Firmware_Header, mcArbDramTimingTable), 2411 offsetof(SMU73_Firmware_Header, mcArbDramTimingTable),
2413 &tmp, SMC_RAM_END); 2412 &tmp, SMC_RAM_END);
@@ -2417,7 +2416,7 @@ int fiji_process_firmware_header(struct pp_hwmgr *hwmgr)
2417 2416
2418 error |= (0 != result); 2417 error |= (0 != result);
2419 2418
2420 result = smu7_read_smc_sram_dword(hwmgr->smumgr, 2419 result = smu7_read_smc_sram_dword(hwmgr,
2421 SMU7_FIRMWARE_HEADER_LOCATION + 2420 SMU7_FIRMWARE_HEADER_LOCATION +
2422 offsetof(SMU73_Firmware_Header, Version), 2421 offsetof(SMU73_Firmware_Header, Version),
2423 &tmp, SMC_RAM_END); 2422 &tmp, SMC_RAM_END);
@@ -2482,6 +2481,6 @@ int fiji_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
2482 levels[i].DownHyst = request->down_hyst; 2481 levels[i].DownHyst = request->down_hyst;
2483 } 2482 }
2484 2483
2485 return smu7_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels, 2484 return smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
2486 array_size, SMC_RAM_END); 2485 array_size, SMC_RAM_END);
2487} 2486}
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
index 6ae948fc524f..dfdcff54947a 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
@@ -58,122 +58,122 @@ static const struct SMU73_Discrete_GraphicsLevel avfs_graphics_level[8] = {
58 { 0xf811d047, 0x80380100, 0x01, 0x00, 0x1e00, 0x00000610, 0x87020000, 0x21680000, 0x12000000, 0, 0, 0x0c, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 } 58 { 0xf811d047, 0x80380100, 0x01, 0x00, 0x1e00, 0x00000610, 0x87020000, 0x21680000, 0x12000000, 0, 0, 0x0c, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 }
59}; 59};
60 60
61static int fiji_start_smu_in_protection_mode(struct pp_smumgr *smumgr) 61static int fiji_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
62{ 62{
63 int result = 0; 63 int result = 0;
64 64
65 /* Wait for smc boot up */ 65 /* Wait for smc boot up */
66 /* SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, 66 /* SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
67 RCU_UC_EVENTS, boot_seq_done, 0); */ 67 RCU_UC_EVENTS, boot_seq_done, 0); */
68 68
69 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, 69 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
70 SMC_SYSCON_RESET_CNTL, rst_reg, 1); 70 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
71 71
72 result = smu7_upload_smu_firmware_image(smumgr); 72 result = smu7_upload_smu_firmware_image(hwmgr);
73 if (result) 73 if (result)
74 return result; 74 return result;
75 75
76 /* Clear status */ 76 /* Clear status */
77 cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, 77 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
78 ixSMU_STATUS, 0); 78 ixSMU_STATUS, 0);
79 79
80 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, 80 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
81 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); 81 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
82 82
83 /* De-assert reset */ 83 /* De-assert reset */
84 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, 84 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
85 SMC_SYSCON_RESET_CNTL, rst_reg, 0); 85 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
86 86
87 /* Wait for ROM firmware to initialize interrupt hendler */ 87 /* Wait for ROM firmware to initialize interrupt hendler */
88 /*SMUM_WAIT_VFPF_INDIRECT_REGISTER(smumgr, SMC_IND, 88 /*SMUM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, SMC_IND,
89 SMC_INTR_CNTL_MASK_0, 0x10040, 0xFFFFFFFF); */ 89 SMC_INTR_CNTL_MASK_0, 0x10040, 0xFFFFFFFF); */
90 90
91 /* Set SMU Auto Start */ 91 /* Set SMU Auto Start */
92 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, 92 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
93 SMU_INPUT_DATA, AUTO_START, 1); 93 SMU_INPUT_DATA, AUTO_START, 1);
94 94
95 /* Clear firmware interrupt enable flag */ 95 /* Clear firmware interrupt enable flag */
96 cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, 96 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
97 ixFIRMWARE_FLAGS, 0); 97 ixFIRMWARE_FLAGS, 0);
98 98
99 SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, RCU_UC_EVENTS, 99 SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS,
100 INTERRUPTS_ENABLED, 1); 100 INTERRUPTS_ENABLED, 1);
101 101
102 cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, 0x20000); 102 cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, 0x20000);
103 cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test); 103 cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test);
104 SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0); 104 SMUM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
105 105
106 /* Wait for done bit to be set */ 106 /* Wait for done bit to be set */
107 SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, 107 SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
108 SMU_STATUS, SMU_DONE, 0); 108 SMU_STATUS, SMU_DONE, 0);
109 109
110 /* Check pass/failed indicator */ 110 /* Check pass/failed indicator */
111 if (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, 111 if (SMUM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
112 SMU_STATUS, SMU_PASS) != 1) { 112 SMU_STATUS, SMU_PASS) != 1) {
113 PP_ASSERT_WITH_CODE(false, 113 PP_ASSERT_WITH_CODE(false,
114 "SMU Firmware start failed!", return -1); 114 "SMU Firmware start failed!", return -1);
115 } 115 }
116 116
117 /* Wait for firmware to initialize */ 117 /* Wait for firmware to initialize */
118 SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, 118 SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
119 FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1); 119 FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
120 120
121 return result; 121 return result;
122} 122}
123 123
124static int fiji_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr) 124static int fiji_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
125{ 125{
126 int result = 0; 126 int result = 0;
127 127
128 /* wait for smc boot up */ 128 /* wait for smc boot up */
129 SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, 129 SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
130 RCU_UC_EVENTS, boot_seq_done, 0); 130 RCU_UC_EVENTS, boot_seq_done, 0);
131 131
132 /* Clear firmware interrupt enable flag */ 132 /* Clear firmware interrupt enable flag */
133 cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, 133 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
134 ixFIRMWARE_FLAGS, 0); 134 ixFIRMWARE_FLAGS, 0);
135 135
136 /* Assert reset */ 136 /* Assert reset */
137 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, 137 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
138 SMC_SYSCON_RESET_CNTL, rst_reg, 1); 138 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
139 139
140 result = smu7_upload_smu_firmware_image(smumgr); 140 result = smu7_upload_smu_firmware_image(hwmgr);
141 if (result) 141 if (result)
142 return result; 142 return result;
143 143
144 /* Set smc instruct start point at 0x0 */ 144 /* Set smc instruct start point at 0x0 */
145 smu7_program_jump_on_start(smumgr); 145 smu7_program_jump_on_start(hwmgr);
146 146
147 /* Enable clock */ 147 /* Enable clock */
148 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, 148 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
149 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); 149 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
150 150
151 /* De-assert reset */ 151 /* De-assert reset */
152 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, 152 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
153 SMC_SYSCON_RESET_CNTL, rst_reg, 0); 153 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
154 154
155 /* Wait for firmware to initialize */ 155 /* Wait for firmware to initialize */
156 SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, 156 SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
157 FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1); 157 FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
158 158
159 return result; 159 return result;
160} 160}
161 161
162static int fiji_setup_pwr_virus(struct pp_smumgr *smumgr) 162static int fiji_setup_pwr_virus(struct pp_hwmgr *hwmgr)
163{ 163{
164 int i; 164 int i;
165 int result = -EINVAL; 165 int result = -EINVAL;
166 uint32_t reg, data; 166 uint32_t reg, data;
167 167
168 const PWR_Command_Table *pvirus = PwrVirusTable; 168 const PWR_Command_Table *pvirus = PwrVirusTable;
169 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend); 169 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend);
170 170
171 for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) { 171 for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) {
172 switch (pvirus->command) { 172 switch (pvirus->command) {
173 case PwrCmdWrite: 173 case PwrCmdWrite:
174 reg = pvirus->reg; 174 reg = pvirus->reg;
175 data = pvirus->data; 175 data = pvirus->data;
176 cgs_write_register(smumgr->device, reg, data); 176 cgs_write_register(hwmgr->device, reg, data);
177 break; 177 break;
178 178
179 case PwrCmdEnd: 179 case PwrCmdEnd:
@@ -192,13 +192,13 @@ static int fiji_setup_pwr_virus(struct pp_smumgr *smumgr)
192 return result; 192 return result;
193} 193}
194 194
195static int fiji_start_avfs_btc(struct pp_smumgr *smumgr) 195static int fiji_start_avfs_btc(struct pp_hwmgr *hwmgr)
196{ 196{
197 int result = 0; 197 int result = 0;
198 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend); 198 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend);
199 199
200 if (0 != smu_data->avfs.avfs_btc_param) { 200 if (0 != smu_data->avfs.avfs_btc_param) {
201 if (0 != smu7_send_msg_to_smc_with_parameter(smumgr, 201 if (0 != smu7_send_msg_to_smc_with_parameter(hwmgr,
202 PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) { 202 PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) {
203 pr_info("[AVFS][Fiji_PerformBtc] PerformBTC SMU msg failed"); 203 pr_info("[AVFS][Fiji_PerformBtc] PerformBTC SMU msg failed");
204 result = -EINVAL; 204 result = -EINVAL;
@@ -206,23 +206,23 @@ static int fiji_start_avfs_btc(struct pp_smumgr *smumgr)
206 } 206 }
207 /* Soft-Reset to reset the engine before loading uCode */ 207 /* Soft-Reset to reset the engine before loading uCode */
208 /* halt */ 208 /* halt */
209 cgs_write_register(smumgr->device, mmCP_MEC_CNTL, 0x50000000); 209 cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000);
210 /* reset everything */ 210 /* reset everything */
211 cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0xffffffff); 211 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0xffffffff);
212 /* clear reset */ 212 /* clear reset */
213 cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0); 213 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0);
214 214
215 return result; 215 return result;
216} 216}
217 217
218static int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr) 218static int fiji_setup_graphics_level_structure(struct pp_hwmgr *hwmgr)
219{ 219{
220 int32_t vr_config; 220 int32_t vr_config;
221 uint32_t table_start; 221 uint32_t table_start;
222 uint32_t level_addr, vr_config_addr; 222 uint32_t level_addr, vr_config_addr;
223 uint32_t level_size = sizeof(avfs_graphics_level); 223 uint32_t level_size = sizeof(avfs_graphics_level);
224 224
225 PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(smumgr, 225 PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr,
226 SMU7_FIRMWARE_HEADER_LOCATION + 226 SMU7_FIRMWARE_HEADER_LOCATION +
227 offsetof(SMU73_Firmware_Header, DpmTable), 227 offsetof(SMU73_Firmware_Header, DpmTable),
228 &table_start, 0x40000), 228 &table_start, 0x40000),
@@ -237,7 +237,7 @@ static int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr)
237 vr_config_addr = table_start + 237 vr_config_addr = table_start +
238 offsetof(SMU73_Discrete_DpmTable, VRConfig); 238 offsetof(SMU73_Discrete_DpmTable, VRConfig);
239 239
240 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, vr_config_addr, 240 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_addr,
241 (uint8_t *)&vr_config, sizeof(int32_t), 0x40000), 241 (uint8_t *)&vr_config, sizeof(int32_t), 0x40000),
242 "[AVFS][Fiji_SetupGfxLvlStruct] Problems copying " 242 "[AVFS][Fiji_SetupGfxLvlStruct] Problems copying "
243 "vr_config value over to SMC", 243 "vr_config value over to SMC",
@@ -245,7 +245,7 @@ static int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr)
245 245
246 level_addr = table_start + offsetof(SMU73_Discrete_DpmTable, GraphicsLevel); 246 level_addr = table_start + offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);
247 247
248 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, level_addr, 248 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, level_addr,
249 (uint8_t *)(&avfs_graphics_level), level_size, 0x40000), 249 (uint8_t *)(&avfs_graphics_level), level_size, 0x40000),
250 "[AVFS][Fiji_SetupGfxLvlStruct] Copying of DPM table failed!", 250 "[AVFS][Fiji_SetupGfxLvlStruct] Copying of DPM table failed!",
251 return -1;); 251 return -1;);
@@ -253,9 +253,9 @@ static int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr)
253 return 0; 253 return 0;
254} 254}
255 255
256static int fiji_avfs_event_mgr(struct pp_smumgr *smumgr, bool smu_started) 256static int fiji_avfs_event_mgr(struct pp_hwmgr *hwmgr, bool smu_started)
257{ 257{
258 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend); 258 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend);
259 259
260 switch (smu_data->avfs.avfs_btc_status) { 260 switch (smu_data->avfs.avfs_btc_status) {
261 case AVFS_BTC_COMPLETED_PREVIOUSLY: 261 case AVFS_BTC_COMPLETED_PREVIOUSLY:
@@ -265,17 +265,17 @@ static int fiji_avfs_event_mgr(struct pp_smumgr *smumgr, bool smu_started)
265 if (!smu_started) 265 if (!smu_started)
266 break; 266 break;
267 smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED; 267 smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED;
268 PP_ASSERT_WITH_CODE(0 == fiji_setup_graphics_level_structure(smumgr), 268 PP_ASSERT_WITH_CODE(0 == fiji_setup_graphics_level_structure(hwmgr),
269 "[AVFS][fiji_avfs_event_mgr] Could not Copy Graphics Level" 269 "[AVFS][fiji_avfs_event_mgr] Could not Copy Graphics Level"
270 " table over to SMU", 270 " table over to SMU",
271 return -EINVAL;); 271 return -EINVAL;);
272 smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL; 272 smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL;
273 PP_ASSERT_WITH_CODE(0 == fiji_setup_pwr_virus(smumgr), 273 PP_ASSERT_WITH_CODE(0 == fiji_setup_pwr_virus(hwmgr),
274 "[AVFS][fiji_avfs_event_mgr] Could not setup " 274 "[AVFS][fiji_avfs_event_mgr] Could not setup "
275 "Pwr Virus for AVFS ", 275 "Pwr Virus for AVFS ",
276 return -EINVAL;); 276 return -EINVAL;);
277 smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED; 277 smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED;
278 PP_ASSERT_WITH_CODE(0 == fiji_start_avfs_btc(smumgr), 278 PP_ASSERT_WITH_CODE(0 == fiji_start_avfs_btc(hwmgr),
279 "[AVFS][fiji_avfs_event_mgr] Failure at " 279 "[AVFS][fiji_avfs_event_mgr] Failure at "
280 "fiji_start_avfs_btc. AVFS Disabled", 280 "fiji_start_avfs_btc. AVFS Disabled",
281 return -EINVAL;); 281 return -EINVAL;);
@@ -293,64 +293,64 @@ static int fiji_avfs_event_mgr(struct pp_smumgr *smumgr, bool smu_started)
293 return 0; 293 return 0;
294} 294}
295 295
296static int fiji_start_smu(struct pp_smumgr *smumgr) 296static int fiji_start_smu(struct pp_hwmgr *hwmgr)
297{ 297{
298 int result = 0; 298 int result = 0;
299 struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend); 299 struct fiji_smumgr *priv = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
300 300
301 /* Only start SMC if SMC RAM is not running */ 301 /* Only start SMC if SMC RAM is not running */
302 if (!(smu7_is_smc_ram_running(smumgr) 302 if (!(smu7_is_smc_ram_running(hwmgr)
303 || cgs_is_virtualization_enabled(smumgr->device))) { 303 || cgs_is_virtualization_enabled(hwmgr->device))) {
304 fiji_avfs_event_mgr(smumgr, false); 304 fiji_avfs_event_mgr(hwmgr, false);
305 305
306 /* Check if SMU is running in protected mode */ 306 /* Check if SMU is running in protected mode */
307 if (0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, 307 if (0 == SMUM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
308 CGS_IND_REG__SMC, 308 CGS_IND_REG__SMC,
309 SMU_FIRMWARE, SMU_MODE)) { 309 SMU_FIRMWARE, SMU_MODE)) {
310 result = fiji_start_smu_in_non_protection_mode(smumgr); 310 result = fiji_start_smu_in_non_protection_mode(hwmgr);
311 if (result) 311 if (result)
312 return result; 312 return result;
313 } else { 313 } else {
314 result = fiji_start_smu_in_protection_mode(smumgr); 314 result = fiji_start_smu_in_protection_mode(hwmgr);
315 if (result) 315 if (result)
316 return result; 316 return result;
317 } 317 }
318 fiji_avfs_event_mgr(smumgr, true); 318 fiji_avfs_event_mgr(hwmgr, true);
319 } 319 }
320 320
321 /* To initialize all clock gating before RLC loaded and running.*/ 321 /* To initialize all clock gating before RLC loaded and running.*/
322 cgs_set_clockgating_state(smumgr->device, 322 cgs_set_clockgating_state(hwmgr->device,
323 AMD_IP_BLOCK_TYPE_GFX, AMD_CG_STATE_GATE); 323 AMD_IP_BLOCK_TYPE_GFX, AMD_CG_STATE_GATE);
324 cgs_set_clockgating_state(smumgr->device, 324 cgs_set_clockgating_state(hwmgr->device,
325 AMD_IP_BLOCK_TYPE_GMC, AMD_CG_STATE_GATE); 325 AMD_IP_BLOCK_TYPE_GMC, AMD_CG_STATE_GATE);
326 cgs_set_clockgating_state(smumgr->device, 326 cgs_set_clockgating_state(hwmgr->device,
327 AMD_IP_BLOCK_TYPE_SDMA, AMD_CG_STATE_GATE); 327 AMD_IP_BLOCK_TYPE_SDMA, AMD_CG_STATE_GATE);
328 cgs_set_clockgating_state(smumgr->device, 328 cgs_set_clockgating_state(hwmgr->device,
329 AMD_IP_BLOCK_TYPE_COMMON, AMD_CG_STATE_GATE); 329 AMD_IP_BLOCK_TYPE_COMMON, AMD_CG_STATE_GATE);
330 330
331 /* Setup SoftRegsStart here for register lookup in case 331 /* Setup SoftRegsStart here for register lookup in case
332 * DummyBackEnd is used and ProcessFirmwareHeader is not executed 332 * DummyBackEnd is used and ProcessFirmwareHeader is not executed
333 */ 333 */
334 smu7_read_smc_sram_dword(smumgr, 334 smu7_read_smc_sram_dword(hwmgr,
335 SMU7_FIRMWARE_HEADER_LOCATION + 335 SMU7_FIRMWARE_HEADER_LOCATION +
336 offsetof(SMU73_Firmware_Header, SoftRegisters), 336 offsetof(SMU73_Firmware_Header, SoftRegisters),
337 &(priv->smu7_data.soft_regs_start), 0x40000); 337 &(priv->smu7_data.soft_regs_start), 0x40000);
338 338
339 result = smu7_request_smu_load_fw(smumgr); 339 result = smu7_request_smu_load_fw(hwmgr);
340 340
341 return result; 341 return result;
342} 342}
343 343
344static bool fiji_is_hw_avfs_present(struct pp_smumgr *smumgr) 344static bool fiji_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
345{ 345{
346 346
347 uint32_t efuse = 0; 347 uint32_t efuse = 0;
348 uint32_t mask = (1 << ((AVFS_EN_MSB - AVFS_EN_LSB) + 1)) - 1; 348 uint32_t mask = (1 << ((AVFS_EN_MSB - AVFS_EN_LSB) + 1)) - 1;
349 349
350 if (cgs_is_virtualization_enabled(smumgr->device)) 350 if (cgs_is_virtualization_enabled(hwmgr->device))
351 return 0; 351 return 0;
352 352
353 if (!atomctrl_read_efuse(smumgr->device, AVFS_EN_LSB, AVFS_EN_MSB, 353 if (!atomctrl_read_efuse(hwmgr->device, AVFS_EN_LSB, AVFS_EN_MSB,
354 mask, &efuse)) { 354 mask, &efuse)) {
355 if (efuse) 355 if (efuse)
356 return true; 356 return true;
@@ -365,7 +365,7 @@ static bool fiji_is_hw_avfs_present(struct pp_smumgr *smumgr)
365* @param smc_addr the address in the SMC RAM to access. 365* @param smc_addr the address in the SMC RAM to access.
366* @param value to write to the SMC SRAM. 366* @param value to write to the SMC SRAM.
367*/ 367*/
368static int fiji_smu_init(struct pp_smumgr *smumgr) 368static int fiji_smu_init(struct pp_hwmgr *hwmgr)
369{ 369{
370 int i; 370 int i;
371 struct fiji_smumgr *fiji_priv = NULL; 371 struct fiji_smumgr *fiji_priv = NULL;
@@ -375,9 +375,9 @@ static int fiji_smu_init(struct pp_smumgr *smumgr)
375 if (fiji_priv == NULL) 375 if (fiji_priv == NULL)
376 return -ENOMEM; 376 return -ENOMEM;
377 377
378 smumgr->backend = fiji_priv; 378 hwmgr->smumgr->backend = fiji_priv;
379 379
380 if (smu7_init(smumgr)) 380 if (smu7_init(hwmgr))
381 return -EINVAL; 381 return -EINVAL;
382 382
383 for (i = 0; i < SMU73_MAX_LEVELS_GRAPHICS; i++) 383 for (i = 0; i < SMU73_MAX_LEVELS_GRAPHICS; i++)
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
index 1ed3214a965f..89d5a272e236 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
@@ -163,7 +163,7 @@ static int iceland_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offs
163 const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults; 163 const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
164 uint32_t temp; 164 uint32_t temp;
165 165
166 if (smu7_read_smc_sram_dword(hwmgr->smumgr, 166 if (smu7_read_smc_sram_dword(hwmgr,
167 fuse_table_offset + 167 fuse_table_offset +
168 offsetof(SMU71_Discrete_PmFuses, TdcWaterfallCtl), 168 offsetof(SMU71_Discrete_PmFuses, TdcWaterfallCtl),
169 (uint32_t *)&temp, SMC_RAM_END)) 169 (uint32_t *)&temp, SMC_RAM_END))
@@ -264,7 +264,7 @@ static int iceland_populate_pm_fuses(struct pp_hwmgr *hwmgr)
264 264
265 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 265 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
266 PHM_PlatformCaps_PowerContainment)) { 266 PHM_PlatformCaps_PowerContainment)) {
267 if (smu7_read_smc_sram_dword(hwmgr->smumgr, 267 if (smu7_read_smc_sram_dword(hwmgr,
268 SMU71_FIRMWARE_HEADER_LOCATION + 268 SMU71_FIRMWARE_HEADER_LOCATION +
269 offsetof(SMU71_Firmware_Header, PmFuseTable), 269 offsetof(SMU71_Firmware_Header, PmFuseTable),
270 &pm_fuse_table_offset, SMC_RAM_END)) 270 &pm_fuse_table_offset, SMC_RAM_END))
@@ -318,7 +318,7 @@ static int iceland_populate_pm_fuses(struct pp_hwmgr *hwmgr)
318 "Attempt to populate BapmVddCBaseLeakage Hi and Lo Sidd Failed!", 318 "Attempt to populate BapmVddCBaseLeakage Hi and Lo Sidd Failed!",
319 return -EINVAL); 319 return -EINVAL);
320 320
321 if (smu7_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset, 321 if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
322 (uint8_t *)&smu_data->power_tune_table, 322 (uint8_t *)&smu_data->power_tune_table,
323 sizeof(struct SMU71_Discrete_PmFuses), SMC_RAM_END)) 323 sizeof(struct SMU71_Discrete_PmFuses), SMC_RAM_END))
324 PP_ASSERT_WITH_CODE(false, 324 PP_ASSERT_WITH_CODE(false,
@@ -881,7 +881,7 @@ int iceland_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
881 smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled; 881 smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled;
882 882
883 /* level count will send to smc once at init smc table and never change*/ 883 /* level count will send to smc once at init smc table and never change*/
884 result = smu7_copy_bytes_to_smc(hwmgr->smumgr, level_array_adress, 884 result = smu7_copy_bytes_to_smc(hwmgr, level_array_adress,
885 (uint8_t *)levels, (uint32_t)level_array_size, 885 (uint8_t *)levels, (uint32_t)level_array_size,
886 SMC_RAM_END); 886 SMC_RAM_END);
887 887
@@ -1246,7 +1246,7 @@ int iceland_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1246 smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH; 1246 smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1247 1247
1248 /* level count will send to smc once at init smc table and never change*/ 1248 /* level count will send to smc once at init smc table and never change*/
1249 result = smu7_copy_bytes_to_smc(hwmgr->smumgr, 1249 result = smu7_copy_bytes_to_smc(hwmgr,
1250 level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size, 1250 level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size,
1251 SMC_RAM_END); 1251 SMC_RAM_END);
1252 1252
@@ -1507,7 +1507,7 @@ static int iceland_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1507 1507
1508 if (0 == result) { 1508 if (0 == result) {
1509 result = smu7_copy_bytes_to_smc( 1509 result = smu7_copy_bytes_to_smc(
1510 hwmgr->smumgr, 1510 hwmgr,
1511 smu_data->smu7_data.arb_table_start, 1511 smu_data->smu7_data.arb_table_start,
1512 (uint8_t *)&arb_regs, 1512 (uint8_t *)&arb_regs,
1513 sizeof(SMU71_Discrete_MCArbDramTimingTable), 1513 sizeof(SMU71_Discrete_MCArbDramTimingTable),
@@ -1561,10 +1561,10 @@ static int iceland_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1561 return result; 1561 return result;
1562} 1562}
1563 1563
1564static int iceland_populate_mc_reg_address(struct pp_smumgr *smumgr, 1564static int iceland_populate_mc_reg_address(struct pp_hwmgr *hwmgr,
1565 SMU71_Discrete_MCRegisters *mc_reg_table) 1565 SMU71_Discrete_MCRegisters *mc_reg_table)
1566{ 1566{
1567 const struct iceland_smumgr *smu_data = (struct iceland_smumgr *)smumgr->backend; 1567 const struct iceland_smumgr *smu_data = (struct iceland_smumgr *)hwmgr->smumgr->backend;
1568 1568
1569 uint32_t i, j; 1569 uint32_t i, j;
1570 1570
@@ -1601,13 +1601,12 @@ static void iceland_convert_mc_registers(
1601 } 1601 }
1602} 1602}
1603 1603
1604static int iceland_convert_mc_reg_table_entry_to_smc( 1604static int iceland_convert_mc_reg_table_entry_to_smc(struct pp_hwmgr *hwmgr,
1605 struct pp_smumgr *smumgr,
1606 const uint32_t memory_clock, 1605 const uint32_t memory_clock,
1607 SMU71_Discrete_MCRegisterSet *mc_reg_table_data 1606 SMU71_Discrete_MCRegisterSet *mc_reg_table_data
1608 ) 1607 )
1609{ 1608{
1610 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(smumgr->backend); 1609 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend);
1611 uint32_t i = 0; 1610 uint32_t i = 0;
1612 1611
1613 for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) { 1612 for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) {
@@ -1637,7 +1636,7 @@ static int iceland_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
1637 1636
1638 for (i = 0; i < data->dpm_table.mclk_table.count; i++) { 1637 for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
1639 res = iceland_convert_mc_reg_table_entry_to_smc( 1638 res = iceland_convert_mc_reg_table_entry_to_smc(
1640 hwmgr->smumgr, 1639 hwmgr,
1641 data->dpm_table.mclk_table.dpm_levels[i].value, 1640 data->dpm_table.mclk_table.dpm_levels[i].value,
1642 &mc_regs->data[i] 1641 &mc_regs->data[i]
1643 ); 1642 );
@@ -1651,8 +1650,7 @@ static int iceland_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
1651 1650
1652static int iceland_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr) 1651static int iceland_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
1653{ 1652{
1654 struct pp_smumgr *smumgr = hwmgr->smumgr; 1653 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend);
1655 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(smumgr->backend);
1656 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1654 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1657 uint32_t address; 1655 uint32_t address;
1658 int32_t result; 1656 int32_t result;
@@ -1671,7 +1669,7 @@ static int iceland_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
1671 1669
1672 address = smu_data->smu7_data.mc_reg_table_start + (uint32_t)offsetof(SMU71_Discrete_MCRegisters, data[0]); 1670 address = smu_data->smu7_data.mc_reg_table_start + (uint32_t)offsetof(SMU71_Discrete_MCRegisters, data[0]);
1673 1671
1674 return smu7_copy_bytes_to_smc(hwmgr->smumgr, address, 1672 return smu7_copy_bytes_to_smc(hwmgr, address,
1675 (uint8_t *)&smu_data->mc_regs.data[0], 1673 (uint8_t *)&smu_data->mc_regs.data[0],
1676 sizeof(SMU71_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count, 1674 sizeof(SMU71_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count,
1677 SMC_RAM_END); 1675 SMC_RAM_END);
@@ -1680,11 +1678,10 @@ static int iceland_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
1680static int iceland_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr) 1678static int iceland_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
1681{ 1679{
1682 int result; 1680 int result;
1683 struct pp_smumgr *smumgr = hwmgr->smumgr; 1681 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend);
1684 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(smumgr->backend);
1685 1682
1686 memset(&smu_data->mc_regs, 0x00, sizeof(SMU71_Discrete_MCRegisters)); 1683 memset(&smu_data->mc_regs, 0x00, sizeof(SMU71_Discrete_MCRegisters));
1687 result = iceland_populate_mc_reg_address(smumgr, &(smu_data->mc_regs)); 1684 result = iceland_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs));
1688 PP_ASSERT_WITH_CODE(0 == result, 1685 PP_ASSERT_WITH_CODE(0 == result,
1689 "Failed to initialize MCRegTable for the MC register addresses!", return result;); 1686 "Failed to initialize MCRegTable for the MC register addresses!", return result;);
1690 1687
@@ -1692,7 +1689,7 @@ static int iceland_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
1692 PP_ASSERT_WITH_CODE(0 == result, 1689 PP_ASSERT_WITH_CODE(0 == result,
1693 "Failed to initialize MCRegTable for driver state!", return result;); 1690 "Failed to initialize MCRegTable for driver state!", return result;);
1694 1691
1695 return smu7_copy_bytes_to_smc(smumgr, smu_data->smu7_data.mc_reg_table_start, 1692 return smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.mc_reg_table_start,
1696 (uint8_t *)&smu_data->mc_regs, sizeof(SMU71_Discrete_MCRegisters), SMC_RAM_END); 1693 (uint8_t *)&smu_data->mc_regs, sizeof(SMU71_Discrete_MCRegisters), SMC_RAM_END);
1697} 1694}
1698 1695
@@ -1944,7 +1941,7 @@ int iceland_init_smc_table(struct pp_hwmgr *hwmgr)
1944 table->BootMVdd = PP_HOST_TO_SMC_US(table->BootMVdd * VOLTAGE_SCALE); 1941 table->BootMVdd = PP_HOST_TO_SMC_US(table->BootMVdd * VOLTAGE_SCALE);
1945 1942
1946 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */ 1943 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
1947 result = smu7_copy_bytes_to_smc(hwmgr->smumgr, smu_data->smu7_data.dpm_table_start + 1944 result = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.dpm_table_start +
1948 offsetof(SMU71_Discrete_DpmTable, SystemFlags), 1945 offsetof(SMU71_Discrete_DpmTable, SystemFlags),
1949 (uint8_t *)&(table->SystemFlags), 1946 (uint8_t *)&(table->SystemFlags),
1950 sizeof(SMU71_Discrete_DpmTable)-3 * sizeof(SMU71_PIDController), 1947 sizeof(SMU71_Discrete_DpmTable)-3 * sizeof(SMU71_PIDController),
@@ -1954,7 +1951,7 @@ int iceland_init_smc_table(struct pp_hwmgr *hwmgr)
1954 "Failed to upload dpm data to SMC memory!", return result;); 1951 "Failed to upload dpm data to SMC memory!", return result;);
1955 1952
1956 /* Upload all ulv setting to SMC memory.(dpm level, dpm level count etc) */ 1953 /* Upload all ulv setting to SMC memory.(dpm level, dpm level count etc) */
1957 result = smu7_copy_bytes_to_smc(hwmgr->smumgr, 1954 result = smu7_copy_bytes_to_smc(hwmgr,
1958 smu_data->smu7_data.ulv_setting_starts, 1955 smu_data->smu7_data.ulv_setting_starts,
1959 (uint8_t *)&(smu_data->ulv_setting), 1956 (uint8_t *)&(smu_data->ulv_setting),
1960 sizeof(SMU71_Discrete_Ulv), 1957 sizeof(SMU71_Discrete_Ulv),
@@ -2053,7 +2050,7 @@ int iceland_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
2053 2050
2054 /* fan_table.FanControl_GL_Flag = 1; */ 2051 /* fan_table.FanControl_GL_Flag = 1; */
2055 2052
2056 res = smu7_copy_bytes_to_smc(hwmgr->smumgr, smu7_data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), SMC_RAM_END); 2053 res = smu7_copy_bytes_to_smc(hwmgr, smu7_data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), SMC_RAM_END);
2057 2054
2058 return 0; 2055 return 0;
2059} 2056}
@@ -2090,7 +2087,7 @@ int iceland_update_sclk_threshold(struct pp_hwmgr *hwmgr)
2090 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold); 2087 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
2091 2088
2092 result = smu7_copy_bytes_to_smc( 2089 result = smu7_copy_bytes_to_smc(
2093 hwmgr->smumgr, 2090 hwmgr,
2094 smu_data->smu7_data.dpm_table_start + 2091 smu_data->smu7_data.dpm_table_start +
2095 offsetof(SMU71_Discrete_DpmTable, 2092 offsetof(SMU71_Discrete_DpmTable,
2096 LowSclkInterruptThreshold), 2093 LowSclkInterruptThreshold),
@@ -2177,7 +2174,7 @@ int iceland_process_firmware_header(struct pp_hwmgr *hwmgr)
2177 int result; 2174 int result;
2178 bool error = false; 2175 bool error = false;
2179 2176
2180 result = smu7_read_smc_sram_dword(hwmgr->smumgr, 2177 result = smu7_read_smc_sram_dword(hwmgr,
2181 SMU71_FIRMWARE_HEADER_LOCATION + 2178 SMU71_FIRMWARE_HEADER_LOCATION +
2182 offsetof(SMU71_Firmware_Header, DpmTable), 2179 offsetof(SMU71_Firmware_Header, DpmTable),
2183 &tmp, SMC_RAM_END); 2180 &tmp, SMC_RAM_END);
@@ -2188,7 +2185,7 @@ int iceland_process_firmware_header(struct pp_hwmgr *hwmgr)
2188 2185
2189 error |= (0 != result); 2186 error |= (0 != result);
2190 2187
2191 result = smu7_read_smc_sram_dword(hwmgr->smumgr, 2188 result = smu7_read_smc_sram_dword(hwmgr,
2192 SMU71_FIRMWARE_HEADER_LOCATION + 2189 SMU71_FIRMWARE_HEADER_LOCATION +
2193 offsetof(SMU71_Firmware_Header, SoftRegisters), 2190 offsetof(SMU71_Firmware_Header, SoftRegisters),
2194 &tmp, SMC_RAM_END); 2191 &tmp, SMC_RAM_END);
@@ -2201,7 +2198,7 @@ int iceland_process_firmware_header(struct pp_hwmgr *hwmgr)
2201 error |= (0 != result); 2198 error |= (0 != result);
2202 2199
2203 2200
2204 result = smu7_read_smc_sram_dword(hwmgr->smumgr, 2201 result = smu7_read_smc_sram_dword(hwmgr,
2205 SMU71_FIRMWARE_HEADER_LOCATION + 2202 SMU71_FIRMWARE_HEADER_LOCATION +
2206 offsetof(SMU71_Firmware_Header, mcRegisterTable), 2203 offsetof(SMU71_Firmware_Header, mcRegisterTable),
2207 &tmp, SMC_RAM_END); 2204 &tmp, SMC_RAM_END);
@@ -2210,7 +2207,7 @@ int iceland_process_firmware_header(struct pp_hwmgr *hwmgr)
2210 smu7_data->mc_reg_table_start = tmp; 2207 smu7_data->mc_reg_table_start = tmp;
2211 } 2208 }
2212 2209
2213 result = smu7_read_smc_sram_dword(hwmgr->smumgr, 2210 result = smu7_read_smc_sram_dword(hwmgr,
2214 SMU71_FIRMWARE_HEADER_LOCATION + 2211 SMU71_FIRMWARE_HEADER_LOCATION +
2215 offsetof(SMU71_Firmware_Header, FanTable), 2212 offsetof(SMU71_Firmware_Header, FanTable),
2216 &tmp, SMC_RAM_END); 2213 &tmp, SMC_RAM_END);
@@ -2221,7 +2218,7 @@ int iceland_process_firmware_header(struct pp_hwmgr *hwmgr)
2221 2218
2222 error |= (0 != result); 2219 error |= (0 != result);
2223 2220
2224 result = smu7_read_smc_sram_dword(hwmgr->smumgr, 2221 result = smu7_read_smc_sram_dword(hwmgr,
2225 SMU71_FIRMWARE_HEADER_LOCATION + 2222 SMU71_FIRMWARE_HEADER_LOCATION +
2226 offsetof(SMU71_Firmware_Header, mcArbDramTimingTable), 2223 offsetof(SMU71_Firmware_Header, mcArbDramTimingTable),
2227 &tmp, SMC_RAM_END); 2224 &tmp, SMC_RAM_END);
@@ -2233,7 +2230,7 @@ int iceland_process_firmware_header(struct pp_hwmgr *hwmgr)
2233 error |= (0 != result); 2230 error |= (0 != result);
2234 2231
2235 2232
2236 result = smu7_read_smc_sram_dword(hwmgr->smumgr, 2233 result = smu7_read_smc_sram_dword(hwmgr,
2237 SMU71_FIRMWARE_HEADER_LOCATION + 2234 SMU71_FIRMWARE_HEADER_LOCATION +
2238 offsetof(SMU71_Firmware_Header, Version), 2235 offsetof(SMU71_Firmware_Header, Version),
2239 &tmp, SMC_RAM_END); 2236 &tmp, SMC_RAM_END);
@@ -2244,7 +2241,7 @@ int iceland_process_firmware_header(struct pp_hwmgr *hwmgr)
2244 2241
2245 error |= (0 != result); 2242 error |= (0 != result);
2246 2243
2247 result = smu7_read_smc_sram_dword(hwmgr->smumgr, 2244 result = smu7_read_smc_sram_dword(hwmgr,
2248 SMU71_FIRMWARE_HEADER_LOCATION + 2245 SMU71_FIRMWARE_HEADER_LOCATION +
2249 offsetof(SMU71_Firmware_Header, UlvSettings), 2246 offsetof(SMU71_Firmware_Header, UlvSettings),
2250 &tmp, SMC_RAM_END); 2247 &tmp, SMC_RAM_END);
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
index 0bf2def3b659..d66527299308 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
@@ -39,55 +39,55 @@
39 39
40#define ICELAND_SMC_SIZE 0x20000 40#define ICELAND_SMC_SIZE 0x20000
41 41
42static int iceland_start_smc(struct pp_smumgr *smumgr) 42static int iceland_start_smc(struct pp_hwmgr *hwmgr)
43{ 43{
44 SMUM_WRITE_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, 44 SMUM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
45 SMC_SYSCON_RESET_CNTL, rst_reg, 0); 45 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
46 46
47 return 0; 47 return 0;
48} 48}
49 49
50static void iceland_reset_smc(struct pp_smumgr *smumgr) 50static void iceland_reset_smc(struct pp_hwmgr *hwmgr)
51{ 51{
52 SMUM_WRITE_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, 52 SMUM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
53 SMC_SYSCON_RESET_CNTL, 53 SMC_SYSCON_RESET_CNTL,
54 rst_reg, 1); 54 rst_reg, 1);
55} 55}
56 56
57 57
58static void iceland_stop_smc_clock(struct pp_smumgr *smumgr) 58static void iceland_stop_smc_clock(struct pp_hwmgr *hwmgr)
59{ 59{
60 SMUM_WRITE_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, 60 SMUM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
61 SMC_SYSCON_CLOCK_CNTL_0, 61 SMC_SYSCON_CLOCK_CNTL_0,
62 ck_disable, 1); 62 ck_disable, 1);
63} 63}
64 64
65static void iceland_start_smc_clock(struct pp_smumgr *smumgr) 65static void iceland_start_smc_clock(struct pp_hwmgr *hwmgr)
66{ 66{
67 SMUM_WRITE_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, 67 SMUM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
68 SMC_SYSCON_CLOCK_CNTL_0, 68 SMC_SYSCON_CLOCK_CNTL_0,
69 ck_disable, 0); 69 ck_disable, 0);
70} 70}
71 71
72static int iceland_smu_start_smc(struct pp_smumgr *smumgr) 72static int iceland_smu_start_smc(struct pp_hwmgr *hwmgr)
73{ 73{
74 /* set smc instruct start point at 0x0 */ 74 /* set smc instruct start point at 0x0 */
75 smu7_program_jump_on_start(smumgr); 75 smu7_program_jump_on_start(hwmgr);
76 76
77 /* enable smc clock */ 77 /* enable smc clock */
78 iceland_start_smc_clock(smumgr); 78 iceland_start_smc_clock(hwmgr);
79 79
80 /* de-assert reset */ 80 /* de-assert reset */
81 iceland_start_smc(smumgr); 81 iceland_start_smc(hwmgr);
82 82
83 SMUM_WAIT_INDIRECT_FIELD(smumgr, SMC_IND, FIRMWARE_FLAGS, 83 SMUM_WAIT_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS,
84 INTERRUPTS_ENABLED, 1); 84 INTERRUPTS_ENABLED, 1);
85 85
86 return 0; 86 return 0;
87} 87}
88 88
89 89
90static int iceland_upload_smc_firmware_data(struct pp_smumgr *smumgr, 90static int iceland_upload_smc_firmware_data(struct pp_hwmgr *hwmgr,
91 uint32_t length, const uint8_t *src, 91 uint32_t length, const uint8_t *src,
92 uint32_t limit, uint32_t start_addr) 92 uint32_t limit, uint32_t start_addr)
93{ 93{
@@ -96,17 +96,17 @@ static int iceland_upload_smc_firmware_data(struct pp_smumgr *smumgr,
96 96
97 PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -EINVAL); 97 PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -EINVAL);
98 98
99 cgs_write_register(smumgr->device, mmSMC_IND_INDEX_0, start_addr); 99 cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, start_addr);
100 SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1); 100 SMUM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1);
101 101
102 while (byte_count >= 4) { 102 while (byte_count >= 4) {
103 data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3]; 103 data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3];
104 cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, data); 104 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data);
105 src += 4; 105 src += 4;
106 byte_count -= 4; 106 byte_count -= 4;
107 } 107 }
108 108
109 SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0); 109 SMUM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
110 110
111 PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be dividable by 4.", return -EINVAL); 111 PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be dividable by 4.", return -EINVAL);
112 112
@@ -114,16 +114,16 @@ static int iceland_upload_smc_firmware_data(struct pp_smumgr *smumgr,
114} 114}
115 115
116 116
117static int iceland_smu_upload_firmware_image(struct pp_smumgr *smumgr) 117static int iceland_smu_upload_firmware_image(struct pp_hwmgr *hwmgr)
118{ 118{
119 uint32_t val; 119 uint32_t val;
120 struct cgs_firmware_info info = {0}; 120 struct cgs_firmware_info info = {0};
121 121
122 if (smumgr == NULL || smumgr->device == NULL) 122 if (hwmgr == NULL || hwmgr->device == NULL)
123 return -EINVAL; 123 return -EINVAL;
124 124
125 /* load SMC firmware */ 125 /* load SMC firmware */
126 cgs_get_firmware_info(smumgr->device, 126 cgs_get_firmware_info(hwmgr->device,
127 smu7_convert_fw_type_to_cgs(UCODE_ID_SMU), &info); 127 smu7_convert_fw_type_to_cgs(UCODE_ID_SMU), &info);
128 128
129 if (info.image_size & 3) { 129 if (info.image_size & 3) {
@@ -137,56 +137,56 @@ static int iceland_smu_upload_firmware_image(struct pp_smumgr *smumgr)
137 } 137 }
138 138
139 /* wait for smc boot up */ 139 /* wait for smc boot up */
140 SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, 140 SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
141 RCU_UC_EVENTS, boot_seq_done, 0); 141 RCU_UC_EVENTS, boot_seq_done, 0);
142 142
143 /* clear firmware interrupt enable flag */ 143 /* clear firmware interrupt enable flag */
144 val = cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC, 144 val = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
145 ixSMC_SYSCON_MISC_CNTL); 145 ixSMC_SYSCON_MISC_CNTL);
146 cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, 146 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
147 ixSMC_SYSCON_MISC_CNTL, val | 1); 147 ixSMC_SYSCON_MISC_CNTL, val | 1);
148 148
149 /* stop smc clock */ 149 /* stop smc clock */
150 iceland_stop_smc_clock(smumgr); 150 iceland_stop_smc_clock(hwmgr);
151 151
152 /* reset smc */ 152 /* reset smc */
153 iceland_reset_smc(smumgr); 153 iceland_reset_smc(hwmgr);
154 iceland_upload_smc_firmware_data(smumgr, info.image_size, 154 iceland_upload_smc_firmware_data(hwmgr, info.image_size,
155 (uint8_t *)info.kptr, ICELAND_SMC_SIZE, 155 (uint8_t *)info.kptr, ICELAND_SMC_SIZE,
156 info.ucode_start_address); 156 info.ucode_start_address);
157 157
158 return 0; 158 return 0;
159} 159}
160 160
161static int iceland_request_smu_load_specific_fw(struct pp_smumgr *smumgr, 161static int iceland_request_smu_load_specific_fw(struct pp_hwmgr *hwmgr,
162 uint32_t firmwareType) 162 uint32_t firmwareType)
163{ 163{
164 return 0; 164 return 0;
165} 165}
166 166
167static int iceland_start_smu(struct pp_smumgr *smumgr) 167static int iceland_start_smu(struct pp_hwmgr *hwmgr)
168{ 168{
169 int result; 169 int result;
170 170
171 result = iceland_smu_upload_firmware_image(smumgr); 171 result = iceland_smu_upload_firmware_image(hwmgr);
172 if (result) 172 if (result)
173 return result; 173 return result;
174 result = iceland_smu_start_smc(smumgr); 174 result = iceland_smu_start_smc(hwmgr);
175 if (result) 175 if (result)
176 return result; 176 return result;
177 177
178 if (!smu7_is_smc_ram_running(smumgr)) { 178 if (!smu7_is_smc_ram_running(hwmgr)) {
179 pr_info("smu not running, upload firmware again \n"); 179 pr_info("smu not running, upload firmware again \n");
180 result = iceland_smu_upload_firmware_image(smumgr); 180 result = iceland_smu_upload_firmware_image(hwmgr);
181 if (result) 181 if (result)
182 return result; 182 return result;
183 183
184 result = iceland_smu_start_smc(smumgr); 184 result = iceland_smu_start_smc(hwmgr);
185 if (result) 185 if (result)
186 return result; 186 return result;
187 } 187 }
188 188
189 result = smu7_request_smu_load_fw(smumgr); 189 result = smu7_request_smu_load_fw(hwmgr);
190 190
191 return result; 191 return result;
192} 192}
@@ -198,7 +198,7 @@ static int iceland_start_smu(struct pp_smumgr *smumgr)
198 * @param smcAddress the address in the SMC RAM to access. 198 * @param smcAddress the address in the SMC RAM to access.
199 * @param value to write to the SMC SRAM. 199 * @param value to write to the SMC SRAM.
200 */ 200 */
201static int iceland_smu_init(struct pp_smumgr *smumgr) 201static int iceland_smu_init(struct pp_hwmgr *hwmgr)
202{ 202{
203 int i; 203 int i;
204 struct iceland_smumgr *iceland_priv = NULL; 204 struct iceland_smumgr *iceland_priv = NULL;
@@ -208,9 +208,9 @@ static int iceland_smu_init(struct pp_smumgr *smumgr)
208 if (iceland_priv == NULL) 208 if (iceland_priv == NULL)
209 return -ENOMEM; 209 return -ENOMEM;
210 210
211 smumgr->backend = iceland_priv; 211 hwmgr->smumgr->backend = iceland_priv;
212 212
213 if (smu7_init(smumgr)) 213 if (smu7_init(hwmgr))
214 return -EINVAL; 214 return -EINVAL;
215 215
216 for (i = 0; i < SMU71_MAX_LEVELS_GRAPHICS; i++) 216 for (i = 0; i < SMU71_MAX_LEVELS_GRAPHICS; i++)
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
index 2d444bb4802a..118315186bc3 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
@@ -231,7 +231,7 @@ static int polaris10_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_of
231 const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults; 231 const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
232 uint32_t temp; 232 uint32_t temp;
233 233
234 if (smu7_read_smc_sram_dword(hwmgr->smumgr, 234 if (smu7_read_smc_sram_dword(hwmgr,
235 fuse_table_offset + 235 fuse_table_offset +
236 offsetof(SMU74_Discrete_PmFuses, TdcWaterfallCtl), 236 offsetof(SMU74_Discrete_PmFuses, TdcWaterfallCtl),
237 (uint32_t *)&temp, SMC_RAM_END)) 237 (uint32_t *)&temp, SMC_RAM_END))
@@ -315,7 +315,7 @@ static int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr)
315 315
316 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 316 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
317 PHM_PlatformCaps_PowerContainment)) { 317 PHM_PlatformCaps_PowerContainment)) {
318 if (smu7_read_smc_sram_dword(hwmgr->smumgr, 318 if (smu7_read_smc_sram_dword(hwmgr,
319 SMU7_FIRMWARE_HEADER_LOCATION + 319 SMU7_FIRMWARE_HEADER_LOCATION +
320 offsetof(SMU74_Firmware_Header, PmFuseTable), 320 offsetof(SMU74_Firmware_Header, PmFuseTable),
321 &pm_fuse_table_offset, SMC_RAM_END)) 321 &pm_fuse_table_offset, SMC_RAM_END))
@@ -358,7 +358,7 @@ static int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr)
358 "Attempt to populate BapmVddCBaseLeakage Hi and Lo " 358 "Attempt to populate BapmVddCBaseLeakage Hi and Lo "
359 "Sidd Failed!", return -EINVAL); 359 "Sidd Failed!", return -EINVAL);
360 360
361 if (smu7_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset, 361 if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
362 (uint8_t *)&smu_data->power_tune_table, 362 (uint8_t *)&smu_data->power_tune_table,
363 (sizeof(struct SMU74_Discrete_PmFuses) - 92), SMC_RAM_END)) 363 (sizeof(struct SMU74_Discrete_PmFuses) - 92), SMC_RAM_END))
364 PP_ASSERT_WITH_CODE(false, 364 PP_ASSERT_WITH_CODE(false,
@@ -484,7 +484,6 @@ static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
484 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 484 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
485 struct phm_ppt_v1_information *table_info = 485 struct phm_ppt_v1_information *table_info =
486 (struct phm_ppt_v1_information *)(hwmgr->pptable); 486 (struct phm_ppt_v1_information *)(hwmgr->pptable);
487 struct pp_smumgr *smumgr = hwmgr->smumgr;
488 487
489 state->CcPwrDynRm = 0; 488 state->CcPwrDynRm = 0;
490 state->CcPwrDynRm1 = 0; 489 state->CcPwrDynRm1 = 0;
@@ -493,7 +492,7 @@ static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
493 state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset * 492 state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
494 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1); 493 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
495 494
496 if (smumgr->chip_id == CHIP_POLARIS12 || smumgr->is_kicker) 495 if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->smumgr->is_kicker)
497 state->VddcPhase = data->vddc_phase_shed_control ^ 0x3; 496 state->VddcPhase = data->vddc_phase_shed_control ^ 0x3;
498 else 497 else
499 state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1; 498 state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
@@ -546,8 +545,7 @@ static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
546static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr, 545static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr,
547 SMU74_Discrete_DpmTable *table) 546 SMU74_Discrete_DpmTable *table)
548{ 547{
549 struct pp_smumgr *smumgr = hwmgr->smumgr; 548 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
550 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
551 uint32_t i, ref_clk; 549 uint32_t i, ref_clk;
552 550
553 struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } }; 551 struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
@@ -597,8 +595,7 @@ static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr,
597static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr, 595static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
598 uint32_t clock, SMU_SclkSetting *sclk_setting) 596 uint32_t clock, SMU_SclkSetting *sclk_setting)
599{ 597{
600 struct pp_smumgr *smumgr = hwmgr->smumgr; 598 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
601 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
602 const SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); 599 const SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
603 struct pp_atomctrl_clock_dividers_ai dividers; 600 struct pp_atomctrl_clock_dividers_ai dividers;
604 uint32_t ref_clock; 601 uint32_t ref_clock;
@@ -741,9 +738,8 @@ static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
741*/ 738*/
742int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) 739int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
743{ 740{
744 struct pp_smumgr *smumgr = hwmgr->smumgr;
745 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); 741 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
746 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); 742 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
747 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; 743 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
748 struct phm_ppt_v1_information *table_info = 744 struct phm_ppt_v1_information *table_info =
749 (struct phm_ppt_v1_information *)(hwmgr->pptable); 745 (struct phm_ppt_v1_information *)(hwmgr->pptable);
@@ -828,7 +824,7 @@ int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
828 levels[1].pcieDpmLevel = mid_pcie_level_enabled; 824 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
829 } 825 }
830 /* level count will send to smc once at init smc table and never change */ 826 /* level count will send to smc once at init smc table and never change */
831 result = smu7_copy_bytes_to_smc(smumgr, array, (uint8_t *)levels, 827 result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
832 (uint32_t)array_size, SMC_RAM_END); 828 (uint32_t)array_size, SMC_RAM_END);
833 829
834 return result; 830 return result;
@@ -890,9 +886,8 @@ static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
890*/ 886*/
891int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr) 887int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
892{ 888{
893 struct pp_smumgr *smumgr = hwmgr->smumgr;
894 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); 889 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
895 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); 890 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
896 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; 891 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
897 int result; 892 int result;
898 /* populate MCLK dpm table to SMU7 */ 893 /* populate MCLK dpm table to SMU7 */
@@ -933,7 +928,7 @@ int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
933 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); 928 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
934 929
935 /* level count will send to smc once at init smc table and never change */ 930 /* level count will send to smc once at init smc table and never change */
936 result = smu7_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels, 931 result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
937 (uint32_t)array_size, SMC_RAM_END); 932 (uint32_t)array_size, SMC_RAM_END);
938 933
939 return result; 934 return result;
@@ -1191,9 +1186,8 @@ static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
1191 1186
1192static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) 1187static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1193{ 1188{
1194 struct pp_smumgr *smumgr = hwmgr->smumgr;
1195 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); 1189 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1196 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); 1190 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
1197 struct SMU74_Discrete_MCArbDramTimingTable arb_regs; 1191 struct SMU74_Discrete_MCArbDramTimingTable arb_regs;
1198 uint32_t i, j; 1192 uint32_t i, j;
1199 int result = 0; 1193 int result = 0;
@@ -1212,7 +1206,7 @@ static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1212 } 1206 }
1213 1207
1214 result = smu7_copy_bytes_to_smc( 1208 result = smu7_copy_bytes_to_smc(
1215 hwmgr->smumgr, 1209 hwmgr,
1216 smu_data->smu7_data.arb_table_start, 1210 smu_data->smu7_data.arb_table_start,
1217 (uint8_t *)&arb_regs, 1211 (uint8_t *)&arb_regs,
1218 sizeof(SMU74_Discrete_MCArbDramTimingTable), 1212 sizeof(SMU74_Discrete_MCArbDramTimingTable),
@@ -1311,9 +1305,8 @@ static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1311 1305
1312static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr) 1306static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
1313{ 1307{
1314 struct pp_smumgr *smumgr = hwmgr->smumgr;
1315 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); 1308 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1316 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); 1309 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
1317 struct phm_ppt_v1_information *table_info = 1310 struct phm_ppt_v1_information *table_info =
1318 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1311 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1319 uint8_t count, level; 1312 uint8_t count, level;
@@ -1344,8 +1337,7 @@ static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
1344static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr) 1337static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1345{ 1338{
1346 uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min; 1339 uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min;
1347 struct pp_smumgr *smumgr = hwmgr->smumgr; 1340 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
1348 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
1349 1341
1350 uint8_t i, stretch_amount, stretch_amount2, volt_offset = 0; 1342 uint8_t i, stretch_amount, stretch_amount2, volt_offset = 0;
1351 struct phm_ppt_v1_information *table_info = 1343 struct phm_ppt_v1_information *table_info =
@@ -1472,8 +1464,7 @@ static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
1472static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr) 1464static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
1473{ 1465{
1474 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1466 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1475 struct pp_smumgr *smumgr = hwmgr->smumgr; 1467 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
1476 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
1477 1468
1478 SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); 1469 SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1479 int result = 0; 1470 int result = 0;
@@ -1524,20 +1515,20 @@ static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
1524 AVFS_SclkOffset.Sclk_Offset[i] = PP_HOST_TO_SMC_US((uint16_t)(sclk_table->entries[i].sclk_offset) / 100); 1515 AVFS_SclkOffset.Sclk_Offset[i] = PP_HOST_TO_SMC_US((uint16_t)(sclk_table->entries[i].sclk_offset) / 100);
1525 } 1516 }
1526 1517
1527 result = smu7_read_smc_sram_dword(smumgr, 1518 result = smu7_read_smc_sram_dword(hwmgr,
1528 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsMeanNSigma), 1519 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsMeanNSigma),
1529 &tmp, SMC_RAM_END); 1520 &tmp, SMC_RAM_END);
1530 1521
1531 smu7_copy_bytes_to_smc(smumgr, 1522 smu7_copy_bytes_to_smc(hwmgr,
1532 tmp, 1523 tmp,
1533 (uint8_t *)&AVFS_meanNsigma, 1524 (uint8_t *)&AVFS_meanNsigma,
1534 sizeof(AVFS_meanNsigma_t), 1525 sizeof(AVFS_meanNsigma_t),
1535 SMC_RAM_END); 1526 SMC_RAM_END);
1536 1527
1537 result = smu7_read_smc_sram_dword(smumgr, 1528 result = smu7_read_smc_sram_dword(hwmgr,
1538 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsSclkOffsetTable), 1529 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsSclkOffsetTable),
1539 &tmp, SMC_RAM_END); 1530 &tmp, SMC_RAM_END);
1540 smu7_copy_bytes_to_smc(smumgr, 1531 smu7_copy_bytes_to_smc(hwmgr,
1541 tmp, 1532 tmp,
1542 (uint8_t *)&AVFS_SclkOffset, 1533 (uint8_t *)&AVFS_SclkOffset,
1543 sizeof(AVFS_Sclk_Offset_t), 1534 sizeof(AVFS_Sclk_Offset_t),
@@ -1559,9 +1550,9 @@ static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
1559* @param hwmgr the address of the powerplay hardware manager. 1550* @param hwmgr the address of the powerplay hardware manager.
1560* @return always 0 1551* @return always 0
1561*/ 1552*/
1562static int polaris10_init_arb_table_index(struct pp_smumgr *smumgr) 1553static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr)
1563{ 1554{
1564 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); 1555 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
1565 uint32_t tmp; 1556 uint32_t tmp;
1566 int result; 1557 int result;
1567 1558
@@ -1573,7 +1564,7 @@ static int polaris10_init_arb_table_index(struct pp_smumgr *smumgr)
1573 * In reality this field should not be in that structure 1564 * In reality this field should not be in that structure
1574 * but in a soft register. 1565 * but in a soft register.
1575 */ 1566 */
1576 result = smu7_read_smc_sram_dword(smumgr, 1567 result = smu7_read_smc_sram_dword(hwmgr,
1577 smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END); 1568 smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
1578 1569
1579 if (result) 1570 if (result)
@@ -1582,7 +1573,7 @@ static int polaris10_init_arb_table_index(struct pp_smumgr *smumgr)
1582 tmp &= 0x00FFFFFF; 1573 tmp &= 0x00FFFFFF;
1583 tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24; 1574 tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
1584 1575
1585 return smu7_write_smc_sram_dword(smumgr, 1576 return smu7_write_smc_sram_dword(hwmgr,
1586 smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END); 1577 smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END);
1587} 1578}
1588 1579
@@ -1648,9 +1639,8 @@ static void polaris10_save_default_power_profile(struct pp_hwmgr *hwmgr)
1648int polaris10_init_smc_table(struct pp_hwmgr *hwmgr) 1639int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
1649{ 1640{
1650 int result; 1641 int result;
1651 struct pp_smumgr *smumgr = hwmgr->smumgr;
1652 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); 1642 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1653 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); 1643 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
1654 struct phm_ppt_v1_information *table_info = 1644 struct phm_ppt_v1_information *table_info =
1655 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1645 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1656 struct SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); 1646 struct SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
@@ -1842,7 +1832,7 @@ int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
1842 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime); 1832 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
1843 1833
1844 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */ 1834 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
1845 result = smu7_copy_bytes_to_smc(hwmgr->smumgr, 1835 result = smu7_copy_bytes_to_smc(hwmgr,
1846 smu_data->smu7_data.dpm_table_start + 1836 smu_data->smu7_data.dpm_table_start +
1847 offsetof(SMU74_Discrete_DpmTable, SystemFlags), 1837 offsetof(SMU74_Discrete_DpmTable, SystemFlags),
1848 (uint8_t *)&(table->SystemFlags), 1838 (uint8_t *)&(table->SystemFlags),
@@ -1851,7 +1841,7 @@ int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
1851 PP_ASSERT_WITH_CODE(0 == result, 1841 PP_ASSERT_WITH_CODE(0 == result,
1852 "Failed to upload dpm data to SMC memory!", return result); 1842 "Failed to upload dpm data to SMC memory!", return result);
1853 1843
1854 result = polaris10_init_arb_table_index(hwmgr->smumgr); 1844 result = polaris10_init_arb_table_index(hwmgr);
1855 PP_ASSERT_WITH_CODE(0 == result, 1845 PP_ASSERT_WITH_CODE(0 == result,
1856 "Failed to upload arb data to SMC memory!", return result); 1846 "Failed to upload arb data to SMC memory!", return result);
1857 1847
@@ -1878,17 +1868,16 @@ static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
1878int polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr) 1868int polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
1879{ 1869{
1880 int ret; 1870 int ret;
1881 struct pp_smumgr *smumgr = (struct pp_smumgr *)(hwmgr->smumgr); 1871 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend);
1882 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
1883 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1872 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1884 1873
1885 if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED) 1874 if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
1886 return 0; 1875 return 0;
1887 1876
1888 ret = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 1877 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1889 PPSMC_MSG_SetGBDroopSettings, data->avfs_vdroop_override_setting); 1878 PPSMC_MSG_SetGBDroopSettings, data->avfs_vdroop_override_setting);
1890 1879
1891 ret = (smum_send_msg_to_smc(smumgr, PPSMC_MSG_EnableAvfs) == 0) ? 1880 ret = (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAvfs) == 0) ?
1892 0 : -1; 1881 0 : -1;
1893 1882
1894 if (!ret) 1883 if (!ret)
@@ -1990,20 +1979,20 @@ int polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
1990 hwmgr->device, CGS_IND_REG__SMC, 1979 hwmgr->device, CGS_IND_REG__SMC,
1991 CG_MULT_THERMAL_CTRL, TEMP_SEL); 1980 CG_MULT_THERMAL_CTRL, TEMP_SEL);
1992 1981
1993 res = smu7_copy_bytes_to_smc(hwmgr->smumgr, smu_data->smu7_data.fan_table_start, 1982 res = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.fan_table_start,
1994 (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), 1983 (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table),
1995 SMC_RAM_END); 1984 SMC_RAM_END);
1996 1985
1997 if (!res && hwmgr->thermal_controller. 1986 if (!res && hwmgr->thermal_controller.
1998 advanceFanControlParameters.ucMinimumPWMLimit) 1987 advanceFanControlParameters.ucMinimumPWMLimit)
1999 res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 1988 res = smum_send_msg_to_smc_with_parameter(hwmgr,
2000 PPSMC_MSG_SetFanMinPwm, 1989 PPSMC_MSG_SetFanMinPwm,
2001 hwmgr->thermal_controller. 1990 hwmgr->thermal_controller.
2002 advanceFanControlParameters.ucMinimumPWMLimit); 1991 advanceFanControlParameters.ucMinimumPWMLimit);
2003 1992
2004 if (!res && hwmgr->thermal_controller. 1993 if (!res && hwmgr->thermal_controller.
2005 advanceFanControlParameters.ulMinFanSCLKAcousticLimit) 1994 advanceFanControlParameters.ulMinFanSCLKAcousticLimit)
2006 res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 1995 res = smum_send_msg_to_smc_with_parameter(hwmgr,
2007 PPSMC_MSG_SetFanSclkTarget, 1996 PPSMC_MSG_SetFanSclkTarget,
2008 hwmgr->thermal_controller. 1997 hwmgr->thermal_controller.
2009 advanceFanControlParameters.ulMinFanSCLKAcousticLimit); 1998 advanceFanControlParameters.ulMinFanSCLKAcousticLimit);
@@ -2041,7 +2030,7 @@ static int polaris10_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
2041 PHM_PlatformCaps_UVDDPM) || 2030 PHM_PlatformCaps_UVDDPM) ||
2042 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 2031 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2043 PHM_PlatformCaps_StablePState)) 2032 PHM_PlatformCaps_StablePState))
2044 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 2033 smum_send_msg_to_smc_with_parameter(hwmgr,
2045 PPSMC_MSG_UVDDPM_SetEnabledMask, 2034 PPSMC_MSG_UVDDPM_SetEnabledMask,
2046 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel)); 2035 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel));
2047 return 0; 2036 return 0;
@@ -2073,7 +2062,7 @@ static int polaris10_update_vce_smc_table(struct pp_hwmgr *hwmgr)
2073 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value); 2062 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
2074 2063
2075 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) 2064 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
2076 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 2065 smum_send_msg_to_smc_with_parameter(hwmgr,
2077 PPSMC_MSG_VCEDPM_SetEnabledMask, 2066 PPSMC_MSG_VCEDPM_SetEnabledMask,
2078 (uint32_t)1 << smu_data->smc_state_table.VceBootLevel); 2067 (uint32_t)1 << smu_data->smc_state_table.VceBootLevel);
2079 return 0; 2068 return 0;
@@ -2100,7 +2089,7 @@ static int polaris10_update_samu_smc_table(struct pp_hwmgr *hwmgr)
2100 2089
2101 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 2090 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2102 PHM_PlatformCaps_StablePState)) 2091 PHM_PlatformCaps_StablePState))
2103 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 2092 smum_send_msg_to_smc_with_parameter(hwmgr,
2104 PPSMC_MSG_SAMUDPM_SetEnabledMask, 2093 PPSMC_MSG_SAMUDPM_SetEnabledMask,
2105 (uint32_t)(1 << smu_data->smc_state_table.SamuBootLevel)); 2094 (uint32_t)(1 << smu_data->smc_state_table.SamuBootLevel));
2106 return 0; 2095 return 0;
@@ -2164,7 +2153,7 @@ int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
2164 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold); 2153 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
2165 2154
2166 result = smu7_copy_bytes_to_smc( 2155 result = smu7_copy_bytes_to_smc(
2167 hwmgr->smumgr, 2156 hwmgr,
2168 smu_data->smu7_data.dpm_table_start + 2157 smu_data->smu7_data.dpm_table_start +
2169 offsetof(SMU74_Discrete_DpmTable, 2158 offsetof(SMU74_Discrete_DpmTable,
2170 LowSclkInterruptThreshold), 2159 LowSclkInterruptThreshold),
@@ -2258,7 +2247,7 @@ int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
2258 int result; 2247 int result;
2259 bool error = false; 2248 bool error = false;
2260 2249
2261 result = smu7_read_smc_sram_dword(hwmgr->smumgr, 2250 result = smu7_read_smc_sram_dword(hwmgr,
2262 SMU7_FIRMWARE_HEADER_LOCATION + 2251 SMU7_FIRMWARE_HEADER_LOCATION +
2263 offsetof(SMU74_Firmware_Header, DpmTable), 2252 offsetof(SMU74_Firmware_Header, DpmTable),
2264 &tmp, SMC_RAM_END); 2253 &tmp, SMC_RAM_END);
@@ -2268,7 +2257,7 @@ int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
2268 2257
2269 error |= (0 != result); 2258 error |= (0 != result);
2270 2259
2271 result = smu7_read_smc_sram_dword(hwmgr->smumgr, 2260 result = smu7_read_smc_sram_dword(hwmgr,
2272 SMU7_FIRMWARE_HEADER_LOCATION + 2261 SMU7_FIRMWARE_HEADER_LOCATION +
2273 offsetof(SMU74_Firmware_Header, SoftRegisters), 2262 offsetof(SMU74_Firmware_Header, SoftRegisters),
2274 &tmp, SMC_RAM_END); 2263 &tmp, SMC_RAM_END);
@@ -2280,7 +2269,7 @@ int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
2280 2269
2281 error |= (0 != result); 2270 error |= (0 != result);
2282 2271
2283 result = smu7_read_smc_sram_dword(hwmgr->smumgr, 2272 result = smu7_read_smc_sram_dword(hwmgr,
2284 SMU7_FIRMWARE_HEADER_LOCATION + 2273 SMU7_FIRMWARE_HEADER_LOCATION +
2285 offsetof(SMU74_Firmware_Header, mcRegisterTable), 2274 offsetof(SMU74_Firmware_Header, mcRegisterTable),
2286 &tmp, SMC_RAM_END); 2275 &tmp, SMC_RAM_END);
@@ -2288,7 +2277,7 @@ int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
2288 if (!result) 2277 if (!result)
2289 smu_data->smu7_data.mc_reg_table_start = tmp; 2278 smu_data->smu7_data.mc_reg_table_start = tmp;
2290 2279
2291 result = smu7_read_smc_sram_dword(hwmgr->smumgr, 2280 result = smu7_read_smc_sram_dword(hwmgr,
2292 SMU7_FIRMWARE_HEADER_LOCATION + 2281 SMU7_FIRMWARE_HEADER_LOCATION +
2293 offsetof(SMU74_Firmware_Header, FanTable), 2282 offsetof(SMU74_Firmware_Header, FanTable),
2294 &tmp, SMC_RAM_END); 2283 &tmp, SMC_RAM_END);
@@ -2298,7 +2287,7 @@ int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
2298 2287
2299 error |= (0 != result); 2288 error |= (0 != result);
2300 2289
2301 result = smu7_read_smc_sram_dword(hwmgr->smumgr, 2290 result = smu7_read_smc_sram_dword(hwmgr,
2302 SMU7_FIRMWARE_HEADER_LOCATION + 2291 SMU7_FIRMWARE_HEADER_LOCATION +
2303 offsetof(SMU74_Firmware_Header, mcArbDramTimingTable), 2292 offsetof(SMU74_Firmware_Header, mcArbDramTimingTable),
2304 &tmp, SMC_RAM_END); 2293 &tmp, SMC_RAM_END);
@@ -2308,7 +2297,7 @@ int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
2308 2297
2309 error |= (0 != result); 2298 error |= (0 != result);
2310 2299
2311 result = smu7_read_smc_sram_dword(hwmgr->smumgr, 2300 result = smu7_read_smc_sram_dword(hwmgr,
2312 SMU7_FIRMWARE_HEADER_LOCATION + 2301 SMU7_FIRMWARE_HEADER_LOCATION +
2313 offsetof(SMU74_Firmware_Header, Version), 2302 offsetof(SMU74_Firmware_Header, Version),
2314 &tmp, SMC_RAM_END); 2303 &tmp, SMC_RAM_END);
@@ -2349,6 +2338,6 @@ int polaris10_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
2349 levels[i].DownHyst = request->down_hyst; 2338 levels[i].DownHyst = request->down_hyst;
2350 } 2339 }
2351 2340
2352 return smu7_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels, 2341 return smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
2353 array_size, SMC_RAM_END); 2342 array_size, SMC_RAM_END);
2354} 2343}
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index 75f43dadc56b..55ba76202aa3 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -60,21 +60,21 @@ static const SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = {
60static const SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 = { 60static const SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 = {
61 0x100ea446, 0, 0x30750000, 0x01, 0x01, 0x01, 0x00, 0x00, 0x64, 0x00, 0x00, 0x1f00, 0x00, 0x00}; 61 0x100ea446, 0, 0x30750000, 0x01, 0x01, 0x01, 0x00, 0x00, 0x64, 0x00, 0x00, 0x1f00, 0x00, 0x00};
62 62
63static int polaris10_setup_pwr_virus(struct pp_smumgr *smumgr) 63static int polaris10_setup_pwr_virus(struct pp_hwmgr *hwmgr)
64{ 64{
65 int i; 65 int i;
66 int result = -EINVAL; 66 int result = -EINVAL;
67 uint32_t reg, data; 67 uint32_t reg, data;
68 68
69 const PWR_Command_Table *pvirus = pwr_virus_table; 69 const PWR_Command_Table *pvirus = pwr_virus_table;
70 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend); 70 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend);
71 71
72 for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) { 72 for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) {
73 switch (pvirus->command) { 73 switch (pvirus->command) {
74 case PwrCmdWrite: 74 case PwrCmdWrite:
75 reg = pvirus->reg; 75 reg = pvirus->reg;
76 data = pvirus->data; 76 data = pvirus->data;
77 cgs_write_register(smumgr->device, reg, data); 77 cgs_write_register(hwmgr->device, reg, data);
78 break; 78 break;
79 79
80 case PwrCmdEnd: 80 case PwrCmdEnd:
@@ -93,13 +93,13 @@ static int polaris10_setup_pwr_virus(struct pp_smumgr *smumgr)
93 return result; 93 return result;
94} 94}
95 95
96static int polaris10_perform_btc(struct pp_smumgr *smumgr) 96static int polaris10_perform_btc(struct pp_hwmgr *hwmgr)
97{ 97{
98 int result = 0; 98 int result = 0;
99 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend); 99 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend);
100 100
101 if (0 != smu_data->avfs.avfs_btc_param) { 101 if (0 != smu_data->avfs.avfs_btc_param) {
102 if (0 != smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) { 102 if (0 != smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) {
103 pr_info("[AVFS][SmuPolaris10_PerformBtc] PerformBTC SMU msg failed"); 103 pr_info("[AVFS][SmuPolaris10_PerformBtc] PerformBTC SMU msg failed");
104 result = -1; 104 result = -1;
105 } 105 }
@@ -107,16 +107,16 @@ static int polaris10_perform_btc(struct pp_smumgr *smumgr)
107 if (smu_data->avfs.avfs_btc_param > 1) { 107 if (smu_data->avfs.avfs_btc_param > 1) {
108 /* Soft-Reset to reset the engine before loading uCode */ 108 /* Soft-Reset to reset the engine before loading uCode */
109 /* halt */ 109 /* halt */
110 cgs_write_register(smumgr->device, mmCP_MEC_CNTL, 0x50000000); 110 cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000);
111 /* reset everything */ 111 /* reset everything */
112 cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0xffffffff); 112 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0xffffffff);
113 cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0); 113 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0);
114 } 114 }
115 return result; 115 return result;
116} 116}
117 117
118 118
119static int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr) 119static int polaris10_setup_graphics_level_structure(struct pp_hwmgr *hwmgr)
120{ 120{
121 uint32_t vr_config; 121 uint32_t vr_config;
122 uint32_t dpm_table_start; 122 uint32_t dpm_table_start;
@@ -127,7 +127,7 @@ static int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
127 graphics_level_size = sizeof(avfs_graphics_level_polaris10); 127 graphics_level_size = sizeof(avfs_graphics_level_polaris10);
128 u16_boot_mvdd = PP_HOST_TO_SMC_US(1300 * VOLTAGE_SCALE); 128 u16_boot_mvdd = PP_HOST_TO_SMC_US(1300 * VOLTAGE_SCALE);
129 129
130 PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(smumgr, 130 PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr,
131 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, DpmTable), 131 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, DpmTable),
132 &dpm_table_start, 0x40000), 132 &dpm_table_start, 0x40000),
133 "[AVFS][Polaris10_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table", 133 "[AVFS][Polaris10_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table",
@@ -138,14 +138,14 @@ static int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
138 138
139 vr_config_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, VRConfig); 139 vr_config_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, VRConfig);
140 140
141 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, vr_config_address, 141 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_address,
142 (uint8_t *)&vr_config, sizeof(uint32_t), 0x40000), 142 (uint8_t *)&vr_config, sizeof(uint32_t), 0x40000),
143 "[AVFS][Polaris10_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC", 143 "[AVFS][Polaris10_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC",
144 return -1); 144 return -1);
145 145
146 graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, GraphicsLevel); 146 graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
147 147
148 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, graphics_level_address, 148 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
149 (uint8_t *)(&avfs_graphics_level_polaris10), 149 (uint8_t *)(&avfs_graphics_level_polaris10),
150 graphics_level_size, 0x40000), 150 graphics_level_size, 0x40000),
151 "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of SCLK DPM table failed!", 151 "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of SCLK DPM table failed!",
@@ -153,7 +153,7 @@ static int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
153 153
154 graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, MemoryLevel); 154 graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
155 155
156 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, graphics_level_address, 156 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
157 (uint8_t *)(&avfs_memory_level_polaris10), sizeof(avfs_memory_level_polaris10), 0x40000), 157 (uint8_t *)(&avfs_memory_level_polaris10), sizeof(avfs_memory_level_polaris10), 0x40000),
158 "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of MCLK DPM table failed!", 158 "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of MCLK DPM table failed!",
159 return -1); 159 return -1);
@@ -162,7 +162,7 @@ static int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
162 162
163 graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, BootMVdd); 163 graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, BootMVdd);
164 164
165 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, graphics_level_address, 165 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
166 (uint8_t *)(&u16_boot_mvdd), sizeof(u16_boot_mvdd), 0x40000), 166 (uint8_t *)(&u16_boot_mvdd), sizeof(u16_boot_mvdd), 0x40000),
167 "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of DPM table failed!", 167 "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of DPM table failed!",
168 return -1); 168 return -1);
@@ -172,9 +172,9 @@ static int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
172 172
173 173
174static int 174static int
175polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT) 175polaris10_avfs_event_mgr(struct pp_hwmgr *hwmgr, bool SMU_VFT_INTACT)
176{ 176{
177 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend); 177 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend);
178 178
179 switch (smu_data->avfs.avfs_btc_status) { 179 switch (smu_data->avfs.avfs_btc_status) {
180 case AVFS_BTC_COMPLETED_PREVIOUSLY: 180 case AVFS_BTC_COMPLETED_PREVIOUSLY:
@@ -183,20 +183,20 @@ polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT)
183 case AVFS_BTC_BOOT: /* Cold Boot State - Post SMU Start */ 183 case AVFS_BTC_BOOT: /* Cold Boot State - Post SMU Start */
184 184
185 smu_data->avfs.avfs_btc_status = AVFS_BTC_DPMTABLESETUP_FAILED; 185 smu_data->avfs.avfs_btc_status = AVFS_BTC_DPMTABLESETUP_FAILED;
186 PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(smumgr), 186 PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(hwmgr),
187 "[AVFS][Polaris10_AVFSEventMgr] Could not Copy Graphics Level table over to SMU", 187 "[AVFS][Polaris10_AVFSEventMgr] Could not Copy Graphics Level table over to SMU",
188 return -EINVAL); 188 return -EINVAL);
189 189
190 if (smu_data->avfs.avfs_btc_param > 1) { 190 if (smu_data->avfs.avfs_btc_param > 1) {
191 pr_info("[AVFS][Polaris10_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting."); 191 pr_info("[AVFS][Polaris10_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting.");
192 smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL; 192 smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL;
193 PP_ASSERT_WITH_CODE(0 == polaris10_setup_pwr_virus(smumgr), 193 PP_ASSERT_WITH_CODE(0 == polaris10_setup_pwr_virus(hwmgr),
194 "[AVFS][Polaris10_AVFSEventMgr] Could not setup Pwr Virus for AVFS ", 194 "[AVFS][Polaris10_AVFSEventMgr] Could not setup Pwr Virus for AVFS ",
195 return -EINVAL); 195 return -EINVAL);
196 } 196 }
197 197
198 smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED; 198 smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED;
199 PP_ASSERT_WITH_CODE(0 == polaris10_perform_btc(smumgr), 199 PP_ASSERT_WITH_CODE(0 == polaris10_perform_btc(hwmgr),
200 "[AVFS][Polaris10_AVFSEventMgr] Failure at SmuPolaris10_PerformBTC. AVFS Disabled", 200 "[AVFS][Polaris10_AVFSEventMgr] Failure at SmuPolaris10_PerformBTC. AVFS Disabled",
201 return -EINVAL); 201 return -EINVAL);
202 smu_data->avfs.avfs_btc_status = AVFS_BTC_ENABLEAVFS; 202 smu_data->avfs.avfs_btc_status = AVFS_BTC_ENABLEAVFS;
@@ -215,7 +215,7 @@ polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT)
215 return 0; 215 return 0;
216} 216}
217 217
218static int polaris10_start_smu_in_protection_mode(struct pp_smumgr *smumgr) 218static int polaris10_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
219{ 219{
220 int result = 0; 220 int result = 0;
221 221
@@ -223,138 +223,138 @@ static int polaris10_start_smu_in_protection_mode(struct pp_smumgr *smumgr)
223 /* SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */ 223 /* SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */
224 224
225 /* Assert reset */ 225 /* Assert reset */
226 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, 226 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
227 SMC_SYSCON_RESET_CNTL, rst_reg, 1); 227 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
228 228
229 result = smu7_upload_smu_firmware_image(smumgr); 229 result = smu7_upload_smu_firmware_image(hwmgr);
230 if (result != 0) 230 if (result != 0)
231 return result; 231 return result;
232 232
233 /* Clear status */ 233 /* Clear status */
234 cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0); 234 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0);
235 235
236 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, 236 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
237 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); 237 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
238 238
239 /* De-assert reset */ 239 /* De-assert reset */
240 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, 240 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
241 SMC_SYSCON_RESET_CNTL, rst_reg, 0); 241 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
242 242
243 243
244 SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1); 244 SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
245 245
246 246
247 /* Call Test SMU message with 0x20000 offset to trigger SMU start */ 247 /* Call Test SMU message with 0x20000 offset to trigger SMU start */
248 smu7_send_msg_to_smc_offset(smumgr); 248 smu7_send_msg_to_smc_offset(hwmgr);
249 249
250 /* Wait done bit to be set */ 250 /* Wait done bit to be set */
251 /* Check pass/failed indicator */ 251 /* Check pass/failed indicator */
252 252
253 SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, SMU_STATUS, SMU_DONE, 0); 253 SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, SMU_STATUS, SMU_DONE, 0);
254 254
255 if (1 != SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, 255 if (1 != SMUM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
256 SMU_STATUS, SMU_PASS)) 256 SMU_STATUS, SMU_PASS))
257 PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1); 257 PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1);
258 258
259 cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0); 259 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0);
260 260
261 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, 261 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
262 SMC_SYSCON_RESET_CNTL, rst_reg, 1); 262 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
263 263
264 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, 264 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
265 SMC_SYSCON_RESET_CNTL, rst_reg, 0); 265 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
266 266
267 /* Wait for firmware to initialize */ 267 /* Wait for firmware to initialize */
268 SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1); 268 SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
269 269
270 return result; 270 return result;
271} 271}
272 272
273static int polaris10_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr) 273static int polaris10_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
274{ 274{
275 int result = 0; 275 int result = 0;
276 276
277 /* wait for smc boot up */ 277 /* wait for smc boot up */
278 SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0); 278 SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0);
279 279
280 /* Clear firmware interrupt enable flag */ 280 /* Clear firmware interrupt enable flag */
281 /* SMUM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */ 281 /* SMUM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */
282 cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, 282 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
283 ixFIRMWARE_FLAGS, 0); 283 ixFIRMWARE_FLAGS, 0);
284 284
285 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, 285 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
286 SMC_SYSCON_RESET_CNTL, 286 SMC_SYSCON_RESET_CNTL,
287 rst_reg, 1); 287 rst_reg, 1);
288 288
289 result = smu7_upload_smu_firmware_image(smumgr); 289 result = smu7_upload_smu_firmware_image(hwmgr);
290 if (result != 0) 290 if (result != 0)
291 return result; 291 return result;
292 292
293 /* Set smc instruct start point at 0x0 */ 293 /* Set smc instruct start point at 0x0 */
294 smu7_program_jump_on_start(smumgr); 294 smu7_program_jump_on_start(hwmgr);
295 295
296 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, 296 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
297 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); 297 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
298 298
299 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, 299 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
300 SMC_SYSCON_RESET_CNTL, rst_reg, 0); 300 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
301 301
302 /* Wait for firmware to initialize */ 302 /* Wait for firmware to initialize */
303 303
304 SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, 304 SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
305 FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1); 305 FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
306 306
307 return result; 307 return result;
308} 308}
309 309
310static int polaris10_start_smu(struct pp_smumgr *smumgr) 310static int polaris10_start_smu(struct pp_hwmgr *hwmgr)
311{ 311{
312 int result = 0; 312 int result = 0;
313 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); 313 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
314 bool SMU_VFT_INTACT; 314 bool SMU_VFT_INTACT;
315 315
316 /* Only start SMC if SMC RAM is not running */ 316 /* Only start SMC if SMC RAM is not running */
317 if (!smu7_is_smc_ram_running(smumgr)) { 317 if (!smu7_is_smc_ram_running(hwmgr)) {
318 SMU_VFT_INTACT = false; 318 SMU_VFT_INTACT = false;
319 smu_data->protected_mode = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE)); 319 smu_data->protected_mode = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE));
320 smu_data->smu7_data.security_hard_key = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL)); 320 smu_data->smu7_data.security_hard_key = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
321 321
322 /* Check if SMU is running in protected mode */ 322 /* Check if SMU is running in protected mode */
323 if (smu_data->protected_mode == 0) { 323 if (smu_data->protected_mode == 0) {
324 result = polaris10_start_smu_in_non_protection_mode(smumgr); 324 result = polaris10_start_smu_in_non_protection_mode(hwmgr);
325 } else { 325 } else {
326 result = polaris10_start_smu_in_protection_mode(smumgr); 326 result = polaris10_start_smu_in_protection_mode(hwmgr);
327 327
328 /* If failed, try with different security Key. */ 328 /* If failed, try with different security Key. */
329 if (result != 0) { 329 if (result != 0) {
330 smu_data->smu7_data.security_hard_key ^= 1; 330 smu_data->smu7_data.security_hard_key ^= 1;
331 cgs_rel_firmware(smumgr->device, CGS_UCODE_ID_SMU); 331 cgs_rel_firmware(hwmgr->device, CGS_UCODE_ID_SMU);
332 result = polaris10_start_smu_in_protection_mode(smumgr); 332 result = polaris10_start_smu_in_protection_mode(hwmgr);
333 } 333 }
334 } 334 }
335 335
336 if (result != 0) 336 if (result != 0)
337 PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result); 337 PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result);
338 338
339 polaris10_avfs_event_mgr(smumgr, true); 339 polaris10_avfs_event_mgr(hwmgr, true);
340 } else 340 } else
341 SMU_VFT_INTACT = true; /*Driver went offline but SMU was still alive and contains the VFT table */ 341 SMU_VFT_INTACT = true; /*Driver went offline but SMU was still alive and contains the VFT table */
342 342
343 polaris10_avfs_event_mgr(smumgr, SMU_VFT_INTACT); 343 polaris10_avfs_event_mgr(hwmgr, SMU_VFT_INTACT);
344 /* Setup SoftRegsStart here for register lookup in case DummyBackEnd is used and ProcessFirmwareHeader is not executed */ 344 /* Setup SoftRegsStart here for register lookup in case DummyBackEnd is used and ProcessFirmwareHeader is not executed */
345 smu7_read_smc_sram_dword(smumgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters), 345 smu7_read_smc_sram_dword(hwmgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters),
346 &(smu_data->smu7_data.soft_regs_start), 0x40000); 346 &(smu_data->smu7_data.soft_regs_start), 0x40000);
347 347
348 result = smu7_request_smu_load_fw(smumgr); 348 result = smu7_request_smu_load_fw(hwmgr);
349 349
350 return result; 350 return result;
351} 351}
352 352
353static bool polaris10_is_hw_avfs_present(struct pp_smumgr *smumgr) 353static bool polaris10_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
354{ 354{
355 uint32_t efuse; 355 uint32_t efuse;
356 356
357 efuse = cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMU_EFUSE_0 + (49*4)); 357 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_EFUSE_0 + (49*4));
358 efuse &= 0x00000001; 358 efuse &= 0x00000001;
359 if (efuse) 359 if (efuse)
360 return true; 360 return true;
@@ -362,7 +362,7 @@ static bool polaris10_is_hw_avfs_present(struct pp_smumgr *smumgr)
362 return false; 362 return false;
363} 363}
364 364
365static int polaris10_smu_init(struct pp_smumgr *smumgr) 365static int polaris10_smu_init(struct pp_hwmgr *hwmgr)
366{ 366{
367 struct polaris10_smumgr *smu_data; 367 struct polaris10_smumgr *smu_data;
368 int i; 368 int i;
@@ -371,9 +371,9 @@ static int polaris10_smu_init(struct pp_smumgr *smumgr)
371 if (smu_data == NULL) 371 if (smu_data == NULL)
372 return -ENOMEM; 372 return -ENOMEM;
373 373
374 smumgr->backend = smu_data; 374 hwmgr->smumgr->backend = smu_data;
375 375
376 if (smu7_init(smumgr)) 376 if (smu7_init(hwmgr))
377 return -EINVAL; 377 return -EINVAL;
378 378
379 for (i = 0; i < SMU74_MAX_LEVELS_GRAPHICS; i++) 379 for (i = 0; i < SMU74_MAX_LEVELS_GRAPHICS; i++)
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
index ce0a30388ea1..54d3052dd157 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
@@ -48,20 +48,20 @@
48#define smnMP1_FIRMWARE_FLAGS 0x3010028 48#define smnMP1_FIRMWARE_FLAGS 0x3010028
49 49
50 50
51bool rv_is_smc_ram_running(struct pp_smumgr *smumgr) 51bool rv_is_smc_ram_running(struct pp_hwmgr *hwmgr)
52{ 52{
53 uint32_t mp1_fw_flags, reg; 53 uint32_t mp1_fw_flags, reg;
54 54
55 reg = soc15_get_register_offset(NBIF_HWID, 0, 55 reg = soc15_get_register_offset(NBIF_HWID, 0,
56 mmPCIE_INDEX2_BASE_IDX, mmPCIE_INDEX2); 56 mmPCIE_INDEX2_BASE_IDX, mmPCIE_INDEX2);
57 57
58 cgs_write_register(smumgr->device, reg, 58 cgs_write_register(hwmgr->device, reg,
59 (MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff))); 59 (MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff)));
60 60
61 reg = soc15_get_register_offset(NBIF_HWID, 0, 61 reg = soc15_get_register_offset(NBIF_HWID, 0,
62 mmPCIE_DATA2_BASE_IDX, mmPCIE_DATA2); 62 mmPCIE_DATA2_BASE_IDX, mmPCIE_DATA2);
63 63
64 mp1_fw_flags = cgs_read_register(smumgr->device, reg); 64 mp1_fw_flags = cgs_read_register(hwmgr->device, reg);
65 65
66 if (mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) 66 if (mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK)
67 return true; 67 return true;
@@ -69,97 +69,97 @@ bool rv_is_smc_ram_running(struct pp_smumgr *smumgr)
69 return false; 69 return false;
70} 70}
71 71
72static uint32_t rv_wait_for_response(struct pp_smumgr *smumgr) 72static uint32_t rv_wait_for_response(struct pp_hwmgr *hwmgr)
73{ 73{
74 uint32_t reg; 74 uint32_t reg;
75 75
76 if (!rv_is_smc_ram_running(smumgr)) 76 if (!rv_is_smc_ram_running(hwmgr))
77 return -EINVAL; 77 return -EINVAL;
78 78
79 reg = soc15_get_register_offset(MP1_HWID, 0, 79 reg = soc15_get_register_offset(MP1_HWID, 0,
80 mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90); 80 mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
81 81
82 smum_wait_for_register_unequal(smumgr, reg, 82 smum_wait_for_register_unequal(hwmgr, reg,
83 0, MP1_C2PMSG_90__CONTENT_MASK); 83 0, MP1_C2PMSG_90__CONTENT_MASK);
84 84
85 return cgs_read_register(smumgr->device, reg); 85 return cgs_read_register(hwmgr->device, reg);
86} 86}
87 87
88int rv_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, 88int rv_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr,
89 uint16_t msg) 89 uint16_t msg)
90{ 90{
91 uint32_t reg; 91 uint32_t reg;
92 92
93 if (!rv_is_smc_ram_running(smumgr)) 93 if (!rv_is_smc_ram_running(hwmgr))
94 return -EINVAL; 94 return -EINVAL;
95 95
96 reg = soc15_get_register_offset(MP1_HWID, 0, 96 reg = soc15_get_register_offset(MP1_HWID, 0,
97 mmMP1_SMN_C2PMSG_66_BASE_IDX, mmMP1_SMN_C2PMSG_66); 97 mmMP1_SMN_C2PMSG_66_BASE_IDX, mmMP1_SMN_C2PMSG_66);
98 cgs_write_register(smumgr->device, reg, msg); 98 cgs_write_register(hwmgr->device, reg, msg);
99 99
100 return 0; 100 return 0;
101} 101}
102 102
103int rv_read_arg_from_smc(struct pp_smumgr *smumgr, uint32_t *arg) 103int rv_read_arg_from_smc(struct pp_hwmgr *hwmgr, uint32_t *arg)
104{ 104{
105 uint32_t reg; 105 uint32_t reg;
106 106
107 reg = soc15_get_register_offset(MP1_HWID, 0, 107 reg = soc15_get_register_offset(MP1_HWID, 0,
108 mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82); 108 mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
109 109
110 *arg = cgs_read_register(smumgr->device, reg); 110 *arg = cgs_read_register(hwmgr->device, reg);
111 111
112 return 0; 112 return 0;
113} 113}
114 114
115int rv_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg) 115int rv_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
116{ 116{
117 uint32_t reg; 117 uint32_t reg;
118 118
119 rv_wait_for_response(smumgr); 119 rv_wait_for_response(hwmgr);
120 120
121 reg = soc15_get_register_offset(MP1_HWID, 0, 121 reg = soc15_get_register_offset(MP1_HWID, 0,
122 mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90); 122 mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
123 cgs_write_register(smumgr->device, reg, 0); 123 cgs_write_register(hwmgr->device, reg, 0);
124 124
125 rv_send_msg_to_smc_without_waiting(smumgr, msg); 125 rv_send_msg_to_smc_without_waiting(hwmgr, msg);
126 126
127 if (rv_wait_for_response(smumgr) == 0) 127 if (rv_wait_for_response(hwmgr) == 0)
128 printk("Failed to send Message %x.\n", msg); 128 printk("Failed to send Message %x.\n", msg);
129 129
130 return 0; 130 return 0;
131} 131}
132 132
133 133
134int rv_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, 134int rv_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
135 uint16_t msg, uint32_t parameter) 135 uint16_t msg, uint32_t parameter)
136{ 136{
137 uint32_t reg; 137 uint32_t reg;
138 138
139 rv_wait_for_response(smumgr); 139 rv_wait_for_response(hwmgr);
140 140
141 reg = soc15_get_register_offset(MP1_HWID, 0, 141 reg = soc15_get_register_offset(MP1_HWID, 0,
142 mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90); 142 mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
143 cgs_write_register(smumgr->device, reg, 0); 143 cgs_write_register(hwmgr->device, reg, 0);
144 144
145 reg = soc15_get_register_offset(MP1_HWID, 0, 145 reg = soc15_get_register_offset(MP1_HWID, 0,
146 mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82); 146 mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
147 cgs_write_register(smumgr->device, reg, parameter); 147 cgs_write_register(hwmgr->device, reg, parameter);
148 148
149 rv_send_msg_to_smc_without_waiting(smumgr, msg); 149 rv_send_msg_to_smc_without_waiting(hwmgr, msg);
150 150
151 151
152 if (rv_wait_for_response(smumgr) == 0) 152 if (rv_wait_for_response(hwmgr) == 0)
153 printk("Failed to send Message %x.\n", msg); 153 printk("Failed to send Message %x.\n", msg);
154 154
155 return 0; 155 return 0;
156} 156}
157 157
158int rv_copy_table_from_smc(struct pp_smumgr *smumgr, 158int rv_copy_table_from_smc(struct pp_hwmgr *hwmgr,
159 uint8_t *table, int16_t table_id) 159 uint8_t *table, int16_t table_id)
160{ 160{
161 struct rv_smumgr *priv = 161 struct rv_smumgr *priv =
162 (struct rv_smumgr *)(smumgr->backend); 162 (struct rv_smumgr *)(hwmgr->smumgr->backend);
163 163
164 PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, 164 PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
165 "Invalid SMU Table ID!", return -EINVAL;); 165 "Invalid SMU Table ID!", return -EINVAL;);
@@ -167,16 +167,16 @@ int rv_copy_table_from_smc(struct pp_smumgr *smumgr,
167 "Invalid SMU Table version!", return -EINVAL;); 167 "Invalid SMU Table version!", return -EINVAL;);
168 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, 168 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
169 "Invalid SMU Table Length!", return -EINVAL;); 169 "Invalid SMU Table Length!", return -EINVAL;);
170 PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr, 170 PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,
171 PPSMC_MSG_SetDriverDramAddrHigh, 171 PPSMC_MSG_SetDriverDramAddrHigh,
172 priv->smu_tables.entry[table_id].table_addr_high) == 0, 172 priv->smu_tables.entry[table_id].table_addr_high) == 0,
173 "[CopyTableFromSMC] Attempt to Set Dram Addr High Failed!", return -EINVAL;); 173 "[CopyTableFromSMC] Attempt to Set Dram Addr High Failed!", return -EINVAL;);
174 PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr, 174 PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,
175 PPSMC_MSG_SetDriverDramAddrLow, 175 PPSMC_MSG_SetDriverDramAddrLow,
176 priv->smu_tables.entry[table_id].table_addr_low) == 0, 176 priv->smu_tables.entry[table_id].table_addr_low) == 0,
177 "[CopyTableFromSMC] Attempt to Set Dram Addr Low Failed!", 177 "[CopyTableFromSMC] Attempt to Set Dram Addr Low Failed!",
178 return -EINVAL;); 178 return -EINVAL;);
179 PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr, 179 PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,
180 PPSMC_MSG_TransferTableSmu2Dram, 180 PPSMC_MSG_TransferTableSmu2Dram,
181 priv->smu_tables.entry[table_id].table_id) == 0, 181 priv->smu_tables.entry[table_id].table_id) == 0,
182 "[CopyTableFromSMC] Attempt to Transfer Table From SMU Failed!", 182 "[CopyTableFromSMC] Attempt to Transfer Table From SMU Failed!",
@@ -188,11 +188,11 @@ int rv_copy_table_from_smc(struct pp_smumgr *smumgr,
188 return 0; 188 return 0;
189} 189}
190 190
191int rv_copy_table_to_smc(struct pp_smumgr *smumgr, 191int rv_copy_table_to_smc(struct pp_hwmgr *hwmgr,
192 uint8_t *table, int16_t table_id) 192 uint8_t *table, int16_t table_id)
193{ 193{
194 struct rv_smumgr *priv = 194 struct rv_smumgr *priv =
195 (struct rv_smumgr *)(smumgr->backend); 195 (struct rv_smumgr *)(hwmgr->smumgr->backend);
196 196
197 PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, 197 PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
198 "Invalid SMU Table ID!", return -EINVAL;); 198 "Invalid SMU Table ID!", return -EINVAL;);
@@ -204,17 +204,17 @@ int rv_copy_table_to_smc(struct pp_smumgr *smumgr,
204 memcpy(priv->smu_tables.entry[table_id].table, table, 204 memcpy(priv->smu_tables.entry[table_id].table, table,
205 priv->smu_tables.entry[table_id].size); 205 priv->smu_tables.entry[table_id].size);
206 206
207 PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr, 207 PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,
208 PPSMC_MSG_SetDriverDramAddrHigh, 208 PPSMC_MSG_SetDriverDramAddrHigh,
209 priv->smu_tables.entry[table_id].table_addr_high) == 0, 209 priv->smu_tables.entry[table_id].table_addr_high) == 0,
210 "[CopyTableToSMC] Attempt to Set Dram Addr High Failed!", 210 "[CopyTableToSMC] Attempt to Set Dram Addr High Failed!",
211 return -EINVAL;); 211 return -EINVAL;);
212 PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr, 212 PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,
213 PPSMC_MSG_SetDriverDramAddrLow, 213 PPSMC_MSG_SetDriverDramAddrLow,
214 priv->smu_tables.entry[table_id].table_addr_low) == 0, 214 priv->smu_tables.entry[table_id].table_addr_low) == 0,
215 "[CopyTableToSMC] Attempt to Set Dram Addr Low Failed!", 215 "[CopyTableToSMC] Attempt to Set Dram Addr Low Failed!",
216 return -EINVAL;); 216 return -EINVAL;);
217 PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr, 217 PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,
218 PPSMC_MSG_TransferTableDram2Smu, 218 PPSMC_MSG_TransferTableDram2Smu,
219 priv->smu_tables.entry[table_id].table_id) == 0, 219 priv->smu_tables.entry[table_id].table_id) == 0,
220 "[CopyTableToSMC] Attempt to Transfer Table To SMU Failed!", 220 "[CopyTableToSMC] Attempt to Transfer Table To SMU Failed!",
@@ -223,15 +223,15 @@ int rv_copy_table_to_smc(struct pp_smumgr *smumgr,
223 return 0; 223 return 0;
224} 224}
225 225
226static int rv_verify_smc_interface(struct pp_smumgr *smumgr) 226static int rv_verify_smc_interface(struct pp_hwmgr *hwmgr)
227{ 227{
228 uint32_t smc_driver_if_version; 228 uint32_t smc_driver_if_version;
229 229
230 PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(smumgr, 230 PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(hwmgr,
231 PPSMC_MSG_GetDriverIfVersion), 231 PPSMC_MSG_GetDriverIfVersion),
232 "Attempt to get SMC IF Version Number Failed!", 232 "Attempt to get SMC IF Version Number Failed!",
233 return -EINVAL); 233 return -EINVAL);
234 PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(smumgr, 234 PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr,
235 &smc_driver_if_version), 235 &smc_driver_if_version),
236 "Attempt to read SMC IF Version Number Failed!", 236 "Attempt to read SMC IF Version Number Failed!",
237 return -EINVAL); 237 return -EINVAL);
@@ -243,9 +243,9 @@ static int rv_verify_smc_interface(struct pp_smumgr *smumgr)
243} 243}
244 244
245/* sdma is disabled by default in vbios, need to re-enable in driver */ 245/* sdma is disabled by default in vbios, need to re-enable in driver */
246static int rv_smc_enable_sdma(struct pp_smumgr *smumgr) 246static int rv_smc_enable_sdma(struct pp_hwmgr *hwmgr)
247{ 247{
248 PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(smumgr, 248 PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(hwmgr,
249 PPSMC_MSG_PowerUpSdma), 249 PPSMC_MSG_PowerUpSdma),
250 "Attempt to power up sdma Failed!", 250 "Attempt to power up sdma Failed!",
251 return -EINVAL); 251 return -EINVAL);
@@ -253,9 +253,9 @@ static int rv_smc_enable_sdma(struct pp_smumgr *smumgr)
253 return 0; 253 return 0;
254} 254}
255 255
256static int rv_smc_disable_sdma(struct pp_smumgr *smumgr) 256static int rv_smc_disable_sdma(struct pp_hwmgr *hwmgr)
257{ 257{
258 PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(smumgr, 258 PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(hwmgr,
259 PPSMC_MSG_PowerDownSdma), 259 PPSMC_MSG_PowerDownSdma),
260 "Attempt to power down sdma Failed!", 260 "Attempt to power down sdma Failed!",
261 return -EINVAL); 261 return -EINVAL);
@@ -264,9 +264,9 @@ static int rv_smc_disable_sdma(struct pp_smumgr *smumgr)
264} 264}
265 265
266/* vcn is disabled by default in vbios, need to re-enable in driver */ 266/* vcn is disabled by default in vbios, need to re-enable in driver */
267static int rv_smc_enable_vcn(struct pp_smumgr *smumgr) 267static int rv_smc_enable_vcn(struct pp_hwmgr *hwmgr)
268{ 268{
269 PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc_with_parameter(smumgr, 269 PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc_with_parameter(hwmgr,
270 PPSMC_MSG_PowerUpVcn, 0), 270 PPSMC_MSG_PowerUpVcn, 0),
271 "Attempt to power up vcn Failed!", 271 "Attempt to power up vcn Failed!",
272 return -EINVAL); 272 return -EINVAL);
@@ -274,9 +274,9 @@ static int rv_smc_enable_vcn(struct pp_smumgr *smumgr)
274 return 0; 274 return 0;
275} 275}
276 276
277static int rv_smc_disable_vcn(struct pp_smumgr *smumgr) 277static int rv_smc_disable_vcn(struct pp_hwmgr *hwmgr)
278{ 278{
279 PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc_with_parameter(smumgr, 279 PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc_with_parameter(hwmgr,
280 PPSMC_MSG_PowerDownVcn, 0), 280 PPSMC_MSG_PowerDownVcn, 0),
281 "Attempt to power down vcn Failed!", 281 "Attempt to power down vcn Failed!",
282 return -EINVAL); 282 return -EINVAL);
@@ -284,38 +284,38 @@ static int rv_smc_disable_vcn(struct pp_smumgr *smumgr)
284 return 0; 284 return 0;
285} 285}
286 286
287static int rv_smu_fini(struct pp_smumgr *smumgr) 287static int rv_smu_fini(struct pp_hwmgr *hwmgr)
288{ 288{
289 struct rv_smumgr *priv = 289 struct rv_smumgr *priv =
290 (struct rv_smumgr *)(smumgr->backend); 290 (struct rv_smumgr *)(hwmgr->smumgr->backend);
291 291
292 if (priv) { 292 if (priv) {
293 rv_smc_disable_sdma(smumgr); 293 rv_smc_disable_sdma(hwmgr);
294 rv_smc_disable_vcn(smumgr); 294 rv_smc_disable_vcn(hwmgr);
295 cgs_free_gpu_mem(smumgr->device, 295 cgs_free_gpu_mem(hwmgr->device,
296 priv->smu_tables.entry[WMTABLE].handle); 296 priv->smu_tables.entry[WMTABLE].handle);
297 cgs_free_gpu_mem(smumgr->device, 297 cgs_free_gpu_mem(hwmgr->device,
298 priv->smu_tables.entry[CLOCKTABLE].handle); 298 priv->smu_tables.entry[CLOCKTABLE].handle);
299 kfree(smumgr->backend); 299 kfree(hwmgr->smumgr->backend);
300 smumgr->backend = NULL; 300 hwmgr->smumgr->backend = NULL;
301 } 301 }
302 302
303 return 0; 303 return 0;
304} 304}
305 305
306static int rv_start_smu(struct pp_smumgr *smumgr) 306static int rv_start_smu(struct pp_hwmgr *hwmgr)
307{ 307{
308 if (rv_verify_smc_interface(smumgr)) 308 if (rv_verify_smc_interface(hwmgr))
309 return -EINVAL; 309 return -EINVAL;
310 if (rv_smc_enable_sdma(smumgr)) 310 if (rv_smc_enable_sdma(hwmgr))
311 return -EINVAL; 311 return -EINVAL;
312 if (rv_smc_enable_vcn(smumgr)) 312 if (rv_smc_enable_vcn(hwmgr))
313 return -EINVAL; 313 return -EINVAL;
314 314
315 return 0; 315 return 0;
316} 316}
317 317
318static int rv_smu_init(struct pp_smumgr *smumgr) 318static int rv_smu_init(struct pp_hwmgr *hwmgr)
319{ 319{
320 struct rv_smumgr *priv; 320 struct rv_smumgr *priv;
321 uint64_t mc_addr; 321 uint64_t mc_addr;
@@ -327,10 +327,10 @@ static int rv_smu_init(struct pp_smumgr *smumgr)
327 if (!priv) 327 if (!priv)
328 return -ENOMEM; 328 return -ENOMEM;
329 329
330 smumgr->backend = priv; 330 hwmgr->smumgr->backend = priv;
331 331
332 /* allocate space for watermarks table */ 332 /* allocate space for watermarks table */
333 smu_allocate_memory(smumgr->device, 333 smu_allocate_memory(hwmgr->device,
334 sizeof(Watermarks_t), 334 sizeof(Watermarks_t),
335 CGS_GPU_MEM_TYPE__GART_CACHEABLE, 335 CGS_GPU_MEM_TYPE__GART_CACHEABLE,
336 PAGE_SIZE, 336 PAGE_SIZE,
@@ -340,8 +340,8 @@ static int rv_smu_init(struct pp_smumgr *smumgr)
340 340
341 PP_ASSERT_WITH_CODE(kaddr, 341 PP_ASSERT_WITH_CODE(kaddr,
342 "[rv_smu_init] Out of memory for wmtable.", 342 "[rv_smu_init] Out of memory for wmtable.",
343 kfree(smumgr->backend); 343 kfree(hwmgr->smumgr->backend);
344 smumgr->backend = NULL; 344 hwmgr->smumgr->backend = NULL;
345 return -EINVAL); 345 return -EINVAL);
346 346
347 priv->smu_tables.entry[WMTABLE].version = 0x01; 347 priv->smu_tables.entry[WMTABLE].version = 0x01;
@@ -355,7 +355,7 @@ static int rv_smu_init(struct pp_smumgr *smumgr)
355 priv->smu_tables.entry[WMTABLE].handle = handle; 355 priv->smu_tables.entry[WMTABLE].handle = handle;
356 356
357 /* allocate space for watermarks table */ 357 /* allocate space for watermarks table */
358 smu_allocate_memory(smumgr->device, 358 smu_allocate_memory(hwmgr->device,
359 sizeof(DpmClocks_t), 359 sizeof(DpmClocks_t),
360 CGS_GPU_MEM_TYPE__GART_CACHEABLE, 360 CGS_GPU_MEM_TYPE__GART_CACHEABLE,
361 PAGE_SIZE, 361 PAGE_SIZE,
@@ -365,10 +365,10 @@ static int rv_smu_init(struct pp_smumgr *smumgr)
365 365
366 PP_ASSERT_WITH_CODE(kaddr, 366 PP_ASSERT_WITH_CODE(kaddr,
367 "[rv_smu_init] Out of memory for CLOCKTABLE.", 367 "[rv_smu_init] Out of memory for CLOCKTABLE.",
368 cgs_free_gpu_mem(smumgr->device, 368 cgs_free_gpu_mem(hwmgr->device,
369 (cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle); 369 (cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle);
370 kfree(smumgr->backend); 370 kfree(hwmgr->smumgr->backend);
371 smumgr->backend = NULL; 371 hwmgr->smumgr->backend = NULL;
372 return -EINVAL); 372 return -EINVAL);
373 373
374 priv->smu_tables.entry[CLOCKTABLE].version = 0x01; 374 priv->smu_tables.entry[CLOCKTABLE].version = 0x01;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h
index 262c8ded87c0..58888400f1b8 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h
@@ -51,11 +51,11 @@ struct rv_smumgr {
51 struct smu_table_array smu_tables; 51 struct smu_table_array smu_tables;
52}; 52};
53 53
54int rv_read_arg_from_smc(struct pp_smumgr *smumgr, uint32_t *arg); 54int rv_read_arg_from_smc(struct pp_hwmgr *hwmgr, uint32_t *arg);
55bool rv_is_smc_ram_running(struct pp_smumgr *smumgr); 55bool rv_is_smc_ram_running(struct pp_hwmgr *hwmgr);
56int rv_copy_table_from_smc(struct pp_smumgr *smumgr, 56int rv_copy_table_from_smc(struct pp_hwmgr *hwmgr,
57 uint8_t *table, int16_t table_id); 57 uint8_t *table, int16_t table_id);
58int rv_copy_table_to_smc(struct pp_smumgr *smumgr, 58int rv_copy_table_to_smc(struct pp_hwmgr *hwmgr,
59 uint8_t *table, int16_t table_id); 59 uint8_t *table, int16_t table_id);
60 60
61 61
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
index f128b03f2327..cd283e5af68c 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
@@ -34,18 +34,18 @@
34 34
35#define SMU7_SMC_SIZE 0x20000 35#define SMU7_SMC_SIZE 0x20000
36 36
37static int smu7_set_smc_sram_address(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t limit) 37static int smu7_set_smc_sram_address(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t limit)
38{ 38{
39 PP_ASSERT_WITH_CODE((0 == (3 & smc_addr)), "SMC address must be 4 byte aligned.", return -EINVAL); 39 PP_ASSERT_WITH_CODE((0 == (3 & smc_addr)), "SMC address must be 4 byte aligned.", return -EINVAL);
40 PP_ASSERT_WITH_CODE((limit > (smc_addr + 3)), "SMC addr is beyond the SMC RAM area.", return -EINVAL); 40 PP_ASSERT_WITH_CODE((limit > (smc_addr + 3)), "SMC addr is beyond the SMC RAM area.", return -EINVAL);
41 41
42 cgs_write_register(smumgr->device, mmSMC_IND_INDEX_11, smc_addr); 42 cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_11, smc_addr);
43 SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0); /* on ci, SMC_IND_ACCESS_CNTL is different */ 43 SMUM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0); /* on ci, SMC_IND_ACCESS_CNTL is different */
44 return 0; 44 return 0;
45} 45}
46 46
47 47
48int smu7_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, uint32_t *dest, uint32_t byte_count, uint32_t limit) 48int smu7_copy_bytes_from_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address, uint32_t *dest, uint32_t byte_count, uint32_t limit)
49{ 49{
50 uint32_t data; 50 uint32_t data;
51 uint32_t addr; 51 uint32_t addr;
@@ -59,7 +59,7 @@ int smu7_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_addres
59 addr = smc_start_address; 59 addr = smc_start_address;
60 60
61 while (byte_count >= 4) { 61 while (byte_count >= 4) {
62 smu7_read_smc_sram_dword(smumgr, addr, &data, limit); 62 smu7_read_smc_sram_dword(hwmgr, addr, &data, limit);
63 63
64 *dest = PP_SMC_TO_HOST_UL(data); 64 *dest = PP_SMC_TO_HOST_UL(data);
65 65
@@ -69,7 +69,7 @@ int smu7_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_addres
69 } 69 }
70 70
71 if (byte_count) { 71 if (byte_count) {
72 smu7_read_smc_sram_dword(smumgr, addr, &data, limit); 72 smu7_read_smc_sram_dword(hwmgr, addr, &data, limit);
73 *pdata = PP_SMC_TO_HOST_UL(data); 73 *pdata = PP_SMC_TO_HOST_UL(data);
74 /* Cast dest into byte type in dest_byte. This way, we don't overflow if the allocated memory is not 4-byte aligned. */ 74 /* Cast dest into byte type in dest_byte. This way, we don't overflow if the allocated memory is not 4-byte aligned. */
75 dest_byte = (uint8_t *)dest; 75 dest_byte = (uint8_t *)dest;
@@ -81,7 +81,7 @@ int smu7_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_addres
81} 81}
82 82
83 83
84int smu7_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, 84int smu7_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address,
85 const uint8_t *src, uint32_t byte_count, uint32_t limit) 85 const uint8_t *src, uint32_t byte_count, uint32_t limit)
86{ 86{
87 int result; 87 int result;
@@ -99,12 +99,12 @@ int smu7_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
99 /* Bytes are written into the SMC addres space with the MSB first. */ 99 /* Bytes are written into the SMC addres space with the MSB first. */
100 data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3]; 100 data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3];
101 101
102 result = smu7_set_smc_sram_address(smumgr, addr, limit); 102 result = smu7_set_smc_sram_address(hwmgr, addr, limit);
103 103
104 if (0 != result) 104 if (0 != result)
105 return result; 105 return result;
106 106
107 cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, data); 107 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, data);
108 108
109 src += 4; 109 src += 4;
110 byte_count -= 4; 110 byte_count -= 4;
@@ -115,13 +115,13 @@ int smu7_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
115 115
116 data = 0; 116 data = 0;
117 117
118 result = smu7_set_smc_sram_address(smumgr, addr, limit); 118 result = smu7_set_smc_sram_address(hwmgr, addr, limit);
119 119
120 if (0 != result) 120 if (0 != result)
121 return result; 121 return result;
122 122
123 123
124 original_data = cgs_read_register(smumgr->device, mmSMC_IND_DATA_11); 124 original_data = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_11);
125 125
126 extra_shift = 8 * (4 - byte_count); 126 extra_shift = 8 * (4 - byte_count);
127 127
@@ -135,53 +135,53 @@ int smu7_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
135 135
136 data |= (original_data & ~((~0UL) << extra_shift)); 136 data |= (original_data & ~((~0UL) << extra_shift));
137 137
138 result = smu7_set_smc_sram_address(smumgr, addr, limit); 138 result = smu7_set_smc_sram_address(hwmgr, addr, limit);
139 139
140 if (0 != result) 140 if (0 != result)
141 return result; 141 return result;
142 142
143 cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, data); 143 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, data);
144 } 144 }
145 145
146 return 0; 146 return 0;
147} 147}
148 148
149 149
150int smu7_program_jump_on_start(struct pp_smumgr *smumgr) 150int smu7_program_jump_on_start(struct pp_hwmgr *hwmgr)
151{ 151{
152 static const unsigned char data[4] = { 0xE0, 0x00, 0x80, 0x40 }; 152 static const unsigned char data[4] = { 0xE0, 0x00, 0x80, 0x40 };
153 153
154 smu7_copy_bytes_to_smc(smumgr, 0x0, data, 4, sizeof(data)+1); 154 smu7_copy_bytes_to_smc(hwmgr, 0x0, data, 4, sizeof(data)+1);
155 155
156 return 0; 156 return 0;
157} 157}
158 158
159bool smu7_is_smc_ram_running(struct pp_smumgr *smumgr) 159bool smu7_is_smc_ram_running(struct pp_hwmgr *hwmgr)
160{ 160{
161 return ((0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) 161 return ((0 == SMUM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable))
162 && (0x20100 <= cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMC_PC_C))); 162 && (0x20100 <= cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMC_PC_C)));
163} 163}
164 164
165int smu7_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg) 165int smu7_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
166{ 166{
167 int ret; 167 int ret;
168 168
169 if (!smu7_is_smc_ram_running(smumgr)) 169 if (!smu7_is_smc_ram_running(hwmgr))
170 return -EINVAL; 170 return -EINVAL;
171 171
172 172
173 SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0); 173 SMUM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
174 174
175 ret = SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP); 175 ret = SMUM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP);
176 176
177 if (ret != 1) 177 if (ret != 1)
178 pr_info("\n failed to send pre message %x ret is %d \n", msg, ret); 178 pr_info("\n failed to send pre message %x ret is %d \n", msg, ret);
179 179
180 cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg); 180 cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, msg);
181 181
182 SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0); 182 SMUM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
183 183
184 ret = SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP); 184 ret = SMUM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP);
185 185
186 if (ret != 1) 186 if (ret != 1)
187 pr_info("\n failed to send message %x ret is %d \n", msg, ret); 187 pr_info("\n failed to send message %x ret is %d \n", msg, ret);
@@ -189,53 +189,53 @@ int smu7_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
189 return 0; 189 return 0;
190} 190}
191 191
192int smu7_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, uint16_t msg) 192int smu7_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr, uint16_t msg)
193{ 193{
194 cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg); 194 cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, msg);
195 195
196 return 0; 196 return 0;
197} 197}
198 198
199int smu7_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter) 199int smu7_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t parameter)
200{ 200{
201 if (!smu7_is_smc_ram_running(smumgr)) { 201 if (!smu7_is_smc_ram_running(hwmgr)) {
202 return -EINVAL; 202 return -EINVAL;
203 } 203 }
204 204
205 SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0); 205 SMUM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
206 206
207 cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter); 207 cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, parameter);
208 208
209 return smu7_send_msg_to_smc(smumgr, msg); 209 return smu7_send_msg_to_smc(hwmgr, msg);
210} 210}
211 211
212int smu7_send_msg_to_smc_with_parameter_without_waiting(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter) 212int smu7_send_msg_to_smc_with_parameter_without_waiting(struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t parameter)
213{ 213{
214 cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter); 214 cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, parameter);
215 215
216 return smu7_send_msg_to_smc_without_waiting(smumgr, msg); 216 return smu7_send_msg_to_smc_without_waiting(hwmgr, msg);
217} 217}
218 218
219int smu7_send_msg_to_smc_offset(struct pp_smumgr *smumgr) 219int smu7_send_msg_to_smc_offset(struct pp_hwmgr *hwmgr)
220{ 220{
221 cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, 0x20000); 221 cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, 0x20000);
222 222
223 cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test); 223 cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test);
224 224
225 SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0); 225 SMUM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
226 226
227 if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP)) 227 if (1 != SMUM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP))
228 pr_info("Failed to send Message.\n"); 228 pr_info("Failed to send Message.\n");
229 229
230 return 0; 230 return 0;
231} 231}
232 232
233int smu7_wait_for_smc_inactive(struct pp_smumgr *smumgr) 233int smu7_wait_for_smc_inactive(struct pp_hwmgr *hwmgr)
234{ 234{
235 if (!smu7_is_smc_ram_running(smumgr)) 235 if (!smu7_is_smc_ram_running(hwmgr))
236 return -EINVAL; 236 return -EINVAL;
237 237
238 SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, SMC_SYSCON_CLOCK_CNTL_0, cken, 0); 238 SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, SMC_SYSCON_CLOCK_CNTL_0, cken, 0);
239 return 0; 239 return 0;
240} 240}
241 241
@@ -289,29 +289,29 @@ enum cgs_ucode_id smu7_convert_fw_type_to_cgs(uint32_t fw_type)
289} 289}
290 290
291 291
292int smu7_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t *value, uint32_t limit) 292int smu7_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t *value, uint32_t limit)
293{ 293{
294 int result; 294 int result;
295 295
296 result = smu7_set_smc_sram_address(smumgr, smc_addr, limit); 296 result = smu7_set_smc_sram_address(hwmgr, smc_addr, limit);
297 297
298 if (result) 298 if (result)
299 return result; 299 return result;
300 300
301 *value = cgs_read_register(smumgr->device, mmSMC_IND_DATA_11); 301 *value = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_11);
302 return 0; 302 return 0;
303} 303}
304 304
305int smu7_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t value, uint32_t limit) 305int smu7_write_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t value, uint32_t limit)
306{ 306{
307 int result; 307 int result;
308 308
309 result = smu7_set_smc_sram_address(smumgr, smc_addr, limit); 309 result = smu7_set_smc_sram_address(hwmgr, smc_addr, limit);
310 310
311 if (result) 311 if (result)
312 return result; 312 return result;
313 313
314 cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, value); 314 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, value);
315 315
316 return 0; 316 return 0;
317} 317}
@@ -354,14 +354,14 @@ static uint32_t smu7_get_mask_for_firmware_type(uint32_t fw_type)
354 return result; 354 return result;
355} 355}
356 356
357static int smu7_populate_single_firmware_entry(struct pp_smumgr *smumgr, 357static int smu7_populate_single_firmware_entry(struct pp_hwmgr *hwmgr,
358 uint32_t fw_type, 358 uint32_t fw_type,
359 struct SMU_Entry *entry) 359 struct SMU_Entry *entry)
360{ 360{
361 int result = 0; 361 int result = 0;
362 struct cgs_firmware_info info = {0}; 362 struct cgs_firmware_info info = {0};
363 363
364 result = cgs_get_firmware_info(smumgr->device, 364 result = cgs_get_firmware_info(hwmgr->device,
365 smu7_convert_fw_type_to_cgs(fw_type), 365 smu7_convert_fw_type_to_cgs(fw_type),
366 &info); 366 &info);
367 367
@@ -374,7 +374,7 @@ static int smu7_populate_single_firmware_entry(struct pp_smumgr *smumgr,
374 entry->meta_data_addr_low = 0; 374 entry->meta_data_addr_low = 0;
375 375
376 /* digest need be excluded out */ 376 /* digest need be excluded out */
377 if (cgs_is_virtualization_enabled(smumgr->device)) 377 if (cgs_is_virtualization_enabled(hwmgr->device))
378 info.image_size -= 20; 378 info.image_size -= 20;
379 entry->data_size_byte = info.image_size; 379 entry->data_size_byte = info.image_size;
380 entry->num_register_entries = 0; 380 entry->num_register_entries = 0;
@@ -389,30 +389,30 @@ static int smu7_populate_single_firmware_entry(struct pp_smumgr *smumgr,
389 return 0; 389 return 0;
390} 390}
391 391
392int smu7_request_smu_load_fw(struct pp_smumgr *smumgr) 392int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
393{ 393{
394 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend); 394 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend);
395 uint32_t fw_to_load; 395 uint32_t fw_to_load;
396 int result = 0; 396 int result = 0;
397 struct SMU_DRAMData_TOC *toc; 397 struct SMU_DRAMData_TOC *toc;
398 398
399 if (!smumgr->reload_fw) { 399 if (!hwmgr->smumgr->reload_fw) {
400 pr_info("skip reloading...\n"); 400 pr_info("skip reloading...\n");
401 return 0; 401 return 0;
402 } 402 }
403 403
404 if (smu_data->soft_regs_start) 404 if (smu_data->soft_regs_start)
405 cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, 405 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
406 smu_data->soft_regs_start + smum_get_offsetof(smumgr, 406 smu_data->soft_regs_start + smum_get_offsetof(hwmgr,
407 SMU_SoftRegisters, UcodeLoadStatus), 407 SMU_SoftRegisters, UcodeLoadStatus),
408 0x0); 408 0x0);
409 409
410 if (smumgr->chip_id > CHIP_TOPAZ) { /* add support for Topaz */ 410 if (hwmgr->chip_id > CHIP_TOPAZ) { /* add support for Topaz */
411 if (!cgs_is_virtualization_enabled(smumgr->device)) { 411 if (!cgs_is_virtualization_enabled(hwmgr->device)) {
412 smu7_send_msg_to_smc_with_parameter(smumgr, 412 smu7_send_msg_to_smc_with_parameter(hwmgr,
413 PPSMC_MSG_SMU_DRAM_ADDR_HI, 413 PPSMC_MSG_SMU_DRAM_ADDR_HI,
414 smu_data->smu_buffer.mc_addr_high); 414 smu_data->smu_buffer.mc_addr_high);
415 smu7_send_msg_to_smc_with_parameter(smumgr, 415 smu7_send_msg_to_smc_with_parameter(hwmgr,
416 PPSMC_MSG_SMU_DRAM_ADDR_LO, 416 PPSMC_MSG_SMU_DRAM_ADDR_LO,
417 smu_data->smu_buffer.mc_addr_low); 417 smu_data->smu_buffer.mc_addr_low);
418 } 418 }
@@ -439,80 +439,80 @@ int smu7_request_smu_load_fw(struct pp_smumgr *smumgr)
439 toc->num_entries = 0; 439 toc->num_entries = 0;
440 toc->structure_version = 1; 440 toc->structure_version = 1;
441 441
442 PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr, 442 PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
443 UCODE_ID_RLC_G, &toc->entry[toc->num_entries++]), 443 UCODE_ID_RLC_G, &toc->entry[toc->num_entries++]),
444 "Failed to Get Firmware Entry.", return -EINVAL); 444 "Failed to Get Firmware Entry.", return -EINVAL);
445 PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr, 445 PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
446 UCODE_ID_CP_CE, &toc->entry[toc->num_entries++]), 446 UCODE_ID_CP_CE, &toc->entry[toc->num_entries++]),
447 "Failed to Get Firmware Entry.", return -EINVAL); 447 "Failed to Get Firmware Entry.", return -EINVAL);
448 PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr, 448 PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
449 UCODE_ID_CP_PFP, &toc->entry[toc->num_entries++]), 449 UCODE_ID_CP_PFP, &toc->entry[toc->num_entries++]),
450 "Failed to Get Firmware Entry.", return -EINVAL); 450 "Failed to Get Firmware Entry.", return -EINVAL);
451 PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr, 451 PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
452 UCODE_ID_CP_ME, &toc->entry[toc->num_entries++]), 452 UCODE_ID_CP_ME, &toc->entry[toc->num_entries++]),
453 "Failed to Get Firmware Entry.", return -EINVAL); 453 "Failed to Get Firmware Entry.", return -EINVAL);
454 PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr, 454 PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
455 UCODE_ID_CP_MEC, &toc->entry[toc->num_entries++]), 455 UCODE_ID_CP_MEC, &toc->entry[toc->num_entries++]),
456 "Failed to Get Firmware Entry.", return -EINVAL); 456 "Failed to Get Firmware Entry.", return -EINVAL);
457 PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr, 457 PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
458 UCODE_ID_CP_MEC_JT1, &toc->entry[toc->num_entries++]), 458 UCODE_ID_CP_MEC_JT1, &toc->entry[toc->num_entries++]),
459 "Failed to Get Firmware Entry.", return -EINVAL); 459 "Failed to Get Firmware Entry.", return -EINVAL);
460 PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr, 460 PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
461 UCODE_ID_CP_MEC_JT2, &toc->entry[toc->num_entries++]), 461 UCODE_ID_CP_MEC_JT2, &toc->entry[toc->num_entries++]),
462 "Failed to Get Firmware Entry.", return -EINVAL); 462 "Failed to Get Firmware Entry.", return -EINVAL);
463 PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr, 463 PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
464 UCODE_ID_SDMA0, &toc->entry[toc->num_entries++]), 464 UCODE_ID_SDMA0, &toc->entry[toc->num_entries++]),
465 "Failed to Get Firmware Entry.", return -EINVAL); 465 "Failed to Get Firmware Entry.", return -EINVAL);
466 PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr, 466 PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
467 UCODE_ID_SDMA1, &toc->entry[toc->num_entries++]), 467 UCODE_ID_SDMA1, &toc->entry[toc->num_entries++]),
468 "Failed to Get Firmware Entry.", return -EINVAL); 468 "Failed to Get Firmware Entry.", return -EINVAL);
469 if (cgs_is_virtualization_enabled(smumgr->device)) 469 if (cgs_is_virtualization_enabled(hwmgr->device))
470 PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr, 470 PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
471 UCODE_ID_MEC_STORAGE, &toc->entry[toc->num_entries++]), 471 UCODE_ID_MEC_STORAGE, &toc->entry[toc->num_entries++]),
472 "Failed to Get Firmware Entry.", return -EINVAL); 472 "Failed to Get Firmware Entry.", return -EINVAL);
473 473
474 smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, smu_data->header_buffer.mc_addr_high); 474 smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, smu_data->header_buffer.mc_addr_high);
475 smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, smu_data->header_buffer.mc_addr_low); 475 smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, smu_data->header_buffer.mc_addr_low);
476 476
477 if (smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_LoadUcodes, fw_to_load)) 477 if (smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_LoadUcodes, fw_to_load))
478 pr_err("Fail to Request SMU Load uCode"); 478 pr_err("Fail to Request SMU Load uCode");
479 479
480 return result; 480 return result;
481} 481}
482 482
483/* Check if the FW has been loaded, SMU will not return if loading has not finished. */ 483/* Check if the FW has been loaded, SMU will not return if loading has not finished. */
484int smu7_check_fw_load_finish(struct pp_smumgr *smumgr, uint32_t fw_type) 484int smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr, uint32_t fw_type)
485{ 485{
486 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend); 486 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend);
487 uint32_t fw_mask = smu7_get_mask_for_firmware_type(fw_type); 487 uint32_t fw_mask = smu7_get_mask_for_firmware_type(fw_type);
488 uint32_t ret; 488 uint32_t ret;
489 489
490 ret = smum_wait_on_indirect_register(smumgr, mmSMC_IND_INDEX_11, 490 ret = smum_wait_on_indirect_register(hwmgr, mmSMC_IND_INDEX_11,
491 smu_data->soft_regs_start + smum_get_offsetof(smumgr, 491 smu_data->soft_regs_start + smum_get_offsetof(hwmgr,
492 SMU_SoftRegisters, UcodeLoadStatus), 492 SMU_SoftRegisters, UcodeLoadStatus),
493 fw_mask, fw_mask); 493 fw_mask, fw_mask);
494 494
495 return ret; 495 return ret;
496} 496}
497 497
498int smu7_reload_firmware(struct pp_smumgr *smumgr) 498int smu7_reload_firmware(struct pp_hwmgr *hwmgr)
499{ 499{
500 return smumgr->smumgr_funcs->start_smu(smumgr); 500 return hwmgr->smumgr->smumgr_funcs->start_smu(hwmgr);
501} 501}
502 502
503static int smu7_upload_smc_firmware_data(struct pp_smumgr *smumgr, uint32_t length, uint32_t *src, uint32_t limit) 503static int smu7_upload_smc_firmware_data(struct pp_hwmgr *hwmgr, uint32_t length, uint32_t *src, uint32_t limit)
504{ 504{
505 uint32_t byte_count = length; 505 uint32_t byte_count = length;
506 506
507 PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -EINVAL); 507 PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -EINVAL);
508 508
509 cgs_write_register(smumgr->device, mmSMC_IND_INDEX_11, 0x20000); 509 cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_11, 0x20000);
510 SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 1); 510 SMUM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 1);
511 511
512 for (; byte_count >= 4; byte_count -= 4) 512 for (; byte_count >= 4; byte_count -= 4)
513 cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, *src++); 513 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, *src++);
514 514
515 SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0); 515 SMUM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0);
516 516
517 PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be dividable by 4.", return -EINVAL); 517 PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be dividable by 4.", return -EINVAL);
518 518
@@ -520,41 +520,41 @@ static int smu7_upload_smc_firmware_data(struct pp_smumgr *smumgr, uint32_t leng
520} 520}
521 521
522 522
523int smu7_upload_smu_firmware_image(struct pp_smumgr *smumgr) 523int smu7_upload_smu_firmware_image(struct pp_hwmgr *hwmgr)
524{ 524{
525 int result = 0; 525 int result = 0;
526 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend); 526 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend);
527 527
528 struct cgs_firmware_info info = {0}; 528 struct cgs_firmware_info info = {0};
529 529
530 if (smu_data->security_hard_key == 1) 530 if (smu_data->security_hard_key == 1)
531 cgs_get_firmware_info(smumgr->device, 531 cgs_get_firmware_info(hwmgr->device,
532 smu7_convert_fw_type_to_cgs(UCODE_ID_SMU), &info); 532 smu7_convert_fw_type_to_cgs(UCODE_ID_SMU), &info);
533 else 533 else
534 cgs_get_firmware_info(smumgr->device, 534 cgs_get_firmware_info(hwmgr->device,
535 smu7_convert_fw_type_to_cgs(UCODE_ID_SMU_SK), &info); 535 smu7_convert_fw_type_to_cgs(UCODE_ID_SMU_SK), &info);
536 536
537 smumgr->is_kicker = info.is_kicker; 537 hwmgr->smumgr->is_kicker = info.is_kicker;
538 538
539 result = smu7_upload_smc_firmware_data(smumgr, info.image_size, (uint32_t *)info.kptr, SMU7_SMC_SIZE); 539 result = smu7_upload_smc_firmware_data(hwmgr, info.image_size, (uint32_t *)info.kptr, SMU7_SMC_SIZE);
540 540
541 return result; 541 return result;
542} 542}
543 543
544int smu7_init(struct pp_smumgr *smumgr) 544int smu7_init(struct pp_hwmgr *hwmgr)
545{ 545{
546 struct smu7_smumgr *smu_data; 546 struct smu7_smumgr *smu_data;
547 uint8_t *internal_buf; 547 uint8_t *internal_buf;
548 uint64_t mc_addr = 0; 548 uint64_t mc_addr = 0;
549 549
550 /* Allocate memory for backend private data */ 550 /* Allocate memory for backend private data */
551 smu_data = (struct smu7_smumgr *)(smumgr->backend); 551 smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend);
552 smu_data->header_buffer.data_size = 552 smu_data->header_buffer.data_size =
553 ((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096; 553 ((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096;
554 554
555/* Allocate FW image data structure and header buffer and 555/* Allocate FW image data structure and header buffer and
556 * send the header buffer address to SMU */ 556 * send the header buffer address to SMU */
557 smu_allocate_memory(smumgr->device, 557 smu_allocate_memory(hwmgr->device,
558 smu_data->header_buffer.data_size, 558 smu_data->header_buffer.data_size,
559 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB, 559 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
560 PAGE_SIZE, 560 PAGE_SIZE,
@@ -568,16 +568,16 @@ int smu7_init(struct pp_smumgr *smumgr)
568 568
569 PP_ASSERT_WITH_CODE((NULL != smu_data->header), 569 PP_ASSERT_WITH_CODE((NULL != smu_data->header),
570 "Out of memory.", 570 "Out of memory.",
571 kfree(smumgr->backend); 571 kfree(hwmgr->smumgr->backend);
572 cgs_free_gpu_mem(smumgr->device, 572 cgs_free_gpu_mem(hwmgr->device,
573 (cgs_handle_t)smu_data->header_buffer.handle); 573 (cgs_handle_t)smu_data->header_buffer.handle);
574 return -EINVAL); 574 return -EINVAL);
575 575
576 if (cgs_is_virtualization_enabled(smumgr->device)) 576 if (cgs_is_virtualization_enabled(hwmgr->device))
577 return 0; 577 return 0;
578 578
579 smu_data->smu_buffer.data_size = 200*4096; 579 smu_data->smu_buffer.data_size = 200*4096;
580 smu_allocate_memory(smumgr->device, 580 smu_allocate_memory(hwmgr->device,
581 smu_data->smu_buffer.data_size, 581 smu_data->smu_buffer.data_size,
582 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB, 582 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
583 PAGE_SIZE, 583 PAGE_SIZE,
@@ -591,12 +591,12 @@ int smu7_init(struct pp_smumgr *smumgr)
591 591
592 PP_ASSERT_WITH_CODE((NULL != internal_buf), 592 PP_ASSERT_WITH_CODE((NULL != internal_buf),
593 "Out of memory.", 593 "Out of memory.",
594 kfree(smumgr->backend); 594 kfree(hwmgr->smumgr->backend);
595 cgs_free_gpu_mem(smumgr->device, 595 cgs_free_gpu_mem(hwmgr->device,
596 (cgs_handle_t)smu_data->smu_buffer.handle); 596 (cgs_handle_t)smu_data->smu_buffer.handle);
597 return -EINVAL); 597 return -EINVAL);
598 598
599 if (smum_is_hw_avfs_present(smumgr)) 599 if (smum_is_hw_avfs_present(hwmgr))
600 smu_data->avfs.avfs_btc_status = AVFS_BTC_BOOT; 600 smu_data->avfs.avfs_btc_status = AVFS_BTC_BOOT;
601 else 601 else
602 smu_data->avfs.avfs_btc_status = AVFS_BTC_NOTSUPPORTED; 602 smu_data->avfs.avfs_btc_status = AVFS_BTC_NOTSUPPORTED;
@@ -605,10 +605,10 @@ int smu7_init(struct pp_smumgr *smumgr)
605} 605}
606 606
607 607
608int smu7_smu_fini(struct pp_smumgr *smumgr) 608int smu7_smu_fini(struct pp_hwmgr *hwmgr)
609{ 609{
610 kfree(smumgr->backend); 610 kfree(hwmgr->smumgr->backend);
611 smumgr->backend = NULL; 611 hwmgr->smumgr->backend = NULL;
612 cgs_rel_firmware(smumgr->device, CGS_UCODE_ID_SMU); 612 cgs_rel_firmware(hwmgr->device, CGS_UCODE_ID_SMU);
613 return 0; 613 return 0;
614} 614}
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h
index ee5e32d2921e..0b63c5c1043c 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h
@@ -60,32 +60,32 @@ struct smu7_smumgr {
60}; 60};
61 61
62 62
63int smu7_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, 63int smu7_copy_bytes_from_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address,
64 uint32_t *dest, uint32_t byte_count, uint32_t limit); 64 uint32_t *dest, uint32_t byte_count, uint32_t limit);
65int smu7_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, 65int smu7_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address,
66 const uint8_t *src, uint32_t byte_count, uint32_t limit); 66 const uint8_t *src, uint32_t byte_count, uint32_t limit);
67int smu7_program_jump_on_start(struct pp_smumgr *smumgr); 67int smu7_program_jump_on_start(struct pp_hwmgr *hwmgr);
68bool smu7_is_smc_ram_running(struct pp_smumgr *smumgr); 68bool smu7_is_smc_ram_running(struct pp_hwmgr *hwmgr);
69int smu7_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg); 69int smu7_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg);
70int smu7_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, uint16_t msg); 70int smu7_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr, uint16_t msg);
71int smu7_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, uint16_t msg, 71int smu7_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, uint16_t msg,
72 uint32_t parameter); 72 uint32_t parameter);
73int smu7_send_msg_to_smc_with_parameter_without_waiting(struct pp_smumgr *smumgr, 73int smu7_send_msg_to_smc_with_parameter_without_waiting(struct pp_hwmgr *hwmgr,
74 uint16_t msg, uint32_t parameter); 74 uint16_t msg, uint32_t parameter);
75int smu7_send_msg_to_smc_offset(struct pp_smumgr *smumgr); 75int smu7_send_msg_to_smc_offset(struct pp_hwmgr *hwmgr);
76int smu7_wait_for_smc_inactive(struct pp_smumgr *smumgr); 76int smu7_wait_for_smc_inactive(struct pp_hwmgr *hwmgr);
77 77
78enum cgs_ucode_id smu7_convert_fw_type_to_cgs(uint32_t fw_type); 78enum cgs_ucode_id smu7_convert_fw_type_to_cgs(uint32_t fw_type);
79int smu7_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, 79int smu7_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr,
80 uint32_t *value, uint32_t limit); 80 uint32_t *value, uint32_t limit);
81int smu7_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, 81int smu7_write_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr,
82 uint32_t value, uint32_t limit); 82 uint32_t value, uint32_t limit);
83 83
84int smu7_request_smu_load_fw(struct pp_smumgr *smumgr); 84int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr);
85int smu7_check_fw_load_finish(struct pp_smumgr *smumgr, uint32_t fw_type); 85int smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr, uint32_t fw_type);
86int smu7_reload_firmware(struct pp_smumgr *smumgr); 86int smu7_reload_firmware(struct pp_hwmgr *hwmgr);
87int smu7_upload_smu_firmware_image(struct pp_smumgr *smumgr); 87int smu7_upload_smu_firmware_image(struct pp_hwmgr *hwmgr);
88int smu7_init(struct pp_smumgr *smumgr); 88int smu7_init(struct pp_hwmgr *hwmgr);
89int smu7_smu_fini(struct pp_smumgr *smumgr); 89int smu7_smu_fini(struct pp_hwmgr *hwmgr);
90 90
91#endif \ No newline at end of file 91#endif \ No newline at end of file
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
index 9c1738f991b6..a58346e78c35 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
@@ -151,10 +151,10 @@ int smum_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
151 return 0; 151 return 0;
152} 152}
153 153
154uint32_t smum_get_offsetof(struct pp_smumgr *smumgr, uint32_t type, uint32_t member) 154uint32_t smum_get_offsetof(struct pp_hwmgr *hwmgr, uint32_t type, uint32_t member)
155{ 155{
156 if (NULL != smumgr->smumgr_funcs->get_offsetof) 156 if (NULL != hwmgr->smumgr->smumgr_funcs->get_offsetof)
157 return smumgr->smumgr_funcs->get_offsetof(type, member); 157 return hwmgr->smumgr->smumgr_funcs->get_offsetof(type, member);
158 158
159 return 0; 159 return 0;
160} 160}
@@ -166,97 +166,96 @@ int smum_process_firmware_header(struct pp_hwmgr *hwmgr)
166 return 0; 166 return 0;
167} 167}
168 168
169int smum_get_argument(struct pp_smumgr *smumgr) 169int smum_get_argument(struct pp_hwmgr *hwmgr)
170{ 170{
171 if (NULL != smumgr->smumgr_funcs->get_argument) 171 if (NULL != hwmgr->smumgr->smumgr_funcs->get_argument)
172 return smumgr->smumgr_funcs->get_argument(smumgr); 172 return hwmgr->smumgr->smumgr_funcs->get_argument(hwmgr);
173 173
174 return 0; 174 return 0;
175} 175}
176 176
177uint32_t smum_get_mac_definition(struct pp_smumgr *smumgr, uint32_t value) 177uint32_t smum_get_mac_definition(struct pp_hwmgr *hwmgr, uint32_t value)
178{ 178{
179 if (NULL != smumgr->smumgr_funcs->get_mac_definition) 179 if (NULL != hwmgr->smumgr->smumgr_funcs->get_mac_definition)
180 return smumgr->smumgr_funcs->get_mac_definition(value); 180 return hwmgr->smumgr->smumgr_funcs->get_mac_definition(value);
181 181
182 return 0; 182 return 0;
183} 183}
184 184
185int smum_download_powerplay_table(struct pp_smumgr *smumgr, 185int smum_download_powerplay_table(struct pp_hwmgr *hwmgr, void **table)
186 void **table)
187{ 186{
188 if (NULL != smumgr->smumgr_funcs->download_pptable_settings) 187 if (NULL != hwmgr->smumgr->smumgr_funcs->download_pptable_settings)
189 return smumgr->smumgr_funcs->download_pptable_settings(smumgr, 188 return hwmgr->smumgr->smumgr_funcs->download_pptable_settings(hwmgr,
190 table); 189 table);
191 return 0; 190 return 0;
192} 191}
193 192
194int smum_upload_powerplay_table(struct pp_smumgr *smumgr) 193int smum_upload_powerplay_table(struct pp_hwmgr *hwmgr)
195{ 194{
196 if (NULL != smumgr->smumgr_funcs->upload_pptable_settings) 195 if (NULL != hwmgr->smumgr->smumgr_funcs->upload_pptable_settings)
197 return smumgr->smumgr_funcs->upload_pptable_settings(smumgr); 196 return hwmgr->smumgr->smumgr_funcs->upload_pptable_settings(hwmgr);
198 197
199 return 0; 198 return 0;
200} 199}
201 200
202int smum_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg) 201int smum_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
203{ 202{
204 if (smumgr == NULL || smumgr->smumgr_funcs->send_msg_to_smc == NULL) 203 if (hwmgr == NULL || hwmgr->smumgr->smumgr_funcs->send_msg_to_smc == NULL)
205 return -EINVAL; 204 return -EINVAL;
206 205
207 return smumgr->smumgr_funcs->send_msg_to_smc(smumgr, msg); 206 return hwmgr->smumgr->smumgr_funcs->send_msg_to_smc(hwmgr, msg);
208} 207}
209 208
210int smum_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, 209int smum_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
211 uint16_t msg, uint32_t parameter) 210 uint16_t msg, uint32_t parameter)
212{ 211{
213 if (smumgr == NULL || 212 if (hwmgr == NULL ||
214 smumgr->smumgr_funcs->send_msg_to_smc_with_parameter == NULL) 213 hwmgr->smumgr->smumgr_funcs->send_msg_to_smc_with_parameter == NULL)
215 return -EINVAL; 214 return -EINVAL;
216 return smumgr->smumgr_funcs->send_msg_to_smc_with_parameter( 215 return hwmgr->smumgr->smumgr_funcs->send_msg_to_smc_with_parameter(
217 smumgr, msg, parameter); 216 hwmgr, msg, parameter);
218} 217}
219 218
220/* 219/*
221 * Returns once the part of the register indicated by the mask has 220 * Returns once the part of the register indicated by the mask has
222 * reached the given value. 221 * reached the given value.
223 */ 222 */
224int smum_wait_on_register(struct pp_smumgr *smumgr, 223int smum_wait_on_register(struct pp_hwmgr *hwmgr,
225 uint32_t index, 224 uint32_t index,
226 uint32_t value, uint32_t mask) 225 uint32_t value, uint32_t mask)
227{ 226{
228 uint32_t i; 227 uint32_t i;
229 uint32_t cur_value; 228 uint32_t cur_value;
230 229
231 if (smumgr == NULL || smumgr->device == NULL) 230 if (hwmgr == NULL || hwmgr->device == NULL)
232 return -EINVAL; 231 return -EINVAL;
233 232
234 for (i = 0; i < smumgr->usec_timeout; i++) { 233 for (i = 0; i < hwmgr->usec_timeout; i++) {
235 cur_value = cgs_read_register(smumgr->device, index); 234 cur_value = cgs_read_register(hwmgr->device, index);
236 if ((cur_value & mask) == (value & mask)) 235 if ((cur_value & mask) == (value & mask))
237 break; 236 break;
238 udelay(1); 237 udelay(1);
239 } 238 }
240 239
241 /* timeout means wrong logic*/ 240 /* timeout means wrong logic*/
242 if (i == smumgr->usec_timeout) 241 if (i == hwmgr->usec_timeout)
243 return -1; 242 return -1;
244 243
245 return 0; 244 return 0;
246} 245}
247 246
248int smum_wait_for_register_unequal(struct pp_smumgr *smumgr, 247int smum_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
249 uint32_t index, 248 uint32_t index,
250 uint32_t value, uint32_t mask) 249 uint32_t value, uint32_t mask)
251{ 250{
252 uint32_t i; 251 uint32_t i;
253 uint32_t cur_value; 252 uint32_t cur_value;
254 253
255 if (smumgr == NULL) 254 if (hwmgr == NULL)
256 return -EINVAL; 255 return -EINVAL;
257 256
258 for (i = 0; i < smumgr->usec_timeout; i++) { 257 for (i = 0; i < hwmgr->usec_timeout; i++) {
259 cur_value = cgs_read_register(smumgr->device, 258 cur_value = cgs_read_register(hwmgr->device,
260 index); 259 index);
261 if ((cur_value & mask) != (value & mask)) 260 if ((cur_value & mask) != (value & mask))
262 break; 261 break;
@@ -264,7 +263,7 @@ int smum_wait_for_register_unequal(struct pp_smumgr *smumgr,
264 } 263 }
265 264
266 /* timeout means wrong logic */ 265 /* timeout means wrong logic */
267 if (i == smumgr->usec_timeout) 266 if (i == hwmgr->usec_timeout)
268 return -1; 267 return -1;
269 268
270 return 0; 269 return 0;
@@ -276,31 +275,31 @@ int smum_wait_for_register_unequal(struct pp_smumgr *smumgr,
276 * has reached the given value.The indirect space is described by 275 * has reached the given value.The indirect space is described by
277 * giving the memory-mapped index of the indirect index register. 276 * giving the memory-mapped index of the indirect index register.
278 */ 277 */
279int smum_wait_on_indirect_register(struct pp_smumgr *smumgr, 278int smum_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
280 uint32_t indirect_port, 279 uint32_t indirect_port,
281 uint32_t index, 280 uint32_t index,
282 uint32_t value, 281 uint32_t value,
283 uint32_t mask) 282 uint32_t mask)
284{ 283{
285 if (smumgr == NULL || smumgr->device == NULL) 284 if (hwmgr == NULL || hwmgr->device == NULL)
286 return -EINVAL; 285 return -EINVAL;
287 286
288 cgs_write_register(smumgr->device, indirect_port, index); 287 cgs_write_register(hwmgr->device, indirect_port, index);
289 return smum_wait_on_register(smumgr, indirect_port + 1, 288 return smum_wait_on_register(hwmgr, indirect_port + 1,
290 mask, value); 289 mask, value);
291} 290}
292 291
293void smum_wait_for_indirect_register_unequal( 292void smum_wait_for_indirect_register_unequal(
294 struct pp_smumgr *smumgr, 293 struct pp_hwmgr *hwmgr,
295 uint32_t indirect_port, 294 uint32_t indirect_port,
296 uint32_t index, 295 uint32_t index,
297 uint32_t value, 296 uint32_t value,
298 uint32_t mask) 297 uint32_t mask)
299{ 298{
300 if (smumgr == NULL || smumgr->device == NULL) 299 if (hwmgr == NULL || hwmgr->device == NULL)
301 return; 300 return;
302 cgs_write_register(smumgr->device, indirect_port, index); 301 cgs_write_register(hwmgr->device, indirect_port, index);
303 smum_wait_for_register_unequal(smumgr, indirect_port + 1, 302 smum_wait_for_register_unequal(hwmgr, indirect_port + 1,
304 value, mask); 303 value, mask);
305} 304}
306 305
@@ -406,10 +405,10 @@ int smum_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
406 return 0; 405 return 0;
407} 406}
408 407
409bool smum_is_hw_avfs_present(struct pp_smumgr *smumgr) 408bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
410{ 409{
411 if (smumgr->smumgr_funcs->is_hw_avfs_present) 410 if (hwmgr->smumgr->smumgr_funcs->is_hw_avfs_present)
412 return smumgr->smumgr_funcs->is_hw_avfs_present(smumgr); 411 return hwmgr->smumgr->smumgr_funcs->is_hw_avfs_present(hwmgr);
413 412
414 return false; 413 return false;
415} 414}
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c
index a628eec5e6da..68e1e19b971b 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c
@@ -690,7 +690,7 @@ int tonga_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
690 smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled; 690 smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled;
691 } 691 }
692 /* level count will send to smc once at init smc table and never change*/ 692 /* level count will send to smc once at init smc table and never change*/
693 result = smu7_copy_bytes_to_smc(hwmgr->smumgr, level_array_address, 693 result = smu7_copy_bytes_to_smc(hwmgr, level_array_address,
694 (uint8_t *)levels, (uint32_t)level_array_size, 694 (uint8_t *)levels, (uint32_t)level_array_size,
695 SMC_RAM_END); 695 SMC_RAM_END);
696 696
@@ -1048,7 +1048,7 @@ int tonga_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1048 smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH; 1048 smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1049 1049
1050 /* level count will send to smc once at init smc table and never change*/ 1050 /* level count will send to smc once at init smc table and never change*/
1051 result = smu7_copy_bytes_to_smc(hwmgr->smumgr, 1051 result = smu7_copy_bytes_to_smc(hwmgr,
1052 level_array_address, (uint8_t *)levels, (uint32_t)level_array_size, 1052 level_array_address, (uint8_t *)levels, (uint32_t)level_array_size,
1053 SMC_RAM_END); 1053 SMC_RAM_END);
1054 1054
@@ -1475,7 +1475,7 @@ static int tonga_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1475 1475
1476 if (!result) { 1476 if (!result) {
1477 result = smu7_copy_bytes_to_smc( 1477 result = smu7_copy_bytes_to_smc(
1478 hwmgr->smumgr, 1478 hwmgr,
1479 smu_data->smu7_data.arb_table_start, 1479 smu_data->smu7_data.arb_table_start,
1480 (uint8_t *)&arb_regs, 1480 (uint8_t *)&arb_regs,
1481 sizeof(SMU72_Discrete_MCArbDramTimingTable), 1481 sizeof(SMU72_Discrete_MCArbDramTimingTable),
@@ -1782,9 +1782,9 @@ static int tonga_populate_vr_config(struct pp_hwmgr *hwmgr,
1782 * @param hwmgr the address of the powerplay hardware manager. 1782 * @param hwmgr the address of the powerplay hardware manager.
1783 * @return always 0 1783 * @return always 0
1784 */ 1784 */
1785static int tonga_init_arb_table_index(struct pp_smumgr *smumgr) 1785static int tonga_init_arb_table_index(struct pp_hwmgr *hwmgr)
1786{ 1786{
1787 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(smumgr->backend); 1787 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend);
1788 uint32_t tmp; 1788 uint32_t tmp;
1789 int result; 1789 int result;
1790 1790
@@ -1797,7 +1797,7 @@ static int tonga_init_arb_table_index(struct pp_smumgr *smumgr)
1797 * In reality this field should not be in that structure 1797 * In reality this field should not be in that structure
1798 * but in a soft register. 1798 * but in a soft register.
1799 */ 1799 */
1800 result = smu7_read_smc_sram_dword(smumgr, 1800 result = smu7_read_smc_sram_dword(hwmgr,
1801 smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END); 1801 smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
1802 1802
1803 if (result != 0) 1803 if (result != 0)
@@ -1806,7 +1806,7 @@ static int tonga_init_arb_table_index(struct pp_smumgr *smumgr)
1806 tmp &= 0x00FFFFFF; 1806 tmp &= 0x00FFFFFF;
1807 tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24; 1807 tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
1808 1808
1809 return smu7_write_smc_sram_dword(smumgr, 1809 return smu7_write_smc_sram_dword(hwmgr,
1810 smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END); 1810 smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END);
1811} 1811}
1812 1812
@@ -1901,7 +1901,7 @@ static int tonga_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset
1901 const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults; 1901 const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults;
1902 uint32_t temp; 1902 uint32_t temp;
1903 1903
1904 if (smu7_read_smc_sram_dword(hwmgr->smumgr, 1904 if (smu7_read_smc_sram_dword(hwmgr,
1905 fuse_table_offset + 1905 fuse_table_offset +
1906 offsetof(SMU72_Discrete_PmFuses, TdcWaterfallCtl), 1906 offsetof(SMU72_Discrete_PmFuses, TdcWaterfallCtl),
1907 (uint32_t *)&temp, SMC_RAM_END)) 1907 (uint32_t *)&temp, SMC_RAM_END))
@@ -1987,7 +1987,7 @@ static int tonga_populate_pm_fuses(struct pp_hwmgr *hwmgr)
1987 1987
1988 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1988 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1989 PHM_PlatformCaps_PowerContainment)) { 1989 PHM_PlatformCaps_PowerContainment)) {
1990 if (smu7_read_smc_sram_dword(hwmgr->smumgr, 1990 if (smu7_read_smc_sram_dword(hwmgr,
1991 SMU72_FIRMWARE_HEADER_LOCATION + 1991 SMU72_FIRMWARE_HEADER_LOCATION +
1992 offsetof(SMU72_Firmware_Header, PmFuseTable), 1992 offsetof(SMU72_Firmware_Header, PmFuseTable),
1993 &pm_fuse_table_offset, SMC_RAM_END)) 1993 &pm_fuse_table_offset, SMC_RAM_END))
@@ -2038,7 +2038,7 @@ static int tonga_populate_pm_fuses(struct pp_hwmgr *hwmgr)
2038 "Hi and Lo Sidd Failed !", 2038 "Hi and Lo Sidd Failed !",
2039 return -EINVAL); 2039 return -EINVAL);
2040 2040
2041 if (smu7_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset, 2041 if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
2042 (uint8_t *)&smu_data->power_tune_table, 2042 (uint8_t *)&smu_data->power_tune_table,
2043 sizeof(struct SMU72_Discrete_PmFuses), SMC_RAM_END)) 2043 sizeof(struct SMU72_Discrete_PmFuses), SMC_RAM_END))
2044 PP_ASSERT_WITH_CODE(false, 2044 PP_ASSERT_WITH_CODE(false,
@@ -2048,10 +2048,10 @@ static int tonga_populate_pm_fuses(struct pp_hwmgr *hwmgr)
2048 return 0; 2048 return 0;
2049} 2049}
2050 2050
2051static int tonga_populate_mc_reg_address(struct pp_smumgr *smumgr, 2051static int tonga_populate_mc_reg_address(struct pp_hwmgr *hwmgr,
2052 SMU72_Discrete_MCRegisters *mc_reg_table) 2052 SMU72_Discrete_MCRegisters *mc_reg_table)
2053{ 2053{
2054 const struct tonga_smumgr *smu_data = (struct tonga_smumgr *)smumgr->backend; 2054 const struct tonga_smumgr *smu_data = (struct tonga_smumgr *)hwmgr->smumgr->backend;
2055 2055
2056 uint32_t i, j; 2056 uint32_t i, j;
2057 2057
@@ -2092,12 +2092,12 @@ static void tonga_convert_mc_registers(
2092} 2092}
2093 2093
2094static int tonga_convert_mc_reg_table_entry_to_smc( 2094static int tonga_convert_mc_reg_table_entry_to_smc(
2095 struct pp_smumgr *smumgr, 2095 struct pp_hwmgr *hwmgr,
2096 const uint32_t memory_clock, 2096 const uint32_t memory_clock,
2097 SMU72_Discrete_MCRegisterSet *mc_reg_table_data 2097 SMU72_Discrete_MCRegisterSet *mc_reg_table_data
2098 ) 2098 )
2099{ 2099{
2100 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(smumgr->backend); 2100 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend);
2101 uint32_t i = 0; 2101 uint32_t i = 0;
2102 2102
2103 for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) { 2103 for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) {
@@ -2127,7 +2127,7 @@ static int tonga_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
2127 2127
2128 for (i = 0; i < data->dpm_table.mclk_table.count; i++) { 2128 for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
2129 res = tonga_convert_mc_reg_table_entry_to_smc( 2129 res = tonga_convert_mc_reg_table_entry_to_smc(
2130 hwmgr->smumgr, 2130 hwmgr,
2131 data->dpm_table.mclk_table.dpm_levels[i].value, 2131 data->dpm_table.mclk_table.dpm_levels[i].value,
2132 &mc_regs->data[i] 2132 &mc_regs->data[i]
2133 ); 2133 );
@@ -2141,8 +2141,7 @@ static int tonga_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
2141 2141
2142static int tonga_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr) 2142static int tonga_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
2143{ 2143{
2144 struct pp_smumgr *smumgr = hwmgr->smumgr; 2144 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend);
2145 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(smumgr->backend);
2146 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2145 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2147 uint32_t address; 2146 uint32_t address;
2148 int32_t result; 2147 int32_t result;
@@ -2163,7 +2162,7 @@ static int tonga_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
2163 (uint32_t)offsetof(SMU72_Discrete_MCRegisters, data[0]); 2162 (uint32_t)offsetof(SMU72_Discrete_MCRegisters, data[0]);
2164 2163
2165 return smu7_copy_bytes_to_smc( 2164 return smu7_copy_bytes_to_smc(
2166 hwmgr->smumgr, address, 2165 hwmgr, address,
2167 (uint8_t *)&smu_data->mc_regs.data[0], 2166 (uint8_t *)&smu_data->mc_regs.data[0],
2168 sizeof(SMU72_Discrete_MCRegisterSet) * 2167 sizeof(SMU72_Discrete_MCRegisterSet) *
2169 data->dpm_table.mclk_table.count, 2168 data->dpm_table.mclk_table.count,
@@ -2173,11 +2172,10 @@ static int tonga_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
2173static int tonga_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr) 2172static int tonga_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
2174{ 2173{
2175 int result; 2174 int result;
2176 struct pp_smumgr *smumgr = hwmgr->smumgr; 2175 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend);
2177 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(smumgr->backend);
2178 2176
2179 memset(&smu_data->mc_regs, 0x00, sizeof(SMU72_Discrete_MCRegisters)); 2177 memset(&smu_data->mc_regs, 0x00, sizeof(SMU72_Discrete_MCRegisters));
2180 result = tonga_populate_mc_reg_address(smumgr, &(smu_data->mc_regs)); 2178 result = tonga_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs));
2181 PP_ASSERT_WITH_CODE(!result, 2179 PP_ASSERT_WITH_CODE(!result,
2182 "Failed to initialize MCRegTable for the MC register addresses !", 2180 "Failed to initialize MCRegTable for the MC register addresses !",
2183 return result;); 2181 return result;);
@@ -2187,7 +2185,7 @@ static int tonga_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
2187 "Failed to initialize MCRegTable for driver state !", 2185 "Failed to initialize MCRegTable for driver state !",
2188 return result;); 2186 return result;);
2189 2187
2190 return smu7_copy_bytes_to_smc(smumgr, smu_data->smu7_data.mc_reg_table_start, 2188 return smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.mc_reg_table_start,
2191 (uint8_t *)&smu_data->mc_regs, sizeof(SMU72_Discrete_MCRegisters), SMC_RAM_END); 2189 (uint8_t *)&smu_data->mc_regs, sizeof(SMU72_Discrete_MCRegisters), SMC_RAM_END);
2192} 2190}
2193 2191
@@ -2471,7 +2469,7 @@ int tonga_init_smc_table(struct pp_hwmgr *hwmgr)
2471 2469
2472 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */ 2470 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2473 result = smu7_copy_bytes_to_smc( 2471 result = smu7_copy_bytes_to_smc(
2474 hwmgr->smumgr, 2472 hwmgr,
2475 smu_data->smu7_data.dpm_table_start + offsetof(SMU72_Discrete_DpmTable, SystemFlags), 2473 smu_data->smu7_data.dpm_table_start + offsetof(SMU72_Discrete_DpmTable, SystemFlags),
2476 (uint8_t *)&(table->SystemFlags), 2474 (uint8_t *)&(table->SystemFlags),
2477 sizeof(SMU72_Discrete_DpmTable) - 3 * sizeof(SMU72_PIDController), 2475 sizeof(SMU72_Discrete_DpmTable) - 3 * sizeof(SMU72_PIDController),
@@ -2480,7 +2478,7 @@ int tonga_init_smc_table(struct pp_hwmgr *hwmgr)
2480 PP_ASSERT_WITH_CODE(!result, 2478 PP_ASSERT_WITH_CODE(!result,
2481 "Failed to upload dpm data to SMC memory !", return result;); 2479 "Failed to upload dpm data to SMC memory !", return result;);
2482 2480
2483 result = tonga_init_arb_table_index(hwmgr->smumgr); 2481 result = tonga_init_arb_table_index(hwmgr);
2484 PP_ASSERT_WITH_CODE(!result, 2482 PP_ASSERT_WITH_CODE(!result,
2485 "Failed to upload arb data to SMC memory !", return result); 2483 "Failed to upload arb data to SMC memory !", return result);
2486 2484
@@ -2588,7 +2586,7 @@ int tonga_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
2588 2586
2589 fan_table.FanControl_GL_Flag = 1; 2587 fan_table.FanControl_GL_Flag = 1;
2590 2588
2591 res = smu7_copy_bytes_to_smc(hwmgr->smumgr, 2589 res = smu7_copy_bytes_to_smc(hwmgr,
2592 smu_data->smu7_data.fan_table_start, 2590 smu_data->smu7_data.fan_table_start,
2593 (uint8_t *)&fan_table, 2591 (uint8_t *)&fan_table,
2594 (uint32_t)sizeof(fan_table), 2592 (uint32_t)sizeof(fan_table),
@@ -2630,7 +2628,7 @@ int tonga_update_sclk_threshold(struct pp_hwmgr *hwmgr)
2630 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold); 2628 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
2631 2629
2632 result = smu7_copy_bytes_to_smc( 2630 result = smu7_copy_bytes_to_smc(
2633 hwmgr->smumgr, 2631 hwmgr,
2634 smu_data->smu7_data.dpm_table_start + 2632 smu_data->smu7_data.dpm_table_start +
2635 offsetof(SMU72_Discrete_DpmTable, 2633 offsetof(SMU72_Discrete_DpmTable,
2636 LowSclkInterruptThreshold), 2634 LowSclkInterruptThreshold),
@@ -2741,7 +2739,7 @@ static int tonga_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
2741 PHM_PlatformCaps_UVDDPM) || 2739 PHM_PlatformCaps_UVDDPM) ||
2742 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 2740 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2743 PHM_PlatformCaps_StablePState)) 2741 PHM_PlatformCaps_StablePState))
2744 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 2742 smum_send_msg_to_smc_with_parameter(hwmgr,
2745 PPSMC_MSG_UVDDPM_SetEnabledMask, 2743 PPSMC_MSG_UVDDPM_SetEnabledMask,
2746 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel)); 2744 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel));
2747 return 0; 2745 return 0;
@@ -2772,7 +2770,7 @@ static int tonga_update_vce_smc_table(struct pp_hwmgr *hwmgr)
2772 2770
2773 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 2771 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2774 PHM_PlatformCaps_StablePState)) 2772 PHM_PlatformCaps_StablePState))
2775 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 2773 smum_send_msg_to_smc_with_parameter(hwmgr,
2776 PPSMC_MSG_VCEDPM_SetEnabledMask, 2774 PPSMC_MSG_VCEDPM_SetEnabledMask,
2777 (uint32_t)1 << smu_data->smc_state_table.VceBootLevel); 2775 (uint32_t)1 << smu_data->smc_state_table.VceBootLevel);
2778 return 0; 2776 return 0;
@@ -2798,7 +2796,7 @@ static int tonga_update_samu_smc_table(struct pp_hwmgr *hwmgr)
2798 2796
2799 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 2797 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2800 PHM_PlatformCaps_StablePState)) 2798 PHM_PlatformCaps_StablePState))
2801 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 2799 smum_send_msg_to_smc_with_parameter(hwmgr,
2802 PPSMC_MSG_SAMUDPM_SetEnabledMask, 2800 PPSMC_MSG_SAMUDPM_SetEnabledMask,
2803 (uint32_t)(1 << smu_data->smc_state_table.SamuBootLevel)); 2801 (uint32_t)(1 << smu_data->smc_state_table.SamuBootLevel));
2804 return 0; 2802 return 0;
@@ -2838,7 +2836,7 @@ int tonga_process_firmware_header(struct pp_hwmgr *hwmgr)
2838 int result; 2836 int result;
2839 bool error = false; 2837 bool error = false;
2840 2838
2841 result = smu7_read_smc_sram_dword(hwmgr->smumgr, 2839 result = smu7_read_smc_sram_dword(hwmgr,
2842 SMU72_FIRMWARE_HEADER_LOCATION + 2840 SMU72_FIRMWARE_HEADER_LOCATION +
2843 offsetof(SMU72_Firmware_Header, DpmTable), 2841 offsetof(SMU72_Firmware_Header, DpmTable),
2844 &tmp, SMC_RAM_END); 2842 &tmp, SMC_RAM_END);
@@ -2848,7 +2846,7 @@ int tonga_process_firmware_header(struct pp_hwmgr *hwmgr)
2848 2846
2849 error |= (result != 0); 2847 error |= (result != 0);
2850 2848
2851 result = smu7_read_smc_sram_dword(hwmgr->smumgr, 2849 result = smu7_read_smc_sram_dword(hwmgr,
2852 SMU72_FIRMWARE_HEADER_LOCATION + 2850 SMU72_FIRMWARE_HEADER_LOCATION +
2853 offsetof(SMU72_Firmware_Header, SoftRegisters), 2851 offsetof(SMU72_Firmware_Header, SoftRegisters),
2854 &tmp, SMC_RAM_END); 2852 &tmp, SMC_RAM_END);
@@ -2861,7 +2859,7 @@ int tonga_process_firmware_header(struct pp_hwmgr *hwmgr)
2861 error |= (result != 0); 2859 error |= (result != 0);
2862 2860
2863 2861
2864 result = smu7_read_smc_sram_dword(hwmgr->smumgr, 2862 result = smu7_read_smc_sram_dword(hwmgr,
2865 SMU72_FIRMWARE_HEADER_LOCATION + 2863 SMU72_FIRMWARE_HEADER_LOCATION +
2866 offsetof(SMU72_Firmware_Header, mcRegisterTable), 2864 offsetof(SMU72_Firmware_Header, mcRegisterTable),
2867 &tmp, SMC_RAM_END); 2865 &tmp, SMC_RAM_END);
@@ -2869,7 +2867,7 @@ int tonga_process_firmware_header(struct pp_hwmgr *hwmgr)
2869 if (!result) 2867 if (!result)
2870 smu_data->smu7_data.mc_reg_table_start = tmp; 2868 smu_data->smu7_data.mc_reg_table_start = tmp;
2871 2869
2872 result = smu7_read_smc_sram_dword(hwmgr->smumgr, 2870 result = smu7_read_smc_sram_dword(hwmgr,
2873 SMU72_FIRMWARE_HEADER_LOCATION + 2871 SMU72_FIRMWARE_HEADER_LOCATION +
2874 offsetof(SMU72_Firmware_Header, FanTable), 2872 offsetof(SMU72_Firmware_Header, FanTable),
2875 &tmp, SMC_RAM_END); 2873 &tmp, SMC_RAM_END);
@@ -2879,7 +2877,7 @@ int tonga_process_firmware_header(struct pp_hwmgr *hwmgr)
2879 2877
2880 error |= (result != 0); 2878 error |= (result != 0);
2881 2879
2882 result = smu7_read_smc_sram_dword(hwmgr->smumgr, 2880 result = smu7_read_smc_sram_dword(hwmgr,
2883 SMU72_FIRMWARE_HEADER_LOCATION + 2881 SMU72_FIRMWARE_HEADER_LOCATION +
2884 offsetof(SMU72_Firmware_Header, mcArbDramTimingTable), 2882 offsetof(SMU72_Firmware_Header, mcArbDramTimingTable),
2885 &tmp, SMC_RAM_END); 2883 &tmp, SMC_RAM_END);
@@ -2889,7 +2887,7 @@ int tonga_process_firmware_header(struct pp_hwmgr *hwmgr)
2889 2887
2890 error |= (result != 0); 2888 error |= (result != 0);
2891 2889
2892 result = smu7_read_smc_sram_dword(hwmgr->smumgr, 2890 result = smu7_read_smc_sram_dword(hwmgr,
2893 SMU72_FIRMWARE_HEADER_LOCATION + 2891 SMU72_FIRMWARE_HEADER_LOCATION +
2894 offsetof(SMU72_Firmware_Header, Version), 2892 offsetof(SMU72_Firmware_Header, Version),
2895 &tmp, SMC_RAM_END); 2893 &tmp, SMC_RAM_END);
@@ -3258,6 +3256,6 @@ int tonga_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
3258 levels[i].DownHyst = request->down_hyst; 3256 levels[i].DownHyst = request->down_hyst;
3259 } 3257 }
3260 3258
3261 return smu7_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels, 3259 return smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
3262 array_size, SMC_RAM_END); 3260 array_size, SMC_RAM_END);
3263} 3261}
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
index c35f4c35c9ca..c10e6f89dbae 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
@@ -37,125 +37,125 @@
37#include "smu7_smumgr.h" 37#include "smu7_smumgr.h"
38 38
39 39
40static int tonga_start_in_protection_mode(struct pp_smumgr *smumgr) 40static int tonga_start_in_protection_mode(struct pp_hwmgr *hwmgr)
41{ 41{
42 int result; 42 int result;
43 43
44 /* Assert reset */ 44 /* Assert reset */
45 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, 45 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
46 SMC_SYSCON_RESET_CNTL, rst_reg, 1); 46 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
47 47
48 result = smu7_upload_smu_firmware_image(smumgr); 48 result = smu7_upload_smu_firmware_image(hwmgr);
49 if (result) 49 if (result)
50 return result; 50 return result;
51 51
52 /* Clear status */ 52 /* Clear status */
53 cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, 53 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
54 ixSMU_STATUS, 0); 54 ixSMU_STATUS, 0);
55 55
56 /* Enable clock */ 56 /* Enable clock */
57 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, 57 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
58 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); 58 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
59 59
60 /* De-assert reset */ 60 /* De-assert reset */
61 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, 61 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
62 SMC_SYSCON_RESET_CNTL, rst_reg, 0); 62 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
63 63
64 /* Set SMU Auto Start */ 64 /* Set SMU Auto Start */
65 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, 65 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
66 SMU_INPUT_DATA, AUTO_START, 1); 66 SMU_INPUT_DATA, AUTO_START, 1);
67 67
68 /* Clear firmware interrupt enable flag */ 68 /* Clear firmware interrupt enable flag */
69 cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, 69 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
70 ixFIRMWARE_FLAGS, 0); 70 ixFIRMWARE_FLAGS, 0);
71 71
72 SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, 72 SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
73 RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1); 73 RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
74 74
75 /** 75 /**
76 * Call Test SMU message with 0x20000 offset to trigger SMU start 76 * Call Test SMU message with 0x20000 offset to trigger SMU start
77 */ 77 */
78 smu7_send_msg_to_smc_offset(smumgr); 78 smu7_send_msg_to_smc_offset(hwmgr);
79 79
80 /* Wait for done bit to be set */ 80 /* Wait for done bit to be set */
81 SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, 81 SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
82 SMU_STATUS, SMU_DONE, 0); 82 SMU_STATUS, SMU_DONE, 0);
83 83
84 /* Check pass/failed indicator */ 84 /* Check pass/failed indicator */
85 if (1 != SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, 85 if (1 != SMUM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
86 CGS_IND_REG__SMC, SMU_STATUS, SMU_PASS)) { 86 CGS_IND_REG__SMC, SMU_STATUS, SMU_PASS)) {
87 pr_err("SMU Firmware start failed\n"); 87 pr_err("SMU Firmware start failed\n");
88 return -EINVAL; 88 return -EINVAL;
89 } 89 }
90 90
91 /* Wait for firmware to initialize */ 91 /* Wait for firmware to initialize */
92 SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, 92 SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
93 FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1); 93 FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
94 94
95 return 0; 95 return 0;
96} 96}
97 97
98 98
99static int tonga_start_in_non_protection_mode(struct pp_smumgr *smumgr) 99static int tonga_start_in_non_protection_mode(struct pp_hwmgr *hwmgr)
100{ 100{
101 int result = 0; 101 int result = 0;
102 102
103 /* wait for smc boot up */ 103 /* wait for smc boot up */
104 SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, 104 SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
105 RCU_UC_EVENTS, boot_seq_done, 0); 105 RCU_UC_EVENTS, boot_seq_done, 0);
106 106
107 /*Clear firmware interrupt enable flag*/ 107 /*Clear firmware interrupt enable flag*/
108 cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, 108 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
109 ixFIRMWARE_FLAGS, 0); 109 ixFIRMWARE_FLAGS, 0);
110 110
111 111
112 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, 112 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
113 SMC_SYSCON_RESET_CNTL, rst_reg, 1); 113 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
114 114
115 result = smu7_upload_smu_firmware_image(smumgr); 115 result = smu7_upload_smu_firmware_image(hwmgr);
116 116
117 if (result != 0) 117 if (result != 0)
118 return result; 118 return result;
119 119
120 /* Set smc instruct start point at 0x0 */ 120 /* Set smc instruct start point at 0x0 */
121 smu7_program_jump_on_start(smumgr); 121 smu7_program_jump_on_start(hwmgr);
122 122
123 123
124 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, 124 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
125 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); 125 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
126 126
127 /*De-assert reset*/ 127 /*De-assert reset*/
128 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, 128 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
129 SMC_SYSCON_RESET_CNTL, rst_reg, 0); 129 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
130 130
131 /* Wait for firmware to initialize */ 131 /* Wait for firmware to initialize */
132 SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, 132 SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
133 FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1); 133 FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
134 134
135 return result; 135 return result;
136} 136}
137 137
138static int tonga_start_smu(struct pp_smumgr *smumgr) 138static int tonga_start_smu(struct pp_hwmgr *hwmgr)
139{ 139{
140 int result; 140 int result;
141 141
142 /* Only start SMC if SMC RAM is not running */ 142 /* Only start SMC if SMC RAM is not running */
143 if (!(smu7_is_smc_ram_running(smumgr) || 143 if (!(smu7_is_smc_ram_running(hwmgr) ||
144 cgs_is_virtualization_enabled(smumgr->device))) { 144 cgs_is_virtualization_enabled(hwmgr->device))) {
145 /*Check if SMU is running in protected mode*/ 145 /*Check if SMU is running in protected mode*/
146 if (0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, 146 if (0 == SMUM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
147 SMU_FIRMWARE, SMU_MODE)) { 147 SMU_FIRMWARE, SMU_MODE)) {
148 result = tonga_start_in_non_protection_mode(smumgr); 148 result = tonga_start_in_non_protection_mode(hwmgr);
149 if (result) 149 if (result)
150 return result; 150 return result;
151 } else { 151 } else {
152 result = tonga_start_in_protection_mode(smumgr); 152 result = tonga_start_in_protection_mode(hwmgr);
153 if (result) 153 if (result)
154 return result; 154 return result;
155 } 155 }
156 } 156 }
157 157
158 result = smu7_request_smu_load_fw(smumgr); 158 result = smu7_request_smu_load_fw(hwmgr);
159 159
160 return result; 160 return result;
161} 161}
@@ -167,7 +167,7 @@ static int tonga_start_smu(struct pp_smumgr *smumgr)
167 * @param smcAddress the address in the SMC RAM to access. 167 * @param smcAddress the address in the SMC RAM to access.
168 * @param value to write to the SMC SRAM. 168 * @param value to write to the SMC SRAM.
169 */ 169 */
170static int tonga_smu_init(struct pp_smumgr *smumgr) 170static int tonga_smu_init(struct pp_hwmgr *hwmgr)
171{ 171{
172 struct tonga_smumgr *tonga_priv = NULL; 172 struct tonga_smumgr *tonga_priv = NULL;
173 int i; 173 int i;
@@ -176,9 +176,9 @@ static int tonga_smu_init(struct pp_smumgr *smumgr)
176 if (tonga_priv == NULL) 176 if (tonga_priv == NULL)
177 return -ENOMEM; 177 return -ENOMEM;
178 178
179 smumgr->backend = tonga_priv; 179 hwmgr->smumgr->backend = tonga_priv;
180 180
181 if (smu7_init(smumgr)) 181 if (smu7_init(hwmgr))
182 return -EINVAL; 182 return -EINVAL;
183 183
184 for (i = 0; i < SMU72_MAX_LEVELS_GRAPHICS; i++) 184 for (i = 0; i < SMU72_MAX_LEVELS_GRAPHICS; i++)
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
index 408514c965a0..c63127058090 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
@@ -53,20 +53,20 @@
53#define smnMP0_FW_INTF 0x3010104 53#define smnMP0_FW_INTF 0x3010104
54#define smnMP1_PUB_CTRL 0x3010b14 54#define smnMP1_PUB_CTRL 0x3010b14
55 55
56static bool vega10_is_smc_ram_running(struct pp_smumgr *smumgr) 56static bool vega10_is_smc_ram_running(struct pp_hwmgr *hwmgr)
57{ 57{
58 uint32_t mp1_fw_flags, reg; 58 uint32_t mp1_fw_flags, reg;
59 59
60 reg = soc15_get_register_offset(NBIF_HWID, 0, 60 reg = soc15_get_register_offset(NBIF_HWID, 0,
61 mmPCIE_INDEX2_BASE_IDX, mmPCIE_INDEX2); 61 mmPCIE_INDEX2_BASE_IDX, mmPCIE_INDEX2);
62 62
63 cgs_write_register(smumgr->device, reg, 63 cgs_write_register(hwmgr->device, reg,
64 (MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff))); 64 (MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff)));
65 65
66 reg = soc15_get_register_offset(NBIF_HWID, 0, 66 reg = soc15_get_register_offset(NBIF_HWID, 0,
67 mmPCIE_DATA2_BASE_IDX, mmPCIE_DATA2); 67 mmPCIE_DATA2_BASE_IDX, mmPCIE_DATA2);
68 68
69 mp1_fw_flags = cgs_read_register(smumgr->device, reg); 69 mp1_fw_flags = cgs_read_register(hwmgr->device, reg);
70 70
71 if (mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) 71 if (mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK)
72 return true; 72 return true;
@@ -80,20 +80,20 @@ static bool vega10_is_smc_ram_running(struct pp_smumgr *smumgr)
80 * @param smumgr the address of the powerplay hardware manager. 80 * @param smumgr the address of the powerplay hardware manager.
81 * @return TRUE SMC has responded, FALSE otherwise. 81 * @return TRUE SMC has responded, FALSE otherwise.
82 */ 82 */
83static uint32_t vega10_wait_for_response(struct pp_smumgr *smumgr) 83static uint32_t vega10_wait_for_response(struct pp_hwmgr *hwmgr)
84{ 84{
85 uint32_t reg; 85 uint32_t reg;
86 86
87 if (!vega10_is_smc_ram_running(smumgr)) 87 if (!vega10_is_smc_ram_running(hwmgr))
88 return -EINVAL; 88 return -EINVAL;
89 89
90 reg = soc15_get_register_offset(MP1_HWID, 0, 90 reg = soc15_get_register_offset(MP1_HWID, 0,
91 mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90); 91 mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
92 92
93 smum_wait_for_register_unequal(smumgr, reg, 93 smum_wait_for_register_unequal(hwmgr, reg,
94 0, MP1_C2PMSG_90__CONTENT_MASK); 94 0, MP1_C2PMSG_90__CONTENT_MASK);
95 95
96 return cgs_read_register(smumgr->device, reg); 96 return cgs_read_register(hwmgr->device, reg);
97} 97}
98 98
99/* 99/*
@@ -102,43 +102,43 @@ static uint32_t vega10_wait_for_response(struct pp_smumgr *smumgr)
102 * @param msg the message to send. 102 * @param msg the message to send.
103 * @return Always return 0. 103 * @return Always return 0.
104 */ 104 */
105int vega10_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, 105int vega10_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr,
106 uint16_t msg) 106 uint16_t msg)
107{ 107{
108 uint32_t reg; 108 uint32_t reg;
109 109
110 if (!vega10_is_smc_ram_running(smumgr)) 110 if (!vega10_is_smc_ram_running(hwmgr))
111 return -EINVAL; 111 return -EINVAL;
112 112
113 reg = soc15_get_register_offset(MP1_HWID, 0, 113 reg = soc15_get_register_offset(MP1_HWID, 0,
114 mmMP1_SMN_C2PMSG_66_BASE_IDX, mmMP1_SMN_C2PMSG_66); 114 mmMP1_SMN_C2PMSG_66_BASE_IDX, mmMP1_SMN_C2PMSG_66);
115 cgs_write_register(smumgr->device, reg, msg); 115 cgs_write_register(hwmgr->device, reg, msg);
116 116
117 return 0; 117 return 0;
118} 118}
119 119
120/* 120/*
121 * Send a message to the SMC, and wait for its response. 121 * Send a message to the SMC, and wait for its response.
122 * @param smumgr the address of the powerplay hardware manager. 122 * @param hwmgr the address of the powerplay hardware manager.
123 * @param msg the message to send. 123 * @param msg the message to send.
124 * @return Always return 0. 124 * @return Always return 0.
125 */ 125 */
126int vega10_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg) 126int vega10_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
127{ 127{
128 uint32_t reg; 128 uint32_t reg;
129 129
130 if (!vega10_is_smc_ram_running(smumgr)) 130 if (!vega10_is_smc_ram_running(hwmgr))
131 return -EINVAL; 131 return -EINVAL;
132 132
133 vega10_wait_for_response(smumgr); 133 vega10_wait_for_response(hwmgr);
134 134
135 reg = soc15_get_register_offset(MP1_HWID, 0, 135 reg = soc15_get_register_offset(MP1_HWID, 0,
136 mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90); 136 mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
137 cgs_write_register(smumgr->device, reg, 0); 137 cgs_write_register(hwmgr->device, reg, 0);
138 138
139 vega10_send_msg_to_smc_without_waiting(smumgr, msg); 139 vega10_send_msg_to_smc_without_waiting(hwmgr, msg);
140 140
141 if (vega10_wait_for_response(smumgr) != 1) 141 if (vega10_wait_for_response(hwmgr) != 1)
142 pr_err("Failed to send message: 0x%x\n", msg); 142 pr_err("Failed to send message: 0x%x\n", msg);
143 143
144 return 0; 144 return 0;
@@ -146,32 +146,32 @@ int vega10_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
146 146
147/* 147/*
148 * Send a message to the SMC with parameter 148 * Send a message to the SMC with parameter
149 * @param smumgr: the address of the powerplay hardware manager. 149 * @param hwmgr: the address of the powerplay hardware manager.
150 * @param msg: the message to send. 150 * @param msg: the message to send.
151 * @param parameter: the parameter to send 151 * @param parameter: the parameter to send
152 * @return Always return 0. 152 * @return Always return 0.
153 */ 153 */
154int vega10_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, 154int vega10_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
155 uint16_t msg, uint32_t parameter) 155 uint16_t msg, uint32_t parameter)
156{ 156{
157 uint32_t reg; 157 uint32_t reg;
158 158
159 if (!vega10_is_smc_ram_running(smumgr)) 159 if (!vega10_is_smc_ram_running(hwmgr))
160 return -EINVAL; 160 return -EINVAL;
161 161
162 vega10_wait_for_response(smumgr); 162 vega10_wait_for_response(hwmgr);
163 163
164 reg = soc15_get_register_offset(MP1_HWID, 0, 164 reg = soc15_get_register_offset(MP1_HWID, 0,
165 mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90); 165 mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
166 cgs_write_register(smumgr->device, reg, 0); 166 cgs_write_register(hwmgr->device, reg, 0);
167 167
168 reg = soc15_get_register_offset(MP1_HWID, 0, 168 reg = soc15_get_register_offset(MP1_HWID, 0,
169 mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82); 169 mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
170 cgs_write_register(smumgr->device, reg, parameter); 170 cgs_write_register(hwmgr->device, reg, parameter);
171 171
172 vega10_send_msg_to_smc_without_waiting(smumgr, msg); 172 vega10_send_msg_to_smc_without_waiting(hwmgr, msg);
173 173
174 if (vega10_wait_for_response(smumgr) != 1) 174 if (vega10_wait_for_response(hwmgr) != 1)
175 pr_err("Failed to send message: 0x%x\n", msg); 175 pr_err("Failed to send message: 0x%x\n", msg);
176 176
177 return 0; 177 return 0;
@@ -180,51 +180,51 @@ int vega10_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
180 180
181/* 181/*
182 * Send a message to the SMC with parameter, do not wait for response 182 * Send a message to the SMC with parameter, do not wait for response
183 * @param smumgr: the address of the powerplay hardware manager. 183 * @param hwmgr: the address of the powerplay hardware manager.
184 * @param msg: the message to send. 184 * @param msg: the message to send.
185 * @param parameter: the parameter to send 185 * @param parameter: the parameter to send
186 * @return The response that came from the SMC. 186 * @return The response that came from the SMC.
187 */ 187 */
188int vega10_send_msg_to_smc_with_parameter_without_waiting( 188int vega10_send_msg_to_smc_with_parameter_without_waiting(
189 struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter) 189 struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t parameter)
190{ 190{
191 uint32_t reg; 191 uint32_t reg;
192 192
193 reg = soc15_get_register_offset(MP1_HWID, 0, 193 reg = soc15_get_register_offset(MP1_HWID, 0,
194 mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82); 194 mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
195 cgs_write_register(smumgr->device, reg, parameter); 195 cgs_write_register(hwmgr->device, reg, parameter);
196 196
197 return vega10_send_msg_to_smc_without_waiting(smumgr, msg); 197 return vega10_send_msg_to_smc_without_waiting(hwmgr, msg);
198} 198}
199 199
200/* 200/*
201 * Retrieve an argument from SMC. 201 * Retrieve an argument from SMC.
202 * @param smumgr the address of the powerplay hardware manager. 202 * @param hwmgr the address of the powerplay hardware manager.
203 * @param arg pointer to store the argument from SMC. 203 * @param arg pointer to store the argument from SMC.
204 * @return Always return 0. 204 * @return Always return 0.
205 */ 205 */
206int vega10_read_arg_from_smc(struct pp_smumgr *smumgr, uint32_t *arg) 206int vega10_read_arg_from_smc(struct pp_hwmgr *hwmgr, uint32_t *arg)
207{ 207{
208 uint32_t reg; 208 uint32_t reg;
209 209
210 reg = soc15_get_register_offset(MP1_HWID, 0, 210 reg = soc15_get_register_offset(MP1_HWID, 0,
211 mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82); 211 mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
212 212
213 *arg = cgs_read_register(smumgr->device, reg); 213 *arg = cgs_read_register(hwmgr->device, reg);
214 214
215 return 0; 215 return 0;
216} 216}
217 217
218/* 218/*
219 * Copy table from SMC into driver FB 219 * Copy table from SMC into driver FB
220 * @param smumgr the address of the SMC manager 220 * @param hwmgr the address of the HW manager
221 * @param table_id the driver's table ID to copy from 221 * @param table_id the driver's table ID to copy from
222 */ 222 */
223int vega10_copy_table_from_smc(struct pp_smumgr *smumgr, 223int vega10_copy_table_from_smc(struct pp_hwmgr *hwmgr,
224 uint8_t *table, int16_t table_id) 224 uint8_t *table, int16_t table_id)
225{ 225{
226 struct vega10_smumgr *priv = 226 struct vega10_smumgr *priv =
227 (struct vega10_smumgr *)(smumgr->backend); 227 (struct vega10_smumgr *)(hwmgr->smumgr->backend);
228 228
229 PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, 229 PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
230 "Invalid SMU Table ID!", return -EINVAL); 230 "Invalid SMU Table ID!", return -EINVAL);
@@ -232,16 +232,16 @@ int vega10_copy_table_from_smc(struct pp_smumgr *smumgr,
232 "Invalid SMU Table version!", return -EINVAL); 232 "Invalid SMU Table version!", return -EINVAL);
233 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, 233 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
234 "Invalid SMU Table Length!", return -EINVAL); 234 "Invalid SMU Table Length!", return -EINVAL);
235 PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr, 235 PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(hwmgr,
236 PPSMC_MSG_SetDriverDramAddrHigh, 236 PPSMC_MSG_SetDriverDramAddrHigh,
237 priv->smu_tables.entry[table_id].table_addr_high) == 0, 237 priv->smu_tables.entry[table_id].table_addr_high) == 0,
238 "[CopyTableFromSMC] Attempt to Set Dram Addr High Failed!", return -EINVAL); 238 "[CopyTableFromSMC] Attempt to Set Dram Addr High Failed!", return -EINVAL);
239 PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr, 239 PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(hwmgr,
240 PPSMC_MSG_SetDriverDramAddrLow, 240 PPSMC_MSG_SetDriverDramAddrLow,
241 priv->smu_tables.entry[table_id].table_addr_low) == 0, 241 priv->smu_tables.entry[table_id].table_addr_low) == 0,
242 "[CopyTableFromSMC] Attempt to Set Dram Addr Low Failed!", 242 "[CopyTableFromSMC] Attempt to Set Dram Addr Low Failed!",
243 return -EINVAL); 243 return -EINVAL);
244 PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr, 244 PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(hwmgr,
245 PPSMC_MSG_TransferTableSmu2Dram, 245 PPSMC_MSG_TransferTableSmu2Dram,
246 priv->smu_tables.entry[table_id].table_id) == 0, 246 priv->smu_tables.entry[table_id].table_id) == 0,
247 "[CopyTableFromSMC] Attempt to Transfer Table From SMU Failed!", 247 "[CopyTableFromSMC] Attempt to Transfer Table From SMU Failed!",
@@ -255,14 +255,14 @@ int vega10_copy_table_from_smc(struct pp_smumgr *smumgr,
255 255
256/* 256/*
257 * Copy table from Driver FB into SMC 257 * Copy table from Driver FB into SMC
258 * @param smumgr the address of the SMC manager 258 * @param hwmgr the address of the HW manager
259 * @param table_id the table to copy from 259 * @param table_id the table to copy from
260 */ 260 */
261int vega10_copy_table_to_smc(struct pp_smumgr *smumgr, 261int vega10_copy_table_to_smc(struct pp_hwmgr *hwmgr,
262 uint8_t *table, int16_t table_id) 262 uint8_t *table, int16_t table_id)
263{ 263{
264 struct vega10_smumgr *priv = 264 struct vega10_smumgr *priv =
265 (struct vega10_smumgr *)(smumgr->backend); 265 (struct vega10_smumgr *)(hwmgr->smumgr->backend);
266 266
267 PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, 267 PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
268 "Invalid SMU Table ID!", return -EINVAL); 268 "Invalid SMU Table ID!", return -EINVAL);
@@ -274,17 +274,17 @@ int vega10_copy_table_to_smc(struct pp_smumgr *smumgr,
274 memcpy(priv->smu_tables.entry[table_id].table, table, 274 memcpy(priv->smu_tables.entry[table_id].table, table,
275 priv->smu_tables.entry[table_id].size); 275 priv->smu_tables.entry[table_id].size);
276 276
277 PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr, 277 PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(hwmgr,
278 PPSMC_MSG_SetDriverDramAddrHigh, 278 PPSMC_MSG_SetDriverDramAddrHigh,
279 priv->smu_tables.entry[table_id].table_addr_high) == 0, 279 priv->smu_tables.entry[table_id].table_addr_high) == 0,
280 "[CopyTableToSMC] Attempt to Set Dram Addr High Failed!", 280 "[CopyTableToSMC] Attempt to Set Dram Addr High Failed!",
281 return -EINVAL;); 281 return -EINVAL;);
282 PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr, 282 PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(hwmgr,
283 PPSMC_MSG_SetDriverDramAddrLow, 283 PPSMC_MSG_SetDriverDramAddrLow,
284 priv->smu_tables.entry[table_id].table_addr_low) == 0, 284 priv->smu_tables.entry[table_id].table_addr_low) == 0,
285 "[CopyTableToSMC] Attempt to Set Dram Addr Low Failed!", 285 "[CopyTableToSMC] Attempt to Set Dram Addr Low Failed!",
286 return -EINVAL); 286 return -EINVAL);
287 PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr, 287 PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(hwmgr,
288 PPSMC_MSG_TransferTableDram2Smu, 288 PPSMC_MSG_TransferTableDram2Smu,
289 priv->smu_tables.entry[table_id].table_id) == 0, 289 priv->smu_tables.entry[table_id].table_id) == 0,
290 "[CopyTableToSMC] Attempt to Transfer Table To SMU Failed!", 290 "[CopyTableToSMC] Attempt to Transfer Table To SMU Failed!",
@@ -293,87 +293,87 @@ int vega10_copy_table_to_smc(struct pp_smumgr *smumgr,
293 return 0; 293 return 0;
294} 294}
295 295
296int vega10_save_vft_table(struct pp_smumgr *smumgr, uint8_t *avfs_table) 296int vega10_save_vft_table(struct pp_hwmgr *hwmgr, uint8_t *avfs_table)
297{ 297{
298 PP_ASSERT_WITH_CODE(avfs_table, 298 PP_ASSERT_WITH_CODE(avfs_table,
299 "No access to SMC AVFS Table", 299 "No access to SMC AVFS Table",
300 return -EINVAL); 300 return -EINVAL);
301 301
302 return vega10_copy_table_from_smc(smumgr, avfs_table, AVFSTABLE); 302 return vega10_copy_table_from_smc(hwmgr, avfs_table, AVFSTABLE);
303} 303}
304 304
305int vega10_restore_vft_table(struct pp_smumgr *smumgr, uint8_t *avfs_table) 305int vega10_restore_vft_table(struct pp_hwmgr *hwmgr, uint8_t *avfs_table)
306{ 306{
307 PP_ASSERT_WITH_CODE(avfs_table, 307 PP_ASSERT_WITH_CODE(avfs_table,
308 "No access to SMC AVFS Table", 308 "No access to SMC AVFS Table",
309 return -EINVAL); 309 return -EINVAL);
310 310
311 return vega10_copy_table_to_smc(smumgr, avfs_table, AVFSTABLE); 311 return vega10_copy_table_to_smc(hwmgr, avfs_table, AVFSTABLE);
312} 312}
313 313
314int vega10_enable_smc_features(struct pp_smumgr *smumgr, 314int vega10_enable_smc_features(struct pp_hwmgr *hwmgr,
315 bool enable, uint32_t feature_mask) 315 bool enable, uint32_t feature_mask)
316{ 316{
317 int msg = enable ? PPSMC_MSG_EnableSmuFeatures : 317 int msg = enable ? PPSMC_MSG_EnableSmuFeatures :
318 PPSMC_MSG_DisableSmuFeatures; 318 PPSMC_MSG_DisableSmuFeatures;
319 319
320 return vega10_send_msg_to_smc_with_parameter(smumgr, 320 return vega10_send_msg_to_smc_with_parameter(hwmgr,
321 msg, feature_mask); 321 msg, feature_mask);
322} 322}
323 323
324int vega10_get_smc_features(struct pp_smumgr *smumgr, 324int vega10_get_smc_features(struct pp_hwmgr *hwmgr,
325 uint32_t *features_enabled) 325 uint32_t *features_enabled)
326{ 326{
327 if (features_enabled == NULL) 327 if (features_enabled == NULL)
328 return -EINVAL; 328 return -EINVAL;
329 329
330 if (!vega10_send_msg_to_smc(smumgr, 330 if (!vega10_send_msg_to_smc(hwmgr,
331 PPSMC_MSG_GetEnabledSmuFeatures)) { 331 PPSMC_MSG_GetEnabledSmuFeatures)) {
332 vega10_read_arg_from_smc(smumgr, features_enabled); 332 vega10_read_arg_from_smc(hwmgr, features_enabled);
333 return 0; 333 return 0;
334 } 334 }
335 335
336 return -EINVAL; 336 return -EINVAL;
337} 337}
338 338
339int vega10_set_tools_address(struct pp_smumgr *smumgr) 339int vega10_set_tools_address(struct pp_hwmgr *hwmgr)
340{ 340{
341 struct vega10_smumgr *priv = 341 struct vega10_smumgr *priv =
342 (struct vega10_smumgr *)(smumgr->backend); 342 (struct vega10_smumgr *)(hwmgr->smumgr->backend);
343 343
344 if (priv->smu_tables.entry[TOOLSTABLE].table_addr_high || 344 if (priv->smu_tables.entry[TOOLSTABLE].table_addr_high ||
345 priv->smu_tables.entry[TOOLSTABLE].table_addr_low) { 345 priv->smu_tables.entry[TOOLSTABLE].table_addr_low) {
346 if (!vega10_send_msg_to_smc_with_parameter(smumgr, 346 if (!vega10_send_msg_to_smc_with_parameter(hwmgr,
347 PPSMC_MSG_SetToolsDramAddrHigh, 347 PPSMC_MSG_SetToolsDramAddrHigh,
348 priv->smu_tables.entry[TOOLSTABLE].table_addr_high)) 348 priv->smu_tables.entry[TOOLSTABLE].table_addr_high))
349 vega10_send_msg_to_smc_with_parameter(smumgr, 349 vega10_send_msg_to_smc_with_parameter(hwmgr,
350 PPSMC_MSG_SetToolsDramAddrLow, 350 PPSMC_MSG_SetToolsDramAddrLow,
351 priv->smu_tables.entry[TOOLSTABLE].table_addr_low); 351 priv->smu_tables.entry[TOOLSTABLE].table_addr_low);
352 } 352 }
353 return 0; 353 return 0;
354} 354}
355 355
356static int vega10_verify_smc_interface(struct pp_smumgr *smumgr) 356static int vega10_verify_smc_interface(struct pp_hwmgr *hwmgr)
357{ 357{
358 uint32_t smc_driver_if_version; 358 uint32_t smc_driver_if_version;
359 struct cgs_system_info sys_info = {0}; 359 struct cgs_system_info sys_info = {0};
360 uint32_t dev_id; 360 uint32_t dev_id;
361 uint32_t rev_id; 361 uint32_t rev_id;
362 362
363 PP_ASSERT_WITH_CODE(!vega10_send_msg_to_smc(smumgr, 363 PP_ASSERT_WITH_CODE(!vega10_send_msg_to_smc(hwmgr,
364 PPSMC_MSG_GetDriverIfVersion), 364 PPSMC_MSG_GetDriverIfVersion),
365 "Attempt to get SMC IF Version Number Failed!", 365 "Attempt to get SMC IF Version Number Failed!",
366 return -EINVAL); 366 return -EINVAL);
367 vega10_read_arg_from_smc(smumgr, &smc_driver_if_version); 367 vega10_read_arg_from_smc(hwmgr, &smc_driver_if_version);
368 368
369 sys_info.size = sizeof(struct cgs_system_info); 369 sys_info.size = sizeof(struct cgs_system_info);
370 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV; 370 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV;
371 cgs_query_system_info(smumgr->device, &sys_info); 371 cgs_query_system_info(hwmgr->device, &sys_info);
372 dev_id = (uint32_t)sys_info.value; 372 dev_id = (uint32_t)sys_info.value;
373 373
374 sys_info.size = sizeof(struct cgs_system_info); 374 sys_info.size = sizeof(struct cgs_system_info);
375 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_REV; 375 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_REV;
376 cgs_query_system_info(smumgr->device, &sys_info); 376 cgs_query_system_info(hwmgr->device, &sys_info);
377 rev_id = (uint32_t)sys_info.value; 377 rev_id = (uint32_t)sys_info.value;
378 378
379 if (!((dev_id == 0x687f) && 379 if (!((dev_id == 0x687f) &&
@@ -392,7 +392,7 @@ static int vega10_verify_smc_interface(struct pp_smumgr *smumgr)
392 return 0; 392 return 0;
393} 393}
394 394
395static int vega10_smu_init(struct pp_smumgr *smumgr) 395static int vega10_smu_init(struct pp_hwmgr *hwmgr)
396{ 396{
397 struct vega10_smumgr *priv; 397 struct vega10_smumgr *priv;
398 uint64_t mc_addr; 398 uint64_t mc_addr;
@@ -401,7 +401,7 @@ static int vega10_smu_init(struct pp_smumgr *smumgr)
401 int ret; 401 int ret;
402 struct cgs_firmware_info info = {0}; 402 struct cgs_firmware_info info = {0};
403 403
404 ret = cgs_get_firmware_info(smumgr->device, 404 ret = cgs_get_firmware_info(hwmgr->device,
405 smu7_convert_fw_type_to_cgs(UCODE_ID_SMU), 405 smu7_convert_fw_type_to_cgs(UCODE_ID_SMU),
406 &info); 406 &info);
407 if (ret || !info.kptr) 407 if (ret || !info.kptr)
@@ -412,10 +412,10 @@ static int vega10_smu_init(struct pp_smumgr *smumgr)
412 if (!priv) 412 if (!priv)
413 return -ENOMEM; 413 return -ENOMEM;
414 414
415 smumgr->backend = priv; 415 hwmgr->smumgr->backend = priv;
416 416
417 /* allocate space for pptable */ 417 /* allocate space for pptable */
418 smu_allocate_memory(smumgr->device, 418 smu_allocate_memory(hwmgr->device,
419 sizeof(PPTable_t), 419 sizeof(PPTable_t),
420 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB, 420 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
421 PAGE_SIZE, 421 PAGE_SIZE,
@@ -425,8 +425,8 @@ static int vega10_smu_init(struct pp_smumgr *smumgr)
425 425
426 PP_ASSERT_WITH_CODE(kaddr, 426 PP_ASSERT_WITH_CODE(kaddr,
427 "[vega10_smu_init] Out of memory for pptable.", 427 "[vega10_smu_init] Out of memory for pptable.",
428 kfree(smumgr->backend); 428 kfree(hwmgr->smumgr->backend);
429 cgs_free_gpu_mem(smumgr->device, 429 cgs_free_gpu_mem(hwmgr->device,
430 (cgs_handle_t)handle); 430 (cgs_handle_t)handle);
431 return -EINVAL); 431 return -EINVAL);
432 432
@@ -441,7 +441,7 @@ static int vega10_smu_init(struct pp_smumgr *smumgr)
441 priv->smu_tables.entry[PPTABLE].handle = handle; 441 priv->smu_tables.entry[PPTABLE].handle = handle;
442 442
443 /* allocate space for watermarks table */ 443 /* allocate space for watermarks table */
444 smu_allocate_memory(smumgr->device, 444 smu_allocate_memory(hwmgr->device,
445 sizeof(Watermarks_t), 445 sizeof(Watermarks_t),
446 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB, 446 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
447 PAGE_SIZE, 447 PAGE_SIZE,
@@ -451,10 +451,10 @@ static int vega10_smu_init(struct pp_smumgr *smumgr)
451 451
452 PP_ASSERT_WITH_CODE(kaddr, 452 PP_ASSERT_WITH_CODE(kaddr,
453 "[vega10_smu_init] Out of memory for wmtable.", 453 "[vega10_smu_init] Out of memory for wmtable.",
454 kfree(smumgr->backend); 454 kfree(hwmgr->smumgr->backend);
455 cgs_free_gpu_mem(smumgr->device, 455 cgs_free_gpu_mem(hwmgr->device,
456 (cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle); 456 (cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle);
457 cgs_free_gpu_mem(smumgr->device, 457 cgs_free_gpu_mem(hwmgr->device,
458 (cgs_handle_t)handle); 458 (cgs_handle_t)handle);
459 return -EINVAL); 459 return -EINVAL);
460 460
@@ -469,7 +469,7 @@ static int vega10_smu_init(struct pp_smumgr *smumgr)
469 priv->smu_tables.entry[WMTABLE].handle = handle; 469 priv->smu_tables.entry[WMTABLE].handle = handle;
470 470
471 /* allocate space for AVFS table */ 471 /* allocate space for AVFS table */
472 smu_allocate_memory(smumgr->device, 472 smu_allocate_memory(hwmgr->device,
473 sizeof(AvfsTable_t), 473 sizeof(AvfsTable_t),
474 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB, 474 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
475 PAGE_SIZE, 475 PAGE_SIZE,
@@ -479,12 +479,12 @@ static int vega10_smu_init(struct pp_smumgr *smumgr)
479 479
480 PP_ASSERT_WITH_CODE(kaddr, 480 PP_ASSERT_WITH_CODE(kaddr,
481 "[vega10_smu_init] Out of memory for avfs table.", 481 "[vega10_smu_init] Out of memory for avfs table.",
482 kfree(smumgr->backend); 482 kfree(hwmgr->smumgr->backend);
483 cgs_free_gpu_mem(smumgr->device, 483 cgs_free_gpu_mem(hwmgr->device,
484 (cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle); 484 (cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle);
485 cgs_free_gpu_mem(smumgr->device, 485 cgs_free_gpu_mem(hwmgr->device,
486 (cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle); 486 (cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle);
487 cgs_free_gpu_mem(smumgr->device, 487 cgs_free_gpu_mem(hwmgr->device,
488 (cgs_handle_t)handle); 488 (cgs_handle_t)handle);
489 return -EINVAL); 489 return -EINVAL);
490 490
@@ -500,7 +500,7 @@ static int vega10_smu_init(struct pp_smumgr *smumgr)
500 500
501 tools_size = 0x19000; 501 tools_size = 0x19000;
502 if (tools_size) { 502 if (tools_size) {
503 smu_allocate_memory(smumgr->device, 503 smu_allocate_memory(hwmgr->device,
504 tools_size, 504 tools_size,
505 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB, 505 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
506 PAGE_SIZE, 506 PAGE_SIZE,
@@ -522,7 +522,7 @@ static int vega10_smu_init(struct pp_smumgr *smumgr)
522 } 522 }
523 523
524 /* allocate space for AVFS Fuse table */ 524 /* allocate space for AVFS Fuse table */
525 smu_allocate_memory(smumgr->device, 525 smu_allocate_memory(hwmgr->device,
526 sizeof(AvfsFuseOverride_t), 526 sizeof(AvfsFuseOverride_t),
527 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB, 527 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
528 PAGE_SIZE, 528 PAGE_SIZE,
@@ -532,16 +532,16 @@ static int vega10_smu_init(struct pp_smumgr *smumgr)
532 532
533 PP_ASSERT_WITH_CODE(kaddr, 533 PP_ASSERT_WITH_CODE(kaddr,
534 "[vega10_smu_init] Out of memory for avfs fuse table.", 534 "[vega10_smu_init] Out of memory for avfs fuse table.",
535 kfree(smumgr->backend); 535 kfree(hwmgr->smumgr->backend);
536 cgs_free_gpu_mem(smumgr->device, 536 cgs_free_gpu_mem(hwmgr->device,
537 (cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle); 537 (cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle);
538 cgs_free_gpu_mem(smumgr->device, 538 cgs_free_gpu_mem(hwmgr->device,
539 (cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle); 539 (cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle);
540 cgs_free_gpu_mem(smumgr->device, 540 cgs_free_gpu_mem(hwmgr->device,
541 (cgs_handle_t)priv->smu_tables.entry[AVFSTABLE].handle); 541 (cgs_handle_t)priv->smu_tables.entry[AVFSTABLE].handle);
542 cgs_free_gpu_mem(smumgr->device, 542 cgs_free_gpu_mem(hwmgr->device,
543 (cgs_handle_t)priv->smu_tables.entry[TOOLSTABLE].handle); 543 (cgs_handle_t)priv->smu_tables.entry[TOOLSTABLE].handle);
544 cgs_free_gpu_mem(smumgr->device, 544 cgs_free_gpu_mem(hwmgr->device,
545 (cgs_handle_t)handle); 545 (cgs_handle_t)handle);
546 return -EINVAL); 546 return -EINVAL);
547 547
@@ -558,36 +558,36 @@ static int vega10_smu_init(struct pp_smumgr *smumgr)
558 return 0; 558 return 0;
559} 559}
560 560
561static int vega10_smu_fini(struct pp_smumgr *smumgr) 561static int vega10_smu_fini(struct pp_hwmgr *hwmgr)
562{ 562{
563 struct vega10_smumgr *priv = 563 struct vega10_smumgr *priv =
564 (struct vega10_smumgr *)(smumgr->backend); 564 (struct vega10_smumgr *)(hwmgr->smumgr->backend);
565 565
566 if (priv) { 566 if (priv) {
567 cgs_free_gpu_mem(smumgr->device, 567 cgs_free_gpu_mem(hwmgr->device,
568 (cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle); 568 (cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle);
569 cgs_free_gpu_mem(smumgr->device, 569 cgs_free_gpu_mem(hwmgr->device,
570 (cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle); 570 (cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle);
571 cgs_free_gpu_mem(smumgr->device, 571 cgs_free_gpu_mem(hwmgr->device,
572 (cgs_handle_t)priv->smu_tables.entry[AVFSTABLE].handle); 572 (cgs_handle_t)priv->smu_tables.entry[AVFSTABLE].handle);
573 if (priv->smu_tables.entry[TOOLSTABLE].table) 573 if (priv->smu_tables.entry[TOOLSTABLE].table)
574 cgs_free_gpu_mem(smumgr->device, 574 cgs_free_gpu_mem(hwmgr->device,
575 (cgs_handle_t)priv->smu_tables.entry[TOOLSTABLE].handle); 575 (cgs_handle_t)priv->smu_tables.entry[TOOLSTABLE].handle);
576 cgs_free_gpu_mem(smumgr->device, 576 cgs_free_gpu_mem(hwmgr->device,
577 (cgs_handle_t)priv->smu_tables.entry[AVFSFUSETABLE].handle); 577 (cgs_handle_t)priv->smu_tables.entry[AVFSFUSETABLE].handle);
578 kfree(smumgr->backend); 578 kfree(hwmgr->smumgr->backend);
579 smumgr->backend = NULL; 579 hwmgr->smumgr->backend = NULL;
580 } 580 }
581 return 0; 581 return 0;
582} 582}
583 583
584static int vega10_start_smu(struct pp_smumgr *smumgr) 584static int vega10_start_smu(struct pp_hwmgr *hwmgr)
585{ 585{
586 PP_ASSERT_WITH_CODE(!vega10_verify_smc_interface(smumgr), 586 PP_ASSERT_WITH_CODE(!vega10_verify_smc_interface(hwmgr),
587 "Failed to verify SMC interface!", 587 "Failed to verify SMC interface!",
588 return -EINVAL); 588 return -EINVAL);
589 589
590 vega10_set_tools_address(smumgr); 590 vega10_set_tools_address(hwmgr);
591 591
592 return 0; 592 return 0;
593} 593}
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h
index 821425c1e4e0..0695455b21b2 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h
@@ -52,19 +52,19 @@ struct vega10_smumgr {
52 struct smu_table_array smu_tables; 52 struct smu_table_array smu_tables;
53}; 53};
54 54
55int vega10_read_arg_from_smc(struct pp_smumgr *smumgr, uint32_t *arg); 55int vega10_read_arg_from_smc(struct pp_hwmgr *hwmgr, uint32_t *arg);
56int vega10_copy_table_from_smc(struct pp_smumgr *smumgr, 56int vega10_copy_table_from_smc(struct pp_hwmgr *hwmgr,
57 uint8_t *table, int16_t table_id); 57 uint8_t *table, int16_t table_id);
58int vega10_copy_table_to_smc(struct pp_smumgr *smumgr, 58int vega10_copy_table_to_smc(struct pp_hwmgr *hwmgr,
59 uint8_t *table, int16_t table_id); 59 uint8_t *table, int16_t table_id);
60int vega10_enable_smc_features(struct pp_smumgr *smumgr, 60int vega10_enable_smc_features(struct pp_hwmgr *hwmgr,
61 bool enable, uint32_t feature_mask); 61 bool enable, uint32_t feature_mask);
62int vega10_get_smc_features(struct pp_smumgr *smumgr, 62int vega10_get_smc_features(struct pp_hwmgr *hwmgr,
63 uint32_t *features_enabled); 63 uint32_t *features_enabled);
64int vega10_save_vft_table(struct pp_smumgr *smumgr, uint8_t *avfs_table); 64int vega10_save_vft_table(struct pp_hwmgr *hwmgr, uint8_t *avfs_table);
65int vega10_restore_vft_table(struct pp_smumgr *smumgr, uint8_t *avfs_table); 65int vega10_restore_vft_table(struct pp_hwmgr *hwmgr, uint8_t *avfs_table);
66 66
67int vega10_set_tools_address(struct pp_smumgr *smumgr); 67int vega10_set_tools_address(struct pp_hwmgr *hwmgr);
68 68
69#endif 69#endif
70 70
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-31 16:40:20 -0400