Merge tag 'v5.2-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip

Pull Rockchip clk driver updates from Heiko Stuebner:

 - Fixes for rk3328 and rk3288
 - New sub-type for an upcoming SoC where mux and divider
   are not necessarily in the same register anymore

* tag 'v5.2-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: undo several noc and special clocks as critical on rk3288
  clk: rockchip: add a COMPOSITE_DIV_OFFSET clock-type
  clk: rockchip: Turn on "aclk_dmac1" for suspend on rk3288
  clk: rockchip: Limit use of USB PHY clock to USB on rk3288
  clk: rockchip: Fix video codec clocks on rk3288
  clk: rockchip: Make rkpwm a critical clock on rk3288
  clk: rockchip: fix wrong clock definitions for rk3328

4 files changed, 60 insertions, 26 deletions

diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 5a67b7869960..24baeb56a1b3 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -200,8 +200,8 @@ PNAME(mux_aclk_cpu_src_p)	= { "cpll_aclk_cpu", "gpll_aclk_cpu" };
 PNAME(mux_pll_src_cpll_gpll_p)          = { "cpll", "gpll" };
 PNAME(mux_pll_src_npll_cpll_gpll_p)     = { "npll", "cpll", "gpll" };
 PNAME(mux_pll_src_cpll_gpll_npll_p)     = { "cpll", "gpll", "npll" };
-PNAME(mux_pll_src_cpll_gpll_usb480m_p)  = { "cpll", "gpll", "usbphy480m_src" };
-PNAME(mux_pll_src_cpll_gll_usb_npll_p)  = { "cpll", "gpll", "usbphy480m_src", "npll" };
+PNAME(mux_pll_src_cpll_gpll_usb480m_p)  = { "cpll", "gpll", "unstable:usbphy480m_src" };
+PNAME(mux_pll_src_cpll_gll_usb_npll_p)  = { "cpll", "gpll", "unstable:usbphy480m_src", "npll" };
 
 PNAME(mux_mmc_src_p)    = { "cpll", "gpll", "xin24m", "xin24m" };
 PNAME(mux_i2s_pre_p)    = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
@@ -219,7 +219,7 @@ PNAME(mux_hsadcout_p)	= { "hsadc_src", "ext_hsadc" };
 PNAME(mux_edp_24m_p)    = { "ext_edp_24m", "xin24m" };
 PNAME(mux_tspout_p)     = { "cpll", "gpll", "npll", "xin27m" };
 
-PNAME(mux_aclk_vcodec_pre_p)    = { "aclk_vepu", "aclk_vdpu" };
+PNAME(mux_aclk_vcodec_pre_p)    = { "aclk_vdpu", "aclk_vepu" };
 PNAME(mux_usbphy480m_p)         = { "sclk_otgphy1_480m", "sclk_otgphy2_480m",
                                     "sclk_otgphy0_480m" };
 PNAME(mux_hsicphy480m_p)        = { "cpll", "gpll", "usbphy480m_src" };
@@ -313,13 +313,13 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
         COMPOSITE_NOMUX(0, "aclk_core_mp", "armclk", CLK_IGNORE_UNUSED,
                         RK3288_CLKSEL_CON(0), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
                         RK3288_CLKGATE_CON(12), 6, GFLAGS),
-        COMPOSITE_NOMUX(0, "atclk", "armclk", CLK_IGNORE_UNUSED,
+        COMPOSITE_NOMUX(0, "atclk", "armclk", 0,
                         RK3288_CLKSEL_CON(37), 4, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
                         RK3288_CLKGATE_CON(12), 7, GFLAGS),
         COMPOSITE_NOMUX(0, "pclk_dbg_pre", "armclk", CLK_IGNORE_UNUSED,
                         RK3288_CLKSEL_CON(37), 9, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
                         RK3288_CLKGATE_CON(12), 8, GFLAGS),
-        GATE(0, "pclk_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED,
+        GATE(0, "pclk_dbg", "pclk_dbg_pre", 0,
                         RK3288_CLKGATE_CON(12), 9, GFLAGS),
         GATE(0, "cs_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED,
                         RK3288_CLKGATE_CON(12), 10, GFLAGS),
@@ -420,7 +420,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
         COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb480m_p, 0,
                         RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
                         RK3288_CLKGATE_CON(3), 11, GFLAGS),
-        MUXGRF(0, "aclk_vcodec_pre", mux_aclk_vcodec_pre_p, 0,
+        MUXGRF(0, "aclk_vcodec_pre", mux_aclk_vcodec_pre_p, CLK_SET_RATE_PARENT,
                         RK3288_GRF_SOC_CON(0), 7, 1, MFLAGS),
         GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 0,
                 RK3288_CLKGATE_CON(9), 0, GFLAGS),
@@ -647,7 +647,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
         INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out",
                         RK3288_CLKSEL_CON(22), 7, IFLAGS),
 
-        GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
+        GATE(0, "jtag", "ext_jtag", 0,
                         RK3288_CLKGATE_CON(4), 14, GFLAGS),
 
         COMPOSITE_NODIV(SCLK_USBPHY480M_SRC, "usbphy480m_src", mux_usbphy480m_p, 0,
@@ -656,7 +656,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
         COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0,
                         RK3288_CLKSEL_CON(29), 0, 2, MFLAGS,
                         RK3288_CLKGATE_CON(3), 6, GFLAGS),
-        GATE(0, "hsicphy12m_xin12m", "xin12m", CLK_IGNORE_UNUSED,
+        GATE(0, "hsicphy12m_xin12m", "xin12m", 0,
                         RK3288_CLKGATE_CON(13), 9, GFLAGS),
         DIV(0, "hsicphy12m_usbphy", "sclk_hsicphy480m", 0,
                         RK3288_CLKSEL_CON(11), 8, 6, DFLAGS),
@@ -697,7 +697,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
         GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 3, GFLAGS),
         GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 9, GFLAGS),
         GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS),
-        GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 11, GFLAGS),
+        GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 11, GFLAGS),
 
         /* ddrctrl [DDR Controller PHY clock] gates */
         GATE(0, "nclk_ddrupctl0", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 4, GFLAGS),
@@ -837,12 +837,9 @@ static const char *const rk3288_critical_clocks[] __initconst = {
         "pclk_alive_niu",
         "pclk_pd_pmu",
         "pclk_pmu_niu",
-        "pclk_core_niu",
-        "pclk_ddrupctl0",
-        "pclk_publ0",
-        "pclk_ddrupctl1",
-        "pclk_publ1",
         "pmu_hclk_otg0",
+        /* pwm-regulators on some boards, so handoff-critical later */
+        "pclk_rkpwm",
 };
 
 static void __iomem *rk3288_cru_base;
@@ -859,6 +856,9 @@ static const int rk3288_saved_cru_reg_ids[] = {
         RK3288_CLKSEL_CON(10),
         RK3288_CLKSEL_CON(33),
         RK3288_CLKSEL_CON(37),
+
+        /* We turn aclk_dmac1 on for suspend; this will restore it */
+        RK3288_CLKGATE_CON(10),
 };
 
 static u32 rk3288_saved_cru_regs[ARRAY_SIZE(rk3288_saved_cru_reg_ids)];
@@ -875,6 +875,14 @@ static int rk3288_clk_suspend(void)
         }
 
         /*
+         * Going into deep sleep (specifically setting PMU_CLR_DMA in
+         * RK3288_PMU_PWRMODE_CON1) appears to fail unless
+         * "aclk_dmac1" is on.
+         */
+        writel_relaxed(1 << (12 + 16),
+                       rk3288_cru_base + RK3288_CLKGATE_CON(10));
+
+        /*
          * Switch PLLs other than DPLL (for SDRAM) to slow mode to
          * avoid crashes on resume. The Mask ROM on the system will
          * put APLL, CPLL, and GPLL into slow mode at resume time
diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c
index 65ab5c2f48b0..f12142d9cea2 100644
--- a/drivers/clk/rockchip/clk-rk3328.c
+++ b/drivers/clk/rockchip/clk-rk3328.c
@@ -458,7 +458,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
                         RK3328_CLKSEL_CON(35), 15, 1, MFLAGS, 8, 7, DFLAGS,
                         RK3328_CLKGATE_CON(2), 12, GFLAGS),
         COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_2plls_p, 0,
-                        RK3328_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 7, DFLAGS,
+                        RK3328_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 5, DFLAGS,
                         RK3328_CLKGATE_CON(2), 4, GFLAGS),
         COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "clk_24m", 0,
                         RK3328_CLKSEL_CON(22), 0, 10, DFLAGS,
@@ -550,15 +550,15 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
         GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc", 0,
                         RK3328_CLKGATE_CON(25), 1, GFLAGS),
         GATE(ACLK_H265, "aclk_h265", "aclk_rkvenc", 0,
-                        RK3328_CLKGATE_CON(25), 0, GFLAGS),
+                        RK3328_CLKGATE_CON(25), 2, GFLAGS),
         GATE(PCLK_H265, "pclk_h265", "hclk_rkvenc", 0,
-                        RK3328_CLKGATE_CON(25), 1, GFLAGS),
+                        RK3328_CLKGATE_CON(25), 3, GFLAGS),
         GATE(ACLK_H264, "aclk_h264", "aclk_rkvenc", 0,
-                        RK3328_CLKGATE_CON(25), 0, GFLAGS),
+                        RK3328_CLKGATE_CON(25), 4, GFLAGS),
         GATE(HCLK_H264, "hclk_h264", "hclk_rkvenc", 0,
-                        RK3328_CLKGATE_CON(25), 1, GFLAGS),
+                        RK3328_CLKGATE_CON(25), 5, GFLAGS),
         GATE(ACLK_AXISRAM, "aclk_axisram", "aclk_rkvenc", CLK_IGNORE_UNUSED,
-                        RK3328_CLKGATE_CON(25), 0, GFLAGS),
+                        RK3328_CLKGATE_CON(25), 6, GFLAGS),
 
         COMPOSITE(SCLK_VENC_CORE, "sclk_venc_core", mux_4plls_p, 0,
                         RK3328_CLKSEL_CON(51), 14, 2, MFLAGS, 8, 5, DFLAGS,
@@ -663,7 +663,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
 
         /* PD_GMAC */
         COMPOSITE(ACLK_GMAC, "aclk_gmac", mux_2plls_hdmiphy_p, 0,
-                        RK3328_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
+                        RK3328_CLKSEL_CON(25), 6, 2, MFLAGS, 0, 5, DFLAGS,
                         RK3328_CLKGATE_CON(3), 2, GFLAGS),
         COMPOSITE_NOMUX(PCLK_GMAC, "pclk_gmac", "aclk_gmac", 0,
                         RK3328_CLKSEL_CON(25), 8, 3, DFLAGS,
@@ -733,7 +733,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
 
         /* PD_PERI */
         GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(19), 11, GFLAGS),
-        GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 0, RK3328_CLKGATE_CON(19), 4, GFLAGS),
+        GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 0, RK3328_CLKGATE_CON(19), 14, GFLAGS),
 
         GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 0, GFLAGS),
         GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 1, GFLAGS),
@@ -913,7 +913,7 @@ static void __init rk3328_clk_init(struct device_node *np)
                                      &rk3328_cpuclk_data, rk3328_cpuclk_rates,
                                      ARRAY_SIZE(rk3328_cpuclk_rates));
 
-        rockchip_register_softrst(np, 11, reg_base + RK3328_SOFTRST_CON(0),
+        rockchip_register_softrst(np, 12, reg_base + RK3328_SOFTRST_CON(0),
                                   ROCKCHIP_SOFTRST_HIWORD_MASK);
 
         rockchip_register_restart_notifier(ctx, RK3328_GLB_SRST_FST, NULL);
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index c3ad92965823..0ea8e8080d1a 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -46,7 +46,7 @@ static struct clk *rockchip_clk_register_branch(const char *name,
                 const char *const *parent_names, u8 num_parents,
                 void __iomem *base,
                 int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags,
-                u8 div_shift, u8 div_width, u8 div_flags,
+                int div_offset, u8 div_shift, u8 div_width, u8 div_flags,
                 struct clk_div_table *div_table, int gate_offset,
                 u8 gate_shift, u8 gate_flags, unsigned long flags,
                 spinlock_t *lock)
@@ -95,7 +95,10 @@ static struct clk *rockchip_clk_register_branch(const char *name,
                 }
 
                 div->flags = div_flags;
-                div->reg = base + muxdiv_offset;
+                if (div_offset)
+                        div->reg = base + div_offset;
+                else
+                        div->reg = base + muxdiv_offset;
                 div->shift = div_shift;
                 div->width = div_width;
                 div->lock = lock;
@@ -516,7 +519,7 @@ void __init rockchip_clk_register_branches(
                                 ctx->reg_base, list->muxdiv_offset,
                                 list->mux_shift,
                                 list->mux_width, list->mux_flags,
-                                list->div_shift, list->div_width,
+                                list->div_offset, list->div_shift, list->div_width,
                                 list->div_flags, list->div_table,
                                 list->gate_offset, list->gate_shift,
                                 list->gate_flags, flags, &ctx->lock);
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 6b53fff4cc96..1b5270755431 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -407,6 +407,7 @@ struct rockchip_clk_branch {
         u8                              mux_shift;
         u8                              mux_width;
         u8                              mux_flags;
+        int                             div_offset;
         u8                              div_shift;
         u8                              div_width;
         u8                              div_flags;
@@ -438,6 +439,28 @@ struct rockchip_clk_branch {
                 .gate_flags     = gf,                           \
         }
 
+#define COMPOSITE_DIV_OFFSET(_id, cname, pnames, f, mo, ms, mw, \
+                             mf, do, ds, dw, df, go, gs, gf)    \
+        {                                                       \
+                .id             = _id,                          \
+                .branch_type    = branch_composite,             \
+                .name           = cname,                        \
+                .parent_names   = pnames,                       \
+                .num_parents    = ARRAY_SIZE(pnames),           \
+                .flags          = f,                            \
+                .muxdiv_offset  = mo,                           \
+                .mux_shift      = ms,                           \
+                .mux_width      = mw,                           \
+                .mux_flags      = mf,                           \
+                .div_offset     = do,                           \
+                .div_shift      = ds,                           \
+                .div_width      = dw,                           \
+                .div_flags      = df,                           \
+                .gate_offset    = go,                           \
+                .gate_shift     = gs,                           \
+                .gate_flags     = gf,                           \
+        }
+
 #define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df,   \
                         go, gs, gf)                             \
         {                                                       \