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authorLukas Wunner <lukas@wunner.de>2017-11-24 18:33:27 -0500
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2017-11-28 09:35:51 -0500
commitd3a96c94163b7c577f4505168d0041ce9ee32a96 (patch)
tree729481afc034180abb8e4686971359baf77f9479
parentd8dcbdd08c653d9a6754b3c775f13cb987fa91ec (diff)
serial: pl011: Use cached copy of IMSC register
Commit 075167ed71b7 ("drivers: PL011: replace UART_MIS reading with _RIS & _IMSC") amended this driver's interrupt handler to read the Raw Interrupt Status (RIS) and Interrupt Mask Set/Clear (IMSC) registers instead of the Masked Interrupt Status (MIS) register. The change was made to attain compatibility with SBSA UARTs which lack the MIS register. However the IMSC register is cached by the driver. Using the cached copy saves one register read per interrupt. I've tested this change successfully on a BCM2837 (Raspberry Pi CM3). Cc: Mathias Duckeck <m.duckeck@kunbus.de> Cc: Phil Elwell <phil@raspberrypi.org> Cc: Stefan Wahren <stefan.wahren@i2se.com> Cc: Andre Przywara <andre.przywara@arm.com> Cc: Mark Langsdorf <mlangsdo@redhat.com> Cc: Naresh Bhat <nbhat@cavium.com> Cc: Russell King <linux@armlinux.org.uk> Signed-off-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r--drivers/tty/serial/amba-pl011.c6
1 files changed, 2 insertions, 4 deletions
diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index 7c8f9804f585..4b40a5b449ee 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -1480,12 +1480,10 @@ static irqreturn_t pl011_int(int irq, void *dev_id)
1480 struct uart_amba_port *uap = dev_id; 1480 struct uart_amba_port *uap = dev_id;
1481 unsigned long flags; 1481 unsigned long flags;
1482 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; 1482 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
1483 u16 imsc;
1484 int handled = 0; 1483 int handled = 0;
1485 1484
1486 spin_lock_irqsave(&uap->port.lock, flags); 1485 spin_lock_irqsave(&uap->port.lock, flags);
1487 imsc = pl011_read(uap, REG_IMSC); 1486 status = pl011_read(uap, REG_RIS) & uap->im;
1488 status = pl011_read(uap, REG_RIS) & imsc;
1489 if (status) { 1487 if (status) {
1490 do { 1488 do {
1491 check_apply_cts_event_workaround(uap); 1489 check_apply_cts_event_workaround(uap);
@@ -1509,7 +1507,7 @@ static irqreturn_t pl011_int(int irq, void *dev_id)
1509 if (pass_counter-- == 0) 1507 if (pass_counter-- == 0)
1510 break; 1508 break;
1511 1509
1512 status = pl011_read(uap, REG_RIS) & imsc; 1510 status = pl011_read(uap, REG_RIS) & uap->im;
1513 } while (status != 0); 1511 } while (status != 0);
1514 handled = 1; 1512 handled = 1;
1515 } 1513 }