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authorLinus Torvalds <torvalds@linux-foundation.org>2018-12-20 10:25:31 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2018-12-20 10:25:31 -0500
commitd31aeb78c6827db17f447f0504fc35afcbb188c2 (patch)
tree7edf9ce9d2532d151001f064d590ba13819203bf
parenta837eca2412051628c0529768c9bc4f3580b040e (diff)
parente3ae3401aa19432ee4943eb0bbc2ec704d07d793 (diff)
Merge tag 'mmc-v4.20-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc
Pull MMC fixes from Ulf Hansson: "MMC core: - Restore code to allow BKOPS and CACHE ctrl even if no HPI support - Reset HPI enabled state during re-init - Use a default minimum timeout when enabling CACHE ctrl MMC host: - omap_hsmmc: Fix DMA API warning - sdhci-tegra: Fix dt parsing of SDMMC pads autocal values - Correct register accesses when enabling v4 mode" * tag 'mmc-v4.20-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: mmc: core: Use a minimum 1600ms timeout when enabling CACHE ctrl mmc: core: Allow BKOPS and CACHE ctrl even if no HPI support mmc: core: Reset HPI enabled state during re-init and in case of errors mmc: omap_hsmmc: fix DMA API warning mmc: tegra: Fix for SDMMC pads autocal parsing from dt mmc: sdhci: Fix sdhci_do_enable_v4_mode
-rw-r--r--drivers/mmc/core/mmc.c24
-rw-r--r--drivers/mmc/host/omap_hsmmc.c12
-rw-r--r--drivers/mmc/host/sdhci-tegra.c8
-rw-r--r--drivers/mmc/host/sdhci.c4
4 files changed, 32 insertions, 16 deletions
diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
index bc1bd2c25613..55997cf84b39 100644
--- a/drivers/mmc/core/mmc.c
+++ b/drivers/mmc/core/mmc.c
@@ -30,6 +30,7 @@
30#include "pwrseq.h" 30#include "pwrseq.h"
31 31
32#define DEFAULT_CMD6_TIMEOUT_MS 500 32#define DEFAULT_CMD6_TIMEOUT_MS 500
33#define MIN_CACHE_EN_TIMEOUT_MS 1600
33 34
34static const unsigned int tran_exp[] = { 35static const unsigned int tran_exp[] = {
35 10000, 100000, 1000000, 10000000, 36 10000, 100000, 1000000, 10000000,
@@ -526,8 +527,7 @@ static int mmc_decode_ext_csd(struct mmc_card *card, u8 *ext_csd)
526 card->cid.year += 16; 527 card->cid.year += 16;
527 528
528 /* check whether the eMMC card supports BKOPS */ 529 /* check whether the eMMC card supports BKOPS */
529 if (!mmc_card_broken_hpi(card) && 530 if (ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1) {
530 ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1) {
531 card->ext_csd.bkops = 1; 531 card->ext_csd.bkops = 1;
532 card->ext_csd.man_bkops_en = 532 card->ext_csd.man_bkops_en =
533 (ext_csd[EXT_CSD_BKOPS_EN] & 533 (ext_csd[EXT_CSD_BKOPS_EN] &
@@ -1782,20 +1782,26 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
1782 if (err) { 1782 if (err) {
1783 pr_warn("%s: Enabling HPI failed\n", 1783 pr_warn("%s: Enabling HPI failed\n",
1784 mmc_hostname(card->host)); 1784 mmc_hostname(card->host));
1785 card->ext_csd.hpi_en = 0;
1785 err = 0; 1786 err = 0;
1786 } else 1787 } else {
1787 card->ext_csd.hpi_en = 1; 1788 card->ext_csd.hpi_en = 1;
1789 }
1788 } 1790 }
1789 1791
1790 /* 1792 /*
1791 * If cache size is higher than 0, this indicates 1793 * If cache size is higher than 0, this indicates the existence of cache
1792 * the existence of cache and it can be turned on. 1794 * and it can be turned on. Note that some eMMCs from Micron has been
1795 * reported to need ~800 ms timeout, while enabling the cache after
1796 * sudden power failure tests. Let's extend the timeout to a minimum of
1797 * DEFAULT_CACHE_EN_TIMEOUT_MS and do it for all cards.
1793 */ 1798 */
1794 if (!mmc_card_broken_hpi(card) && 1799 if (card->ext_csd.cache_size > 0) {
1795 card->ext_csd.cache_size > 0) { 1800 unsigned int timeout_ms = MIN_CACHE_EN_TIMEOUT_MS;
1801
1802 timeout_ms = max(card->ext_csd.generic_cmd6_time, timeout_ms);
1796 err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, 1803 err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
1797 EXT_CSD_CACHE_CTRL, 1, 1804 EXT_CSD_CACHE_CTRL, 1, timeout_ms);
1798 card->ext_csd.generic_cmd6_time);
1799 if (err && err != -EBADMSG) 1805 if (err && err != -EBADMSG)
1800 goto free_card; 1806 goto free_card;
1801 1807
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 467d889a1638..3f4ea8f624be 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -1909,7 +1909,6 @@ static int omap_hsmmc_probe(struct platform_device *pdev)
1909 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 1909 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1910 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 1910 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1911 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1911 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1912 mmc->max_seg_size = mmc->max_req_size;
1913 1912
1914 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 1913 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1915 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE | MMC_CAP_CMD23; 1914 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE | MMC_CAP_CMD23;
@@ -1939,6 +1938,17 @@ static int omap_hsmmc_probe(struct platform_device *pdev)
1939 goto err_irq; 1938 goto err_irq;
1940 } 1939 }
1941 1940
1941 /*
1942 * Limit the maximum segment size to the lower of the request size
1943 * and the DMA engine device segment size limits. In reality, with
1944 * 32-bit transfers, the DMA engine can do longer segments than this
1945 * but there is no way to represent that in the DMA model - if we
1946 * increase this figure here, we get warnings from the DMA API debug.
1947 */
1948 mmc->max_seg_size = min3(mmc->max_req_size,
1949 dma_get_max_seg_size(host->rx_chan->device->dev),
1950 dma_get_max_seg_size(host->tx_chan->device->dev));
1951
1942 /* Request IRQ for MMC operations */ 1952 /* Request IRQ for MMC operations */
1943 ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0, 1953 ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0,
1944 mmc_hostname(mmc), host); 1954 mmc_hostname(mmc), host);
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 7b95d088fdef..e6ace31e2a41 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -510,25 +510,25 @@ static void tegra_sdhci_parse_pad_autocal_dt(struct sdhci_host *host)
510 510
511 err = device_property_read_u32(host->mmc->parent, 511 err = device_property_read_u32(host->mmc->parent,
512 "nvidia,pad-autocal-pull-up-offset-3v3-timeout", 512 "nvidia,pad-autocal-pull-up-offset-3v3-timeout",
513 &autocal->pull_up_3v3); 513 &autocal->pull_up_3v3_timeout);
514 if (err) 514 if (err)
515 autocal->pull_up_3v3_timeout = 0; 515 autocal->pull_up_3v3_timeout = 0;
516 516
517 err = device_property_read_u32(host->mmc->parent, 517 err = device_property_read_u32(host->mmc->parent,
518 "nvidia,pad-autocal-pull-down-offset-3v3-timeout", 518 "nvidia,pad-autocal-pull-down-offset-3v3-timeout",
519 &autocal->pull_down_3v3); 519 &autocal->pull_down_3v3_timeout);
520 if (err) 520 if (err)
521 autocal->pull_down_3v3_timeout = 0; 521 autocal->pull_down_3v3_timeout = 0;
522 522
523 err = device_property_read_u32(host->mmc->parent, 523 err = device_property_read_u32(host->mmc->parent,
524 "nvidia,pad-autocal-pull-up-offset-1v8-timeout", 524 "nvidia,pad-autocal-pull-up-offset-1v8-timeout",
525 &autocal->pull_up_1v8); 525 &autocal->pull_up_1v8_timeout);
526 if (err) 526 if (err)
527 autocal->pull_up_1v8_timeout = 0; 527 autocal->pull_up_1v8_timeout = 0;
528 528
529 err = device_property_read_u32(host->mmc->parent, 529 err = device_property_read_u32(host->mmc->parent,
530 "nvidia,pad-autocal-pull-down-offset-1v8-timeout", 530 "nvidia,pad-autocal-pull-down-offset-1v8-timeout",
531 &autocal->pull_down_1v8); 531 &autocal->pull_down_1v8_timeout);
532 if (err) 532 if (err)
533 autocal->pull_down_1v8_timeout = 0; 533 autocal->pull_down_1v8_timeout = 0;
534 534
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 451b08a818a9..df05352b6a4a 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -127,12 +127,12 @@ static void sdhci_do_enable_v4_mode(struct sdhci_host *host)
127{ 127{
128 u16 ctrl2; 128 u16 ctrl2;
129 129
130 ctrl2 = sdhci_readb(host, SDHCI_HOST_CONTROL2); 130 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
131 if (ctrl2 & SDHCI_CTRL_V4_MODE) 131 if (ctrl2 & SDHCI_CTRL_V4_MODE)
132 return; 132 return;
133 133
134 ctrl2 |= SDHCI_CTRL_V4_MODE; 134 ctrl2 |= SDHCI_CTRL_V4_MODE;
135 sdhci_writeb(host, ctrl2, SDHCI_HOST_CONTROL); 135 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
136} 136}
137 137
138/* 138/*