iommu: Add driver for Renesas VMSA-compatible IPMMU

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>

4 files changed, 1107 insertions, 0 deletions

diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
index df56e4c74a7e..a22b537caacd 100644
--- a/drivers/iommu/Kconfig
+++ b/drivers/iommu/Kconfig
@@ -272,6 +272,18 @@ config SHMOBILE_IOMMU_L1SIZE
         default 256 if SHMOBILE_IOMMU_ADDRSIZE_64MB
         default 128 if SHMOBILE_IOMMU_ADDRSIZE_32MB
 
+config IPMMU_VMSA
+        bool "Renesas VMSA-compatible IPMMU"
+        depends on ARM_LPAE
+        depends on ARCH_SHMOBILE || COMPILE_TEST
+        select IOMMU_API
+        select ARM_DMA_USE_IOMMU
+        help
+          Support for the Renesas VMSA-compatible IPMMU Renesas found in the
+          R-Mobile APE6 and R-Car H2/M2 SoCs.
+
+          If unsure, say N.
+
 config SPAPR_TCE_IOMMU
         bool "sPAPR TCE IOMMU Support"
         depends on PPC_POWERNV || PPC_PSERIES
diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile
index 5d58bf16e9e3..8893bad048e0 100644
--- a/drivers/iommu/Makefile
+++ b/drivers/iommu/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_AMD_IOMMU_V2) += amd_iommu_v2.o
 obj-$(CONFIG_ARM_SMMU) += arm-smmu.o
 obj-$(CONFIG_DMAR_TABLE) += dmar.o
 obj-$(CONFIG_INTEL_IOMMU) += iova.o intel-iommu.o
+obj-$(CONFIG_IPMMU_VMSA) += ipmmu-vmsa.o
 obj-$(CONFIG_IRQ_REMAP) += intel_irq_remapping.o irq_remapping.o
 obj-$(CONFIG_OMAP_IOMMU) += omap-iommu.o
 obj-$(CONFIG_OMAP_IOMMU) += omap-iommu2.o
diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c
new file mode 100644
index 000000000000..b084530babf4
--- /dev/null
+++ b/drivers/iommu/ipmmu-vmsa.c
@@ -0,0 +1,1070 @@
+/*
+ * IPMMU VMSA
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/export.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/iommu.h>
+#include <linux/module.h>
+#include <linux/platform_data/ipmmu-vmsa.h>
+#include <linux/platform_device.h>
+#include <linux/sizes.h>
+#include <linux/slab.h>
+
+#include <asm/dma-iommu.h>
+#include <asm/pgalloc.h>
+
+struct ipmmu_vmsa_device {
+        struct device *dev;
+        void __iomem *base;
+        struct list_head list;
+
+        const struct ipmmu_vmsa_platform_data *pdata;
+        unsigned int num_utlbs;
+
+        struct dma_iommu_mapping *mapping;
+};
+
+struct ipmmu_vmsa_domain {
+        struct ipmmu_vmsa_device *mmu;
+        struct iommu_domain *io_domain;
+
+        unsigned int context_id;
+        spinlock_t lock;                        /* Protects mappings */
+        pgd_t *pgd;
+};
+
+static DEFINE_SPINLOCK(ipmmu_devices_lock);
+static LIST_HEAD(ipmmu_devices);
+
+#define TLB_LOOP_TIMEOUT                100     /* 100us */
+
+/* -----------------------------------------------------------------------------
+ * Registers Definition
+ */
+
+#define IM_CTX_SIZE                     0x40
+
+#define IMCTR                           0x0000
+#define IMCTR_TRE                       (1 << 17)
+#define IMCTR_AFE                       (1 << 16)
+#define IMCTR_RTSEL_MASK                (3 << 4)
+#define IMCTR_RTSEL_SHIFT               4
+#define IMCTR_TREN                      (1 << 3)
+#define IMCTR_INTEN                     (1 << 2)
+#define IMCTR_FLUSH                     (1 << 1)
+#define IMCTR_MMUEN                     (1 << 0)
+
+#define IMCAAR                          0x0004
+
+#define IMTTBCR                         0x0008
+#define IMTTBCR_EAE                     (1 << 31)
+#define IMTTBCR_PMB                     (1 << 30)
+#define IMTTBCR_SH1_NON_SHAREABLE       (0 << 28)
+#define IMTTBCR_SH1_OUTER_SHAREABLE     (2 << 28)
+#define IMTTBCR_SH1_INNER_SHAREABLE     (3 << 28)
+#define IMTTBCR_SH1_MASK                (3 << 28)
+#define IMTTBCR_ORGN1_NC                (0 << 26)
+#define IMTTBCR_ORGN1_WB_WA             (1 << 26)
+#define IMTTBCR_ORGN1_WT                (2 << 26)
+#define IMTTBCR_ORGN1_WB                (3 << 26)
+#define IMTTBCR_ORGN1_MASK              (3 << 26)
+#define IMTTBCR_IRGN1_NC                (0 << 24)
+#define IMTTBCR_IRGN1_WB_WA             (1 << 24)
+#define IMTTBCR_IRGN1_WT                (2 << 24)
+#define IMTTBCR_IRGN1_WB                (3 << 24)
+#define IMTTBCR_IRGN1_MASK              (3 << 24)
+#define IMTTBCR_TSZ1_MASK               (7 << 16)
+#define IMTTBCR_TSZ1_SHIFT              16
+#define IMTTBCR_SH0_NON_SHAREABLE       (0 << 12)
+#define IMTTBCR_SH0_OUTER_SHAREABLE     (2 << 12)
+#define IMTTBCR_SH0_INNER_SHAREABLE     (3 << 12)
+#define IMTTBCR_SH0_MASK                (3 << 12)
+#define IMTTBCR_ORGN0_NC                (0 << 10)
+#define IMTTBCR_ORGN0_WB_WA             (1 << 10)
+#define IMTTBCR_ORGN0_WT                (2 << 10)
+#define IMTTBCR_ORGN0_WB                (3 << 10)
+#define IMTTBCR_ORGN0_MASK              (3 << 10)
+#define IMTTBCR_IRGN0_NC                (0 << 8)
+#define IMTTBCR_IRGN0_WB_WA             (1 << 8)
+#define IMTTBCR_IRGN0_WT                (2 << 8)
+#define IMTTBCR_IRGN0_WB                (3 << 8)
+#define IMTTBCR_IRGN0_MASK              (3 << 8)
+#define IMTTBCR_SL0_LVL_2               (0 << 4)
+#define IMTTBCR_SL0_LVL_1               (1 << 4)
+#define IMTTBCR_TSZ0_MASK               (7 << 0)
+#define IMTTBCR_TSZ0_SHIFT              O
+
+#define IMBUSCR                         0x000c
+#define IMBUSCR_DVM                     (1 << 2)
+#define IMBUSCR_BUSSEL_SYS              (0 << 0)
+#define IMBUSCR_BUSSEL_CCI              (1 << 0)
+#define IMBUSCR_BUSSEL_IMCAAR           (2 << 0)
+#define IMBUSCR_BUSSEL_CCI_IMCAAR       (3 << 0)
+#define IMBUSCR_BUSSEL_MASK             (3 << 0)
+
+#define IMTTLBR0                        0x0010
+#define IMTTUBR0                        0x0014
+#define IMTTLBR1                        0x0018
+#define IMTTUBR1                        0x001c
+
+#define IMSTR                           0x0020
+#define IMSTR_ERRLVL_MASK               (3 << 12)
+#define IMSTR_ERRLVL_SHIFT              12
+#define IMSTR_ERRCODE_TLB_FORMAT        (1 << 8)
+#define IMSTR_ERRCODE_ACCESS_PERM       (4 << 8)
+#define IMSTR_ERRCODE_SECURE_ACCESS     (5 << 8)
+#define IMSTR_ERRCODE_MASK              (7 << 8)
+#define IMSTR_MHIT                      (1 << 4)
+#define IMSTR_ABORT                     (1 << 2)
+#define IMSTR_PF                        (1 << 1)
+#define IMSTR_TF                        (1 << 0)
+
+#define IMMAIR0                         0x0028
+#define IMMAIR1                         0x002c
+#define IMMAIR_ATTR_MASK                0xff
+#define IMMAIR_ATTR_DEVICE              0x04
+#define IMMAIR_ATTR_NC                  0x44
+#define IMMAIR_ATTR_WBRWA               0xff
+#define IMMAIR_ATTR_SHIFT(n)            ((n) << 3)
+#define IMMAIR_ATTR_IDX_NC              0
+#define IMMAIR_ATTR_IDX_WBRWA           1
+#define IMMAIR_ATTR_IDX_DEV             2
+
+#define IMEAR                           0x0030
+
+#define IMPCTR                          0x0200
+#define IMPSTR                          0x0208
+#define IMPEAR                          0x020c
+#define IMPMBA(n)                       (0x0280 + ((n) * 4))
+#define IMPMBD(n)                       (0x02c0 + ((n) * 4))
+
+#define IMUCTR(n)                       (0x0300 + ((n) * 16))
+#define IMUCTR_FIXADDEN                 (1 << 31)
+#define IMUCTR_FIXADD_MASK              (0xff << 16)
+#define IMUCTR_FIXADD_SHIFT             16
+#define IMUCTR_TTSEL_MMU(n)             ((n) << 4)
+#define IMUCTR_TTSEL_PMB                (8 << 4)
+#define IMUCTR_TTSEL_MASK               (15 << 4)
+#define IMUCTR_FLUSH                    (1 << 1)
+#define IMUCTR_MMUEN                    (1 << 0)
+
+#define IMUASID(n)                      (0x0308 + ((n) * 16))
+#define IMUASID_ASID8_MASK              (0xff << 8)
+#define IMUASID_ASID8_SHIFT             8
+#define IMUASID_ASID0_MASK              (0xff << 0)
+#define IMUASID_ASID0_SHIFT             0
+