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authorChunming Zhou <david1.zhou@amd.com>2015-07-30 05:59:43 -0400
committerAlex Deucher <alexander.deucher@amd.com>2015-08-17 16:50:43 -0400
commitd1ff9086c1b8e67390161599006a34056b437a72 (patch)
treeaaaf8b04c136fb05fd9d863f501450974ac5cfcf
parent51b9db27d07869cf565ba135e97e2ed5f858612e (diff)
drm/amdgpu: fix seq in ctx_add_fence
if enabling scheduler, then the queued seq is assigned when pushing job before emitting job. Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian K?nig <christian.koenig@amd.com>
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c5
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c6
6 files changed, 15 insertions, 13 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 6e1fea473a66..2619c78ec303 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -419,7 +419,6 @@ struct amdgpu_user_fence {
419 struct amdgpu_bo *bo; 419 struct amdgpu_bo *bo;
420 /* write-back address offset to bo start */ 420 /* write-back address offset to bo start */
421 uint32_t offset; 421 uint32_t offset;
422 uint64_t sequence;
423}; 422};
424 423
425int amdgpu_fence_driver_init(struct amdgpu_device *adev); 424int amdgpu_fence_driver_init(struct amdgpu_device *adev);
@@ -1031,7 +1030,7 @@ struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
1031int amdgpu_ctx_put(struct amdgpu_ctx *ctx); 1030int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
1032 1031
1033uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, 1032uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
1034 struct fence *fence); 1033 struct fence *fence, uint64_t queued_seq);
1035struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 1034struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
1036 struct amdgpu_ring *ring, uint64_t seq); 1035 struct amdgpu_ring *ring, uint64_t seq);
1037 1036
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index c41360e443be..40e85bfcdf91 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -739,7 +739,6 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
739 ib->oa_size = amdgpu_bo_size(oa); 739 ib->oa_size = amdgpu_bo_size(oa);
740 } 740 }
741 } 741 }
742
743 /* wrap the last IB with user fence */ 742 /* wrap the last IB with user fence */
744 if (parser->uf.bo) { 743 if (parser->uf.bo) {
745 struct amdgpu_ib *ib = &parser->ibs[parser->num_ibs - 1]; 744 struct amdgpu_ib *ib = &parser->ibs[parser->num_ibs - 1];
@@ -908,7 +907,7 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
908 if (amdgpu_enable_scheduler && parser->num_ibs) { 907 if (amdgpu_enable_scheduler && parser->num_ibs) {
909 struct amdgpu_ring * ring = 908 struct amdgpu_ring * ring =
910 amdgpu_cs_parser_get_ring(adev, parser); 909 amdgpu_cs_parser_get_ring(adev, parser);
911 parser->uf.sequence = atomic64_inc_return( 910 parser->ibs[parser->num_ibs - 1].sequence = atomic64_inc_return(
912 &parser->ctx->rings[ring->idx].c_entity.last_queued_v_seq); 911 &parser->ctx->rings[ring->idx].c_entity.last_queued_v_seq);
913 if (ring->is_pte_ring || (parser->bo_list && parser->bo_list->has_userptr)) { 912 if (ring->is_pte_ring || (parser->bo_list && parser->bo_list->has_userptr)) {
914 r = amdgpu_cs_parser_prepare_job(parser); 913 r = amdgpu_cs_parser_prepare_job(parser);
@@ -922,7 +921,7 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
922 amd_sched_push_job(ring->scheduler, 921 amd_sched_push_job(ring->scheduler,
923 &parser->ctx->rings[ring->idx].c_entity, 922 &parser->ctx->rings[ring->idx].c_entity,
924 parser); 923 parser);
925 cs->out.handle = parser->uf.sequence; 924 cs->out.handle = parser->ibs[parser->num_ibs - 1].sequence;
926 up_read(&adev->exclusive_lock); 925 up_read(&adev->exclusive_lock);
927 return 0; 926 return 0;
928 } 927 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 95807b678b6a..e0eaa55bf636 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -258,7 +258,7 @@ int amdgpu_ctx_put(struct amdgpu_ctx *ctx)
258} 258}
259 259
260uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, 260uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
261 struct fence *fence) 261 struct fence *fence, uint64_t queued_seq)
262{ 262{
263 struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx]; 263 struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx];
264 uint64_t seq = 0; 264 uint64_t seq = 0;
@@ -266,7 +266,7 @@ uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
266 struct fence *other = NULL; 266 struct fence *other = NULL;
267 267
268 if (amdgpu_enable_scheduler) 268 if (amdgpu_enable_scheduler)
269 seq = atomic64_read(&cring->c_entity.last_queued_v_seq); 269 seq = queued_seq;
270 else 270 else
271 seq = cring->sequence; 271 seq = cring->sequence;
272 idx = seq % AMDGPU_CTX_MAX_CS_PENDING; 272 idx = seq % AMDGPU_CTX_MAX_CS_PENDING;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 42d6298eb9d7..eed409c59492 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -143,6 +143,7 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
143 struct amdgpu_ring *ring; 143 struct amdgpu_ring *ring;
144 struct amdgpu_ctx *ctx, *old_ctx; 144 struct amdgpu_ctx *ctx, *old_ctx;
145 struct amdgpu_vm *vm; 145 struct amdgpu_vm *vm;
146 uint64_t sequence;
146 unsigned i; 147 unsigned i;
147 int r = 0; 148 int r = 0;
148 149
@@ -215,9 +216,12 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
215 return r; 216 return r;
216 } 217 }
217 218
219 sequence = amdgpu_enable_scheduler ? ib->sequence : 0;
220
218 if (ib->ctx) 221 if (ib->ctx)
219 ib->sequence = amdgpu_ctx_add_fence(ib->ctx, ring, 222 ib->sequence = amdgpu_ctx_add_fence(ib->ctx, ring,
220 &ib->fence->base); 223 &ib->fence->base,
224 sequence);
221 225
222 /* wrap the last IB with fence */ 226 /* wrap the last IB with fence */
223 if (ib->user) { 227 if (ib->user) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
index 46ec915c9344..b913c22dd6b2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
@@ -62,7 +62,7 @@ static void amdgpu_sched_run_job(struct amd_gpu_scheduler *sched,
62 goto err; 62 goto err;
63 } 63 }
64 atomic64_set(&c_entity->last_emitted_v_seq, 64 atomic64_set(&c_entity->last_emitted_v_seq,
65 sched_job->uf.sequence); 65 sched_job->ibs[sched_job->num_ibs - 1].sequence);
66 wake_up_all(&c_entity->wait_emit); 66 wake_up_all(&c_entity->wait_emit);
67 67
68 mutex_unlock(&sched_job->job_lock); 68 mutex_unlock(&sched_job->job_lock);
@@ -93,7 +93,7 @@ static void amdgpu_sched_process_job(struct amd_gpu_scheduler *sched, void *job)
93 if (sched_job->ctx) { 93 if (sched_job->ctx) {
94 c_entity = &sched_job->ctx->rings[ring->idx].c_entity; 94 c_entity = &sched_job->ctx->rings[ring->idx].c_entity;
95 atomic64_set(&c_entity->last_signaled_v_seq, 95 atomic64_set(&c_entity->last_signaled_v_seq,
96 sched_job->uf.sequence); 96 sched_job->ibs[sched_job->num_ibs - 1].sequence);
97 } 97 }
98 98
99 /* wake up users waiting for time stamp */ 99 /* wake up users waiting for time stamp */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 26c55a7a1a88..5624d4484fb6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -380,7 +380,7 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
380 sched_job->run_job = amdgpu_vm_run_job; 380 sched_job->run_job = amdgpu_vm_run_job;
381 sched_job->free_job = amdgpu_vm_free_job; 381 sched_job->free_job = amdgpu_vm_free_job;
382 v_seq = atomic64_inc_return(&adev->kernel_ctx->rings[ring->idx].c_entity.last_queued_v_seq); 382 v_seq = atomic64_inc_return(&adev->kernel_ctx->rings[ring->idx].c_entity.last_queued_v_seq);
383 sched_job->uf.sequence = v_seq; 383 ib->sequence = v_seq;
384 amd_sched_push_job(ring->scheduler, 384 amd_sched_push_job(ring->scheduler,
385 &adev->kernel_ctx->rings[ring->idx].c_entity, 385 &adev->kernel_ctx->rings[ring->idx].c_entity,
386 sched_job); 386 sched_job);
@@ -531,7 +531,7 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
531 sched_job->run_job = amdgpu_vm_run_job; 531 sched_job->run_job = amdgpu_vm_run_job;
532 sched_job->free_job = amdgpu_vm_free_job; 532 sched_job->free_job = amdgpu_vm_free_job;
533 v_seq = atomic64_inc_return(&adev->kernel_ctx->rings[ring->idx].c_entity.last_queued_v_seq); 533 v_seq = atomic64_inc_return(&adev->kernel_ctx->rings[ring->idx].c_entity.last_queued_v_seq);
534 sched_job->uf.sequence = v_seq; 534 ib->sequence = v_seq;
535 amd_sched_push_job(ring->scheduler, 535 amd_sched_push_job(ring->scheduler,
536 &adev->kernel_ctx->rings[ring->idx].c_entity, 536 &adev->kernel_ctx->rings[ring->idx].c_entity,
537 sched_job); 537 sched_job);
@@ -884,7 +884,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
884 sched_job->run_job = amdgpu_vm_bo_update_mapping_run_job; 884 sched_job->run_job = amdgpu_vm_bo_update_mapping_run_job;
885 sched_job->free_job = amdgpu_vm_free_job; 885 sched_job->free_job = amdgpu_vm_free_job;
886 v_seq = atomic64_inc_return(&adev->kernel_ctx->rings[ring->idx].c_entity.last_queued_v_seq); 886 v_seq = atomic64_inc_return(&adev->kernel_ctx->rings[ring->idx].c_entity.last_queued_v_seq);
887 sched_job->uf.sequence = v_seq; 887 ib->sequence = v_seq;
888 amd_sched_push_job(ring->scheduler, 888 amd_sched_push_job(ring->scheduler,
889 &adev->kernel_ctx->rings[ring->idx].c_entity, 889 &adev->kernel_ctx->rings[ring->idx].c_entity,
890 sched_job); 890 sched_job);