diff options
author | Stephane Eranian <eranian@google.com> | 2018-04-05 02:29:51 -0400 |
---|---|---|
committer | Ingo Molnar <mingo@kernel.org> | 2018-04-05 03:28:40 -0400 |
commit | d1e7e602cd64cf61f87dbf30df07c24df9eb1d99 (patch) | |
tree | 137ea917b68c5de6611da8b5a23d8d66ca34d62a | |
parent | b89e7914f0291bbb58f6a1f024923ceffcde4fc7 (diff) |
perf/x86/intel: Move regs->flags EXACT bit init
This patch removes a redundant store on regs->flags introduced
by commit:
71eb9ee9596d ("perf/x86/intel: Fix linear IP of PEBS real_ip on Haswell and later CPUs")
We were clearing the PERF_EFLAGS_EXACT but it was overwritten by
regs->flags = pebs->flags later on.
The PERF_EFLAGS_EXACT is a software flag using bit 3 of regs->flags.
X86 marks this bit as Reserved. To make sure this bit is zero before
we do any IP processing, we clear it explicitly.
Patch also removes the following assignment:
regs->flags = pebs->flags | (regs->flags & PERF_EFLAGS_VM);
Because there is no regs->flags to preserve anymore because
set_linear_ip() is not called until later.
Signed-off-by: Stephane Eranian <eranian@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Cc: kan.liang@intel.com
Link: http://lkml.kernel.org/r/1522909791-32498-1-git-send-email-eranian@google.com
[ Improve capitalization, punctuation and clarity of comments. ]
Signed-off-by: Ingo Molnar <mingo@kernel.org>
-rw-r--r-- | arch/x86/events/intel/ds.c | 34 |
1 files changed, 24 insertions, 10 deletions
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index da6780122786..8a10a045b57b 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c | |||
@@ -1153,7 +1153,6 @@ static void setup_pebs_sample_data(struct perf_event *event, | |||
1153 | if (pebs == NULL) | 1153 | if (pebs == NULL) |
1154 | return; | 1154 | return; |
1155 | 1155 | ||
1156 | regs->flags &= ~PERF_EFLAGS_EXACT; | ||
1157 | sample_type = event->attr.sample_type; | 1156 | sample_type = event->attr.sample_type; |
1158 | dsrc = sample_type & PERF_SAMPLE_DATA_SRC; | 1157 | dsrc = sample_type & PERF_SAMPLE_DATA_SRC; |
1159 | 1158 | ||
@@ -1197,7 +1196,13 @@ static void setup_pebs_sample_data(struct perf_event *event, | |||
1197 | * and PMI. | 1196 | * and PMI. |
1198 | */ | 1197 | */ |
1199 | *regs = *iregs; | 1198 | *regs = *iregs; |
1200 | regs->flags = pebs->flags; | 1199 | |
1200 | /* | ||
1201 | * Initialize regs_>flags from PEBS, | ||
1202 | * Clear exact bit (which uses x86 EFLAGS Reserved bit 3), | ||
1203 | * i.e., do not rely on it being zero: | ||
1204 | */ | ||
1205 | regs->flags = pebs->flags & ~PERF_EFLAGS_EXACT; | ||
1201 | 1206 | ||
1202 | if (sample_type & PERF_SAMPLE_REGS_INTR) { | 1207 | if (sample_type & PERF_SAMPLE_REGS_INTR) { |
1203 | regs->ax = pebs->ax; | 1208 | regs->ax = pebs->ax; |
@@ -1217,10 +1222,6 @@ static void setup_pebs_sample_data(struct perf_event *event, | |||
1217 | regs->sp = pebs->sp; | 1222 | regs->sp = pebs->sp; |
1218 | } | 1223 | } |
1219 | 1224 | ||
1220 | /* | ||
1221 | * Preserve PERF_EFLAGS_VM from set_linear_ip(). | ||
1222 | */ | ||
1223 | regs->flags = pebs->flags | (regs->flags & PERF_EFLAGS_VM); | ||
1224 | #ifndef CONFIG_X86_32 | 1225 | #ifndef CONFIG_X86_32 |
1225 | regs->r8 = pebs->r8; | 1226 | regs->r8 = pebs->r8; |
1226 | regs->r9 = pebs->r9; | 1227 | regs->r9 = pebs->r9; |
@@ -1234,20 +1235,33 @@ static void setup_pebs_sample_data(struct perf_event *event, | |||
1234 | } | 1235 | } |
1235 | 1236 | ||
1236 | if (event->attr.precise_ip > 1) { | 1237 | if (event->attr.precise_ip > 1) { |
1237 | /* Haswell and later have the eventing IP, so use it: */ | 1238 | /* |
1239 | * Haswell and later processors have an 'eventing IP' | ||
1240 | * (real IP) which fixes the off-by-1 skid in hardware. | ||
1241 | * Use it when precise_ip >= 2 : | ||
1242 | */ | ||
1238 | if (x86_pmu.intel_cap.pebs_format >= 2) { | 1243 | if (x86_pmu.intel_cap.pebs_format >= 2) { |
1239 | set_linear_ip(regs, pebs->real_ip); | 1244 | set_linear_ip(regs, pebs->real_ip); |
1240 | regs->flags |= PERF_EFLAGS_EXACT; | 1245 | regs->flags |= PERF_EFLAGS_EXACT; |
1241 | } else { | 1246 | } else { |
1242 | /* Otherwise use PEBS off-by-1 IP: */ | 1247 | /* Otherwise, use PEBS off-by-1 IP: */ |
1243 | set_linear_ip(regs, pebs->ip); | 1248 | set_linear_ip(regs, pebs->ip); |
1244 | 1249 | ||
1245 | /* ... and try to fix it up using the LBR entries: */ | 1250 | /* |
1251 | * With precise_ip >= 2, try to fix up the off-by-1 IP | ||
1252 | * using the LBR. If successful, the fixup function | ||
1253 | * corrects regs->ip and calls set_linear_ip() on regs: | ||
1254 | */ | ||
1246 | if (intel_pmu_pebs_fixup_ip(regs)) | 1255 | if (intel_pmu_pebs_fixup_ip(regs)) |
1247 | regs->flags |= PERF_EFLAGS_EXACT; | 1256 | regs->flags |= PERF_EFLAGS_EXACT; |
1248 | } | 1257 | } |
1249 | } else | 1258 | } else { |
1259 | /* | ||
1260 | * When precise_ip == 1, return the PEBS off-by-1 IP, | ||
1261 | * no fixup attempted: | ||
1262 | */ | ||
1250 | set_linear_ip(regs, pebs->ip); | 1263 | set_linear_ip(regs, pebs->ip); |
1264 | } | ||
1251 | 1265 | ||
1252 | 1266 | ||
1253 | if ((sample_type & (PERF_SAMPLE_ADDR | PERF_SAMPLE_PHYS_ADDR)) && | 1267 | if ((sample_type & (PERF_SAMPLE_ADDR | PERF_SAMPLE_PHYS_ADDR)) && |