diff options
author | Ji-Ze Hong (Peter Hong) <hpeter@gmail.com> | 2018-01-11 01:47:20 -0500 |
---|---|---|
committer | Johan Hovold <johan@kernel.org> | 2018-01-11 05:00:25 -0500 |
commit | d1c48227d7c45fbb35c81f846a62ec92a74f4701 (patch) | |
tree | c392eb4b308459b85833ec49b4b232468f66348c | |
parent | bb543ca287f5b14a61533f959e3f62ae58890311 (diff) |
USB: serial: f81534: fix tx error on some baud rate
The F81532/534 had 4 clocksource 1.846/18.46/14.77/24MHz and baud rates
can be up to 1.5Mbits with 24MHz. But on some baud rate (384~500kps), the
TX side will send the data frame too close to treat frame error on RX
side. This patch will force all TX data frame with delay 1bit gap.
Signed-off-by: Ji-Ze Hong (Peter Hong) <hpeter+linux_kernel@gmail.com>
Signed-off-by: Johan Hovold <johan@kernel.org>
-rw-r--r-- | drivers/usb/serial/f81534.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/usb/serial/f81534.c b/drivers/usb/serial/f81534.c index 86edec3e8c05..4dfbff20bda4 100644 --- a/drivers/usb/serial/f81534.c +++ b/drivers/usb/serial/f81534.c | |||
@@ -131,6 +131,7 @@ | |||
131 | #define F81534_CLK_24_MHZ BIT(2) | 131 | #define F81534_CLK_24_MHZ BIT(2) |
132 | #define F81534_CLK_14_77_MHZ (BIT(1) | BIT(2)) | 132 | #define F81534_CLK_14_77_MHZ (BIT(1) | BIT(2)) |
133 | #define F81534_CLK_MASK GENMASK(2, 1) | 133 | #define F81534_CLK_MASK GENMASK(2, 1) |
134 | #define F81534_CLK_TX_DELAY_1BIT BIT(3) | ||
134 | #define F81534_CLK_RS485_MODE BIT(4) | 135 | #define F81534_CLK_RS485_MODE BIT(4) |
135 | #define F81534_CLK_RS485_INVERT BIT(5) | 136 | #define F81534_CLK_RS485_INVERT BIT(5) |
136 | 137 | ||
@@ -1386,7 +1387,11 @@ static int f81534_port_probe(struct usb_serial_port *port) | |||
1386 | if (!port_priv) | 1387 | if (!port_priv) |
1387 | return -ENOMEM; | 1388 | return -ENOMEM; |
1388 | 1389 | ||
1389 | port_priv->shadow_clk = F81534_UART_EN; | 1390 | /* |
1391 | * We'll make tx frame error when baud rate from 384~500kps. So we'll | ||
1392 | * delay all tx data frame with 1bit. | ||
1393 | */ | ||
1394 | port_priv->shadow_clk = F81534_UART_EN | F81534_CLK_TX_DELAY_1BIT; | ||
1390 | spin_lock_init(&port_priv->msr_lock); | 1395 | spin_lock_init(&port_priv->msr_lock); |
1391 | mutex_init(&port_priv->mcr_mutex); | 1396 | mutex_init(&port_priv->mcr_mutex); |
1392 | mutex_init(&port_priv->lcr_mutex); | 1397 | mutex_init(&port_priv->lcr_mutex); |