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authorArnd Bergmann <arnd@arndb.de>2018-02-22 11:46:40 -0500
committerArnd Bergmann <arnd@arndb.de>2018-02-22 11:46:40 -0500
commitd1b8b9657a19d3793e09145b66dc0f5324950587 (patch)
treecf9520a3cc681852dec6a3b094b0bce2eb3e6356
parentc209d25e4696083923778353ee2d387862c01fa4 (diff)
parente78c637127ee7683d606737f2e62b5da6fd7b1c3 (diff)
Merge tag 'v4.16-rockchip-dts32fixes-1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into fixes
Pull "Rockchip dts32 fixes for 4.16" from Heiko Stübner: Fix wrong dwmmc tuning clocks that may make probing HS cards fail to probe and removal of special opps from the phycore boards that may run the cpu outside the soc-vendor specs. * tag 'v4.16-rockchip-dts32fixes-1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rockchip: Fix DWMMC clocks ARM: dts: rockchip: Remove 1.8 GHz operation point from phycore som
-rw-r--r--arch/arm/boot/dts/rk3036.dtsi4
-rw-r--r--arch/arm/boot/dts/rk322x.dtsi6
-rw-r--r--arch/arm/boot/dts/rk3288-phycore-som.dtsi20
3 files changed, 5 insertions, 25 deletions
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index 3b704cfed69a..a97458112ff6 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -280,7 +280,7 @@
280 max-frequency = <37500000>; 280 max-frequency = <37500000>;
281 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 281 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
282 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 282 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
283 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 283 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
284 fifo-depth = <0x100>; 284 fifo-depth = <0x100>;
285 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 285 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
286 resets = <&cru SRST_SDIO>; 286 resets = <&cru SRST_SDIO>;
@@ -298,7 +298,7 @@
298 max-frequency = <37500000>; 298 max-frequency = <37500000>;
299 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 299 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
300 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 300 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
301 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 301 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
302 default-sample-phase = <158>; 302 default-sample-phase = <158>;
303 disable-wp; 303 disable-wp;
304 dmas = <&pdma 12>; 304 dmas = <&pdma 12>;
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index 780ec3a99b21..341deaf62ff6 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -621,7 +621,7 @@
621 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 621 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
622 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 622 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
623 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 623 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
624 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 624 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
625 fifo-depth = <0x100>; 625 fifo-depth = <0x100>;
626 pinctrl-names = "default"; 626 pinctrl-names = "default";
627 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; 627 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
@@ -634,7 +634,7 @@
634 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 634 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
635 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 635 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
636 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 636 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
637 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 637 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
638 fifo-depth = <0x100>; 638 fifo-depth = <0x100>;
639 pinctrl-names = "default"; 639 pinctrl-names = "default";
640 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; 640 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
@@ -649,7 +649,7 @@
649 max-frequency = <37500000>; 649 max-frequency = <37500000>;
650 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 650 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
651 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 651 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
652 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 652 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
653 bus-width = <8>; 653 bus-width = <8>;
654 default-sample-phase = <158>; 654 default-sample-phase = <158>;
655 fifo-depth = <0x100>; 655 fifo-depth = <0x100>;
diff --git a/arch/arm/boot/dts/rk3288-phycore-som.dtsi b/arch/arm/boot/dts/rk3288-phycore-som.dtsi
index 99cfae875e12..5eae4776ffde 100644
--- a/arch/arm/boot/dts/rk3288-phycore-som.dtsi
+++ b/arch/arm/boot/dts/rk3288-phycore-som.dtsi
@@ -110,26 +110,6 @@
110 }; 110 };
111}; 111};
112 112
113&cpu0 {
114 cpu0-supply = <&vdd_cpu>;
115 operating-points = <
116 /* KHz uV */
117 1800000 1400000
118 1608000 1350000
119 1512000 1300000
120 1416000 1200000
121 1200000 1100000
122 1008000 1050000
123 816000 1000000
124 696000 950000
125 600000 900000
126 408000 900000
127 312000 900000
128 216000 900000
129 126000 900000
130 >;
131};
132
133&emmc { 113&emmc {
134 status = "okay"; 114 status = "okay";
135 bus-width = <8>; 115 bus-width = <8>;