ARM: dts: r8a7794: Add L2 cache-controller node

Add a device node for the L2 cache, and link the CPU nodes to it.

The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as
64 KiB x 8 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

1 files changed, 8 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index df0861e84a4b..21a02df3609b 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -40,6 +40,7 @@
                         compatible = "arm,cortex-a7";
                         reg = <0>;
                         clock-frequency = <1000000000>;
+                        next-level-cache = <&L2_CA7>;
                 };
 
                 cpu1: cpu@1 {
@@ -47,9 +48,16 @@
                         compatible = "arm,cortex-a7";
                         reg = <1>;
                         clock-frequency = <1000000000>;
+                        next-level-cache = <&L2_CA7>;
                 };
         };
 
+        L2_CA7: cache-controller@1 {
+                compatible = "cache";
+                cache-unified;
+                cache-level = <2>;
+        };
+
         gic: interrupt-controller@f1001000 {
                 compatible = "arm,gic-400";
                 #interrupt-cells = <3>;