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authorAlex Deucher <alexander.deucher@amd.com>2017-06-09 08:22:31 -0400
committerAlex Deucher <alexander.deucher@amd.com>2017-06-09 11:30:42 -0400
commitd0c55cdf4fc02483a4851f86e3f010a061d8c9cc (patch)
tree309fc1b51e44f87aca4399ce977cbc18e8da8368
parentf06fed92dcf27d83ad546c9a510165d1bd54fc3f (diff)
drm/amdgpu/gfx: fix MEC interrupt enablement for pipes != 0
The interrupt registers are not indexed. Fixes: 763a47b8e (drm/amdgpu: teach amdgpu how to enable interrupts for any pipe v3) Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c57
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c57
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c59
3 files changed, 124 insertions, 49 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index e30c7d0bd0f9..fb0a94c52945 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -5015,28 +5015,51 @@ static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
5015 int me, int pipe, 5015 int me, int pipe,
5016 enum amdgpu_interrupt_state state) 5016 enum amdgpu_interrupt_state state)
5017{ 5017{
5018 /* Me 0 is for graphics and Me 2 is reserved for HW scheduling 5018 u32 mec_int_cntl, mec_int_cntl_reg;
5019 * So we should only really be configuring ME 1 i.e. MEC0 5019
5020 /*
5021 * amdgpu controls only the first MEC. That's why this function only
5022 * handles the setting of interrupts for this specific MEC. All other
5023 * pipes' interrupts are set by amdkfd.
5020 */ 5024 */
5021 if (me != 1) {
5022 DRM_ERROR("Ignoring request to enable interrupts for invalid me:%d\n", me);
5023 return;
5024 }
5025 5025
5026 if (pipe >= adev->gfx.mec.num_pipe_per_mec) { 5026 if (me == 1) {
5027 DRM_ERROR("Ignoring request to enable interrupts for invalid " 5027 switch (pipe) {
5028 "me:%d pipe:%d\n", pipe, me); 5028 case 0:
5029 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
5030 break;
5031 case 1:
5032 mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL;
5033 break;
5034 case 2:
5035 mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL;
5036 break;
5037 case 3:
5038 mec_int_cntl_reg = mmCP_ME1_PIPE3_INT_CNTL;
5039 break;
5040 default:
5041 DRM_DEBUG("invalid pipe %d\n", pipe);
5042 return;
5043 }
5044 } else {
5045 DRM_DEBUG("invalid me %d\n", me);
5029 return; 5046 return;
5030 } 5047 }
5031 5048
5032 mutex_lock(&adev->srbm_mutex); 5049 switch (state) {
5033 cik_srbm_select(adev, me, pipe, 0, 0); 5050 case AMDGPU_IRQ_STATE_DISABLE:
5034 5051 mec_int_cntl = RREG32(mec_int_cntl_reg);
5035 WREG32_FIELD(CPC_INT_CNTL, TIME_STAMP_INT_ENABLE, 5052 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
5036 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1); 5053 WREG32(mec_int_cntl_reg, mec_int_cntl);
5037 5054 break;
5038 cik_srbm_select(adev, 0, 0, 0, 0); 5055 case AMDGPU_IRQ_STATE_ENABLE:
5039 mutex_unlock(&adev->srbm_mutex); 5056 mec_int_cntl = RREG32(mec_int_cntl_reg);
5057 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
5058 WREG32(mec_int_cntl_reg, mec_int_cntl);
5059 break;
5060 default:
5061 break;
5062 }
5040} 5063}
5041 5064
5042static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 5065static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 6e541af0e899..1a75ab1d1823 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -6610,26 +6610,51 @@ static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
6610 int me, int pipe, 6610 int me, int pipe,
6611 enum amdgpu_interrupt_state state) 6611 enum amdgpu_interrupt_state state)
6612{ 6612{
6613 /* Me 0 is reserved for graphics */ 6613 u32 mec_int_cntl, mec_int_cntl_reg;
6614 if (me < 1 || me > adev->gfx.mec.num_mec) {
6615 DRM_ERROR("Ignoring request to enable interrupts for invalid me:%d\n", me);
6616 return;
6617 }
6618 6614
6619 if (pipe >= adev->gfx.mec.num_pipe_per_mec) { 6615 /*
6620 DRM_ERROR("Ignoring request to enable interrupts for invalid " 6616 * amdgpu controls only the first MEC. That's why this function only
6621 "me:%d pipe:%d\n", pipe, me); 6617 * handles the setting of interrupts for this specific MEC. All other
6618 * pipes' interrupts are set by amdkfd.
6619 */
6620
6621 if (me == 1) {
6622 switch (pipe) {
6623 case 0:
6624 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
6625 break;
6626 case 1:
6627 mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL;
6628 break;
6629 case 2:
6630 mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL;
6631 break;
6632 case 3:
6633 mec_int_cntl_reg = mmCP_ME1_PIPE3_INT_CNTL;
6634 break;
6635 default:
6636 DRM_DEBUG("invalid pipe %d\n", pipe);
6637 return;
6638 }
6639 } else {
6640 DRM_DEBUG("invalid me %d\n", me);
6622 return; 6641 return;
6623 } 6642 }
6624 6643
6625 mutex_lock(&adev->srbm_mutex); 6644 switch (state) {
6626 vi_srbm_select(adev, me, pipe, 0, 0); 6645 case AMDGPU_IRQ_STATE_DISABLE:
6627 6646 mec_int_cntl = RREG32(mec_int_cntl_reg);
6628 WREG32_FIELD(CPC_INT_CNTL, TIME_STAMP_INT_ENABLE, 6647 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
6629 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1); 6648 WREG32(mec_int_cntl_reg, mec_int_cntl);
6630 6649 break;
6631 vi_srbm_select(adev, 0, 0, 0, 0); 6650 case AMDGPU_IRQ_STATE_ENABLE:
6632 mutex_unlock(&adev->srbm_mutex); 6651 mec_int_cntl = RREG32(mec_int_cntl_reg);
6652 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
6653 WREG32(mec_int_cntl_reg, mec_int_cntl);
6654 break;
6655 default:
6656 break;
6657 }
6633} 6658}
6634 6659
6635static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 6660static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 375620afd328..e9dd2c183a58 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3982,26 +3982,53 @@ static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3982 int me, int pipe, 3982 int me, int pipe,
3983 enum amdgpu_interrupt_state state) 3983 enum amdgpu_interrupt_state state)
3984{ 3984{
3985 /* Me 0 is reserved for graphics */ 3985 u32 mec_int_cntl, mec_int_cntl_reg;
3986 if (me < 1 || me > adev->gfx.mec.num_mec) {
3987 DRM_ERROR("Ignoring request to enable interrupts for invalid me:%d\n", me);
3988 return;
3989 }
3990 3986
3991 if (pipe >= adev->gfx.mec.num_pipe_per_mec) { 3987 /*
3992 DRM_ERROR("Ignoring request to enable interrupts for invalid " 3988 * amdgpu controls only the first MEC. That's why this function only
3993 "me:%d pipe:%d\n", pipe, me); 3989 * handles the setting of interrupts for this specific MEC. All other
3990 * pipes' interrupts are set by amdkfd.
3991 */
3992
3993 if (me == 1) {
3994 switch (pipe) {
3995 case 0:
3996 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
3997 break;
3998 case 1:
3999 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
4000 break;
4001 case 2:
4002 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
4003 break;
4004 case 3:
4005 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
4006 break;
4007 default:
4008 DRM_DEBUG("invalid pipe %d\n", pipe);
4009 return;
4010 }
4011 } else {
4012 DRM_DEBUG("invalid me %d\n", me);
3994 return; 4013 return;
3995 } 4014 }
3996 4015
3997 mutex_lock(&adev->srbm_mutex); 4016 switch (state) {
3998 soc15_grbm_select(adev, me, pipe, 0, 0); 4017 case AMDGPU_IRQ_STATE_DISABLE:
3999 4018 mec_int_cntl = RREG32(mec_int_cntl_reg);
4000 WREG32_FIELD(CPC_INT_CNTL, TIME_STAMP_INT_ENABLE, 4019 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4001 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1); 4020 TIME_STAMP_INT_ENABLE, 0);
4002 4021 WREG32(mec_int_cntl_reg, mec_int_cntl);
4003 soc15_grbm_select(adev, 0, 0, 0, 0); 4022 break;
4004 mutex_unlock(&adev->srbm_mutex); 4023 case AMDGPU_IRQ_STATE_ENABLE:
4024 mec_int_cntl = RREG32(mec_int_cntl_reg);
4025 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4026 TIME_STAMP_INT_ENABLE, 1);
4027 WREG32(mec_int_cntl_reg, mec_int_cntl);
4028 break;
4029 default:
4030 break;
4031 }
4005} 4032}
4006 4033
4007static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4034static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-11 20:41:07 -0400