aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorArnd Bergmann <arnd@arndb.de>2016-11-25 18:52:10 -0500
committerArnd Bergmann <arnd@arndb.de>2016-11-25 18:52:10 -0500
commitd0bf34f39b7ee3f040da0a9be7ed5e169936c578 (patch)
tree5daf0038309b66eb3e8b845e5ea9a9d9ef158fdd
parent6c3026980ecec99b39ebec4191f8316955a4c9da (diff)
parent0fa1c17c162f9a5f5ca8b244f7bad7fd0aa7bc60 (diff)
Merge tag 'sunxi-dt-for-4.10-bis' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/dt
Pull "Allwinner DT additions for 4.10, bis" from Maxime Ripard: The usual bunch of DT additions, but most notably: - A31 DRM driver - A31 audio codec - WiFi for the A80-Based boards and the CHIP - Support for the NextThing Co CHIP Pro (the first board with NAND enabled) - New board: NanoPi M1 * tag 'sunxi-dt-for-4.10-bis' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: (41 commits) ARM: dts: sun6i: hummingbird-a31: Enable display output through VGA bridge ARM: dts: sun5i: Add touchscreen node to reference-design-tablet.dtsi ARM: sunxi: Add the missing clocks to the pinctrl nodes ARM: dts: sun7i: bananapi-m1-plus: Enable USB OTG ARM: dts: sun7i: bananapi-m1-plus: Add PMIC regulators ARM: dts: sun7i: bananapi-m1-plus: Enable USB PHY for USB host support ARM: sun8i: sina33: Enable USB gadget ARM: dts: sun8i: reference-design-tablet: ldo_io1 is vcc-touchscreen ARM: dts: sun8i: replace enable-sdio-wakeup with wakeup-source for BananaPi M1+ ARM: gr8: evb: Add i2s codec ARM: dts: sun6i: sina31s: Enable internal audio codec ARM: dts: sun6i: hummingbird: Enable internal audio codec ARM: dts: sun6i: Add audio codec device node ARM: gr8: evb: Enable SPDIF ARM: dts: sun8i: Add SPI controller node in H3 ARM: dts: sun8i: Add SPI pinctrl node in H3 ARM: dts: sun8i: Add dts file for NanoPi M1 SBC ARM: dts: sun8i: Use the common file in NanoPi NEO SBC ARM: dts: sun8i: Add common dtsi file for NanoPi SBCs ARM: dts: sun9i: cubieboard4: Enable AP6330 WiFi ...
Diffstat
-rw-r--r--arch/arm/boot/dts/Makefile3
-rw-r--r--arch/arm/boot/dts/sun4i-a10.dtsi3
-rw-r--r--arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts4
-rw-r--r--arch/arm/boot/dts/sun5i-a10s.dtsi4
-rw-r--r--arch/arm/boot/dts/sun5i-a13-olinuxino.dts54
-rw-r--r--arch/arm/boot/dts/sun5i-a13-utoo-p66.dts38
-rw-r--r--arch/arm/boot/dts/sun5i-gr8-chip-pro.dts266
-rw-r--r--arch/arm/boot/dts/sun5i-gr8-evb.dts (renamed from arch/arm/boot/dts/ntc-gr8-evb.dts)35
-rw-r--r--arch/arm/boot/dts/sun5i-gr8.dtsi (renamed from arch/arm/boot/dts/ntc-gr8.dtsi)47
-rw-r--r--arch/arm/boot/dts/sun5i-r8-chip.dts69
-rw-r--r--arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi25
-rw-r--r--arch/arm/boot/dts/sun5i.dtsi27
-rw-r--r--arch/arm/boot/dts/sun6i-a31-hummingbird.dts80
-rw-r--r--arch/arm/boot/dts/sun6i-a31.dtsi266
-rw-r--r--arch/arm/boot/dts/sun6i-a31s-sina31s.dts8
-rw-r--r--arch/arm/boot/dts/sun6i-a31s.dtsi8
-rw-r--r--arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts62
-rw-r--r--arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts4
-rw-r--r--arch/arm/boot/dts/sun7i-a20.dtsi3
-rw-r--r--arch/arm/boot/dts/sun8i-a23-a33.dtsi10
-rw-r--r--arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts7
-rw-r--r--arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts5
-rw-r--r--arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts64
-rw-r--r--arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts79
-rw-r--r--arch/arm/boot/dts/sun8i-h3-nanopi.dtsi144
-rw-r--r--arch/arm/boot/dts/sun8i-h3.dtsi52
-rw-r--r--arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi7
-rw-r--r--arch/arm/boot/dts/sun9i-a80-cubieboard4.dts32
-rw-r--r--arch/arm/boot/dts/sun9i-a80-optimus.dts30
-rw-r--r--arch/arm/boot/dts/sun9i-a80.dtsi14
30 files changed, 1277 insertions, 173 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 9181613c9344..3ba77c4f2943 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -760,7 +760,6 @@ dtb-$(CONFIG_MACH_SUN4I) += \
760 sun4i-a10-pcduino2.dtb \ 760 sun4i-a10-pcduino2.dtb \
761 sun4i-a10-pov-protab2-ips9.dtb 761 sun4i-a10-pov-protab2-ips9.dtb
762dtb-$(CONFIG_MACH_SUN5I) += \ 762dtb-$(CONFIG_MACH_SUN5I) += \
763 ntc-gr8-evb.dtb \
764 sun5i-a10s-auxtek-t003.dtb \ 763 sun5i-a10s-auxtek-t003.dtb \
765 sun5i-a10s-auxtek-t004.dtb \ 764 sun5i-a10s-auxtek-t004.dtb \
766 sun5i-a10s-mk802.dtb \ 765 sun5i-a10s-mk802.dtb \
@@ -776,6 +775,8 @@ dtb-$(CONFIG_MACH_SUN5I) += \
776 sun5i-a13-olinuxino-micro.dtb \ 775 sun5i-a13-olinuxino-micro.dtb \
777 sun5i-a13-q8-tablet.dtb \ 776 sun5i-a13-q8-tablet.dtb \
778 sun5i-a13-utoo-p66.dtb \ 777 sun5i-a13-utoo-p66.dtb \
778 sun5i-gr8-chip-pro.dtb \
779 sun5i-gr8-evb.dtb \
779 sun5i-r8-chip.dtb 780 sun5i-r8-chip.dtb
780dtb-$(CONFIG_MACH_SUN6I) += \ 781dtb-$(CONFIG_MACH_SUN6I) += \
781 sun6i-a31-app4-evb1.dtb \ 782 sun6i-a31-app4-evb1.dtb \
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 7e7dfc2b43db..b14a4281058d 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -967,7 +967,8 @@
967 compatible = "allwinner,sun4i-a10-pinctrl"; 967 compatible = "allwinner,sun4i-a10-pinctrl";
968 reg = <0x01c20800 0x400>; 968 reg = <0x01c20800 0x400>;
969 interrupts = <28>; 969 interrupts = <28>;
970 clocks = <&apb0_gates 5>; 970 clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>;
971 clock-names = "apb", "hosc", "losc";
971 gpio-controller; 972 gpio-controller;
972 interrupt-controller; 973 interrupt-controller;
973 #interrupt-cells = <3>; 974 #interrupt-cells = <3>;
diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
index aef91476f9ae..0684d7930d65 100644
--- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
@@ -250,8 +250,8 @@
250 250
251&spi2 { 251&spi2 {
252 pinctrl-names = "default"; 252 pinctrl-names = "default";
253 pinctrl-0 = <&spi2_pins_a>, 253 pinctrl-0 = <&spi2_pins_b>,
254 <&spi2_cs0_pins_a>; 254 <&spi2_cs0_pins_b>;
255 status = "okay"; 255 status = "okay";
256}; 256};
257 257
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index c41a2ba34dde..7aa8c7aa0153 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -243,14 +243,14 @@
243 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 243 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
244 }; 244 };
245 245
246 spi2_pins_a: spi2@0 { 246 spi2_pins_b: spi2@1 {
247 allwinner,pins = "PB12", "PB13", "PB14"; 247 allwinner,pins = "PB12", "PB13", "PB14";
248 allwinner,function = "spi2"; 248 allwinner,function = "spi2";
249 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 249 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
250 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 250 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
251 }; 251 };
252 252
253 spi2_cs0_pins_a: spi2_cs0@0 { 253 spi2_cs0_pins_b: spi2_cs0@1 {
254 allwinner,pins = "PB11"; 254 allwinner,pins = "PB11";
255 allwinner,function = "spi2"; 255 allwinner,function = "spi2";
256 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 256 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index b3c234c65ea1..bb7210e0e4a9 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -72,6 +72,47 @@
72 default-state = "on"; 72 default-state = "on";
73 }; 73 };
74 }; 74 };
75
76 bridge {
77 compatible = "dumb-vga-dac";
78 #address-cells = <1>;
79 #size-cells = <0>;
80
81 ports {
82 #address-cells = <1>;
83 #size-cells = <0>;
84
85 port@0 {
86 reg = <0>;
87
88 vga_bridge_in: endpoint {
89 remote-endpoint = <&tcon0_out_vga>;
90 };
91 };
92
93 port@1 {
94 reg = <1>;
95
96 vga_bridge_out: endpoint {
97 remote-endpoint = <&vga_con_in>;
98 };
99 };
100 };
101 };
102
103 vga {
104 compatible = "vga-connector";
105
106 port {
107 vga_con_in: endpoint {
108 remote-endpoint = <&vga_bridge_out>;
109 };
110 };
111 };
112};
113
114&be0 {
115 status = "okay";
75}; 116};
76 117
77&ehci0 { 118&ehci0 {
@@ -211,6 +252,19 @@
211 status = "okay"; 252 status = "okay";
212}; 253};
213 254
255&tcon0 {
256 pinctrl-names = "default";
257 pinctrl-0 = <&lcd_rgb666_pins>;
258 status = "okay";
259};
260
261&tcon0_out {
262 tcon0_out_vga: endpoint@0 {
263 reg = <0>;
264 remote-endpoint = <&vga_bridge_in>;
265 };
266};
267
214&uart1 { 268&uart1 {
215 pinctrl-names = "default"; 269 pinctrl-names = "default";
216 pinctrl-0 = <&uart1_pins_b>; 270 pinctrl-0 = <&uart1_pins_b>;
diff --git a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts
index a8b0bcc04514..3d7ff10a48e9 100644
--- a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts
+++ b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts
@@ -83,22 +83,6 @@
83 allwinner,pins = "PG3"; 83 allwinner,pins = "PG3";
84}; 84};
85 85
86&i2c1 {
87 icn8318: touchscreen@40 {
88 compatible = "chipone,icn8318";
89 reg = <0x40>;
90 interrupt-parent = <&pio>;
91 interrupts = <6 9 IRQ_TYPE_EDGE_FALLING>; /* EINT9 (PG9) */
92 pinctrl-names = "default";
93 pinctrl-0 = <&ts_wake_pin_p66>;
94 wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
95 touchscreen-size-x = <800>;
96 touchscreen-size-y = <480>;
97 touchscreen-inverted-x;
98 touchscreen-swapped-x-y;
99 };
100};
101
102&mmc2 { 86&mmc2 {
103 pinctrl-names = "default"; 87 pinctrl-names = "default";
104 pinctrl-0 = <&mmc2_pins_a>; 88 pinctrl-0 = <&mmc2_pins_a>;
@@ -121,20 +105,26 @@
121 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 105 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
122 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; 106 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
123 }; 107 };
124
125 ts_wake_pin_p66: ts_wake_pin@0 {
126 allwinner,pins = "PB3";
127 allwinner,function = "gpio_out";
128 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
129 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
130 };
131
132}; 108};
133 109
134&reg_usb0_vbus { 110&reg_usb0_vbus {
135 gpio = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ 111 gpio = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
136}; 112};
137 113
114&touchscreen {
115 compatible = "chipone,icn8318";
116 reg = <0x40>;
117 /* The P66 uses a different EINT then the reference design */
118 interrupts = <6 9 IRQ_TYPE_EDGE_FALLING>; /* EINT9 (PG9) */
119 /* The icn8318 binding expects wake-gpios instead of power-gpios */
120 wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
121 touchscreen-size-x = <800>;
122 touchscreen-size-y = <480>;
123 touchscreen-inverted-x;
124 touchscreen-swapped-x-y;
125 status = "okay";
126};
127
138&uart1 { 128&uart1 {
139 /* The P66 uses the uart pins as gpios */ 129 /* The P66 uses the uart pins as gpios */
140 status = "disabled"; 130 status = "disabled";
diff --git a/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts b/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts
new file mode 100644
index 000000000000..92a2dc6250a5
--- /dev/null
+++ b/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts
@@ -0,0 +1,266 @@
1/*
2 * Copyright 2016 Free Electrons
3 * Copyright 2016 NextThing Co
4 *
5 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 *
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
10 * whole.
11 *
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * Or, alternatively,
23 *
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
31 * conditions:
32 *
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
35 *
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
44 */
45
46/dts-v1/;
47#include "sun5i-gr8.dtsi"
48#include "sunxi-common-regulators.dtsi"
49
50#include <dt-bindings/gpio/gpio.h>
51#include <dt-bindings/input/input.h>
52#include <dt-bindings/interrupt-controller/irq.h>
53
54/ {
55 model = "NextThing C.H.I.P. Pro";
56 compatible = "nextthing,chip-pro", "nextthing,gr8";
57
58 aliases {
59 i2c0 = &i2c0;
60 i2c1 = &i2c1;
61 serial0 = &uart1;
62 serial1 = &uart2;
63 serial2 = &uart3;
64 };
65
66 chosen {
67 stdout-path = "serial0:115200n8";
68 };
69
70 leds {
71 compatible = "gpio-leds";
72
73 status {
74 label = "chip-pro:white:status";
75 gpios = <&axp_gpio 2 GPIO_ACTIVE_HIGH>;
76 default-state = "on";
77 };
78 };
79
80 mmc0_pwrseq: mmc0_pwrseq {
81 compatible = "mmc-pwrseq-simple";
82 pinctrl-names = "default";
83 pinctrl-0 = <&wifi_reg_on_pin_chip_pro>;
84 reset-gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; /* PB10 */
85 };
86};
87
88&codec {
89 status = "okay";
90};
91
92&ehci0 {
93 status = "okay";
94};
95
96&i2c0 {
97 pinctrl-names = "default";
98 pinctrl-0 = <&i2c0_pins_a>;
99 status = "okay";
100
101 axp209: pmic@34 {
102 reg = <0x34>;
103
104 /*
105 * The interrupt is routed through the "External Fast
106 * Interrupt Request" pin (ball G13 of the module)
107 * directly to the main interrupt controller, without
108 * any other controller interfering.
109 */
110 interrupts = <0>;
111 };
112};
113
114#include "axp209.dtsi"
115
116&i2c1 {
117 pinctrl-names = "default";
118 pinctrl-0 = <&i2c1_pins_a>;
119 status = "disabled";
120};
121
122&i2s0 {
123 pinctrl-names = "default";
124 pinctrl-0 = <&i2s0_mclk_pins_a>, <&i2s0_data_pins_a>;
125 status = "disabled";
126};
127
128&mmc0 {
129 pinctrl-names = "default";
130 pinctrl-0 = <&mmc0_pins_a>;
131 vmmc-supply = <&reg_vcc3v3>;
132 mmc-pwrseq = <&mmc0_pwrseq>;
133 bus-width = <4>;
134 non-removable;
135 status = "okay";
136};
137
138&nfc {
139 pinctrl-names = "default";
140 pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>;
141 status = "okay";
142
143 nand@0 {
144 #address-cells = <2>;
145 #size-cells = <2>;
146 reg = <0>;
147 allwinner,rb = <0>;
148 nand-ecc-mode = "hw";
149 };
150};
151
152&ohci0 {
153 status = "okay";
154};
155
156&otg_sram {
157 status = "okay";
158};
159
160&pio {
161 usb0_id_pin_chip_pro: usb0-id-pin@0 {
162 allwinner,pins = "PG2";
163 allwinner,function = "gpio_in";
164 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
165 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
166 };
167
168 wifi_reg_on_pin_chip_pro: wifi-reg-on-pin@0 {
169 allwinner,pins = "PB10";
170 allwinner,function = "gpio_out";
171 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
172 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
173 };
174};
175
176&pwm {
177 pinctrl-names = "default";
178 pinctrl-0 = <&pwm0_pins_a>, <&pwm1_pins>;
179 status = "disabled";
180};
181
182&reg_dcdc2 {
183 regulator-min-microvolt = <1000000>;
184 regulator-max-microvolt = <1400000>;
185 regulator-name = "vdd-cpu";
186 regulator-always-on;
187};
188
189&reg_dcdc3 {
190 regulator-min-microvolt = <1000000>;
191 regulator-max-microvolt = <1300000>;
192 regulator-name = "vdd-sys";
193 regulator-always-on;
194};
195
196&reg_ldo1 {
197 regulator-name = "vdd-rtc";
198};
199
200&reg_ldo2 {
201 regulator-min-microvolt = <2700000>;
202 regulator-max-microvolt = <3300000>;
203 regulator-name = "avcc";
204 regulator-always-on;
205};
206
207/*
208 * Both LDO3 and LDO4 are used in parallel to power up the
209 * WiFi/BT chip.
210 */
211&reg_ldo3 {
212 regulator-min-microvolt = <3300000>;
213 regulator-max-microvolt = <3300000>;
214 regulator-name = "vcc-wifi-1";
215 regulator-always-on;
216};
217
218&reg_ldo4 {
219 regulator-min-microvolt = <3300000>;
220 regulator-max-microvolt = <3300000>;
221 regulator-name = "vcc-wifi-2";
222 regulator-always-on;
223};
224
225&uart1 {
226 pinctrl-names = "default";
227 pinctrl-0 = <&uart1_pins_a>, <&uart1_cts_rts_pins_a>;
228 status = "okay";
229};
230
231&uart2 {
232 pinctrl-names = "default";
233 pinctrl-0 = <&uart2_pins_a>, <&uart2_cts_rts_pins_a>;
234 status = "disabled";
235};
236
237&uart3 {
238 pinctrl-names = "default";
239 pinctrl-0 = <&uart3_pins_a>, <&uart3_cts_rts_pins_a>;
240 status = "okay";
241};
242
243&usb_otg {
244 /*
245 * The CHIP Pro doesn't have a controllable VBUS, nor does it
246 * have any 5v rail on the board itself.
247 *
248 * If one wants to use it as a true OTG port, it should be
249 * done in the baseboard, and its DT / overlay will add it.
250 */
251 dr_mode = "otg";
252 status = "okay";
253};
254
255&usb_power_supply {
256 status = "okay";
257};
258
259&usbphy {
260 pinctrl-names = "default";
261 pinctrl-0 = <&usb0_id_pin_chip_pro>;
262 usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
263 usb0_vbus_power-supply = <&usb_power_supply>;
264 usb1_vbus-supply = <&reg_vcc5v0>;
265 status = "okay";
266};
diff --git a/arch/arm/boot/dts/ntc-gr8-evb.dts b/arch/arm/boot/dts/sun5i-gr8-evb.dts
index 4b622f3b5220..030605aa8065 100644
--- a/arch/arm/boot/dts/ntc-gr8-evb.dts
+++ b/arch/arm/boot/dts/sun5i-gr8-evb.dts
@@ -44,7 +44,7 @@
44 */ 44 */
45 45
46/dts-v1/; 46/dts-v1/;
47#include "ntc-gr8.dtsi" 47#include "sun5i-gr8.dtsi"
48#include "sunxi-common-regulators.dtsi" 48#include "sunxi-common-regulators.dtsi"
49 49
50#include <dt-bindings/gpio/gpio.h> 50#include <dt-bindings/gpio/gpio.h>
@@ -75,6 +75,39 @@
75 brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; 75 brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
76 default-brightness-level = <8>; 76 default-brightness-level = <8>;
77 }; 77 };
78
79 sound-analog {
80 compatible = "simple-audio-card";
81 simple-audio-card,name = "gr8-evb-wm8978";
82 simple-audio-card,format = "i2s";
83 simple-audio-card,mclk-fs = <512>;
84
85 simple-audio-card,cpu {
86 sound-dai = <&i2s0>;
87 };
88
89 simple-audio-card,codec {
90 sound-dai = <&wm8978>;
91 };
92 };
93
94 sound-spdif {
95 compatible = "simple-audio-card";
96 simple-audio-card,name = "On-board SPDIF";
97
98 simple-audio-card,cpu {
99 sound-dai = <&spdif>;
100 };
101
102 simple-audio-card,codec {
103 sound-dai = <&spdif_out>;
104 };
105 };
106
107 spdif_out: spdif-out {
108 #sound-dai-cells = <0>;
109 compatible = "linux,spdif-dit";
110 };
78}; 111};
79 112
80&be0 { 113&be0 {
diff --git a/arch/arm/boot/dts/ntc-gr8.dtsi b/arch/arm/boot/dts/sun5i-gr8.dtsi
index ca54e03ef366..ea86d4d58db6 100644
--- a/arch/arm/boot/dts/ntc-gr8.dtsi
+++ b/arch/arm/boot/dts/sun5i-gr8.dtsi
@@ -792,7 +792,7 @@
792 }; 792 };
793 793
794 i2s0_mclk_pins_a: i2s0-mclk@0 { 794 i2s0_mclk_pins_a: i2s0-mclk@0 {
795 allwinner,pins = "PB6", "PB7", "PB8", "PB9"; 795 allwinner,pins = "PB5";
796 allwinner,function = "i2s0"; 796 allwinner,function = "i2s0";
797 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 797 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
798 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 798 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
@@ -854,6 +854,13 @@
854 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 854 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
855 }; 855 };
856 856
857 pwm1_pins: pwm1 {
858 allwinner,pins = "PG13";
859 allwinner,function = "pwm1";
860 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
861 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
862 };
863
857 spdif_tx_pins_a: spdif@0 { 864 spdif_tx_pins_a: spdif@0 {
858 allwinner,pins = "PB10"; 865 allwinner,pins = "PB10";
859 allwinner,function = "spdif"; 866 allwinner,function = "spdif";
@@ -874,6 +881,34 @@
874 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 881 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
875 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 882 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
876 }; 883 };
884
885 uart2_pins_a: uart2@1 {
886 allwinner,pins = "PD2", "PD3";
887 allwinner,function = "uart2";
888 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
889 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
890 };
891
892 uart2_cts_rts_pins_a: uart2-cts-rts@0 {
893 allwinner,pins = "PD4", "PD5";
894 allwinner,function = "uart2";
895 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
896 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
897 };
898
899 uart3_pins_a: uart3@1 {
900 allwinner,pins = "PG9", "PG10";
901 allwinner,function = "uart3";
902 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
903 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
904 };
905
906 uart3_cts_rts_pins_a: uart3-cts-rts@0 {
907 allwinner,pins = "PG11", "PG12";
908 allwinner,function = "uart3";
909 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
910 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
911 };
877 }; 912 };
878 913
879 pwm: pwm@01c20e00 { 914 pwm: pwm@01c20e00 {
@@ -978,6 +1013,16 @@
978 status = "disabled"; 1013 status = "disabled";
979 }; 1014 };
980 1015
1016 uart3: serial@01c28c00 {
1017 compatible = "snps,dw-apb-uart";
1018 reg = <0x01c28c00 0x400>;
1019 interrupts = <4>;
1020 reg-shift = <2>;
1021 reg-io-width = <4>;
1022 clocks = <&apb1_gates 19>;
1023 status = "disabled";
1024 };
1025
981 i2c0: i2c@01c2ac00 { 1026 i2c0: i2c@01c2ac00 {
982 compatible = "allwinner,sun4i-a10-i2c"; 1027 compatible = "allwinner,sun4i-a10-i2c";
983 reg = <0x01c2ac00 0x400>; 1028 reg = <0x01c2ac00 0x400>;
diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts
index b68a12374b35..c6da5ad37152 100644
--- a/arch/arm/boot/dts/sun5i-r8-chip.dts
+++ b/arch/arm/boot/dts/sun5i-r8-chip.dts
@@ -56,9 +56,11 @@
56 56
57 aliases { 57 aliases {
58 i2c0 = &i2c0; 58 i2c0 = &i2c0;
59 i2c1 = &i2c1;
59 i2c2 = &i2c2; 60 i2c2 = &i2c2;
60 serial0 = &uart1; 61 serial0 = &uart1;
61 serial1 = &uart3; 62 serial1 = &uart3;
63 spi0 = &spi2;
62 }; 64 };
63 65
64 chosen { 66 chosen {
@@ -74,6 +76,20 @@
74 default-state = "on"; 76 default-state = "on";
75 }; 77 };
76 }; 78 };
79
80 mmc0_pwrseq: mmc0_pwrseq {
81 compatible = "mmc-pwrseq-simple";
82 pinctrl-names = "default";
83 pinctrl-0 = <&chip_wifi_reg_on_pin>;
84 reset-gpios = <&pio 2 19 GPIO_ACTIVE_LOW>; /* PC19 */
85 };
86
87 onewire {
88 compatible = "w1-gpio";
89 gpios = <&pio 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */
90 pinctrl-names = "default";
91 pinctrl-0 = <&chip_w1_pin>;
92 };
77}; 93};
78 94
79&be0 { 95&be0 {
@@ -112,6 +128,12 @@
112 128
113#include "axp209.dtsi" 129#include "axp209.dtsi"
114 130
131&i2c1 {
132 pinctrl-names = "default";
133 pinctrl-0 = <&i2c1_pins_a>;
134 status = "disabled";
135};
136
115&i2c2 { 137&i2c2 {
116 pinctrl-names = "default"; 138 pinctrl-names = "default";
117 pinctrl-0 = <&i2c2_pins_a>; 139 pinctrl-0 = <&i2c2_pins_a>;
@@ -131,10 +153,15 @@
131 }; 153 };
132}; 154};
133 155
156&mmc0_pins_a {
157 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
158};
159
134&mmc0 { 160&mmc0 {
135 pinctrl-names = "default"; 161 pinctrl-names = "default";
136 pinctrl-0 = <&mmc0_pins_a>; 162 pinctrl-0 = <&mmc0_pins_a>;
137 vmmc-supply = <&reg_vcc3v3>; 163 vmmc-supply = <&reg_vcc3v3>;
164 mmc-pwrseq = <&mmc0_pwrseq>;
138 bus-width = <4>; 165 bus-width = <4>;
139 non-removable; 166 non-removable;
140 status = "okay"; 167 status = "okay";
@@ -156,12 +183,26 @@
156 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 183 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
157 }; 184 };
158 185
186 chip_wifi_reg_on_pin: chip_wifi_reg_on_pin@0 {
187 allwinner,pins = "PC19";
188 allwinner,function = "gpio_out";
189 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
190 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
191 };
192
159 chip_id_det_pin: chip_id_det_pin@0 { 193 chip_id_det_pin: chip_id_det_pin@0 {
160 allwinner,pins = "PG2"; 194 allwinner,pins = "PG2";
161 allwinner,function = "gpio_in"; 195 allwinner,function = "gpio_in";
162 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 196 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
163 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 197 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
164 }; 198 };
199
200 chip_w1_pin: chip_w1_pin@0 {
201 allwinner,pins = "PD2";
202 allwinner,function = "gpio_in";
203 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
204 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
205 };
165}; 206};
166 207
167&reg_dcdc2 { 208&reg_dcdc2 {
@@ -189,6 +230,28 @@
189 regulator-always-on; 230 regulator-always-on;
190}; 231};
191 232
233/*
234 * Both LDO3 and LDO4 are used in parallel to power up the WiFi/BT
235 * Chip.
236 *
237 * If those are not enabled, the SDIO part will not enumerate, and
238 * since there's no way currently to pass DT infos to an SDIO device,
239 * we cannot really do better than this ugly hack for now.
240 */
241&reg_ldo3 {
242 regulator-min-microvolt = <3300000>;
243 regulator-max-microvolt = <3300000>;
244 regulator-name = "vcc-wifi-1";
245 regulator-always-on;
246};
247
248&reg_ldo4 {
249 regulator-min-microvolt = <3300000>;
250 regulator-max-microvolt = <3300000>;
251 regulator-name = "vcc-wifi-2";
252 regulator-always-on;
253};
254
192&reg_ldo5 { 255&reg_ldo5 {
193 regulator-min-microvolt = <1800000>; 256 regulator-min-microvolt = <1800000>;
194 regulator-max-microvolt = <1800000>; 257 regulator-max-microvolt = <1800000>;
@@ -202,6 +265,12 @@
202 status = "okay"; 265 status = "okay";
203}; 266};
204 267
268&spi2 {
269 pinctrl-names = "default";
270 pinctrl-0 = <&spi2_pins_a>;
271 status = "disabled";
272};
273
205&tcon0 { 274&tcon0 {
206 status = "okay"; 275 status = "okay";
207}; 276};
diff --git a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi
index 20cc940f5f91..82f87cdcd164 100644
--- a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi
+++ b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi
@@ -41,6 +41,7 @@
41 */ 41 */
42#include "sunxi-reference-design-tablet.dtsi" 42#include "sunxi-reference-design-tablet.dtsi"
43 43
44#include <dt-bindings/interrupt-controller/irq.h>
44#include <dt-bindings/pwm/pwm.h> 45#include <dt-bindings/pwm/pwm.h>
45 46
46/ { 47/ {
@@ -84,6 +85,23 @@
84}; 85};
85 86
86&i2c1 { 87&i2c1 {
88 /*
89 * The gsl1680 is rated at 400KHz and it will not work reliable at
90 * 100KHz, this has been confirmed on multiple different q8 tablets.
91 * All other devices on this bus are also rated for 400KHz.
92 */
93 clock-frequency = <400000>;
94
95 touchscreen: touchscreen {
96 interrupt-parent = <&pio>;
97 interrupts = <6 11 IRQ_TYPE_EDGE_FALLING>; /* EINT11 (PG11) */
98 pinctrl-names = "default";
99 pinctrl-0 = <&ts_power_pin>;
100 power-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
101 /* Tablet dts must provide reg and compatible */
102 status = "disabled";
103 };
104
87 pcf8563: rtc@51 { 105 pcf8563: rtc@51 {
88 compatible = "nxp,pcf8563"; 106 compatible = "nxp,pcf8563";
89 reg = <0x51>; 107 reg = <0x51>;
@@ -125,6 +143,13 @@
125 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; 143 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
126 }; 144 };
127 145
146 ts_power_pin: ts_power_pin {
147 pins = "PB3";
148 function = "gpio_out";
149 drive-strength = <10>;
150 bias-disable;
151 };
152
128 usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { 153 usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
129 allwinner,pins = "PG1"; 154 allwinner,pins = "PG1";
130 allwinner,function = "gpio_in"; 155 allwinner,function = "gpio_in";
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index e374f4fc8073..b0fca4ef4dae 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -547,7 +547,8 @@
547 pio: pinctrl@01c20800 { 547 pio: pinctrl@01c20800 {
548 reg = <0x01c20800 0x400>; 548 reg = <0x01c20800 0x400>;
549 interrupts = <28>; 549 interrupts = <28>;
550 clocks = <&apb0_gates 5>; 550 clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>;
551 clock-names = "apb", "hosc", "losc";
551 gpio-controller; 552 gpio-controller;
552 interrupt-controller; 553 interrupt-controller;
553 #interrupt-cells = <3>; 554 #interrupt-cells = <3>;
@@ -574,6 +575,16 @@
574 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 575 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
575 }; 576 };
576 577
578 lcd_rgb565_pins: lcd_rgb565@0 {
579 allwinner,pins = "PD3", "PD4", "PD5", "PD6", "PD7",
580 "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
581 "PD19", "PD20", "PD21", "PD22", "PD23",
582 "PD24", "PD25", "PD26", "PD27";
583 allwinner,function = "lcd0";
584 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
585 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
586 };
587
577 mmc0_pins_a: mmc0@0 { 588 mmc0_pins_a: mmc0@0 {
578 allwinner,pins = "PF0", "PF1", "PF2", "PF3", 589 allwinner,pins = "PF0", "PF1", "PF2", "PF3",
579 "PF4", "PF5"; 590 "PF4", "PF5";
@@ -591,6 +602,20 @@
591 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; 602 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
592 }; 603 };
593 604
605 spi2_pins_a: spi2@0 {
606 allwinner,pins = "PE1", "PE2", "PE3";
607 allwinner,function = "spi2";
608 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
609 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
610 };
611
612 spi2_cs0_pins_a: spi2-cs0@0 {
613 allwinner,pins = "PE0";
614 allwinner,function = "spi2";
615 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
616 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
617 };
618
594 uart3_pins_a: uart3@0 { 619 uart3_pins_a: uart3@0 {
595 allwinner,pins = "PG9", "PG10"; 620 allwinner,pins = "PG9", "PG10";
596 allwinner,function = "uart3"; 621 allwinner,function = "uart3";
diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
index 9a74637f677f..735914f6ae44 100644
--- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
+++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
@@ -63,12 +63,79 @@
63 stdout-path = "serial0:115200n8"; 63 stdout-path = "serial0:115200n8";
64 }; 64 };
65 65
66 vga-connector {
67 compatible = "vga-connector";
68
69 port {
70 vga_con_in: endpoint {
71 remote-endpoint = <&vga_dac_out>;
72 };
73 };
74 };
75
76 vga-dac {
77 compatible = "dumb-vga-dac";
78 vdd-supply = <&reg_vga_3v3>;
79 #address-cells = <1>;
80 #size-cells = <0>;
81
82 ports {
83 #address-cells = <1>;
84 #size-cells = <0>;
85
86 port@0 {
87 #address-cells = <1>;
88 #size-cells = <0>;
89 reg = <0>;
90
91 vga_dac_in: endpoint@0 {
92 reg = <0>;
93 remote-endpoint = <&tcon0_out_vga>;
94 };
95 };
96
97 port@1 {
98 #address-cells = <1>;
99 #size-cells = <0>;
100 reg = <1>;
101
102 vga_dac_out: endpoint@0 {
103 reg = <0>;
104 remote-endpoint = <&vga_con_in>;
105 };
106 };
107 };
108 };
109
110 reg_vga_3v3: vga_3v3_regulator {
111 compatible = "regulator-fixed";
112 regulator-name = "vga-3v3";
113 regulator-min-microvolt = <3300000>;
114 regulator-max-microvolt = <3300000>;
115 regulator-boot-on;
116 enable-active-high;
117 gpio = <&pio 7 25 GPIO_ACTIVE_HIGH>; /* PH25 */
118 };
119
66 wifi_pwrseq: wifi_pwrseq { 120 wifi_pwrseq: wifi_pwrseq {
67 compatible = "mmc-pwrseq-simple"; 121 compatible = "mmc-pwrseq-simple";
68 reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 */ 122 reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 */
69 }; 123 };
70}; 124};
71 125
126&codec {
127 allwinner,audio-routing =
128 "Headphone", "HP",
129 "Speaker", "LINEOUT",
130 "LINEIN", "Line In",
131 "MIC1", "Mic",
132 "MIC2", "Headset Mic",
133 "Mic", "MBIAS",
134 "Headset Mic", "HBIAS";
135 allwinner,pa-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */
136 status = "okay";
137};
138
72&cpu0 { 139&cpu0 {
73 cpu-supply = <&reg_dcdc3>; 140 cpu-supply = <&reg_dcdc3>;
74}; 141};
@@ -245,6 +312,19 @@
245 status = "okay"; 312 status = "okay";
246}; 313};
247 314
315&tcon0 {
316 pinctrl-names = "default";
317 pinctrl-0 = <&lcd0_rgb888_pins>;
318 status = "okay";
319};
320
321&tcon0_out {
322 tcon0_out_vga: endpoint@0 {
323 reg = <0>;
324 remote-endpoint = <&vga_dac_in>;
325 };
326};
327
248&uart0 { 328&uart0 {
249 pinctrl-names = "default"; 329 pinctrl-names = "default";
250 pinctrl-0 = <&uart0_pins_a>; 330 pinctrl-0 = <&uart0_pins_a>;
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index ce1960453a0b..2b26175d55d1 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -231,6 +231,11 @@
231 }; 231 };
232 }; 232 };
233 233
234 de: display-engine {
235 compatible = "allwinner,sun6i-a31-display-engine";
236 allwinner,pipelines = <&fe0>;
237 };
238
234 soc@01c00000 { 239 soc@01c00000 {
235 compatible = "simple-bus"; 240 compatible = "simple-bus";
236 #address-cells = <1>; 241 #address-cells = <1>;
@@ -246,6 +251,44 @@
246 #dma-cells = <1>; 251 #dma-cells = <1>;
247 }; 252 };
248 253
254 tcon0: lcd-controller@01c0c000 {
255 compatible = "allwinner,sun6i-a31-tcon";
256 reg = <0x01c0c000 0x1000>;
257 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
258 resets = <&ccu RST_AHB1_LCD0>;
259 reset-names = "lcd";
260 clocks = <&ccu CLK_AHB1_LCD0>,
261 <&ccu CLK_LCD0_CH0>,
262 <&ccu CLK_LCD0_CH1>;
263 clock-names = "ahb",
264 "tcon-ch0",
265 "tcon-ch1";
266 clock-output-names = "tcon0-pixel-clock";
267 status = "disabled";
268
269 ports {
270 #address-cells = <1>;
271 #size-cells = <0>;
272
273 tcon0_in: port@0 {
274 #address-cells = <1>;
275 #size-cells = <0>;
276 reg = <0>;
277
278 tcon0_in_drc0: endpoint@0 {
279 reg = <0>;
280 remote-endpoint = <&drc0_out_tcon0>;
281 };
282 };
283
284 tcon0_out: port@1 {
285 #address-cells = <1>;
286 #size-cells = <0>;
287 reg = <1>;
288 };
289 };
290 };
291
249 mmc0: mmc@01c0f000 { 292 mmc0: mmc@01c0f000 {
250 compatible = "allwinner,sun7i-a20-mmc"; 293 compatible = "allwinner,sun7i-a20-mmc";
251 reg = <0x01c0f000 0x1000>; 294 reg = <0x01c0f000 0x1000>;
@@ -428,19 +471,55 @@
428 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
429 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 472 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
430 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 473 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&ccu CLK_APB1_PIO>; 474 clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&osc32k>;
475 clock-names = "apb", "hosc", "losc";
432 gpio-controller; 476 gpio-controller;
433 interrupt-controller; 477 interrupt-controller;
434 #interrupt-cells = <3>; 478 #interrupt-cells = <3>;
435 #gpio-cells = <3>; 479 #gpio-cells = <3>;
436 480
437 uart0_pins_a: uart0@0 { 481 gmac_pins_gmii_a: gmac_gmii@0 {
438 allwinner,pins = "PH20", "PH21"; 482 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
439 allwinner,function = "uart0"; 483 "PA4", "PA5", "PA6", "PA7",
484 "PA8", "PA9", "PA10", "PA11",
485 "PA12", "PA13", "PA14", "PA15",
486 "PA16", "PA17", "PA18", "PA19",
487 "PA20", "PA21", "PA22", "PA23",
488 "PA24", "PA25", "PA26", "PA27";
489 allwinner,function = "gmac";
490 /*
491 * data lines in GMII mode run at 125MHz and
492 * might need a higher signal drive strength
493 */
494 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
495 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
496 };
497
498 gmac_pins_mii_a: gmac_mii@0 {
499 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
500 "PA8", "PA9", "PA11",
501 "PA12", "PA13", "PA14", "PA19",
502 "PA20", "PA21", "PA22", "PA23",
503 "PA24", "PA26", "PA27";
504 allwinner,function = "gmac";
440 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 505 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
441 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 506 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
442 }; 507 };
443 508
509 gmac_pins_rgmii_a: gmac_rgmii@0 {
510 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
511 "PA9", "PA10", "PA11",
512 "PA12", "PA13", "PA14", "PA19",
513 "PA20", "PA25", "PA26", "PA27";
514 allwinner,function = "gmac";
515 /*
516 * data lines in RGMII mode use DDR mode
517 * and need a higher signal drive strength
518 */
519 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
520 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
521 };
522
444 i2c0_pins_a: i2c0@0 { 523 i2c0_pins_a: i2c0@0 {
445 allwinner,pins = "PH14", "PH15"; 524 allwinner,pins = "PH14", "PH15";
446 allwinner,function = "i2c0"; 525 allwinner,function = "i2c0";
@@ -462,6 +541,19 @@
462 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 541 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
463 }; 542 };
464 543
544 lcd0_rgb888_pins: lcd0_rgb888 {
545 allwinner,pins = "PD0", "PD1", "PD2", "PD3",
546 "PD4", "PD5", "PD6", "PD7",
547 "PD8", "PD9", "PD10", "PD11",
548 "PD12", "PD13", "PD14", "PD15",
549 "PD16", "PD17", "PD18", "PD19",
550 "PD20", "PD21", "PD22", "PD23",
551 "PD24", "PD25", "PD26", "PD27";
552 allwinner,function = "lcd0";
553 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
554 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
555 };
556
465 mmc0_pins_a: mmc0@0 { 557 mmc0_pins_a: mmc0@0 {
466 allwinner,pins = "PF0", "PF1", "PF2", 558 allwinner,pins = "PF0", "PF1", "PF2",
467 "PF3", "PF4", "PF5"; 559 "PF3", "PF4", "PF5";
@@ -506,47 +598,12 @@
506 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 598 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
507 }; 599 };
508 600
509 gmac_pins_mii_a: gmac_mii@0 { 601 uart0_pins_a: uart0@0 {
510 allwinner,pins = "PA0", "PA1", "PA2", "PA3", 602 allwinner,pins = "PH20", "PH21";
511 "PA8", "PA9", "PA11", 603 allwinner,function = "uart0";
512 "PA12", "PA13", "PA14", "PA19",
513 "PA20", "PA21", "PA22", "PA23",
514 "PA24", "PA26", "PA27";
515 allwinner,function = "gmac";
516 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 604 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
517 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 605 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
518 }; 606 };
519
520 gmac_pins_gmii_a: gmac_gmii@0 {
521 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
522 "PA4", "PA5", "PA6", "PA7",
523 "PA8", "PA9", "PA10", "PA11",
524 "PA12", "PA13", "PA14", "PA15",
525 "PA16", "PA17", "PA18", "PA19",
526 "PA20", "PA21", "PA22", "PA23",
527 "PA24", "PA25", "PA26", "PA27";
528 allwinner,function = "gmac";
529 /*
530 * data lines in GMII mode run at 125MHz and
531 * might need a higher signal drive strength
532 */
533 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
534 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
535 };
536
537 gmac_pins_rgmii_a: gmac_rgmii@0 {
538 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
539 "PA9", "PA10", "PA11",
540 "PA12", "PA13", "PA14", "PA19",
541 "PA20", "PA25", "PA26", "PA27";
542 allwinner,function = "gmac";
543 /*
544 * data lines in RGMII mode use DDR mode
545 * and need a higher signal drive strength
546 */
547 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
548 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
549 };
550 }; 607 };
551 608
552 timer@01c20c00 { 609 timer@01c20c00 {
@@ -728,6 +785,19 @@
728 reset-names = "ahb"; 785 reset-names = "ahb";
729 }; 786 };
730 787
788 codec: codec@01c22c00 {
789 #sound-dai-cells = <0>;
790 compatible = "allwinner,sun6i-a31-codec";
791 reg = <0x01c22c00 0x400>;
792 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
793 clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>;
794 clock-names = "apb", "codec";
795 resets = <&ccu RST_APB1_CODEC>;
796 dmas = <&dma 15>, <&dma 15>;
797 dma-names = "rx", "tx";
798 status = "disabled";
799 };
800
731 timer@01c60000 { 801 timer@01c60000 {
732 compatible = "allwinner,sun6i-a31-hstimer", 802 compatible = "allwinner,sun6i-a31-hstimer",
733 "allwinner,sun7i-a20-hstimer"; 803 "allwinner,sun7i-a20-hstimer";
@@ -799,6 +869,115 @@
799 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 869 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
800 }; 870 };
801 871
872 fe0: display-frontend@01e00000 {
873 compatible = "allwinner,sun6i-a31-display-frontend";
874 reg = <0x01e00000 0x20000>;
875 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
876 clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>,
877 <&ccu CLK_DRAM_FE0>;
878 clock-names = "ahb", "mod",
879 "ram";
880 resets = <&ccu RST_AHB1_FE0>;
881
882 ports {
883 #address-cells = <1>;
884 #size-cells = <0>;
885
886 fe0_out: port@1 {
887 #address-cells = <1>;
888 #size-cells = <0>;
889 reg = <1>;
890
891 fe0_out_be0: endpoint@0 {
892 reg = <0>;
893 remote-endpoint = <&be0_in_fe0>;
894 };
895 };
896 };
897 };
898
899 be0: display-backend@01e60000 {
900 compatible = "allwinner,sun6i-a31-display-backend";
901 reg = <0x01e60000 0x10000>;
902 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
903 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>,
904 <&ccu CLK_DRAM_BE0>;
905 clock-names = "ahb", "mod",
906 "ram";
907 resets = <&ccu RST_AHB1_BE0>;
908
909 assigned-clocks = <&ccu CLK_BE0>;
910 assigned-clock-rates = <300000000>;
911
912 ports {
913 #address-cells = <1>;
914 #size-cells = <0>;
915
916 be0_in: port@0 {
917 #address-cells = <1>;
918 #size-cells = <0>;
919 reg = <0>;
920
921 be0_in_fe0: endpoint@0 {
922 reg = <0>;
923 remote-endpoint = <&fe0_out_be0>;
924 };
925 };
926
927 be0_out: port@1 {
928 #address-cells = <1>;
929 #size-cells = <0>;
930 reg = <1>;
931
932 be0_out_drc0: endpoint@0 {
933 reg = <0>;
934 remote-endpoint = <&drc0_in_be0>;
935 };
936 };
937 };
938 };
939
940 drc0: drc@01e70000 {
941 compatible = "allwinner,sun6i-a31-drc";
942 reg = <0x01e70000 0x10000>;
943 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
944 clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>,
945 <&ccu CLK_DRAM_DRC0>;
946 clock-names = "ahb", "mod",
947 "ram";
948 resets = <&ccu RST_AHB1_DRC0>;
949
950 assigned-clocks = <&ccu CLK_IEP_DRC0>;
951 assigned-clock-rates = <300000000>;
952
953 ports {
954 #address-cells = <1>;
955 #size-cells = <0>;
956
957 drc0_in: port@0 {
958 #address-cells = <1>;
959 #size-cells = <0>;
960 reg = <0>;
961
962 drc0_in_be0: endpoint@0 {
963 reg = <0>;
964 remote-endpoint = <&be0_out_drc0>;
965 };
966 };
967
968 drc0_out: port@1 {
969 #address-cells = <1>;
970 #size-cells = <0>;
971 reg = <1>;
972
973 drc0_out_tcon0: endpoint@0 {
974 reg = <0>;
975 remote-endpoint = <&tcon0_in_drc0>;
976 };
977 };
978 };
979 };
980
802 rtc: rtc@01f00000 { 981 rtc: rtc@01f00000 {
803 compatible = "allwinner,sun6i-a31-rtc"; 982 compatible = "allwinner,sun6i-a31-rtc";
804 reg = <0x01f00000 0x54>; 983 reg = <0x01f00000 0x54>;
@@ -886,7 +1065,8 @@
886 reg = <0x01f02c00 0x400>; 1065 reg = <0x01f02c00 0x400>;
887 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1066 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
888 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 1067 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
889 clocks = <&apb0_gates 0>; 1068 clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
1069 clock-names = "apb", "hosc", "losc";
890 resets = <&apb0_rst 0>; 1070 resets = <&apb0_rst 0>;
891 gpio-controller; 1071 gpio-controller;
892 interrupt-controller; 1072 interrupt-controller;
diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts
index 6ead2f5c847a..c35ec112f5a0 100644
--- a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts
+++ b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts
@@ -65,6 +65,14 @@
65 }; 65 };
66}; 66};
67 67
68&codec {
69 allwinner,audio-routing =
70 "Line Out", "LINEOUT",
71 "MIC1", "Mic",
72 "Mic", "MBIAS";
73 status = "okay";
74};
75
68&ehci0 { 76&ehci0 {
69 /* USB 2.0 4 port hub IC */ 77 /* USB 2.0 4 port hub IC */
70 status = "okay"; 78 status = "okay";
diff --git a/arch/arm/boot/dts/sun6i-a31s.dtsi b/arch/arm/boot/dts/sun6i-a31s.dtsi
index c17a32771b98..97e2c51d0aea 100644
--- a/arch/arm/boot/dts/sun6i-a31s.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31s.dtsi
@@ -48,6 +48,14 @@
48 48
49#include "sun6i-a31.dtsi" 49#include "sun6i-a31.dtsi"
50 50
51&de {
52 compatible = "allwinner,sun6i-a31s-display-engine";
53};
54
51&pio { 55&pio {
52 compatible = "allwinner,sun6i-a31s-pinctrl"; 56 compatible = "allwinner,sun6i-a31s-pinctrl";
53}; 57};
58
59&tcon0 {
60 compatible = "allwinner,sun6i-a31s-tcon";
61};
diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts
index ba5bca0fe997..532f1a160560 100644
--- a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts
+++ b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts
@@ -105,6 +105,10 @@
105 status = "okay"; 105 status = "okay";
106}; 106};
107 107
108&cpu0 {
109 cpu-supply = <&reg_dcdc2>;
110};
111
108&ehci0 { 112&ehci0 {
109 status = "okay"; 113 status = "okay";
110}; 114};
@@ -132,16 +136,14 @@
132 status = "okay"; 136 status = "okay";
133 137
134 axp209: pmic@34 { 138 axp209: pmic@34 {
135 compatible = "x-powers,axp209";
136 reg = <0x34>; 139 reg = <0x34>;
137 interrupt-parent = <&nmi_intc>; 140 interrupt-parent = <&nmi_intc>;
138 interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 141 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
139
140 interrupt-controller;
141 #interrupt-cells = <1>;
142 }; 142 };
143}; 143};
144 144
145#include "axp209.dtsi"
146
145&ir0 { 147&ir0 {
146 pinctrl-names = "default"; 148 pinctrl-names = "default";
147 pinctrl-0 = <&ir0_rx_pins_a>; 149 pinctrl-0 = <&ir0_rx_pins_a>;
@@ -167,7 +169,7 @@
167 mmc-pwrseq = <&mmc3_pwrseq>; 169 mmc-pwrseq = <&mmc3_pwrseq>;
168 bus-width = <4>; 170 bus-width = <4>;
169 non-removable; 171 non-removable;
170 enable-sdio-wakeup; 172 wakeup-source;
171 status = "okay"; 173 status = "okay";
172 174
173 brcmf: bcrmf@1 { 175 brcmf: bcrmf@1 {
@@ -192,6 +194,10 @@
192 status = "okay"; 194 status = "okay";
193}; 195};
194 196
197&otg_sram {
198 status = "okay";
199};
200
195&pio { 201&pio {
196 gmac_power_pin_bpi_m1p: gmac_power_pin@0 { 202 gmac_power_pin_bpi_m1p: gmac_power_pin@0 {
197 allwinner,pins = "PH23"; 203 allwinner,pins = "PH23";
@@ -222,8 +228,54 @@
222 }; 228 };
223}; 229};
224 230
231&reg_dcdc2 {
232 regulator-always-on;
233 regulator-min-microvolt = <1000000>;
234 regulator-max-microvolt = <1400000>;
235 regulator-name = "vdd-cpu";
236};
237
238&reg_dcdc3 {
239 regulator-always-on;
240 regulator-min-microvolt = <1000000>;
241 regulator-max-microvolt = <1400000>;
242 regulator-name = "vdd-int-dll";
243};
244
245&reg_ldo1 {
246 regulator-name = "vdd-rtc";
247};
248
249&reg_ldo2 {
250 regulator-always-on;
251 regulator-min-microvolt = <3000000>;
252 regulator-max-microvolt = <3000000>;
253 regulator-name = "avcc";
254};
255
256&reg_usb0_vbus {
257 status = "okay";
258};
259
225&uart0 { 260&uart0 {
226 pinctrl-names = "default"; 261 pinctrl-names = "default";
227 pinctrl-0 = <&uart0_pins_a>; 262 pinctrl-0 = <&uart0_pins_a>;
228 status = "okay"; 263 status = "okay";
229}; 264};
265
266&usb_otg {
267 dr_mode = "otg";
268 status = "okay";
269};
270
271&usb_power_supply {
272 status = "okay";
273};
274
275&usbphy {
276 usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
277 usb0_vbus_power-supply = <&usb_power_supply>;
278 usb0_vbus-supply = <&reg_usb0_vbus>;
279 /* VBUS on usb host ports are tied to DC5V and therefore always on */
280 status = "okay";
281};
diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts
index 23aacce4d6c7..134e0c1b129d 100644
--- a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts
@@ -88,6 +88,10 @@
88 status = "okay"; 88 status = "okay";
89}; 89};
90 90
91&cpu0 {
92 cpu-supply = <&reg_dcdc2>;
93};
94
91&codec { 95&codec {
92 status = "okay"; 96 status = "okay";
93}; 97};
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 94cf5a1c7172..f7db067b0de0 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -1085,7 +1085,8 @@
1085 compatible = "allwinner,sun7i-a20-pinctrl"; 1085 compatible = "allwinner,sun7i-a20-pinctrl";
1086 reg = <0x01c20800 0x400>; 1086 reg = <0x01c20800 0x400>;
1087 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 1087 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1088 clocks = <&apb0_gates 5>; 1088 clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>;
1089 clock-names = "apb", "hosc", "losc";
1089 gpio-controller; 1090 gpio-controller;
1090 interrupt-controller; 1091 interrupt-controller;
1091 #interrupt-cells = <3>; 1092 #interrupt-cells = <3>;
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index 48fc24f36fcb..e4991a78ad73 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -266,7 +266,8 @@
266 /* compatible gets set in SoC specific dtsi file */ 266 /* compatible gets set in SoC specific dtsi file */
267 reg = <0x01c20800 0x400>; 267 reg = <0x01c20800 0x400>;
268 /* interrupts get set in SoC specific dtsi file */ 268 /* interrupts get set in SoC specific dtsi file */
269 clocks = <&ccu CLK_BUS_PIO>; 269 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
270 clock-names = "apb", "hosc", "losc";
270 gpio-controller; 271 gpio-controller;
271 interrupt-controller; 272 interrupt-controller;
272 #interrupt-cells = <3>; 273 #interrupt-cells = <3>;
@@ -282,11 +283,15 @@
282 uart1_pins_a: uart1@0 { 283 uart1_pins_a: uart1@0 {
283 allwinner,pins = "PG6", "PG7"; 284 allwinner,pins = "PG6", "PG7";
284 allwinner,function = "uart1"; 285 allwinner,function = "uart1";
286 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
287 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
285 }; 288 };
286 289
287 uart1_pins_cts_rts_a: uart1-cts-rts@0 { 290 uart1_pins_cts_rts_a: uart1-cts-rts@0 {
288 allwinner,pins = "PG8", "PG9"; 291 allwinner,pins = "PG8", "PG9";
289 allwinner,function = "uart1"; 292 allwinner,function = "uart1";
293 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
294 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
290 }; 295 };
291 296
292 mmc0_pins_a: mmc0@0 { 297 mmc0_pins_a: mmc0@0 {
@@ -571,7 +576,8 @@
571 compatible = "allwinner,sun8i-a23-r-pinctrl"; 576 compatible = "allwinner,sun8i-a23-r-pinctrl";
572 reg = <0x01f02c00 0x400>; 577 reg = <0x01f02c00 0x400>;
573 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 578 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
574 clocks = <&apb0_gates 0>; 579 clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
580 clock-names = "apb", "hosc", "losc";
575 resets = <&apb0_rst 0>; 581 resets = <&apb0_rst 0>;
576 gpio-controller; 582 gpio-controller;
577 interrupt-controller; 583 interrupt-controller;
diff --git a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts
index a86cbedda34c..21bb291b9568 100644
--- a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts
+++ b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts
@@ -98,13 +98,6 @@
98 }; 98 };
99}; 99};
100 100
101&reg_ldo_io1 {
102 regulator-min-microvolt = <3300000>;
103 regulator-max-microvolt = <3300000>;
104 regulator-name = "vcc-touchscreen";
105 status = "okay";
106};
107
108&touchscreen { 101&touchscreen {
109 reg = <0x40>; 102 reg = <0x40>;
110 compatible = "silead,gsl1680"; 103 compatible = "silead,gsl1680";
diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
index fef6abc0a703..71bb9418c5f9 100644
--- a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
+++ b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
@@ -213,6 +213,11 @@
213 status = "okay"; 213 status = "okay";
214}; 214};
215 215
216&usb_otg {
217 dr_mode = "peripheral";
218 status = "okay";
219};
220
216&usbphy { 221&usbphy {
217 status = "okay"; 222 status = "okay";
218 usb1_vbus-supply = <&reg_vcc5v0>; /* USB1 VBUS is always on */ 223 usb1_vbus-supply = <&reg_vcc5v0>; /* USB1 VBUS is always on */
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts
new file mode 100644
index 000000000000..ec63d104b404
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts
@@ -0,0 +1,64 @@
1/*
2 * Copyright (C) 2016 Milo Kim <woogyom.kim@gmail.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include "sun8i-h3-nanopi.dtsi"
44
45/ {
46 model = "FriendlyArm NanoPi M1";
47 compatible = "friendlyarm,nanopi-m1", "allwinner,sun8i-h3";
48};
49
50&ehci1 {
51 status = "okay";
52};
53
54&ehci2 {
55 status = "okay";
56};
57
58&ohci1 {
59 status = "okay";
60};
61
62&ohci2 {
63 status = "okay";
64};
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
index 3d64cafc1e90..8d2cc6e9a03f 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
@@ -40,86 +40,9 @@
40 * OTHER DEALINGS IN THE SOFTWARE. 40 * OTHER DEALINGS IN THE SOFTWARE.
41 */ 41 */
42 42
43/dts-v1/; 43#include "sun8i-h3-nanopi.dtsi"
44#include "sun8i-h3.dtsi"
45#include "sunxi-common-regulators.dtsi"
46
47#include <dt-bindings/gpio/gpio.h>
48#include <dt-bindings/pinctrl/sun4i-a10.h>
49 44
50/ { 45/ {
51 model = "FriendlyARM NanoPi NEO"; 46 model = "FriendlyARM NanoPi NEO";
52 compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3"; 47 compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3";
53
54 aliases {
55 serial0 = &uart0;
56 };
57
58 chosen {
59 stdout-path = "serial0:115200n8";
60 };
61
62 leds {
63 compatible = "gpio-leds";
64 pinctrl-names = "default";
65 pinctrl-0 = <&leds_opc>, <&leds_r_opc>;
66
67 pwr {
68 label = "nanopi:green:pwr";
69 gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
70 default-state = "on";
71 };
72
73 status {
74 label = "nanopi:blue:status";
75 gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */
76 };
77 };
78};
79
80&ehci3 {
81 status = "okay";
82};
83
84&mmc0 {
85 pinctrl-names = "default";
86 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
87 vmmc-supply = <&reg_vcc3v3>;
88 bus-width = <4>;
89 cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
90 cd-inverted;
91 status = "okay";
92};
93
94&ohci3 {
95 status = "okay";
96};
97
98&pio {
99 leds_opc: led-pins {
100 allwinner,pins = "PA10";
101 allwinner,function = "gpio_out";
102 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
103 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
104 };
105};
106
107&r_pio {
108 leds_r_opc: led-pins {
109 allwinner,pins = "PL10";
110 allwinner,function = "gpio_out";
111 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
112 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
113 };
114};
115
116&uart0 {
117 pinctrl-names = "default";
118 pinctrl-0 = <&uart0_pins_a>;
119 status = "okay";
120};
121
122&usbphy {
123 /* USB VBUS is always on */
124 status = "okay";
125}; 48};
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi
new file mode 100644
index 000000000000..8038aa29a5a7
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi
@@ -0,0 +1,144 @@
1/*
2 * Copyright (C) 2016 James Pettigrew <james@innovum.com.au>
3 * Copyright (C) 2016 Milo Kim <woogyom.kim@gmail.com>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44/dts-v1/;
45#include "sun8i-h3.dtsi"
46#include "sunxi-common-regulators.dtsi"
47
48#include <dt-bindings/gpio/gpio.h>
49#include <dt-bindings/input/input.h>
50#include <dt-bindings/pinctrl/sun4i-a10.h>
51
52/ {
53 aliases {
54 serial0 = &uart0;
55 };
56
57 chosen {
58 stdout-path = "serial0:115200n8";
59 };
60
61 leds {
62 compatible = "gpio-leds";
63 pinctrl-names = "default";
64 pinctrl-0 = <&leds_npi>, <&leds_r_npi>;
65
66 status {
67 label = "nanopi:blue:status";
68 gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;
69 linux,default-trigger = "heartbeat";
70 };
71
72 pwr {
73 label = "nanopi:green:pwr";
74 gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
75 default-state = "on";
76 };
77 };
78
79 r_gpio_keys {
80 compatible = "gpio-keys";
81 input-name = "k1";
82 pinctrl-names = "default";
83 pinctrl-0 = <&sw_r_npi>;
84
85 k1@0 {
86 label = "k1";
87 linux,code = <KEY_POWER>;
88 gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
89 };
90 };
91};
92
93&ehci3 {
94 status = "okay";
95};
96
97&mmc0 {
98 bus-width = <4>;
99 cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
100 cd-inverted;
101 pinctrl-names = "default";
102 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
103 status = "okay";
104 vmmc-supply = <&reg_vcc3v3>;
105};
106
107&ohci3 {
108 status = "okay";
109};
110
111&pio {
112 leds_npi: led_pins@0 {
113 allwinner,pins = "PA10";
114 allwinner,function = "gpio_out";
115 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
116 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
117 };
118};
119
120&r_pio {
121 leds_r_npi: led_pins@0 {
122 allwinner,pins = "PL10";
123 allwinner,function = "gpio_out";
124 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
125 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
126 };
127
128 sw_r_npi: key_pins@0 {
129 allwinner,pins = "PL3";
130 allwinner,function = "gpio_in";
131 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
132 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
133 };
134};
135
136&uart0 {
137 pinctrl-names = "default";
138 pinctrl-0 = <&uart0_pins_a>;
139 status = "okay";
140};
141
142&usbphy {
143 status = "okay";
144};
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 75a865406d3e..3c6596f06ebc 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -321,7 +321,8 @@
321 reg = <0x01c20800 0x400>; 321 reg = <0x01c20800 0x400>;
322 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 322 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 323 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&ccu CLK_BUS_PIO>; 324 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
325 clock-names = "apb", "hosc", "losc";
325 gpio-controller; 326 gpio-controller;
326 #gpio-cells = <3>; 327 #gpio-cells = <3>;
327 interrupt-controller; 328 interrupt-controller;
@@ -381,6 +382,20 @@
381 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 382 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
382 }; 383 };
383 384
385 spi0_pins: spi0 {
386 allwinner,pins = "PC0", "PC1", "PC2", "PC3";
387 allwinner,function = "spi0";
388 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
389 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
390 };
391
392 spi1_pins: spi1 {
393 allwinner,pins = "PA15", "PA16", "PA14", "PA13";
394 allwinner,function = "spi1";
395 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
396 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
397 };
398
384 uart0_pins_a: uart0@0 { 399 uart0_pins_a: uart0@0 {
385 allwinner,pins = "PA4", "PA5"; 400 allwinner,pins = "PA4", "PA5";
386 allwinner,function = "uart0"; 401 allwinner,function = "uart0";
@@ -425,6 +440,38 @@
425 clocks = <&osc24M>; 440 clocks = <&osc24M>;
426 }; 441 };
427 442
443 spi0: spi@01c68000 {
444 compatible = "allwinner,sun8i-h3-spi";
445 reg = <0x01c68000 0x1000>;
446 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
447 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
448 clock-names = "ahb", "mod";
449 dmas = <&dma 23>, <&dma 23>;
450 dma-names = "rx", "tx";
451 pinctrl-names = "default";
452 pinctrl-0 = <&spi0_pins>;
453 resets = <&ccu RST_BUS_SPI0>;
454 status = "disabled";
455 #address-cells = <1>;
456 #size-cells = <0>;
457 };
458
459 spi1: spi@01c69000 {
460 compatible = "allwinner,sun8i-h3-spi";
461 reg = <0x01c69000 0x1000>;
462 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
463 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
464 clock-names = "ahb", "mod";
465 dmas = <&dma 24>, <&dma 24>;
466 dma-names = "rx", "tx";
467 pinctrl-names = "default";
468 pinctrl-0 = <&spi1_pins>;
469 resets = <&ccu RST_BUS_SPI1>;
470 status = "disabled";
471 #address-cells = <1>;
472 #size-cells = <0>;
473 };
474
428 wdt0: watchdog@01c20ca0 { 475 wdt0: watchdog@01c20ca0 {
429 compatible = "allwinner,sun6i-a31-wdt"; 476 compatible = "allwinner,sun6i-a31-wdt";
430 reg = <0x01c20ca0 0x20>; 477 reg = <0x01c20ca0 0x20>;
@@ -568,7 +615,8 @@
568 compatible = "allwinner,sun8i-h3-r-pinctrl"; 615 compatible = "allwinner,sun8i-h3-r-pinctrl";
569 reg = <0x01f02c00 0x400>; 616 reg = <0x01f02c00 0x400>;
570 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 617 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&apb0_gates 0>; 618 clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
619 clock-names = "apb", "hosc", "losc";
572 resets = <&apb0_reset 0>; 620 resets = <&apb0_reset 0>;
573 gpio-controller; 621 gpio-controller;
574 #gpio-cells = <3>; 622 #gpio-cells = <3>;
diff --git a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
index 08cd00143635..69bc0cd26ca7 100644
--- a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
+++ b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
@@ -209,6 +209,13 @@
209 status = "okay"; 209 status = "okay";
210}; 210};
211 211
212&reg_ldo_io1 {
213 regulator-min-microvolt = <3300000>;
214 regulator-max-microvolt = <3300000>;
215 regulator-name = "vcc-touchscreen";
216 status = "okay";
217};
218
212&reg_rtc_ldo { 219&reg_rtc_ldo {
213 regulator-name = "vcc-rtc"; 220 regulator-name = "vcc-rtc";
214}; 221};
diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
index 439847acd41e..67b02fe7f11c 100644
--- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
+++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
@@ -76,6 +76,14 @@
76 gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ 76 gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
77 }; 77 };
78 }; 78 };
79
80 wifi_pwrseq: wifi_pwrseq {
81 compatible = "mmc-pwrseq-simple";
82 clocks = <&ac100_rtc 1>;
83 clock-names = "ext_clock";
84 /* enables internal regulator and de-asserts reset */
85 reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
86 };
79}; 87};
80 88
81&mmc0 { 89&mmc0 {
@@ -88,6 +96,21 @@
88 status = "okay"; 96 status = "okay";
89}; 97};
90 98
99&mmc1 {
100 pinctrl-names = "default";
101 pinctrl-0 = <&mmc1_pins>, <&wifi_en_pin_cubieboard4>;
102 vmmc-supply = <&reg_dldo1>;
103 vqmmc-supply = <&reg_cldo3>;
104 mmc-pwrseq = <&wifi_pwrseq>;
105 bus-width = <4>;
106 non-removable;
107 status = "okay";
108};
109
110&mmc1_pins {
111 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
112};
113
91&mmc2 { 114&mmc2 {
92 pinctrl-names = "default"; 115 pinctrl-names = "default";
93 pinctrl-0 = <&mmc2_8bit_pins>; 116 pinctrl-0 = <&mmc2_8bit_pins>;
@@ -128,6 +151,15 @@
128 status = "okay"; 151 status = "okay";
129}; 152};
130 153
154&r_pio {
155 wifi_en_pin_cubieboard4: wifi_en_pin@0 {
156 allwinner,pins = "PL2";
157 allwinner,function = "gpio_out";
158 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
159 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
160 };
161};
162
131&r_rsb { 163&r_rsb {
132 status = "okay"; 164 status = "okay";
133 165
diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts
index ceb6ef15d669..7e036b2be762 100644
--- a/arch/arm/boot/dts/sun9i-a80-optimus.dts
+++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts
@@ -105,6 +105,14 @@
105 enable-active-high; 105 enable-active-high;
106 gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ 106 gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
107 }; 107 };
108
109 wifi_pwrseq: wifi_pwrseq {
110 compatible = "mmc-pwrseq-simple";
111 clocks = <&ac100_rtc 1>;
112 clock-names = "ext_clock";
113 /* enables internal regulator and de-asserts reset */
114 reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
115 };
108}; 116};
109 117
110&ehci0 { 118&ehci0 {
@@ -130,6 +138,21 @@
130 status = "okay"; 138 status = "okay";
131}; 139};
132 140
141&mmc1 {
142 pinctrl-names = "default";
143 pinctrl-0 = <&mmc1_pins>, <&wifi_en_pin_optimus>;
144 vmmc-supply = <&reg_dldo1>;
145 vqmmc-supply = <&reg_cldo3>;
146 mmc-pwrseq = <&wifi_pwrseq>;
147 bus-width = <4>;
148 non-removable;
149 status = "okay";
150};
151
152&mmc1_pins {
153 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
154};
155
133&mmc2 { 156&mmc2 {
134 pinctrl-names = "default"; 157 pinctrl-names = "default";
135 pinctrl-0 = <&mmc2_8bit_pins>; 158 pinctrl-0 = <&mmc2_8bit_pins>;
@@ -199,6 +222,13 @@
199 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 222 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
200 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 223 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
201 }; 224 };
225
226 wifi_en_pin_optimus: wifi_en_pin@0 {
227 allwinner,pins = "PL2";
228 allwinner,function = "gpio_out";
229 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
230 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
231 };
202}; 232};
203 233
204&r_rsb { 234&r_rsb {
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index 3c5214cbe4e6..979ad1aacfb1 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -678,7 +678,8 @@
678 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 678 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
679 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 679 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
680 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 680 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
681 clocks = <&apb0_gates 5>; 681 clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>;
682 clock-names = "apb", "hosc", "losc";
682 gpio-controller; 683 gpio-controller;
683 interrupt-controller; 684 interrupt-controller;
684 #interrupt-cells = <3>; 685 #interrupt-cells = <3>;
@@ -700,6 +701,14 @@
700 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 701 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
701 }; 702 };
702 703
704 mmc1_pins: mmc1 {
705 allwinner,pins = "PG0", "PG1" ,"PG2", "PG3",
706 "PG4", "PG5";
707 allwinner,function = "mmc1";
708 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
709 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
710 };
711
703 mmc2_8bit_pins: mmc2_8bit { 712 mmc2_8bit_pins: mmc2_8bit {
704 allwinner,pins = "PC6", "PC7", "PC8", "PC9", 713 allwinner,pins = "PC6", "PC7", "PC8", "PC9",
705 "PC10", "PC11", "PC12", 714 "PC10", "PC11", "PC12",
@@ -894,7 +903,8 @@
894 reg = <0x08002c00 0x400>; 903 reg = <0x08002c00 0x400>;
895 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 904 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
896 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 905 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
897 clocks = <&apbs_gates 0>; 906 clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>;
907 clock-names = "apb", "hosc", "losc";
898 resets = <&apbs_rst 0>; 908 resets = <&apbs_rst 0>;
899 gpio-controller; 909 gpio-controller;
900 interrupt-controller; 910 interrupt-controller;
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-14 18:31:37 -0400