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authorZhang, Jerry <Jerry.Zhang@amd.com>2017-04-18 21:53:29 -0400
committerAlex Deucher <alexander.deucher@amd.com>2017-04-28 17:32:47 -0400
commitd0766e981b36608f9fe9b29985d4cd696099c3f8 (patch)
treee14f2ab4d5dc2856096a384a470b7e4f088964fc
parentfc6aa33da4b1043ad1b337d051770993418256d2 (diff)
drm/amdgpu: PRT support for gfx9 (v3)
Fix PRT handling on gfx9 v2: unify PRT bit for all ASICs v3: move PRT flag checking in amdgpu_vm_bo_split_mapping() Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Acked-by: David Zhou <david1.zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h3
2 files changed, 8 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index f34d822f92ac..c42a9979d056 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1338,6 +1338,12 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
1338 flags &= ~AMDGPU_PTE_MTYPE_MASK; 1338 flags &= ~AMDGPU_PTE_MTYPE_MASK;
1339 flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK); 1339 flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK);
1340 1340
1341 if ((mapping->flags & AMDGPU_PTE_PRT) &&
1342 (adev->asic_type >= CHIP_VEGA10)) {
1343 flags |= AMDGPU_PTE_PRT;
1344 flags &= ~AMDGPU_PTE_VALID;
1345 }
1346
1341 trace_amdgpu_vm_bo_update(mapping); 1347 trace_amdgpu_vm_bo_update(mapping);
1342 1348
1343 pfn = mapping->offset >> PAGE_SHIFT; 1349 pfn = mapping->offset >> PAGE_SHIFT;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 661a8f6826ef..d97e28b4bdc4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -65,7 +65,8 @@ struct amdgpu_bo_list_entry;
65 65
66#define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7) 66#define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7)
67 67
68#define AMDGPU_PTE_PRT (1ULL << 63) 68/* TILED for VEGA10, reserved for older ASICs */
69#define AMDGPU_PTE_PRT (1ULL << 51)
69 70
70/* VEGA10 only */ 71/* VEGA10 only */
71#define AMDGPU_PTE_MTYPE(a) ((uint64_t)a << 57) 72#define AMDGPU_PTE_MTYPE(a) ((uint64_t)a << 57)