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authorRoy Spliet <r.spliet@ultimaker.com>2015-06-26 05:00:11 -0400
committerBrian Norris <computersforpeace@gmail.com>2015-07-20 13:45:53 -0400
commitd052e508a4069f0711ea68156f4b1565bf14c41c (patch)
treeac298d86ef0e68d48ddff22982c8835b0327560b
parent9c618292dba6aa9b82e8a2e4e6fe70f54bd87a81 (diff)
mtd: nand: sunxi: Set serial access mode correctly
Replaces the hard coded "always use EDO" policy with that prescribed by the ONFI 3.1 specification that EDO mode should always be used if tRC is below 30ns. Signed-off-by: Roy Spliet <r.spliet@ultimaker.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
-rw-r--r--drivers/mtd/nand/sunxi_nand.c17
1 files changed, 12 insertions, 5 deletions
diff --git a/drivers/mtd/nand/sunxi_nand.c b/drivers/mtd/nand/sunxi_nand.c
index 663e3314bb83..f97a58d6aae1 100644
--- a/drivers/mtd/nand/sunxi_nand.c
+++ b/drivers/mtd/nand/sunxi_nand.c
@@ -99,6 +99,9 @@
99 NFC_CMD_INT_ENABLE | \ 99 NFC_CMD_INT_ENABLE | \
100 NFC_DMA_INT_ENABLE) 100 NFC_DMA_INT_ENABLE)
101 101
102/* define bit use in NFC_TIMING_CTL */
103#define NFC_TIMING_CTL_EDO BIT(8)
104
102/* define NFC_TIMING_CFG register layout */ 105/* define NFC_TIMING_CFG register layout */
103#define NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD) \ 106#define NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD) \
104 (((tWB) & 0x3) | (((tADL) & 0x3) << 2) | \ 107 (((tWB) & 0x3) | (((tADL) & 0x3) << 2) | \
@@ -225,6 +228,7 @@ struct sunxi_nand_chip {
225 struct mtd_info mtd; 228 struct mtd_info mtd;
226 unsigned long clk_rate; 229 unsigned long clk_rate;
227 u32 timing_cfg; 230 u32 timing_cfg;
231 u32 timing_ctl;
228 int selected; 232 int selected;
229 int nsels; 233 int nsels;
230 struct sunxi_nand_chip_sel sels[0]; 234 struct sunxi_nand_chip_sel sels[0];
@@ -411,6 +415,7 @@ static void sunxi_nfc_select_chip(struct mtd_info *mtd, int chip)
411 } 415 }
412 } 416 }
413 417
418 writel(sunxi_nand->timing_ctl, nfc->regs + NFC_REG_TIMING_CTL);
414 writel(sunxi_nand->timing_cfg, nfc->regs + NFC_REG_TIMING_CFG); 419 writel(sunxi_nand->timing_cfg, nfc->regs + NFC_REG_TIMING_CFG);
415 writel(ctl, nfc->regs + NFC_REG_CTL); 420 writel(ctl, nfc->regs + NFC_REG_CTL);
416 421
@@ -940,6 +945,13 @@ static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip,
940 /* TODO: A83 has some more bits for CDQSS, CS, CLHZ, CCS, WC */ 945 /* TODO: A83 has some more bits for CDQSS, CS, CLHZ, CCS, WC */
941 chip->timing_cfg = NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD); 946 chip->timing_cfg = NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD);
942 947
948 /*
949 * ONFI specification 3.1, paragraph 4.15.2 dictates that EDO data
950 * output cycle timings shall be used if the host drives tRC less than
951 * 30 ns.
952 */
953 chip->timing_ctl = (timings->tRC_min < 30000) ? NFC_TIMING_CTL_EDO : 0;
954
943 /* Convert min_clk_period from picoseconds to nanoseconds */ 955 /* Convert min_clk_period from picoseconds to nanoseconds */
944 min_clk_period = DIV_ROUND_UP(min_clk_period, 1000); 956 min_clk_period = DIV_ROUND_UP(min_clk_period, 1000);
945 957
@@ -1441,11 +1453,6 @@ static int sunxi_nfc_probe(struct platform_device *pdev)
1441 1453
1442 platform_set_drvdata(pdev, nfc); 1454 platform_set_drvdata(pdev, nfc);
1443 1455
1444 /*
1445 * TODO: replace this magic value with EDO flag
1446 */
1447 writel(0x100, nfc->regs + NFC_REG_TIMING_CTL);
1448
1449 ret = sunxi_nand_chips_init(dev, nfc); 1456 ret = sunxi_nand_chips_init(dev, nfc);
1450 if (ret) { 1457 if (ret) {
1451 dev_err(dev, "failed to init nand chips\n"); 1458 dev_err(dev, "failed to init nand chips\n");