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authorOlof Johansson <olof@lixom.net>2016-11-18 12:42:08 -0500
committerOlof Johansson <olof@lixom.net>2016-11-18 12:42:08 -0500
commitd02262afe0d52548b84e1686fe850f5c680d1495 (patch)
treee228a5ac02b17ef10ac98e37f913e1c48f50f64f
parentfce566ff9706eeff7458002af2a34249bb76e568 (diff)
parentaec89f78cf01647d8f60713ac1a324ab1a7e2e31 (diff)
Merge branch 'clk-qcom-8994' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux into next/dt64
* 'clk-qcom-8994' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: qcom: Add support for msm8994 global clock controller dt-bindings: qcom: clocks: Add msm8994 clock bindings
Diffstat
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,gcc.txt1
-rw-r--r--drivers/clk/qcom/Kconfig8
-rw-r--r--drivers/clk/qcom/Makefile1
-rw-r--r--drivers/clk/qcom/gcc-msm8994.c2300
-rw-r--r--include/dt-bindings/clock/qcom,gcc-msm8994.h137
5 files changed, 2447 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index 3cf44217068e..5b4dfc1ea54f 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -14,6 +14,7 @@ Required properties :
14 "qcom,gcc-msm8974" 14 "qcom,gcc-msm8974"
15 "qcom,gcc-msm8974pro" 15 "qcom,gcc-msm8974pro"
16 "qcom,gcc-msm8974pro-ac" 16 "qcom,gcc-msm8974pro-ac"
17 "qcom,gcc-msm8994"
17 "qcom,gcc-msm8996" 18 "qcom,gcc-msm8996"
18 "qcom,gcc-mdm9615" 19 "qcom,gcc-mdm9615"
19 20
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 0146d3c2547f..a8d3dc22740b 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -132,6 +132,14 @@ config MSM_MMCC_8974
132 Say Y if you want to support multimedia devices such as display, 132 Say Y if you want to support multimedia devices such as display,
133 graphics, video encode/decode, camera, etc. 133 graphics, video encode/decode, camera, etc.
134 134
135config MSM_GCC_8994
136 tristate "MSM8994 Global Clock Controller"
137 depends on COMMON_CLK_QCOM
138 help
139 Support for the global clock controller on msm8994 devices.
140 Say Y if you want to use peripheral devices such as UART, SPI,
141 i2c, USB, UFS, SD/eMMC, PCIe, etc.
142
135config MSM_GCC_8996 143config MSM_GCC_8996
136 tristate "MSM8996 Global Clock Controller" 144 tristate "MSM8996 Global Clock Controller"
137 select QCOM_GDSC 145 select QCOM_GDSC
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 1fb1f5476cb0..9f14927431ad 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o
24obj-$(CONFIG_MSM_GCC_8916) += gcc-msm8916.o 24obj-$(CONFIG_MSM_GCC_8916) += gcc-msm8916.o
25obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o 25obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o
26obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o 26obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o
27obj-$(CONFIG_MSM_GCC_8994) += gcc-msm8994.o
27obj-$(CONFIG_MSM_GCC_8996) += gcc-msm8996.o 28obj-$(CONFIG_MSM_GCC_8996) += gcc-msm8996.o
28obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o 29obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o
29obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o 30obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c
new file mode 100644
index 000000000000..84093c19caa6
--- /dev/null
+++ b/drivers/clk/qcom/gcc-msm8994.c
@@ -0,0 +1,2300 @@
1/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/err.h>
16#include <linux/ctype.h>
17#include <linux/io.h>
18#include <linux/of.h>
19#include <linux/platform_device.h>
20#include <linux/module.h>
21#include <linux/regmap.h>
22
23#include <dt-bindings/clock/qcom,gcc-msm8994.h>
24
25#include "common.h"
26#include "clk-regmap.h"
27#include "clk-alpha-pll.h"
28#include "clk-rcg.h"
29#include "clk-branch.h"
30#include "reset.h"
31
32enum {
33 P_XO,
34 P_GPLL0,
35 P_GPLL4,
36};
37
38static const struct parent_map gcc_xo_gpll0_map[] = {
39 { P_XO, 0 },
40 { P_GPLL0, 1 },
41};
42
43static const char * const gcc_xo_gpll0[] = {
44 "xo",
45 "gpll0",
46};
47
48static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
49 { P_XO, 0 },
50 { P_GPLL0, 1 },
51 { P_GPLL4, 5 },
52};
53
54static const char * const gcc_xo_gpll0_gpll4[] = {
55 "xo",
56 "gpll0",
57 "gpll4",
58};
59
60#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
61
62static struct clk_fixed_factor xo = {
63 .mult = 1,
64 .div = 1,
65 .hw.init = &(struct clk_init_data)
66 {
67 .name = "xo",
68 .parent_names = (const char *[]) { "xo_board" },
69 .num_parents = 1,
70 .ops = &clk_fixed_factor_ops,
71 },
72};
73
74static struct clk_alpha_pll gpll0_early = {
75 .offset = 0x00000,
76 .clkr = {
77 .enable_reg = 0x1480,
78 .enable_mask = BIT(0),
79 .hw.init = &(struct clk_init_data)
80 {
81 .name = "gpll0_early",
82 .parent_names = (const char *[]) { "xo" },
83 .num_parents = 1,
84 .ops = &clk_alpha_pll_ops,
85 },
86 },
87};
88
89static struct clk_alpha_pll_postdiv gpll0 = {
90 .offset = 0x00000,
91 .clkr.hw.init = &(struct clk_init_data)
92 {
93 .name = "gpll0",
94 .parent_names = (const char *[]) { "gpll0_early" },
95 .num_parents = 1,
96 .ops = &clk_alpha_pll_postdiv_ops,
97 },
98};
99
100static struct clk_alpha_pll gpll4_early = {
101 .offset = 0x1dc0,
102 .clkr = {
103 .enable_reg = 0x1480,
104 .enable_mask = BIT(4),
105 .hw.init = &(struct clk_init_data)
106 {
107 .name = "gpll4_early",
108 .parent_names = (const char *[]) { "xo" },
109 .num_parents = 1,
110 .ops = &clk_alpha_pll_ops,
111 },
112 },
113};
114
115static struct clk_alpha_pll_postdiv gpll4 = {
116 .offset = 0x1dc0,
117 .clkr.hw.init = &(struct clk_init_data)
118 {
119 .name = "gpll4",
120 .parent_names = (const char *[]) { "gpll4_early" },
121 .num_parents = 1,
122 .ops = &clk_alpha_pll_postdiv_ops,
123 },
124};
125
126static struct freq_tbl ftbl_ufs_axi_clk_src[] = {
127 F(50000000, P_GPLL0, 12, 0, 0),
128 F(100000000, P_GPLL0, 6, 0, 0),
129 F(150000000, P_GPLL0, 4, 0, 0),
130 F(171430000, P_GPLL0, 3.5, 0, 0),
131 F(200000000, P_GPLL0, 3, 0, 0),
132 F(240000000, P_GPLL0, 2.5, 0, 0),
133 { }
134};
135
136static struct clk_rcg2 ufs_axi_clk_src = {
137 .cmd_rcgr = 0x1d68,
138 .mnd_width = 8,
139 .hid_width = 5,
140 .parent_map = gcc_xo_gpll0_map,
141 .freq_tbl = ftbl_ufs_axi_clk_src,
142 .clkr.hw.init = &(struct clk_init_data)
143 {
144 .name = "ufs_axi_clk_src",
145 .parent_names = gcc_xo_gpll0,
146 .num_parents = 2,
147 .ops = &clk_rcg2_ops,
148 },
149};
150
151static struct freq_tbl ftbl_usb30_master_clk_src[] = {
152 F(19200000, P_XO, 1, 0, 0),
153 F(125000000, P_GPLL0, 1, 5, 24),
154 { }
155};
156
157static struct clk_rcg2 usb30_master_clk_src = {
158 .cmd_rcgr = 0x03d4,
159 .mnd_width = 8,
160 .hid_width = 5,
161 .parent_map = gcc_xo_gpll0_map,
162 .freq_tbl = ftbl_usb30_master_clk_src,
163 .clkr.hw.init = &(struct clk_init_data)
164 {
165 .name = "usb30_master_clk_src",
166 .parent_names = gcc_xo_gpll0,
167 .num_parents = 2,
168 .ops = &clk_rcg2_ops,
169 },
170};
171
172static struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {
173 F(19200000, P_XO, 1, 0, 0),
174 F(50000000, P_GPLL0, 12, 0, 0),
175 { }
176};
177
178static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
179 .cmd_rcgr = 0x0660,
180 .hid_width = 5,
181 .parent_map = gcc_xo_gpll0_map,
182 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
183 .clkr.hw.init = &(struct clk_init_data)
184 {
185 .name = "blsp1_qup1_i2c_apps_clk_src",
186 .parent_names = gcc_xo_gpll0,
187 .num_parents = 2,
188 .ops = &clk_rcg2_ops,
189 },
190};
191
192static struct freq_tbl ftbl_blspqup_spi_apps_clk_src[] = {
193 F(960000, P_XO, 10, 1, 2),
194 F(4800000, P_XO, 4, 0, 0),
195 F(9600000, P_XO, 2, 0, 0),
196 F(15000000, P_GPLL0, 10, 1, 4),
197 F(19200000, P_XO, 1, 0, 0),
198 F(24000000, P_GPLL0, 12.5, 1, 2),
199 F(25000000, P_GPLL0, 12, 1, 2),
200 F(48000000, P_GPLL0, 12.5, 0, 0),
201 F(50000000, P_GPLL0, 12, 0, 0),
202 { }
203};
204
205static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
206 .cmd_rcgr = 0x064c,
207 .mnd_width = 8,
208 .hid_width = 5,
209 .parent_map = gcc_xo_gpll0_map,
210 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
211 .clkr.hw.init = &(struct clk_init_data)
212 {
213 .name = "blsp1_qup1_spi_apps_clk_src",
214 .parent_names = gcc_xo_gpll0,
215 .num_parents = 2,
216 .ops = &clk_rcg2_ops,
217 },
218};
219
220static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
221 .cmd_rcgr = 0x06e0,
222 .hid_width = 5,
223 .parent_map = gcc_xo_gpll0_map,
224 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
225 .clkr.hw.init = &(struct clk_init_data)
226 {
227 .name = "blsp1_qup2_i2c_apps_clk_src",
228 .parent_names = gcc_xo_gpll0,
229 .num_parents = 2,
230 .ops = &clk_rcg2_ops,
231 },
232};
233
234static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
235 .cmd_rcgr = 0x06cc,
236 .mnd_width = 8,
237 .hid_width = 5,
238 .parent_map = gcc_xo_gpll0_map,
239 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
240 .clkr.hw.init = &(struct clk_init_data)
241 {
242 .name = "blsp1_qup2_spi_apps_clk_src",
243 .parent_names = gcc_xo_gpll0,
244 .num_parents = 2,
245 .ops = &clk_rcg2_ops,
246 },
247};
248
249static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
250 .cmd_rcgr = 0x0760,
251 .hid_width = 5,
252 .parent_map = gcc_xo_gpll0_map,
253 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
254 .clkr.hw.init = &(struct clk_init_data)
255 {
256 .name = "blsp1_qup3_i2c_apps_clk_src",
257 .parent_names = gcc_xo_gpll0,
258 .num_parents = 2,
259 .ops = &clk_rcg2_ops,
260 },
261};
262
263static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
264 .cmd_rcgr = 0x074c,
265 .mnd_width = 8,
266 .hid_width = 5,
267 .parent_map = gcc_xo_gpll0_map,
268 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
269 .clkr.hw.init = &(struct clk_init_data)
270 {
271 .name = "blsp1_qup3_spi_apps_clk_src",
272 .parent_names = gcc_xo_gpll0,
273 .num_parents = 2,
274 .ops = &clk_rcg2_ops,
275 },
276};
277
278static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
279 .cmd_rcgr = 0x07e0,
280 .hid_width = 5,
281 .parent_map = gcc_xo_gpll0_map,
282 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
283 .clkr.hw.init = &(struct clk_init_data)
284 {
285 .name = "blsp1_qup4_i2c_apps_clk_src",
286 .parent_names = gcc_xo_gpll0,
287 .num_parents = 2,
288 .ops = &clk_rcg2_ops,
289 },
290};
291
292static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
293 .cmd_rcgr = 0x07cc,
294 .mnd_width = 8,
295 .hid_width = 5,
296 .parent_map = gcc_xo_gpll0_map,
297 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
298 .clkr.hw.init = &(struct clk_init_data)
299 {
300 .name = "blsp1_qup4_spi_apps_clk_src",
301 .parent_names = gcc_xo_gpll0,
302 .num_parents = 2,
303 .ops = &clk_rcg2_ops,
304 },
305};
306
307static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
308 .cmd_rcgr = 0x0860,
309 .hid_width = 5,
310 .parent_map = gcc_xo_gpll0_map,
311 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
312 .clkr.hw.init = &(struct clk_init_data)
313 {
314 .name = "blsp1_qup5_i2c_apps_clk_src",
315 .parent_names = gcc_xo_gpll0,
316 .num_parents = 2,
317 .ops = &clk_rcg2_ops,
318 },
319};
320
321static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
322 .cmd_rcgr = 0x084c,
323 .mnd_width = 8,
324 .hid_width = 5,
325 .parent_map = gcc_xo_gpll0_map,
326 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
327 .clkr.hw.init = &(struct clk_init_data)
328 {
329 .name = "blsp1_qup5_spi_apps_clk_src",
330 .parent_names = gcc_xo_gpll0,
331 .num_parents = 2,
332 .ops = &clk_rcg2_ops,
333 },
334};
335
336static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
337 .cmd_rcgr = 0x08e0,
338 .hid_width = 5,
339 .parent_map = gcc_xo_gpll0_map,
340 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
341 .clkr.hw.init = &(struct clk_init_data)
342 {
343 .name = "blsp1_qup6_i2c_apps_clk_src",
344 .parent_names = gcc_xo_gpll0,
345 .num_parents = 2,
346 .ops = &clk_rcg2_ops,
347 },
348};
349
350static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
351 .cmd_rcgr = 0x08cc,
352 .mnd_width = 8,
353 .hid_width = 5,
354 .parent_map = gcc_xo_gpll0_map,
355 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
356 .clkr.hw.init = &(struct clk_init_data)
357 {
358 .name = "blsp1_qup6_spi_apps_clk_src",
359 .parent_names = gcc_xo_gpll0,
360 .num_parents = 2,
361 .ops = &clk_rcg2_ops,
362 },
363};
364
365static struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
366 F(3686400, P_GPLL0, 1, 96, 15625),
367 F(7372800, P_GPLL0, 1, 192, 15625),
368 F(14745600, P_GPLL0, 1, 384, 15625),
369 F(16000000, P_GPLL0, 5, 2, 15),
370 F(19200000, P_XO, 1, 0, 0),
371 F(24000000, P_GPLL0, 5, 1, 5),
372 F(32000000, P_GPLL0, 1, 4, 75),
373 F(40000000, P_GPLL0, 15, 0, 0),
374 F(46400000, P_GPLL0, 1, 29, 375),
375 F(48000000, P_GPLL0, 12.5, 0, 0),
376 F(51200000, P_GPLL0, 1, 32, 375),
377 F(56000000, P_GPLL0, 1, 7, 75),
378 F(58982400, P_GPLL0, 1, 1536, 15625),
379 F(60000000, P_GPLL0, 10, 0, 0),
380 F(63160000, P_GPLL0, 9.5, 0, 0),
381 { }
382};
383
384static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
385 .cmd_rcgr = 0x068c,
386 .mnd_width = 16,
387 .hid_width = 5,
388 .parent_map = gcc_xo_gpll0_map,
389 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
390 .clkr.hw.init = &(struct clk_init_data)
391 {
392 .name = "blsp1_uart1_apps_clk_src",
393 .parent_names = gcc_xo_gpll0,
394 .num_parents = 2,
395 .ops = &clk_rcg2_ops,
396 },
397};
398
399static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
400 .cmd_rcgr = 0x070c,
401 .mnd_width = 16,
402 .hid_width = 5,
403 .parent_map = gcc_xo_gpll0_map,
404 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
405 .clkr.hw.init = &(struct clk_init_data)
406 {
407 .name = "blsp1_uart2_apps_clk_src",
408 .parent_names = gcc_xo_gpll0,
409 .num_parents = 2,
410 .ops = &clk_rcg2_ops,
411 },
412};
413
414static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
415 .cmd_rcgr = 0x078c,
416 .mnd_width = 16,
417 .hid_width = 5,
418 .parent_map = gcc_xo_gpll0_map,
419 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
420 .clkr.hw.init = &(struct clk_init_data)
421 {
422 .name = "blsp1_uart3_apps_clk_src",
423 .parent_names = gcc_xo_gpll0,
424 .num_parents = 2,
425 .ops = &clk_rcg2_ops,
426 },
427};
428
429static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
430 .cmd_rcgr = 0x080c,
431 .mnd_width = 16,
432 .hid_width = 5,
433 .parent_map = gcc_xo_gpll0_map,
434 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
435 .clkr.hw.init = &(struct clk_init_data)
436 {
437 .name = "blsp1_uart4_apps_clk_src",
438 .parent_names = gcc_xo_gpll0,
439 .num_parents = 2,
440 .ops = &clk_rcg2_ops,
441 },
442};
443
444static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
445 .cmd_rcgr = 0x088c,
446 .mnd_width = 16,
447 .hid_width = 5,
448 .parent_map = gcc_xo_gpll0_map,
449 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
450 .clkr.hw.init = &(struct clk_init_data)
451 {
452 .name = "blsp1_uart5_apps_clk_src",
453 .parent_names = gcc_xo_gpll0,
454 .num_parents = 2,
455 .ops = &clk_rcg2_ops,
456 },
457};
458
459static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
460 .cmd_rcgr = 0x090c,
461 .mnd_width = 16,
462 .hid_width = 5,
463 .parent_map = gcc_xo_gpll0_map,
464 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
465 .clkr.hw.init = &(struct clk_init_data)
466 {
467 .name = "blsp1_uart6_apps_clk_src",
468 .parent_names = gcc_xo_gpll0,
469 .num_parents = 2,
470 .ops = &clk_rcg2_ops,
471 },
472};
473
474static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
475 .cmd_rcgr = 0x09a0,
476 .hid_width = 5,
477 .parent_map = gcc_xo_gpll0_map,
478 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
479 .clkr.hw.init = &(struct clk_init_data)
480 {
481 .name = "blsp2_qup1_i2c_apps_clk_src",
482 .parent_names = gcc_xo_gpll0,
483 .num_parents = 2,
484 .ops = &clk_rcg2_ops,
485 },
486};
487
488static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
489 .cmd_rcgr = 0x098c,
490 .mnd_width = 8,
491 .hid_width = 5,
492 .parent_map = gcc_xo_gpll0_map,
493 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
494 .clkr.hw.init = &(struct clk_init_data)
495 {
496 .name = "blsp2_qup1_spi_apps_clk_src",
497 .parent_names = gcc_xo_gpll0,
498 .num_parents = 2,
499 .ops = &clk_rcg2_ops,
500 },
501};
502
503static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
504 .cmd_rcgr = 0x0a20,
505 .hid_width = 5,
506 .parent_map = gcc_xo_gpll0_map,
507 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
508 .clkr.hw.init = &(struct clk_init_data)
509 {
510 .name = "blsp2_qup2_i2c_apps_clk_src",
511 .parent_names = gcc_xo_gpll0,
512 .num_parents = 2,
513 .ops = &clk_rcg2_ops,
514 },
515};
516
517static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
518 .cmd_rcgr = 0x0a0c,
519 .mnd_width = 8,
520 .hid_width = 5,
521 .parent_map = gcc_xo_gpll0_map,
522 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
523 .clkr.hw.init = &(struct clk_init_data)
524 {
525 .name = "blsp2_qup2_spi_apps_clk_src",
526 .parent_names = gcc_xo_gpll0,
527 .num_parents = 2,
528 .ops = &clk_rcg2_ops,
529 },
530};
531
532static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
533 .cmd_rcgr = 0x0aa0,
534 .hid_width = 5,
535 .parent_map = gcc_xo_gpll0_map,
536 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
537 .clkr.hw.init = &(struct clk_init_data)
538 {
539 .name = "blsp2_qup3_i2c_apps_clk_src",
540 .parent_names = gcc_xo_gpll0,
541 .num_parents = 2,
542 .ops = &clk_rcg2_ops,
543 },
544};
545
546static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
547 .cmd_rcgr = 0x0a8c,
548 .mnd_width = 8,
549 .hid_width = 5,
550 .parent_map = gcc_xo_gpll0_map,
551 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
552 .clkr.hw.init = &(struct clk_init_data)
553 {
554 .name = "blsp2_qup3_spi_apps_clk_src",
555 .parent_names = gcc_xo_gpll0,
556 .num_parents = 2,
557 .ops = &clk_rcg2_ops,
558 },
559};
560
561static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
562 .cmd_rcgr = 0x0b20,
563 .hid_width = 5,
564 .parent_map = gcc_xo_gpll0_map,
565 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
566 .clkr.hw.init = &(struct clk_init_data)
567 {
568 .name = "blsp2_qup4_i2c_apps_clk_src",
569 .parent_names = gcc_xo_gpll0,
570 .num_parents = 2,
571 .ops = &clk_rcg2_ops,
572 },
573};
574
575static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
576 .cmd_rcgr = 0x0b0c,
577 .mnd_width = 8,
578 .hid_width = 5,
579 .parent_map = gcc_xo_gpll0_map,
580 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
581 .clkr.hw.init = &(struct clk_init_data)
582 {
583 .name = "blsp2_qup4_spi_apps_clk_src",
584 .parent_names = gcc_xo_gpll0,
585 .num_parents = 2,
586 .ops = &clk_rcg2_ops,
587 },
588};
589
590static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
591 .cmd_rcgr = 0x0ba0,
592 .hid_width = 5,
593 .parent_map = gcc_xo_gpll0_map,
594 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
595 .clkr.hw.init = &(struct clk_init_data)
596 {
597 .name = "blsp2_qup5_i2c_apps_clk_src",
598 .parent_names = gcc_xo_gpll0,
599 .num_parents = 2,
600 .ops = &clk_rcg2_ops,
601 },
602};
603
604static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
605 .cmd_rcgr = 0x0b8c,
606 .mnd_width = 8,
607 .hid_width = 5,
608 .parent_map = gcc_xo_gpll0_map,
609 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
610 .clkr.hw.init = &(struct clk_init_data)
611 {
612 .name = "blsp2_qup5_spi_apps_clk_src",
613 .parent_names = gcc_xo_gpll0,
614 .num_parents = 2,
615 .ops = &clk_rcg2_ops,
616 },
617};
618
619static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
620 .cmd_rcgr = 0x0c20,
621 .hid_width = 5,
622 .parent_map = gcc_xo_gpll0_map,
623 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
624 .clkr.hw.init = &(struct clk_init_data)
625 {
626 .name = "blsp2_qup6_i2c_apps_clk_src",
627 .parent_names = gcc_xo_gpll0,
628 .num_parents = 2,
629 .ops = &clk_rcg2_ops,
630 },
631};
632
633static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
634 .cmd_rcgr = 0x0c0c,
635 .mnd_width = 8,
636 .hid_width = 5,
637 .parent_map = gcc_xo_gpll0_map,
638 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
639 .clkr.hw.init = &(struct clk_init_data)
640 {
641 .name = "blsp2_qup6_spi_apps_clk_src",
642 .parent_names = gcc_xo_gpll0,
643 .num_parents = 2,
644 .ops = &clk_rcg2_ops,
645 },
646};
647
648static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
649 .cmd_rcgr = 0x09cc,
650 .mnd_width = 16,
651 .hid_width = 5,
652 .parent_map = gcc_xo_gpll0_map,
653 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
654 .clkr.hw.init = &(struct clk_init_data)
655 {
656 .name = "blsp2_uart1_apps_clk_src",
657 .parent_names = gcc_xo_gpll0,
658 .num_parents = 2,
659 .ops = &clk_rcg2_ops,
660 },
661};
662
663static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
664 .cmd_rcgr = 0x0a4c,
665 .mnd_width = 16,
666 .hid_width = 5,
667 .parent_map = gcc_xo_gpll0_map,
668 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
669 .clkr.hw.init = &(struct clk_init_data)
670 {
671 .name = "blsp2_uart2_apps_clk_src",
672 .parent_names = gcc_xo_gpll0,
673 .num_parents = 2,
674 .ops = &clk_rcg2_ops,
675 },
676};
677
678static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
679 .cmd_rcgr = 0x0acc,
680 .mnd_width = 16,
681 .hid_width = 5,
682 .parent_map = gcc_xo_gpll0_map,
683 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
684 .clkr.hw.init = &(struct clk_init_data)
685 {
686 .name = "blsp2_uart3_apps_clk_src",
687 .parent_names = gcc_xo_gpll0,
688 .num_parents = 2,
689 .ops = &clk_rcg2_ops,
690 },
691};
692
693static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
694 .cmd_rcgr = 0x0b4c,
695 .mnd_width = 16,
696 .hid_width = 5,
697 .parent_map = gcc_xo_gpll0_map,
698 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
699 .clkr.hw.init = &(struct clk_init_data)
700 {
701 .name = "blsp2_uart4_apps_clk_src",
702 .parent_names = gcc_xo_gpll0,
703 .num_parents = 2,
704 .ops = &clk_rcg2_ops,
705 },
706};
707
708static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
709 .cmd_rcgr = 0x0bcc,
710 .mnd_width = 16,
711 .hid_width = 5,
712 .parent_map = gcc_xo_gpll0_map,
713 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
714 .clkr.hw.init = &(struct clk_init_data)
715 {
716 .name = "blsp2_uart5_apps_clk_src",
717 .parent_names = gcc_xo_gpll0,
718 .num_parents = 2,
719 .ops = &clk_rcg2_ops,
720 },
721};
722
723static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
724 .cmd_rcgr = 0x0c4c,
725 .mnd_width = 16,
726 .hid_width = 5,
727 .parent_map = gcc_xo_gpll0_map,
728 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
729 .clkr.hw.init = &(struct clk_init_data)
730 {
731 .name = "blsp2_uart6_apps_clk_src",
732 .parent_names = gcc_xo_gpll0,
733 .num_parents = 2,
734 .ops = &clk_rcg2_ops,
735 },
736};
737
738static struct freq_tbl ftbl_gp1_clk_src[] = {
739 F(19200000, P_XO, 1, 0, 0),
740 F(100000000, P_GPLL0, 6, 0, 0),
741 F(200000000, P_GPLL0, 3, 0, 0),
742 { }
743};
744
745static struct clk_rcg2 gp1_clk_src = {
746 .cmd_rcgr = 0x1904,
747 .mnd_width = 8,
748 .hid_width = 5,
749 .parent_map = gcc_xo_gpll0_map,
750 .freq_tbl = ftbl_gp1_clk_src,
751 .clkr.hw.init = &(struct clk_init_data)
752 {
753 .name = "gp1_clk_src",
754 .parent_names = gcc_xo_gpll0,
755 .num_parents = 2,
756 .ops = &clk_rcg2_ops,
757 },
758};
759
760static struct freq_tbl ftbl_gp2_clk_src[] = {
761 F(19200000, P_XO, 1, 0, 0),
762 F(100000000, P_GPLL0, 6, 0, 0),
763 F(200000000, P_GPLL0, 3, 0, 0),
764 { }
765};
766
767static struct clk_rcg2 gp2_clk_src = {
768 .cmd_rcgr = 0x1944,
769 .mnd_width = 8,
770 .hid_width = 5,
771 .parent_map = gcc_xo_gpll0_map,
772 .freq_tbl = ftbl_gp2_clk_src,
773 .clkr.hw.init = &(struct clk_init_data)
774 {
775 .name = "gp2_clk_src",
776 .parent_names = gcc_xo_gpll0,
777 .num_parents = 2,
778 .ops = &clk_rcg2_ops,
779 },
780};
781
782static struct freq_tbl ftbl_gp3_clk_src[] = {
783 F(19200000, P_XO, 1, 0, 0),
784 F(100000000, P_GPLL0, 6, 0, 0),
785 F(200000000, P_GPLL0, 3, 0, 0),
786 { }
787};
788
789static struct clk_rcg2 gp3_clk_src = {
790 .cmd_rcgr = 0x1984,
791 .mnd_width = 8,
792 .hid_width = 5,
793 .parent_map = gcc_xo_gpll0_map,
794 .freq_tbl = ftbl_gp3_clk_src,
795 .clkr.hw.init = &(struct clk_init_data)
796 {
797 .name = "gp3_clk_src",
798 .parent_names = gcc_xo_gpll0,
799 .num_parents = 2,
800 .ops = &clk_rcg2_ops,
801 },
802};
803
804static struct freq_tbl ftbl_pcie_0_aux_clk_src[] = {
805 F(1011000, P_XO, 1, 1, 19),
806 { }
807};
808
809static struct clk_rcg2 pcie_0_aux_clk_src = {
810 .cmd_rcgr = 0x1b00,
811 .mnd_width = 8,
812 .hid_width = 5,
813 .freq_tbl = ftbl_pcie_0_aux_clk_src,
814 .clkr.hw.init = &(struct clk_init_data)
815 {
816 .name = "pcie_0_aux_clk_src",
817 .parent_names = (const char *[]) { "xo" },
818 .num_parents = 1,
819 .ops = &clk_rcg2_ops,
820 },
821};
822
823static struct freq_tbl ftbl_pcie_pipe_clk_src[] = {
824 F(125000000, P_XO, 1, 0, 0),
825 { }
826};
827
828static struct clk_rcg2 pcie_0_pipe_clk_src = {
829 .cmd_rcgr = 0x1adc,
830 .hid_width = 5,
831 .freq_tbl = ftbl_pcie_pipe_clk_src,
832 .clkr.hw.init = &(struct clk_init_data)
833 {
834 .name = "pcie_0_pipe_clk_src",
835 .parent_names = (const char *[]) { "xo" },
836 .num_parents = 1,
837 .ops = &clk_rcg2_ops,
838 },
839};
840
841static struct freq_tbl ftbl_pcie_1_aux_clk_src[] = {
842 F(1011000, P_XO, 1, 1, 19),
843 { }
844};
845
846static struct clk_rcg2 pcie_1_aux_clk_src = {
847 .cmd_rcgr = 0x1b80,
848 .mnd_width = 8,
849 .hid_width = 5,
850 .freq_tbl = ftbl_pcie_1_aux_clk_src,
851 .clkr.hw.init = &(struct clk_init_data)
852 {
853 .name = "pcie_1_aux_clk_src",
854 .parent_names = (const char *[]) { "xo" },
855 .num_parents = 1,
856 .ops = &clk_rcg2_ops,
857 },
858};
859
860static struct clk_rcg2 pcie_1_pipe_clk_src = {
861 .cmd_rcgr = 0x1b5c,
862 .hid_width = 5,
863 .freq_tbl = ftbl_pcie_pipe_clk_src,
864 .clkr.hw.init = &(struct clk_init_data)
865 {
866 .name = "pcie_1_pipe_clk_src",
867 .parent_names = (const char *[]) { "xo" },
868 .num_parents = 1,
869 .ops = &clk_rcg2_ops,
870 },
871};
872
873static struct freq_tbl ftbl_pdm2_clk_src[] = {
874 F(60000000, P_GPLL0, 10, 0, 0),
875 { }
876};
877
878static struct clk_rcg2 pdm2_clk_src = {
879 .cmd_rcgr = 0x0cd0,
880 .hid_width = 5,
881 .parent_map = gcc_xo_gpll0_map,
882 .freq_tbl = ftbl_pdm2_clk_src,
883 .clkr.hw.init = &(struct clk_init_data)
884 {
885 .name = "pdm2_clk_src",
886 .parent_names = gcc_xo_gpll0,
887 .num_parents = 2,
888 .ops = &clk_rcg2_ops,
889 },
890};
891
892static struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
893 F(144000, P_XO, 16, 3, 25),
894 F(400000, P_XO, 12, 1, 4),
895 F(20000000, P_GPLL0, 15, 1, 2),
896 F(25000000, P_GPLL0, 12, 1, 2),
897 F(50000000, P_GPLL0, 12, 0, 0),
898 F(100000000, P_GPLL0, 6, 0, 0),
899 F(192000000, P_GPLL4, 2, 0, 0),
900 F(384000000, P_GPLL4, 1, 0, 0),
901 { }
902};
903
904static struct clk_rcg2 sdcc1_apps_clk_src = {
905 .cmd_rcgr = 0x04d0,
906 .mnd_width = 8,
907 .hid_width = 5,
908 .parent_map = gcc_xo_gpll0_gpll4_map,
909 .freq_tbl = ftbl_sdcc1_apps_clk_src,
910 .clkr.hw.init = &(struct clk_init_data)
911 {
912 .name = "sdcc1_apps_clk_src",
913 .parent_names = gcc_xo_gpll0_gpll4,
914 .num_parents = 3,
915 .ops = &clk_rcg2_ops,
916 },
917};
918
919static struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = {
920 F(144000, P_XO, 16, 3, 25),
921 F(400000, P_XO, 12, 1, 4),
922 F(20000000, P_GPLL0, 15, 1, 2),
923 F(25000000, P_GPLL0, 12, 1, 2),
924 F(50000000, P_GPLL0, 12, 0, 0),
925 F(100000000, P_GPLL0, 6, 0, 0),
926 F(200000000, P_GPLL0, 3, 0, 0),
927 { }
928};
929
930static struct clk_rcg2 sdcc2_apps_clk_src = {
931 .cmd_rcgr = 0x0510,
932 .mnd_width = 8,
933 .hid_width = 5,
934 .parent_map = gcc_xo_gpll0_map,
935 .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
936 .clkr.hw.init = &(struct clk_init_data)
937 {
938 .name = "sdcc2_apps_clk_src",
939 .parent_names = gcc_xo_gpll0,
940 .num_parents = 2,
941 .ops = &clk_rcg2_ops,
942 },
943};
944
945static struct clk_rcg2 sdcc3_apps_clk_src = {
946 .cmd_rcgr = 0x0550,
947 .mnd_width = 8,
948 .hid_width = 5,
949 .parent_map = gcc_xo_gpll0_map,
950 .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
951 .clkr.hw.init = &(struct clk_init_data)
952 {
953 .name = "sdcc3_apps_clk_src",
954 .parent_names = gcc_xo_gpll0,
955 .num_parents = 2,
956 .ops = &clk_rcg2_ops,
957 },
958};
959
960static struct clk_rcg2 sdcc4_apps_clk_src = {
961 .cmd_rcgr = 0x0590,
962 .mnd_width = 8,
963 .hid_width = 5,
964 .parent_map = gcc_xo_gpll0_map,
965 .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
966 .clkr.hw.init = &(struct clk_init_data)
967 {
968 .name = "sdcc4_apps_clk_src",
969 .parent_names = gcc_xo_gpll0,
970 .num_parents = 2,
971 .ops = &clk_rcg2_ops,
972 },
973};
974
975static struct freq_tbl ftbl_tsif_ref_clk_src[] = {
976 F(105500, P_XO, 1, 1, 182),
977 { }
978};
979
980static struct clk_rcg2 tsif_ref_clk_src = {
981 .cmd_rcgr = 0x0d90,
982 .mnd_width = 8,
983 .hid_width = 5,
984 .freq_tbl = ftbl_tsif_ref_clk_src,
985 .clkr.hw.init = &(struct clk_init_data)
986 {
987 .name = "tsif_ref_clk_src",
988 .parent_names = (const char *[]) { "xo" },
989 .num_parents = 1,
990 .ops = &clk_rcg2_ops,
991 },
992};
993
994static struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
995 F(19200000, P_XO, 1, 0, 0),
996 F(60000000, P_GPLL0, 10, 0, 0),
997 { }
998};
999
1000static struct clk_rcg2 usb30_mock_utmi_clk_src = {
1001 .cmd_rcgr = 0x03e8,
1002 .hid_width = 5,
1003 .parent_map = gcc_xo_gpll0_map,
1004 .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
1005 .clkr.hw.init = &(struct clk_init_data)
1006 {
1007 .name = "usb30_mock_utmi_clk_src",
1008 .parent_names = gcc_xo_gpll0,
1009 .num_parents = 2,
1010 .ops = &clk_rcg2_ops,
1011 },
1012};
1013
1014static struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
1015 F(1200000, P_XO, 16, 0, 0),
1016 { }
1017};
1018
1019static struct clk_rcg2 usb3_phy_aux_clk_src = {
1020 .cmd_rcgr = 0x1414,
1021 .hid_width = 5,
1022 .freq_tbl = ftbl_usb3_phy_aux_clk_src,
1023 .clkr.hw.init = &(struct clk_init_data)
1024 {
1025 .name = "usb3_phy_aux_clk_src",
1026 .parent_names = (const char *[]) { "xo" },
1027 .num_parents = 1,
1028 .ops = &clk_rcg2_ops,
1029 },
1030};
1031
1032static struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
1033 F(75000000, P_GPLL0, 8, 0, 0),
1034 { }
1035};
1036
1037static struct clk_rcg2 usb_hs_system_clk_src = {
1038 .cmd_rcgr = 0x0490,
1039 .hid_width = 5,
1040 .parent_map = gcc_xo_gpll0_map,
1041 .freq_tbl = ftbl_usb_hs_system_clk_src,
1042 .clkr.hw.init = &(struct clk_init_data)
1043 {
1044 .name = "usb_hs_system_clk_src",
1045 .parent_names = gcc_xo_gpll0,
1046 .num_parents = 2,
1047 .ops = &clk_rcg2_ops,
1048 },
1049};
1050
1051static struct clk_branch gcc_blsp1_ahb_clk = {
1052 .halt_reg = 0x05c4,
1053 .halt_check = BRANCH_HALT_VOTED,
1054 .clkr = {
1055 .enable_reg = 0x1484,
1056 .enable_mask = BIT(17),
1057 .hw.init = &(struct clk_init_data)
1058 {
1059 .name = "gcc_blsp1_ahb_clk",
1060 .ops = &clk_branch2_ops,
1061 },
1062 },
1063};
1064
1065static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1066 .halt_reg = 0x0648,
1067 .clkr = {
1068 .enable_reg = 0x0648,
1069 .enable_mask = BIT(0),
1070 .hw.init = &(struct clk_init_data)
1071 {
1072 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1073 .parent_names = (const char *[]) {
1074 "blsp1_qup1_i2c_apps_clk_src",
1075 },
1076 .num_parents = 1,
1077 .flags = CLK_SET_RATE_PARENT,
1078 .ops = &clk_branch2_ops,
1079 },
1080 },
1081};
1082
1083static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1084 .halt_reg = 0x0644,
1085 .clkr = {
1086 .enable_reg = 0x0644,
1087 .enable_mask = BIT(0),
1088 .hw.init = &(struct clk_init_data)
1089 {
1090 .name = "gcc_blsp1_qup1_spi_apps_clk",
1091 .parent_names = (const char *[]) {
1092 "blsp1_qup1_spi_apps_clk_src",
1093 },
1094 .num_parents = 1,
1095 .flags = CLK_SET_RATE_PARENT,
1096 .ops = &clk_branch2_ops,
1097 },
1098 },
1099};
1100
1101static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1102 .halt_reg = 0x06c8,
1103 .clkr = {
1104 .enable_reg = 0x06c8,
1105 .enable_mask = BIT(0),
1106 .hw.init = &(struct clk_init_data)
1107 {
1108 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1109 .parent_names = (const char *[]) {
1110 "blsp1_qup2_i2c_apps_clk_src",
1111 },
1112 .num_parents = 1,
1113 .flags = CLK_SET_RATE_PARENT,
1114 .ops = &clk_branch2_ops,
1115 },
1116 },
1117};
1118
1119static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1120 .halt_reg = 0x06c4,
1121 .clkr = {
1122 .enable_reg = 0x06c4,
1123 .enable_mask = BIT(0),
1124 .hw.init = &(struct clk_init_data)
1125 {
1126 .name = "gcc_blsp1_qup2_spi_apps_clk",
1127 .parent_names = (const char *[]) {
1128 "blsp1_qup2_spi_apps_clk_src",
1129 },
1130 .num_parents = 1,
1131 .flags = CLK_SET_RATE_PARENT,
1132 .ops = &clk_branch2_ops,
1133 },
1134 },
1135};
1136
1137static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1138 .halt_reg = 0x0748,
1139 .clkr = {
1140 .enable_reg = 0x0748,
1141 .enable_mask = BIT(0),
1142 .hw.init = &(struct clk_init_data)
1143 {
1144 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1145 .parent_names = (const char *[]) {
1146 "blsp1_qup3_i2c_apps_clk_src",
1147 },
1148 .num_parents = 1,
1149 .flags = CLK_SET_RATE_PARENT,
1150 .ops = &clk_branch2_ops,
1151 },
1152 },
1153};
1154
1155static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1156 .halt_reg = 0x0744,
1157 .clkr = {
1158 .enable_reg = 0x0744,
1159 .enable_mask = BIT(0),
1160 .hw.init = &(struct clk_init_data)
1161 {
1162 .name = "gcc_blsp1_qup3_spi_apps_clk",
1163 .parent_names = (const char *[]) {
1164 "blsp1_qup3_spi_apps_clk_src",
1165 },
1166 .num_parents = 1,
1167 .flags = CLK_SET_RATE_PARENT,
1168 .ops = &clk_branch2_ops,
1169 },
1170 },
1171};
1172
1173static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1174 .halt_reg = 0x07c8,
1175 .clkr = {
1176 .enable_reg = 0x07c8,
1177 .enable_mask = BIT(0),
1178 .hw.init = &(struct clk_init_data)
1179 {
1180 .name = "gcc_blsp1_qup4_i2c_apps_clk",
1181 .parent_names = (const char *[]) {
1182 "blsp1_qup4_i2c_apps_clk_src",
1183 },
1184 .num_parents = 1,
1185 .flags = CLK_SET_RATE_PARENT,
1186 .ops = &clk_branch2_ops,
1187 },
1188 },
1189};
1190
1191static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1192 .halt_reg = 0x07c4,
1193 .clkr = {
1194 .enable_reg = 0x07c4,
1195 .enable_mask = BIT(0),
1196 .hw.init = &(struct clk_init_data)
1197 {
1198 .name = "gcc_blsp1_qup4_spi_apps_clk",
1199 .parent_names = (const char *[]) {
1200 "blsp1_qup4_spi_apps_clk_src",
1201 },
1202 .num_parents = 1,
1203 .flags = CLK_SET_RATE_PARENT,
1204 .ops = &clk_branch2_ops,
1205 },
1206 },
1207};
1208
1209static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1210 .halt_reg = 0x0848,
1211 .clkr = {
1212 .enable_reg = 0x0848,
1213 .enable_mask = BIT(0),
1214 .hw.init = &(struct clk_init_data)
1215 {
1216 .name = "gcc_blsp1_qup5_i2c_apps_clk",
1217 .parent_names = (const char *[]) {
1218 "blsp1_qup5_i2c_apps_clk_src",
1219 },
1220 .num_parents = 1,
1221 .flags = CLK_SET_RATE_PARENT,
1222 .ops = &clk_branch2_ops,
1223 },
1224 },
1225};
1226
1227static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1228 .halt_reg = 0x0844,
1229 .clkr = {
1230 .enable_reg = 0x0844,
1231 .enable_mask = BIT(0),
1232 .hw.init = &(struct clk_init_data)
1233 {
1234 .name = "gcc_blsp1_qup5_spi_apps_clk",
1235 .parent_names = (const char *[]) {
1236 "blsp1_qup5_spi_apps_clk_src",
1237 },
1238 .num_parents = 1,
1239 .flags = CLK_SET_RATE_PARENT,
1240 .ops = &clk_branch2_ops,
1241 },
1242 },
1243};
1244
1245static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1246 .halt_reg = 0x08c8,
1247 .clkr = {
1248 .enable_reg = 0x08c8,
1249 .enable_mask = BIT(0),
1250 .hw.init = &(struct clk_init_data)
1251 {
1252 .name = "gcc_blsp1_qup6_i2c_apps_clk",
1253 .parent_names = (const char *[]) {
1254 "blsp1_qup6_i2c_apps_clk_src",
1255 },
1256 .num_parents = 1,
1257 .flags = CLK_SET_RATE_PARENT,
1258 .ops = &clk_branch2_ops,
1259 },
1260 },
1261};
1262
1263static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1264 .halt_reg = 0x08c4,
1265 .clkr = {
1266 .enable_reg = 0x08c4,
1267 .enable_mask = BIT(0),
1268 .hw.init = &(struct clk_init_data)
1269 {
1270 .name = "gcc_blsp1_qup6_spi_apps_clk",
1271 .parent_names = (const char *[]) {
1272 "blsp1_qup6_spi_apps_clk_src",
1273 },
1274 .num_parents = 1,
1275 .flags = CLK_SET_RATE_PARENT,
1276 .ops = &clk_branch2_ops,
1277 },
1278 },
1279};
1280
1281static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1282 .halt_reg = 0x0684,
1283 .clkr = {
1284 .enable_reg = 0x0684,
1285 .enable_mask = BIT(0),
1286 .hw.init = &(struct clk_init_data)
1287 {
1288 .name = "gcc_blsp1_uart1_apps_clk",
1289 .parent_names = (const char *[]) {
1290 "blsp1_uart1_apps_clk_src",
1291 },
1292 .num_parents = 1,
1293 .flags = CLK_SET_RATE_PARENT,
1294 .ops = &clk_branch2_ops,
1295 },
1296 },
1297};
1298
1299static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1300 .halt_reg = 0x0704,
1301 .clkr = {
1302 .enable_reg = 0x0704,
1303 .enable_mask = BIT(0),
1304 .hw.init = &(struct clk_init_data)
1305 {
1306 .name = "gcc_blsp1_uart2_apps_clk",
1307 .parent_names = (const char *[]) {
1308 "blsp1_uart2_apps_clk_src",
1309 },
1310 .num_parents = 1,
1311 .flags = CLK_SET_RATE_PARENT,
1312 .ops = &clk_branch2_ops,
1313 },
1314 },
1315};
1316
1317static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1318 .halt_reg = 0x0784,
1319 .clkr = {
1320 .enable_reg = 0x0784,
1321 .enable_mask = BIT(0),
1322 .hw.init = &(struct clk_init_data)
1323 {
1324 .name = "gcc_blsp1_uart3_apps_clk",
1325 .parent_names = (const char *[]) {
1326 "blsp1_uart3_apps_clk_src",
1327 },
1328 .num_parents = 1,
1329 .flags = CLK_SET_RATE_PARENT,
1330 .ops = &clk_branch2_ops,
1331 },
1332 },
1333};
1334
1335static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1336 .halt_reg = 0x0804,
1337 .clkr = {
1338 .enable_reg = 0x0804,
1339 .enable_mask = BIT(0),
1340 .hw.init = &(struct clk_init_data)
1341 {
1342 .name = "gcc_blsp1_uart4_apps_clk",
1343 .parent_names = (const char *[]) {
1344 "blsp1_uart4_apps_clk_src",
1345 },
1346 .num_parents = 1,
1347 .flags = CLK_SET_RATE_PARENT,
1348 .ops = &clk_branch2_ops,
1349 },
1350 },
1351};
1352
1353static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1354 .halt_reg = 0x0884,
1355 .clkr = {
1356 .enable_reg = 0x0884,
1357 .enable_mask = BIT(0),
1358 .hw.init = &(struct clk_init_data)
1359 {
1360 .name = "gcc_blsp1_uart5_apps_clk",
1361 .parent_names = (const char *[]) {
1362 "blsp1_uart5_apps_clk_src",
1363 },
1364 .num_parents = 1,
1365 .flags = CLK_SET_RATE_PARENT,
1366 .ops = &clk_branch2_ops,
1367 },
1368 },
1369};
1370
1371static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1372 .halt_reg = 0x0904,
1373 .clkr = {
1374 .enable_reg = 0x0904,
1375 .enable_mask = BIT(0),
1376 .hw.init = &(struct clk_init_data)
1377 {
1378 .name = "gcc_blsp1_uart6_apps_clk",
1379 .parent_names = (const char *[]) {
1380 "blsp1_uart6_apps_clk_src",
1381 },
1382 .num_parents = 1,
1383 .flags = CLK_SET_RATE_PARENT,
1384 .ops = &clk_branch2_ops,
1385 },
1386 },
1387};
1388
1389static struct clk_branch gcc_blsp2_ahb_clk = {
1390 .halt_reg = 0x0944,
1391 .halt_check = BRANCH_HALT_VOTED,
1392 .clkr = {
1393 .enable_reg = 0x1484,
1394 .enable_mask = BIT(15),
1395 .hw.init = &(struct clk_init_data)
1396 {
1397 .name = "gcc_blsp2_ahb_clk",
1398 .ops = &clk_branch2_ops,
1399 },
1400 },
1401};
1402
1403static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1404 .halt_reg = 0x0988,
1405 .clkr = {
1406 .enable_reg = 0x0988,
1407 .enable_mask = BIT(0),
1408 .hw.init = &(struct clk_init_data)
1409 {
1410 .name = "gcc_blsp2_qup1_i2c_apps_clk",
1411 .parent_names = (const char *[]) {
1412 "blsp2_qup1_i2c_apps_clk_src",
1413 },
1414 .num_parents = 1,
1415 .flags = CLK_SET_RATE_PARENT,
1416 .ops = &clk_branch2_ops,
1417 },
1418 },
1419};
1420
1421static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1422 .halt_reg = 0x0984,
1423 .clkr = {
1424 .enable_reg = 0x0984,
1425 .enable_mask = BIT(0),
1426 .hw.init = &(struct clk_init_data)
1427 {
1428 .name = "gcc_blsp2_qup1_spi_apps_clk",
1429 .parent_names = (const char *[]) {
1430 "blsp2_qup1_spi_apps_clk_src",
1431 },
1432 .num_parents = 1,
1433 .flags = CLK_SET_RATE_PARENT,
1434 .ops = &clk_branch2_ops,
1435 },
1436 },
1437};
1438
1439static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1440 .halt_reg = 0x0a08,
1441 .clkr = {
1442 .enable_reg = 0x0a08,
1443 .enable_mask = BIT(0),
1444 .hw.init = &(struct clk_init_data)
1445 {
1446 .name = "gcc_blsp2_qup2_i2c_apps_clk",
1447 .parent_names = (const char *[]) {
1448 "blsp2_qup2_i2c_apps_clk_src",
1449 },
1450 .num_parents = 1,
1451 .flags = CLK_SET_RATE_PARENT,
1452 .ops = &clk_branch2_ops,
1453 },
1454 },
1455};
1456
1457static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1458 .halt_reg = 0x0a04,
1459 .clkr = {
1460 .enable_reg = 0x0a04,
1461 .enable_mask = BIT(0),
1462 .hw.init = &(struct clk_init_data)
1463 {
1464 .name = "gcc_blsp2_qup2_spi_apps_clk",
1465 .parent_names = (const char *[]) {
1466 "blsp2_qup2_spi_apps_clk_src",
1467 },
1468 .num_parents = 1,
1469 .flags = CLK_SET_RATE_PARENT,
1470 .ops = &clk_branch2_ops,
1471 },
1472 },
1473};
1474
1475static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1476 .halt_reg = 0x0a88,
1477 .clkr = {
1478 .enable_reg = 0x0a88,
1479 .enable_mask = BIT(0),
1480 .hw.init = &(struct clk_init_data)
1481 {
1482 .name = "gcc_blsp2_qup3_i2c_apps_clk",
1483 .parent_names = (const char *[]) {
1484 "blsp2_qup3_i2c_apps_clk_src",
1485 },
1486 .num_parents = 1,
1487 .flags = CLK_SET_RATE_PARENT,
1488 .ops = &clk_branch2_ops,
1489 },
1490 },
1491};
1492
1493static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1494 .halt_reg = 0x0a84,
1495 .clkr = {
1496 .enable_reg = 0x0a84,
1497 .enable_mask = BIT(0),
1498 .hw.init = &(struct clk_init_data)
1499 {
1500 .name = "gcc_blsp2_qup3_spi_apps_clk",
1501 .parent_names = (const char *[]) {
1502 "blsp2_qup3_spi_apps_clk_src",
1503 },
1504 .num_parents = 1,
1505 .flags = CLK_SET_RATE_PARENT,
1506 .ops = &clk_branch2_ops,
1507 },
1508 },
1509};
1510
1511static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1512 .halt_reg = 0x0b08,
1513 .clkr = {
1514 .enable_reg = 0x0b08,
1515 .enable_mask = BIT(0),
1516 .hw.init = &(struct clk_init_data)
1517 {
1518 .name = "gcc_blsp2_qup4_i2c_apps_clk",
1519 .parent_names = (const char *[]) {
1520 "blsp2_qup4_i2c_apps_clk_src",
1521 },
1522 .num_parents = 1,
1523 .flags = CLK_SET_RATE_PARENT,
1524 .ops = &clk_branch2_ops,
1525 },
1526 },
1527};
1528
1529static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1530 .halt_reg = 0x0b04,
1531 .clkr = {
1532 .enable_reg = 0x0b04,
1533 .enable_mask = BIT(0),
1534 .hw.init = &(struct clk_init_data)
1535 {
1536 .name = "gcc_blsp2_qup4_spi_apps_clk",
1537 .parent_names = (const char *[]) {
1538 "blsp2_qup4_spi_apps_clk_src",
1539 },
1540 .num_parents = 1,
1541 .flags = CLK_SET_RATE_PARENT,
1542 .ops = &clk_branch2_ops,
1543 },
1544 },
1545};
1546
1547static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
1548 .halt_reg = 0x0b88,
1549 .clkr = {
1550 .enable_reg = 0x0b88,
1551 .enable_mask = BIT(0),
1552 .hw.init = &(struct clk_init_data)
1553 {
1554 .name = "gcc_blsp2_qup5_i2c_apps_clk",
1555 .parent_names = (const char *[]) {
1556 "blsp2_qup5_i2c_apps_clk_src",
1557 },
1558 .num_parents = 1,
1559 .flags = CLK_SET_RATE_PARENT,
1560 .ops = &clk_branch2_ops,
1561 },
1562 },
1563};
1564
1565static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
1566 .halt_reg = 0x0b84,
1567 .clkr = {
1568 .enable_reg = 0x0b84,
1569 .enable_mask = BIT(0),
1570 .hw.init = &(struct clk_init_data)
1571 {
1572 .name = "gcc_blsp2_qup5_spi_apps_clk",
1573 .parent_names = (const char *[]) {
1574 "blsp2_qup5_spi_apps_clk_src",
1575 },
1576 .num_parents = 1,
1577 .flags = CLK_SET_RATE_PARENT,
1578 .ops = &clk_branch2_ops,
1579 },
1580 },
1581};
1582
1583static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
1584 .halt_reg = 0x0c08,
1585 .clkr = {
1586 .enable_reg = 0x0c08,
1587 .enable_mask = BIT(0),
1588 .hw.init = &(struct clk_init_data)
1589 {
1590 .name = "gcc_blsp2_qup6_i2c_apps_clk",
1591 .parent_names = (const char *[]) {
1592 "blsp2_qup6_i2c_apps_clk_src",
1593 },
1594 .num_parents = 1,
1595 .flags = CLK_SET_RATE_PARENT,
1596 .ops = &clk_branch2_ops,
1597 },
1598 },
1599};
1600
1601static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
1602 .halt_reg = 0x0c04,
1603 .clkr = {
1604 .enable_reg = 0x0c04,
1605 .enable_mask = BIT(0),
1606 .hw.init = &(struct clk_init_data)
1607 {
1608 .name = "gcc_blsp2_qup6_spi_apps_clk",
1609 .parent_names = (const char *[]) {
1610 "blsp2_qup6_spi_apps_clk_src",
1611 },
1612 .num_parents = 1,
1613 .flags = CLK_SET_RATE_PARENT,
1614 .ops = &clk_branch2_ops,
1615 },
1616 },
1617};
1618
1619static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1620 .halt_reg = 0x09c4,
1621 .clkr = {
1622 .enable_reg = 0x09c4,
1623 .enable_mask = BIT(0),
1624 .hw.init = &(struct clk_init_data)
1625 {
1626 .name = "gcc_blsp2_uart1_apps_clk",
1627 .parent_names = (const char *[]) {
1628 "blsp2_uart1_apps_clk_src",
1629 },
1630 .num_parents = 1,
1631 .flags = CLK_SET_RATE_PARENT,
1632 .ops = &clk_branch2_ops,
1633 },
1634 },
1635};
1636
1637static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1638 .halt_reg = 0x0a44,
1639 .clkr = {
1640 .enable_reg = 0x0a44,
1641 .enable_mask = BIT(0),
1642 .hw.init = &(struct clk_init_data)
1643 {
1644 .name = "gcc_blsp2_uart2_apps_clk",
1645 .parent_names = (const char *[]) {
1646 "blsp2_uart2_apps_clk_src",
1647 },
1648 .num_parents = 1,
1649 .flags = CLK_SET_RATE_PARENT,
1650 .ops = &clk_branch2_ops,
1651 },
1652 },
1653};
1654
1655static struct clk_branch gcc_blsp2_uart3_apps_clk = {
1656 .halt_reg = 0x0ac4,
1657 .clkr = {
1658 .enable_reg = 0x0ac4,
1659 .enable_mask = BIT(0),
1660 .hw.init = &(struct clk_init_data)
1661 {
1662 .name = "gcc_blsp2_uart3_apps_clk",
1663 .parent_names = (const char *[]) {
1664 "blsp2_uart3_apps_clk_src",
1665 },
1666 .num_parents = 1,
1667 .flags = CLK_SET_RATE_PARENT,
1668 .ops = &clk_branch2_ops,
1669 },
1670 },
1671};
1672
1673static struct clk_branch gcc_blsp2_uart4_apps_clk = {
1674 .halt_reg = 0x0b44,
1675 .clkr = {
1676 .enable_reg = 0x0b44,
1677 .enable_mask = BIT(0),
1678 .hw.init = &(struct clk_init_data)
1679 {
1680 .name = "gcc_blsp2_uart4_apps_clk",
1681 .parent_names = (const char *[]) {
1682 "blsp2_uart4_apps_clk_src",
1683 },
1684 .num_parents = 1,
1685 .flags = CLK_SET_RATE_PARENT,
1686 .ops = &clk_branch2_ops,
1687 },
1688 },
1689};
1690
1691static struct clk_branch gcc_blsp2_uart5_apps_clk = {
1692 .halt_reg = 0x0bc4,
1693 .clkr = {
1694 .enable_reg = 0x0bc4,
1695 .enable_mask = BIT(0),
1696 .hw.init = &(struct clk_init_data)
1697 {
1698 .name = "gcc_blsp2_uart5_apps_clk",
1699 .parent_names = (const char *[]) {
1700 "blsp2_uart5_apps_clk_src",
1701 },
1702 .num_parents = 1,
1703 .flags = CLK_SET_RATE_PARENT,
1704 .ops = &clk_branch2_ops,
1705 },
1706 },
1707};
1708
1709static struct clk_branch gcc_blsp2_uart6_apps_clk = {
1710 .halt_reg = 0x0c44,
1711 .clkr = {
1712 .enable_reg = 0x0c44,
1713 .enable_mask = BIT(0),
1714 .hw.init = &(struct clk_init_data)
1715 {
1716 .name = "gcc_blsp2_uart6_apps_clk",
1717 .parent_names = (const char *[]) {
1718 "blsp2_uart6_apps_clk_src",
1719 },
1720 .num_parents = 1,
1721 .flags = CLK_SET_RATE_PARENT,
1722 .ops = &clk_branch2_ops,
1723 },
1724 },
1725};
1726
1727static struct clk_branch gcc_gp1_clk = {
1728 .halt_reg = 0x1900,
1729 .clkr = {
1730 .enable_reg = 0x1900,
1731 .enable_mask = BIT(0),
1732 .hw.init = &(struct clk_init_data)
1733 {
1734 .name = "gcc_gp1_clk",
1735 .parent_names = (const char *[]) {
1736 "gp1_clk_src",
1737 },
1738 .num_parents = 1,
1739 .flags = CLK_SET_RATE_PARENT,
1740 .ops = &clk_branch2_ops,
1741 },
1742 },
1743};
1744
1745static struct clk_branch gcc_gp2_clk = {
1746 .halt_reg = 0x1940,
1747 .clkr = {
1748 .enable_reg = 0x1940,
1749 .enable_mask = BIT(0),
1750 .hw.init = &(struct clk_init_data)
1751 {
1752 .name = "gcc_gp2_clk",
1753 .parent_names = (const char *[]) {
1754 "gp2_clk_src",
1755 },
1756 .num_parents = 1,
1757 .flags = CLK_SET_RATE_PARENT,
1758 .ops = &clk_branch2_ops,
1759 },
1760 },
1761};
1762
1763static struct clk_branch gcc_gp3_clk = {
1764 .halt_reg = 0x1980,
1765 .clkr = {
1766 .enable_reg = 0x1980,
1767 .enable_mask = BIT(0),
1768 .hw.init = &(struct clk_init_data)
1769 {
1770 .name = "gcc_gp3_clk",
1771 .parent_names = (const char *[]) {
1772 "gp3_clk_src",
1773 },
1774 .num_parents = 1,
1775 .flags = CLK_SET_RATE_PARENT,
1776 .ops = &clk_branch2_ops,
1777 },
1778 },
1779};
1780
1781static struct clk_branch gcc_pcie_0_aux_clk = {
1782 .halt_reg = 0x1ad4,
1783 .clkr = {
1784 .enable_reg = 0x1ad4,
1785 .enable_mask = BIT(0),
1786 .hw.init = &(struct clk_init_data)
1787 {
1788 .name = "gcc_pcie_0_aux_clk",
1789 .parent_names = (const char *[]) {
1790 "pcie_0_aux_clk_src",
1791 },
1792 .num_parents = 1,
1793 .flags = CLK_SET_RATE_PARENT,
1794 .ops = &clk_branch2_ops,
1795 },
1796 },
1797};
1798
1799static struct clk_branch gcc_pcie_0_pipe_clk = {
1800 .halt_reg = 0x1ad8,
1801 .halt_check = BRANCH_HALT_DELAY,
1802 .clkr = {
1803 .enable_reg = 0x1ad8,
1804 .enable_mask = BIT(0),
1805 .hw.init = &(struct clk_init_data)
1806 {
1807 .name = "gcc_pcie_0_pipe_clk",
1808 .parent_names = (const char *[]) {
1809 "pcie_0_pipe_clk_src",
1810 },
1811 .num_parents = 1,
1812 .flags = CLK_SET_RATE_PARENT,
1813 .ops = &clk_branch2_ops,
1814 },
1815 },
1816};
1817
1818static struct clk_branch gcc_pcie_1_aux_clk = {
1819 .halt_reg = 0x1b54,
1820 .clkr = {
1821 .enable_reg = 0x1b54,
1822 .enable_mask = BIT(0),
1823 .hw.init = &(struct clk_init_data)
1824 {
1825 .name = "gcc_pcie_1_aux_clk",
1826 .parent_names = (const char *[]) {
1827 "pcie_1_aux_clk_src",
1828 },
1829 .num_parents = 1,
1830 .flags = CLK_SET_RATE_PARENT,
1831 .ops = &clk_branch2_ops,
1832 },
1833 },
1834};
1835
1836static struct clk_branch gcc_pcie_1_pipe_clk = {
1837 .halt_reg = 0x1b58,
1838 .halt_check = BRANCH_HALT_DELAY,
1839 .clkr = {
1840 .enable_reg = 0x1b58,
1841 .enable_mask = BIT(0),
1842 .hw.init = &(struct clk_init_data)
1843 {
1844 .name = "gcc_pcie_1_pipe_clk",
1845 .parent_names = (const char *[]) {
1846 "pcie_1_pipe_clk_src",
1847 },
1848 .num_parents = 1,
1849 .flags = CLK_SET_RATE_PARENT,
1850 .ops = &clk_branch2_ops,
1851 },
1852 },
1853};
1854
1855static struct clk_branch gcc_pdm2_clk = {
1856 .halt_reg = 0x0ccc,
1857 .clkr = {
1858 .enable_reg = 0x0ccc,
1859 .enable_mask = BIT(0),
1860 .hw.init = &(struct clk_init_data)
1861 {
1862 .name = "gcc_pdm2_clk",
1863 .parent_names = (const char *[]) {
1864 "pdm2_clk_src",
1865 },
1866 .num_parents = 1,
1867 .flags = CLK_SET_RATE_PARENT,
1868 .ops = &clk_branch2_ops,
1869 },
1870 },
1871};
1872
1873static struct clk_branch gcc_sdcc1_apps_clk = {
1874 .halt_reg = 0x04c4,
1875 .clkr = {
1876 .enable_reg = 0x04c4,
1877 .enable_mask = BIT(0),
1878 .hw.init = &(struct clk_init_data)
1879 {
1880 .name = "gcc_sdcc1_apps_clk",
1881 .parent_names = (const char *[]) {
1882 "sdcc1_apps_clk_src",
1883 },
1884 .num_parents = 1,
1885 .flags = CLK_SET_RATE_PARENT,
1886 .ops = &clk_branch2_ops,
1887 },
1888 },
1889};
1890
1891static struct clk_branch gcc_sdcc2_apps_clk = {
1892 .halt_reg = 0x0504,
1893 .clkr = {
1894 .enable_reg = 0x0504,
1895 .enable_mask = BIT(0),
1896 .hw.init = &(struct clk_init_data)
1897 {
1898 .name = "gcc_sdcc2_apps_clk",
1899 .parent_names = (const char *[]) {
1900 "sdcc2_apps_clk_src",
1901 },
1902 .num_parents = 1,
1903 .flags = CLK_SET_RATE_PARENT,
1904 .ops = &clk_branch2_ops,
1905 },
1906 },
1907};
1908
1909static struct clk_branch gcc_sdcc3_apps_clk = {
1910 .halt_reg = 0x0544,
1911 .clkr = {
1912 .enable_reg = 0x0544,
1913 .enable_mask = BIT(0),
1914 .hw.init = &(struct clk_init_data)
1915 {
1916 .name = "gcc_sdcc3_apps_clk",
1917 .parent_names = (const char *[]) {
1918 "sdcc3_apps_clk_src",
1919 },
1920 .num_parents = 1,
1921 .flags = CLK_SET_RATE_PARENT,
1922 .ops = &clk_branch2_ops,
1923 },
1924 },
1925};
1926
1927static struct clk_branch gcc_sdcc4_apps_clk = {
1928 .halt_reg = 0x0584,
1929 .clkr = {
1930 .enable_reg = 0x0584,
1931 .enable_mask = BIT(0),
1932 .hw.init = &(struct clk_init_data)
1933 {
1934 .name = "gcc_sdcc4_apps_clk",
1935 .parent_names = (const char *[]) {
1936 "sdcc4_apps_clk_src",
1937 },
1938 .num_parents = 1,
1939 .flags = CLK_SET_RATE_PARENT,
1940 .ops = &clk_branch2_ops,
1941 },
1942 },
1943};
1944
1945static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
1946 .halt_reg = 0x1d7c,
1947 .clkr = {
1948 .enable_reg = 0x1d7c,
1949 .enable_mask = BIT(0),
1950 .hw.init = &(struct clk_init_data)
1951 {
1952 .name = "gcc_sys_noc_ufs_axi_clk",
1953 .parent_names = (const char *[]) {
1954 "ufs_axi_clk_src",
1955 },
1956 .num_parents = 1,
1957 .flags = CLK_SET_RATE_PARENT,
1958 .ops = &clk_branch2_ops,
1959 },
1960 },
1961};
1962
1963static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
1964 .halt_reg = 0x03fc,
1965 .clkr = {
1966 .enable_reg = 0x03fc,
1967 .enable_mask = BIT(0),
1968 .hw.init = &(struct clk_init_data)
1969 {
1970 .name = "gcc_sys_noc_usb3_axi_clk",
1971 .parent_names = (const char *[]) {
1972 "usb30_master_clk_src",
1973 },
1974 .num_parents = 1,
1975 .flags = CLK_SET_RATE_PARENT,
1976 .ops = &clk_branch2_ops,
1977 },
1978 },
1979};
1980
1981static struct clk_branch gcc_tsif_ref_clk = {
1982 .halt_reg = 0x0d88,
1983 .clkr = {
1984 .enable_reg = 0x0d88,
1985 .enable_mask = BIT(0),
1986 .hw.init = &(struct clk_init_data)
1987 {
1988 .name = "gcc_tsif_ref_clk",
1989 .parent_names = (const char *[]) {
1990 "tsif_ref_clk_src",
1991 },
1992 .num_parents = 1,
1993 .flags = CLK_SET_RATE_PARENT,
1994 .ops = &clk_branch2_ops,
1995 },
1996 },
1997};
1998
1999static struct clk_branch gcc_ufs_axi_clk = {
2000 .halt_reg = 0x1d48,
2001 .clkr = {
2002 .enable_reg = 0x1d48,
2003 .enable_mask = BIT(0),
2004 .hw.init = &(struct clk_init_data)
2005 {
2006 .name = "gcc_ufs_axi_clk",
2007 .parent_names = (const char *[]) {
2008 "ufs_axi_clk_src",
2009 },
2010 .num_parents = 1,
2011 .flags = CLK_SET_RATE_PARENT,
2012 .ops = &clk_branch2_ops,
2013 },
2014 },
2015};
2016
2017static struct clk_branch gcc_ufs_rx_cfg_clk = {
2018 .halt_reg = 0x1d54,
2019 .clkr = {
2020 .enable_reg = 0x1d54,
2021 .enable_mask = BIT(0),
2022 .hw.init = &(struct clk_init_data)
2023 {
2024 .name = "gcc_ufs_rx_cfg_clk",
2025 .parent_names = (const char *[]) {
2026 "ufs_axi_clk_src",
2027 },
2028 .num_parents = 1,
2029 .flags = CLK_SET_RATE_PARENT,
2030 .ops = &clk_branch2_ops,
2031 },
2032 },
2033};
2034
2035static struct clk_branch gcc_ufs_tx_cfg_clk = {
2036 .halt_reg = 0x1d50,
2037 .clkr = {
2038 .enable_reg = 0x1d50,
2039 .enable_mask = BIT(0),
2040 .hw.init = &(struct clk_init_data)
2041 {
2042 .name = "gcc_ufs_tx_cfg_clk",
2043 .parent_names = (const char *[]) {
2044 "ufs_axi_clk_src",
2045 },
2046 .num_parents = 1,
2047 .flags = CLK_SET_RATE_PARENT,
2048 .ops = &clk_branch2_ops,
2049 },
2050 },
2051};
2052
2053static struct clk_branch gcc_usb30_master_clk = {
2054 .halt_reg = 0x03c8,
2055 .clkr = {
2056 .enable_reg = 0x03c8,
2057 .enable_mask = BIT(0),
2058 .hw.init = &(struct clk_init_data)
2059 {
2060 .name = "gcc_usb30_master_clk",
2061 .parent_names = (const char *[]) {
2062 "usb30_master_clk_src",
2063 },
2064 .num_parents = 1,
2065 .flags = CLK_SET_RATE_PARENT,
2066 .ops = &clk_branch2_ops,
2067 },
2068 },
2069};
2070
2071static struct clk_branch gcc_usb30_mock_utmi_clk = {
2072 .halt_reg = 0x03d0,
2073 .clkr = {
2074 .enable_reg = 0x03d0,
2075 .enable_mask = BIT(0),
2076 .hw.init = &(struct clk_init_data)
2077 {
2078 .name = "gcc_usb30_mock_utmi_clk",
2079 .parent_names = (const char *[]) {
2080 "usb30_mock_utmi_clk_src",
2081 },
2082 .num_parents = 1,
2083 .flags = CLK_SET_RATE_PARENT,
2084 .ops = &clk_branch2_ops,
2085 },
2086 },
2087};
2088
2089static struct clk_branch gcc_usb3_phy_aux_clk = {
2090 .halt_reg = 0x1408,
2091 .clkr = {
2092 .enable_reg = 0x1408,
2093 .enable_mask = BIT(0),
2094 .hw.init = &(struct clk_init_data)
2095 {
2096 .name = "gcc_usb3_phy_aux_clk",
2097 .parent_names = (const char *[]) {
2098 "usb3_phy_aux_clk_src",
2099 },
2100 .num_parents = 1,
2101 .flags = CLK_SET_RATE_PARENT,
2102 .ops = &clk_branch2_ops,
2103 },
2104 },
2105};
2106
2107static struct clk_branch gcc_usb_hs_system_clk = {
2108 .halt_reg = 0x0484,
2109 .clkr = {
2110 .enable_reg = 0x0484,
2111 .enable_mask = BIT(0),
2112 .hw.init = &(struct clk_init_data)
2113 {
2114 .name = "gcc_usb_hs_system_clk",
2115 .parent_names = (const char *[]) {
2116 "usb_hs_system_clk_src",
2117 },
2118 .num_parents = 1,
2119 .flags = CLK_SET_RATE_PARENT,
2120 .ops = &clk_branch2_ops,
2121 },
2122 },
2123};
2124
2125static struct clk_regmap *gcc_msm8994_clocks[] = {
2126 [GPLL0_EARLY] = &gpll0_early.clkr,
2127 [GPLL0] = &gpll0.clkr,
2128 [GPLL4_EARLY] = &gpll4_early.clkr,
2129 [GPLL4] = &gpll4.clkr,
2130 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
2131 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2132 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2133 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2134 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2135 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2136 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2137 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2138 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2139 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2140 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
2141 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
2142 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
2143 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
2144 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2145 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2146 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2147 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
2148 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
2149 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
2150 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
2151 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
2152 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
2153 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
2154 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
2155 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
2156 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
2157 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
2158 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
2159 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
2160 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
2161 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
2162 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
2163 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
2164 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
2165 [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
2166 [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
2167 [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
2168 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
2169 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
2170 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
2171 [PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr,
2172 [PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr,
2173 [PCIE_1_AUX_CLK_SRC] = &pcie_1_aux_clk_src.clkr,
2174 [PCIE_1_PIPE_CLK_SRC] = &pcie_1_pipe_clk_src.clkr,
2175 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2176 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2177 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2178 [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
2179 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
2180 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
2181 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2182 [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
2183 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
2184 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2185 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2186 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2187 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2188 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2189 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2190 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2191 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2192 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2193 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
2194 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
2195 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
2196 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
2197 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2198 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2199 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2200 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
2201 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
2202 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
2203 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2204 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
2205 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
2206 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
2207 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
2208 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
2209 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
2210 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
2211 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
2212 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
2213 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
2214 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
2215 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
2216 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
2217 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
2218 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
2219 [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
2220 [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
2221 [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
2222 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2223 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2224 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2225 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
2226 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
2227 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
2228 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
2229 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2230 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2231 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2232 [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
2233 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
2234 [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
2235 [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
2236 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
2237 [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
2238 [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
2239 [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
2240 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2241 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2242 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
2243 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
2244};
2245
2246static const struct regmap_config gcc_msm8994_regmap_config = {
2247 .reg_bits = 32,
2248 .reg_stride = 4,
2249 .val_bits = 32,
2250 .max_register = 0x2000,
2251 .fast_io = true,
2252};
2253
2254static const struct qcom_cc_desc gcc_msm8994_desc = {
2255 .config = &gcc_msm8994_regmap_config,
2256 .clks = gcc_msm8994_clocks,
2257 .num_clks = ARRAY_SIZE(gcc_msm8994_clocks),
2258};
2259
2260static const struct of_device_id gcc_msm8994_match_table[] = {
2261 { .compatible = "qcom,gcc-msm8994" },
2262 {}
2263};
2264MODULE_DEVICE_TABLE(of, gcc_msm8994_match_table);
2265
2266static int gcc_msm8994_probe(struct platform_device *pdev)
2267{
2268 struct device *dev = &pdev->dev;
2269 struct clk *clk;
2270
2271 clk = devm_clk_register(dev, &xo.hw);
2272 if (IS_ERR(clk))
2273 return PTR_ERR(clk);
2274
2275 return qcom_cc_probe(pdev, &gcc_msm8994_desc);
2276}
2277
2278static struct platform_driver gcc_msm8994_driver = {
2279 .probe = gcc_msm8994_probe,
2280 .driver = {
2281 .name = "gcc-msm8994",
2282 .of_match_table = gcc_msm8994_match_table,
2283 },
2284};
2285
2286static int __init gcc_msm8994_init(void)
2287{
2288 return platform_driver_register(&gcc_msm8994_driver);
2289}
2290core_initcall(gcc_msm8994_init);
2291
2292static void __exit gcc_msm8994_exit(void)
2293{
2294 platform_driver_unregister(&gcc_msm8994_driver);
2295}
2296module_exit(gcc_msm8994_exit);
2297
2298MODULE_DESCRIPTION("Qualcomm GCC MSM8994 Driver");
2299MODULE_LICENSE("GPL v2");
2300MODULE_ALIAS("platform:gcc-msm8994");
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8994.h b/include/dt-bindings/clock/qcom,gcc-msm8994.h
new file mode 100644
index 000000000000..8fa535be2ebc
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-msm8994.h
@@ -0,0 +1,137 @@
1/*
2 * Copyright (c) 2016, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14
15#ifndef _DT_BINDINGS_CLK_MSM_GCC_8994_H
16#define _DT_BINDINGS_CLK_MSM_GCC_8994_H
17
18#define GPLL0_EARLY 0
19#define GPLL0 1
20#define GPLL4_EARLY 2
21#define GPLL4 3
22#define UFS_AXI_CLK_SRC 4
23#define USB30_MASTER_CLK_SRC 5
24#define BLSP1_QUP1_I2C_APPS_CLK_SRC 6
25#define BLSP1_QUP1_SPI_APPS_CLK_SRC 7
26#define BLSP1_QUP2_I2C_APPS_CLK_SRC 8
27#define BLSP1_QUP2_SPI_APPS_CLK_SRC 9
28#define BLSP1_QUP3_I2C_APPS_CLK_SRC 10
29#define BLSP1_QUP3_SPI_APPS_CLK_SRC 11
30#define BLSP1_QUP4_I2C_APPS_CLK_SRC 12
31#define BLSP1_QUP4_SPI_APPS_CLK_SRC 13
32#define BLSP1_QUP5_I2C_APPS_CLK_SRC 14
33#define BLSP1_QUP5_SPI_APPS_CLK_SRC 15
34#define BLSP1_QUP6_I2C_APPS_CLK_SRC 16
35#define BLSP1_QUP6_SPI_APPS_CLK_SRC 17
36#define BLSP1_UART1_APPS_CLK_SRC 18
37#define BLSP1_UART2_APPS_CLK_SRC 19
38#define BLSP1_UART3_APPS_CLK_SRC 20
39#define BLSP1_UART4_APPS_CLK_SRC 21
40#define BLSP1_UART5_APPS_CLK_SRC 22
41#define BLSP1_UART6_APPS_CLK_SRC 23
42#define BLSP2_QUP1_I2C_APPS_CLK_SRC 24
43#define BLSP2_QUP1_SPI_APPS_CLK_SRC 25
44#define BLSP2_QUP2_I2C_APPS_CLK_SRC 26
45#define BLSP2_QUP2_SPI_APPS_CLK_SRC 27
46#define BLSP2_QUP3_I2C_APPS_CLK_SRC 28
47#define BLSP2_QUP3_SPI_APPS_CLK_SRC 29
48#define BLSP2_QUP4_I2C_APPS_CLK_SRC 30
49#define BLSP2_QUP4_SPI_APPS_CLK_SRC 31
50#define BLSP2_QUP5_I2C_APPS_CLK_SRC 32
51#define BLSP2_QUP5_SPI_APPS_CLK_SRC 33
52#define BLSP2_QUP6_I2C_APPS_CLK_SRC 34
53#define BLSP2_QUP6_SPI_APPS_CLK_SRC 35
54#define BLSP2_UART1_APPS_CLK_SRC 36
55#define BLSP2_UART2_APPS_CLK_SRC 37
56#define BLSP2_UART3_APPS_CLK_SRC 38
57#define BLSP2_UART4_APPS_CLK_SRC 39
58#define BLSP2_UART5_APPS_CLK_SRC 40
59#define BLSP2_UART6_APPS_CLK_SRC 41
60#define GP1_CLK_SRC 42
61#define GP2_CLK_SRC 43
62#define GP3_CLK_SRC 44
63#define PCIE_0_AUX_CLK_SRC 45
64#define PCIE_0_PIPE_CLK_SRC 46
65#define PCIE_1_AUX_CLK_SRC 47
66#define PCIE_1_PIPE_CLK_SRC 48
67#define PDM2_CLK_SRC 49
68#define SDCC1_APPS_CLK_SRC 50
69#define SDCC2_APPS_CLK_SRC 51
70#define SDCC3_APPS_CLK_SRC 52
71#define SDCC4_APPS_CLK_SRC 53
72#define TSIF_REF_CLK_SRC 54
73#define USB30_MOCK_UTMI_CLK_SRC 55
74#define USB3_PHY_AUX_CLK_SRC 56
75#define USB_HS_SYSTEM_CLK_SRC 57
76#define GCC_BLSP1_AHB_CLK 58
77#define GCC_BLSP1_QUP1_I2C_APPS_CLK 59
78#define GCC_BLSP1_QUP1_SPI_APPS_CLK 60
79#define GCC_BLSP1_QUP2_I2C_APPS_CLK 61
80#define GCC_BLSP1_QUP2_SPI_APPS_CLK 62
81#define GCC_BLSP1_QUP3_I2C_APPS_CLK 63
82#define GCC_BLSP1_QUP3_SPI_APPS_CLK 64
83#define GCC_BLSP1_QUP4_I2C_APPS_CLK 65
84#define GCC_BLSP1_QUP4_SPI_APPS_CLK 66
85#define GCC_BLSP1_QUP5_I2C_APPS_CLK 67
86#define GCC_BLSP1_QUP5_SPI_APPS_CLK 68
87#define GCC_BLSP1_QUP6_I2C_APPS_CLK 69
88#define GCC_BLSP1_QUP6_SPI_APPS_CLK 70
89#define GCC_BLSP1_UART1_APPS_CLK 71
90#define GCC_BLSP1_UART2_APPS_CLK 72
91#define GCC_BLSP1_UART3_APPS_CLK 73
92#define GCC_BLSP1_UART4_APPS_CLK 74
93#define GCC_BLSP1_UART5_APPS_CLK 75
94#define GCC_BLSP1_UART6_APPS_CLK 76
95#define GCC_BLSP2_AHB_CLK 77
96#define GCC_BLSP2_QUP1_I2C_APPS_CLK 78
97#define GCC_BLSP2_QUP1_SPI_APPS_CLK 79
98#define GCC_BLSP2_QUP2_I2C_APPS_CLK 80
99#define GCC_BLSP2_QUP2_SPI_APPS_CLK 81
100#define GCC_BLSP2_QUP3_I2C_APPS_CLK 82
101#define GCC_BLSP2_QUP3_SPI_APPS_CLK 83
102#define GCC_BLSP2_QUP4_I2C_APPS_CLK 84
103#define GCC_BLSP2_QUP4_SPI_APPS_CLK 85
104#define GCC_BLSP2_QUP5_I2C_APPS_CLK 86
105#define GCC_BLSP2_QUP5_SPI_APPS_CLK 87
106#define GCC_BLSP2_QUP6_I2C_APPS_CLK 88
107#define GCC_BLSP2_QUP6_SPI_APPS_CLK 89
108#define GCC_BLSP2_UART1_APPS_CLK 90
109#define GCC_BLSP2_UART2_APPS_CLK 91
110#define GCC_BLSP2_UART3_APPS_CLK 92
111#define GCC_BLSP2_UART4_APPS_CLK 93
112#define GCC_BLSP2_UART5_APPS_CLK 94
113#define GCC_BLSP2_UART6_APPS_CLK 95
114#define GCC_GP1_CLK 96
115#define GCC_GP2_CLK 97
116#define GCC_GP3_CLK 98
117#define GCC_PCIE_0_AUX_CLK 99
118#define GCC_PCIE_0_PIPE_CLK 100
119#define GCC_PCIE_1_AUX_CLK 101
120#define GCC_PCIE_1_PIPE_CLK 102
121#define GCC_PDM2_CLK 103
122#define GCC_SDCC1_APPS_CLK 104
123#define GCC_SDCC2_APPS_CLK 105
124#define GCC_SDCC3_APPS_CLK 106
125#define GCC_SDCC4_APPS_CLK 107
126#define GCC_SYS_NOC_UFS_AXI_CLK 108
127#define GCC_SYS_NOC_USB3_AXI_CLK 109
128#define GCC_TSIF_REF_CLK 110
129#define GCC_UFS_AXI_CLK 111
130#define GCC_UFS_RX_CFG_CLK 112
131#define GCC_UFS_TX_CFG_CLK 113
132#define GCC_USB30_MASTER_CLK 114
133#define GCC_USB30_MOCK_UTMI_CLK 115
134#define GCC_USB3_PHY_AUX_CLK 116
135#define GCC_USB_HS_SYSTEM_CLK 117
136
137#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-24 03:33:10 -0400