x86: msr-index.h: define EPB mid-points

These are currently open-coded into intel_pstate.c

Signed-off-by: Len Brown <len.brown@intel.com>

1 files changed, 5 insertions, 3 deletions

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 710273c617b8..a92d9bd154f6 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -462,9 +462,11 @@
 #define MSR_MISC_PWR_MGMT               0x000001aa
 
 #define MSR_IA32_ENERGY_PERF_BIAS       0x000001b0
-#define ENERGY_PERF_BIAS_PERFORMANCE    0
-#define ENERGY_PERF_BIAS_NORMAL         6
-#define ENERGY_PERF_BIAS_POWERSAVE      15
+#define ENERGY_PERF_BIAS_PERFORMANCE            0
+#define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE    4
+#define ENERGY_PERF_BIAS_NORMAL                 6
+#define ENERGY_PERF_BIAS_BALANCE_POWERSAVE      8
+#define ENERGY_PERF_BIAS_POWERSAVE              15
 
 #define MSR_IA32_PACKAGE_THERM_STATUS           0x000001b1