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authorStephen Boyd <sboyd@codeaurora.org>2017-08-23 18:33:45 -0400
committerStephen Boyd <sboyd@codeaurora.org>2017-08-23 18:33:45 -0400
commitcf657bb940b3106a52d329c039fb705fa8437724 (patch)
treec52e9cf9939f9563df01deec19ffd86deb3cc7ad
parent1fea70bc1839ac60a89f4b5d50e2b3e160aa74e2 (diff)
parent64a1644bc3baa62b769455d811b7999b9a1c6cd1 (diff)
Merge tag 'v4.14-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Pull Rockchip clk driver updates from Heiko Stuebner: The biggest change is fixing the jitter on the fractional clock-type Rockchip socs experience with the default approximation. For that we introduce the ability to override it with a clock-specific approximation and use that to create the needed rate settings as described in the Rockchip soc manuals (same for all Rockchip socs). Apart from that we have support for the rk3126 clock controller which is similar to the rk3128 with some minimal differences and a lot of improvements and fixes for the rv1108 clock controller (missing clocks, some clock-ids, naming fixes, register fixes). * tag 'v4.14-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: fix the rv1108 clk_mac sel register description clk: rockchip: rename rv1108 macphy clock to mac clk: rockchip: add rv1108 ACLK_GMAC and PCLK_GMAC clocks clk: rockchip: add rk3228 SCLK_SDIO_SRC clk id clk: rockchip: add rv1108 ACLK_GAMC and PCLK_GMAC ID clk: rockchip: add rk3228 sclk_sdio_src ID clk: rockchip: add special approximation to fix up fractional clk's jitter clk: fractional-divider: allow overriding of approximation clk: rockchip: modify rk3128 clk driver to also support rk3126 dt-bindings: add documentation for rk3126 clock clk: rockchip: add some critical clocks for rv1108 SoC clk: rockchip: rename some of clks for rv1108 SoC clk: rockchip: fix up some clks describe error for rv1108 SoC clk: rockchip: support more clks for rv1108 clk: rockchip: fix up the pll clks error for rv1108 SoC clk: rockchip: support more rates for rv1108 cpuclk clk: rockchip: fix up indentation of some RV1108 clock-ids clk: rockchip: rename the clk id for HCLK_I2S1_2CH clk: rockchip: add more clk ids for rv1108
Diffstat
-rw-r--r--Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.txt8
-rw-r--r--drivers/clk/clk-fractional-divider.c28
-rw-r--r--drivers/clk/rockchip/clk-rk3128.c69
-rw-r--r--drivers/clk/rockchip/clk-rk3228.c2
-rw-r--r--drivers/clk/rockchip/clk-rv1108.c462
-rw-r--r--drivers/clk/rockchip/clk.c36
-rw-r--r--include/dt-bindings/clock/rk3228-cru.h1
-rw-r--r--include/dt-bindings/clock/rv1108-cru.h125
-rw-r--r--include/linux/clk-provider.h3
9 files changed, 611 insertions, 123 deletions
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.txt
index 455a9a00a623..6f8744fd301b 100644
--- a/Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.txt
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.txt
@@ -1,12 +1,14 @@
1* Rockchip RK3128 Clock and Reset Unit 1* Rockchip RK3126/RK3128 Clock and Reset Unit
2 2
3The RK3128 clock controller generates and supplies clock to various 3The RK3126/RK3128 clock controller generates and supplies clock to various
4controllers within the SoC and also implements a reset controller for SoC 4controllers within the SoC and also implements a reset controller for SoC
5peripherals. 5peripherals.
6 6
7Required Properties: 7Required Properties:
8 8
9- compatible: should be "rockchip,rk3128-cru" 9- compatible: should be "rockchip,rk3126-cru" or "rockchip,rk3128-cru"
10 "rockchip,rk3126-cru" - controller compatible with RK3126 SoC.
11 "rockchip,rk3128-cru" - controller compatible with RK3128 SoC.
10- reg: physical base address of the controller and length of memory mapped 12- reg: physical base address of the controller and length of memory mapped
11 region. 13 region.
12- #clock-cells: should be 1. 14- #clock-cells: should be 1.
diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c
index aab904618eb6..fdf625fb10fa 100644
--- a/drivers/clk/clk-fractional-divider.c
+++ b/drivers/clk/clk-fractional-divider.c
@@ -49,16 +49,12 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
49 return ret; 49 return ret;
50} 50}
51 51
52static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate, 52static void clk_fd_general_approximation(struct clk_hw *hw, unsigned long rate,
53 unsigned long *parent_rate) 53 unsigned long *parent_rate,
54 unsigned long *m, unsigned long *n)
54{ 55{
55 struct clk_fractional_divider *fd = to_clk_fd(hw); 56 struct clk_fractional_divider *fd = to_clk_fd(hw);
56 unsigned long scale; 57 unsigned long scale;
57 unsigned long m, n;
58 u64 ret;
59
60 if (!rate || rate >= *parent_rate)
61 return *parent_rate;
62 58
63 /* 59 /*
64 * Get rate closer to *parent_rate to guarantee there is no overflow 60 * Get rate closer to *parent_rate to guarantee there is no overflow
@@ -71,7 +67,23 @@ static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
71 67
72 rational_best_approximation(rate, *parent_rate, 68 rational_best_approximation(rate, *parent_rate,
73 GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0), 69 GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
74 &m, &n); 70 m, n);
71}
72
73static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
74 unsigned long *parent_rate)
75{
76 struct clk_fractional_divider *fd = to_clk_fd(hw);
77 unsigned long m, n;
78 u64 ret;
79
80 if (!rate || rate >= *parent_rate)
81 return *parent_rate;
82
83 if (fd->approximation)
84 fd->approximation(hw, rate, parent_rate, &m, &n);
85 else
86 clk_fd_general_approximation(hw, rate, parent_rate, &m, &n);
75 87
76 ret = (u64)*parent_rate * m; 88 ret = (u64)*parent_rate * m;
77 do_div(ret, n); 89 do_div(ret, n);
diff --git a/drivers/clk/rockchip/clk-rk3128.c b/drivers/clk/rockchip/clk-rk3128.c
index e243f2eae68f..62d7854e4b87 100644
--- a/drivers/clk/rockchip/clk-rk3128.c
+++ b/drivers/clk/rockchip/clk-rk3128.c
@@ -201,7 +201,7 @@ static struct rockchip_clk_branch rk3128_uart2_fracmux __initdata =
201 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, 201 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
202 RK2928_CLKSEL_CON(15), 8, 2, MFLAGS); 202 RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
203 203
204static struct rockchip_clk_branch rk3128_clk_branches[] __initdata = { 204static struct rockchip_clk_branch common_clk_branches[] __initdata = {
205 /* 205 /*
206 * Clock-Architecture Diagram 1 206 * Clock-Architecture Diagram 1
207 */ 207 */
@@ -459,10 +459,6 @@ static struct rockchip_clk_branch rk3128_clk_branches[] __initdata = {
459 RK2928_CLKSEL_CON(2), 14, 2, MFLAGS, 8, 5, DFLAGS, 459 RK2928_CLKSEL_CON(2), 14, 2, MFLAGS, 8, 5, DFLAGS,
460 RK2928_CLKGATE_CON(10), 15, GFLAGS), 460 RK2928_CLKGATE_CON(10), 15, GFLAGS),
461 461
462 COMPOSITE(SCLK_SFC, "sclk_sfc", mux_sclk_sfc_src_p, 0,
463 RK2928_CLKSEL_CON(11), 14, 2, MFLAGS, 8, 5, DFLAGS,
464 RK2928_CLKGATE_CON(3), 15, GFLAGS),
465
466 COMPOSITE_NOMUX(PCLK_PMU_PRE, "pclk_pmu_pre", "cpll", 0, 462 COMPOSITE_NOMUX(PCLK_PMU_PRE, "pclk_pmu_pre", "cpll", 0,
467 RK2928_CLKSEL_CON(29), 8, 6, DFLAGS, 463 RK2928_CLKSEL_CON(29), 8, 6, DFLAGS,
468 RK2928_CLKGATE_CON(1), 0, GFLAGS), 464 RK2928_CLKGATE_CON(1), 0, GFLAGS),
@@ -495,7 +491,6 @@ static struct rockchip_clk_branch rk3128_clk_branches[] __initdata = {
495 GATE(ACLK_DMAC, "aclk_dmac", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 1, GFLAGS), 491 GATE(ACLK_DMAC, "aclk_dmac", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 1, GFLAGS),
496 GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 15, GFLAGS), 492 GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 15, GFLAGS),
497 GATE(0, "aclk_cpu_to_peri", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 2, GFLAGS), 493 GATE(0, "aclk_cpu_to_peri", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 2, GFLAGS),
498 GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS),
499 494
500 GATE(HCLK_I2S_8CH, "hclk_i2s_8ch", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS), 495 GATE(HCLK_I2S_8CH, "hclk_i2s_8ch", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
501 GATE(0, "hclk_peri_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS), 496 GATE(0, "hclk_peri_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS),
@@ -541,7 +536,6 @@ static struct rockchip_clk_branch rk3128_clk_branches[] __initdata = {
541 GATE(0, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 6, GFLAGS), 536 GATE(0, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 6, GFLAGS),
542 GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_cpu", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS), 537 GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_cpu", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS),
543 538
544 GATE(PCLK_HDMI, "pclk_hdmi", "pclk_cpu", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS),
545 GATE(PCLK_ACODEC, "pclk_acodec", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 14, GFLAGS), 539 GATE(PCLK_ACODEC, "pclk_acodec", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 14, GFLAGS),
546 GATE(0, "pclk_ddrupctl", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 7, GFLAGS), 540 GATE(0, "pclk_ddrupctl", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 7, GFLAGS),
547 GATE(0, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS), 541 GATE(0, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS),
@@ -561,6 +555,21 @@ static struct rockchip_clk_branch rk3128_clk_branches[] __initdata = {
561 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3228_EMMC_CON1, 0), 555 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3228_EMMC_CON1, 0),
562}; 556};
563 557
558static struct rockchip_clk_branch rk3126_clk_branches[] __initdata = {
559 GATE(0, "pclk_stimer", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 15, GFLAGS),
560 GATE(0, "pclk_s_efuse", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS),
561 GATE(0, "pclk_sgrf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 8, GFLAGS),
562};
563
564static struct rockchip_clk_branch rk3128_clk_branches[] __initdata = {
565 COMPOSITE(SCLK_SFC, "sclk_sfc", mux_sclk_sfc_src_p, 0,
566 RK2928_CLKSEL_CON(11), 14, 2, MFLAGS, 8, 5, DFLAGS,
567 RK2928_CLKGATE_CON(3), 15, GFLAGS),
568
569 GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS),
570 GATE(PCLK_HDMI, "pclk_hdmi", "pclk_cpu", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS),
571};
572
564static const char *const rk3128_critical_clocks[] __initconst = { 573static const char *const rk3128_critical_clocks[] __initconst = {
565 "aclk_cpu", 574 "aclk_cpu",
566 "hclk_cpu", 575 "hclk_cpu",
@@ -570,7 +579,7 @@ static const char *const rk3128_critical_clocks[] __initconst = {
570 "pclk_peri", 579 "pclk_peri",
571}; 580};
572 581
573static void __init rk3128_clk_init(struct device_node *np) 582static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device_node *np)
574{ 583{
575 struct rockchip_clk_provider *ctx; 584 struct rockchip_clk_provider *ctx;
576 void __iomem *reg_base; 585 void __iomem *reg_base;
@@ -578,23 +587,21 @@ static void __init rk3128_clk_init(struct device_node *np)
578 reg_base = of_iomap(np, 0); 587 reg_base = of_iomap(np, 0);
579 if (!reg_base) { 588 if (!reg_base) {
580 pr_err("%s: could not map cru region\n", __func__); 589 pr_err("%s: could not map cru region\n", __func__);
581 return; 590 return ERR_PTR(-ENOMEM);
582 } 591 }
583 592
584 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); 593 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
585 if (IS_ERR(ctx)) { 594 if (IS_ERR(ctx)) {
586 pr_err("%s: rockchip clk init failed\n", __func__); 595 pr_err("%s: rockchip clk init failed\n", __func__);
587 iounmap(reg_base); 596 iounmap(reg_base);
588 return; 597 return ERR_PTR(-ENOMEM);
589 } 598 }
590 599
591 rockchip_clk_register_plls(ctx, rk3128_pll_clks, 600 rockchip_clk_register_plls(ctx, rk3128_pll_clks,
592 ARRAY_SIZE(rk3128_pll_clks), 601 ARRAY_SIZE(rk3128_pll_clks),
593 RK3128_GRF_SOC_STATUS0); 602 RK3128_GRF_SOC_STATUS0);
594 rockchip_clk_register_branches(ctx, rk3128_clk_branches, 603 rockchip_clk_register_branches(ctx, common_clk_branches,
595 ARRAY_SIZE(rk3128_clk_branches)); 604 ARRAY_SIZE(common_clk_branches));
596 rockchip_clk_protect_critical(rk3128_critical_clocks,
597 ARRAY_SIZE(rk3128_critical_clocks));
598 605
599 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 606 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
600 mux_armclk_p, ARRAY_SIZE(mux_armclk_p), 607 mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
@@ -606,6 +613,40 @@ static void __init rk3128_clk_init(struct device_node *np)
606 613
607 rockchip_register_restart_notifier(ctx, RK2928_GLB_SRST_FST, NULL); 614 rockchip_register_restart_notifier(ctx, RK2928_GLB_SRST_FST, NULL);
608 615
616 return ctx;
617}
618
619static void __init rk3126_clk_init(struct device_node *np)
620{
621 struct rockchip_clk_provider *ctx;
622
623 ctx = rk3128_common_clk_init(np);
624 if (IS_ERR(ctx))
625 return;
626
627 rockchip_clk_register_branches(ctx, rk3126_clk_branches,
628 ARRAY_SIZE(rk3126_clk_branches));
629 rockchip_clk_protect_critical(rk3128_critical_clocks,
630 ARRAY_SIZE(rk3128_critical_clocks));
631
632 rockchip_clk_of_add_provider(np, ctx);
633}
634
635CLK_OF_DECLARE(rk3126_cru, "rockchip,rk3126-cru", rk3126_clk_init);
636
637static void __init rk3128_clk_init(struct device_node *np)
638{
639 struct rockchip_clk_provider *ctx;
640
641 ctx = rk3128_common_clk_init(np);
642 if (IS_ERR(ctx))
643 return;
644
645 rockchip_clk_register_branches(ctx, rk3128_clk_branches,
646 ARRAY_SIZE(rk3128_clk_branches));
647 rockchip_clk_protect_critical(rk3128_critical_clocks,
648 ARRAY_SIZE(rk3128_critical_clocks));
649
609 rockchip_clk_of_add_provider(np, ctx); 650 rockchip_clk_of_add_provider(np, ctx);
610} 651}
611 652
diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
index bb405d9044a3..11e7f2d1c054 100644
--- a/drivers/clk/rockchip/clk-rk3228.c
+++ b/drivers/clk/rockchip/clk-rk3228.c
@@ -391,7 +391,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
391 RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 8, DFLAGS, 391 RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 8, DFLAGS,
392 RK2928_CLKGATE_CON(2), 11, GFLAGS), 392 RK2928_CLKGATE_CON(2), 11, GFLAGS),
393 393
394 COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0, 394 COMPOSITE_NODIV(SCLK_SDIO_SRC, "sclk_sdio_src", mux_mmc_src_p, 0,
395 RK2928_CLKSEL_CON(11), 10, 2, MFLAGS, 395 RK2928_CLKSEL_CON(11), 10, 2, MFLAGS,
396 RK2928_CLKGATE_CON(2), 13, GFLAGS), 396 RK2928_CLKGATE_CON(2), 13, GFLAGS),
397 DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0, 397 DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0,
diff --git a/drivers/clk/rockchip/clk-rv1108.c b/drivers/clk/rockchip/clk-rv1108.c
index 7c05ab366348..089cb17925e5 100644
--- a/drivers/clk/rockchip/clk-rv1108.c
+++ b/drivers/clk/rockchip/clk-rv1108.c
@@ -93,9 +93,24 @@ static struct rockchip_pll_rate_table rv1108_pll_rates[] = {
93 } 93 }
94 94
95static struct rockchip_cpuclk_rate_table rv1108_cpuclk_rates[] __initdata = { 95static struct rockchip_cpuclk_rate_table rv1108_cpuclk_rates[] __initdata = {
96 RV1108_CPUCLK_RATE(816000000, 4), 96 RV1108_CPUCLK_RATE(1608000000, 7),
97 RV1108_CPUCLK_RATE(600000000, 4), 97 RV1108_CPUCLK_RATE(1512000000, 7),
98 RV1108_CPUCLK_RATE(312000000, 4), 98 RV1108_CPUCLK_RATE(1488000000, 5),
99 RV1108_CPUCLK_RATE(1416000000, 5),
100 RV1108_CPUCLK_RATE(1392000000, 5),
101 RV1108_CPUCLK_RATE(1296000000, 5),
102 RV1108_CPUCLK_RATE(1200000000, 5),
103 RV1108_CPUCLK_RATE(1104000000, 5),
104 RV1108_CPUCLK_RATE(1008000000, 5),
105 RV1108_CPUCLK_RATE(912000000, 5),
106 RV1108_CPUCLK_RATE(816000000, 3),
107 RV1108_CPUCLK_RATE(696000000, 3),
108 RV1108_CPUCLK_RATE(600000000, 3),
109 RV1108_CPUCLK_RATE(500000000, 3),
110 RV1108_CPUCLK_RATE(408000000, 1),
111 RV1108_CPUCLK_RATE(312000000, 1),
112 RV1108_CPUCLK_RATE(216000000, 1),
113 RV1108_CPUCLK_RATE(96000000, 1),
99}; 114};
100 115
101static const struct rockchip_cpuclk_reg_data rv1108_cpuclk_data = { 116static const struct rockchip_cpuclk_reg_data rv1108_cpuclk_data = {
@@ -105,7 +120,7 @@ static const struct rockchip_cpuclk_reg_data rv1108_cpuclk_data = {
105 .mux_core_alt = 1, 120 .mux_core_alt = 1,
106 .mux_core_main = 0, 121 .mux_core_main = 0,
107 .mux_core_shift = 8, 122 .mux_core_shift = 8,
108 .mux_core_mask = 0x1, 123 .mux_core_mask = 0x3,
109}; 124};
110 125
111PNAME(mux_pll_p) = { "xin24m", "xin24m"}; 126PNAME(mux_pll_p) = { "xin24m", "xin24m"};
@@ -114,30 +129,42 @@ PNAME(mux_armclk_p) = { "apll_core", "gpll_core", "dpll_core" };
114PNAME(mux_usb480m_pre_p) = { "usbphy", "xin24m" }; 129PNAME(mux_usb480m_pre_p) = { "usbphy", "xin24m" };
115PNAME(mux_hdmiphy_phy_p) = { "hdmiphy", "xin24m" }; 130PNAME(mux_hdmiphy_phy_p) = { "hdmiphy", "xin24m" };
116PNAME(mux_dclk_hdmiphy_pre_p) = { "dclk_hdmiphy_src_gpll", "dclk_hdmiphy_src_dpll" }; 131PNAME(mux_dclk_hdmiphy_pre_p) = { "dclk_hdmiphy_src_gpll", "dclk_hdmiphy_src_dpll" };
117PNAME(mux_pll_src_4plls_p) = { "dpll", "hdmiphy", "gpll", "usb480m" }; 132PNAME(mux_pll_src_4plls_p) = { "dpll", "gpll", "hdmiphy", "usb480m" };
118PNAME(mux_pll_src_3plls_p) = { "apll", "gpll", "dpll" }; 133PNAME(mux_pll_src_3plls_p) = { "apll", "gpll", "dpll" };
119PNAME(mux_pll_src_2plls_p) = { "dpll", "gpll" }; 134PNAME(mux_pll_src_2plls_p) = { "dpll", "gpll" };
120PNAME(mux_pll_src_apll_gpll_p) = { "apll", "gpll" }; 135PNAME(mux_pll_src_apll_gpll_p) = { "apll", "gpll" };
121PNAME(mux_aclk_peri_src_p) = { "aclk_peri_src_dpll", "aclk_peri_src_gpll" }; 136PNAME(mux_aclk_peri_src_p) = { "aclk_peri_src_gpll", "aclk_peri_src_dpll" };
122PNAME(mux_aclk_bus_src_p) = { "aclk_bus_src_gpll", "aclk_bus_src_apll", "aclk_bus_src_dpll" }; 137PNAME(mux_aclk_bus_src_p) = { "aclk_bus_src_gpll", "aclk_bus_src_apll", "aclk_bus_src_dpll" };
123PNAME(mux_mmc_src_p) = { "dpll", "gpll", "xin24m", "usb480m" }; 138PNAME(mux_mmc_src_p) = { "dpll", "gpll", "xin24m", "usb480m" };
124PNAME(mux_pll_src_dpll_gpll_usb480m_p) = { "dpll", "gpll", "usb480m" }; 139PNAME(mux_pll_src_dpll_gpll_usb480m_p) = { "dpll", "gpll", "usb480m" };
125PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" }; 140PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
126PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" }; 141PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
127PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" }; 142PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
128PNAME(mux_sclk_macphy_p) = { "sclk_macphy_pre", "ext_gmac" }; 143PNAME(mux_sclk_mac_p) = { "sclk_mac_pre", "ext_gmac" };
129PNAME(mux_i2s0_pre_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" }; 144PNAME(mux_i2s0_pre_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" };
130PNAME(mux_i2s_out_p) = { "i2s0_pre", "xin12m" }; 145PNAME(mux_i2s_out_p) = { "i2s0_pre", "xin12m" };
131PNAME(mux_i2s1_p) = { "i2s1_src", "i2s1_frac", "xin12m" }; 146PNAME(mux_i2s1_p) = { "i2s1_src", "i2s1_frac", "dummy", "xin12m" };
132PNAME(mux_i2s2_p) = { "i2s2_src", "i2s2_frac", "xin12m" }; 147PNAME(mux_i2s2_p) = { "i2s2_src", "i2s2_frac", "dummy", "xin12m" };
148PNAME(mux_wifi_src_p) = { "gpll", "xin24m" };
149PNAME(mux_cifout_src_p) = { "hdmiphy", "gpll" };
150PNAME(mux_cifout_p) = { "sclk_cifout_src", "xin24m" };
151PNAME(mux_sclk_cif0_src_p) = { "pclk_vip", "clk_cif0_chn_out", "pclkin_cvbs2cif" };
152PNAME(mux_sclk_cif1_src_p) = { "pclk_vip", "clk_cif1_chn_out", "pclkin_cvbs2cif" };
153PNAME(mux_sclk_cif2_src_p) = { "pclk_vip", "clk_cif2_chn_out", "pclkin_cvbs2cif" };
154PNAME(mux_sclk_cif3_src_p) = { "pclk_vip", "clk_cif3_chn_out", "pclkin_cvbs2cif" };
155PNAME(mux_dsp_src_p) = { "dpll", "gpll", "apll", "usb480m" };
156PNAME(mux_dclk_hdmiphy_p) = { "hdmiphy", "xin24m" };
157PNAME(mux_dclk_vop_p) = { "dclk_hdmiphy", "dclk_vop_src" };
158PNAME(mux_hdmi_cec_src_p) = { "dpll", "gpll", "xin24m" };
159PNAME(mux_cvbs_src_p) = { "apll", "io_cvbs_clkin", "hdmiphy", "gpll" };
133 160
134static struct rockchip_pll_clock rv1108_pll_clks[] __initdata = { 161static struct rockchip_pll_clock rv1108_pll_clks[] __initdata = {
135 [apll] = PLL(pll_rk3399, PLL_APLL, "apll", mux_pll_p, 0, RV1108_PLL_CON(0), 162 [apll] = PLL(pll_rk3399, PLL_APLL, "apll", mux_pll_p, 0, RV1108_PLL_CON(0),
136 RV1108_PLL_CON(3), 8, 31, 0, rv1108_pll_rates), 163 RV1108_PLL_CON(3), 8, 0, 0, rv1108_pll_rates),
137 [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RV1108_PLL_CON(8), 164 [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RV1108_PLL_CON(8),
138 RV1108_PLL_CON(11), 8, 31, 0, NULL), 165 RV1108_PLL_CON(11), 8, 1, 0, NULL),
139 [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RV1108_PLL_CON(16), 166 [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RV1108_PLL_CON(16),
140 RV1108_PLL_CON(19), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rv1108_pll_rates), 167 RV1108_PLL_CON(19), 8, 2, 0, rv1108_pll_rates),
141}; 168};
142 169
143#define MFLAGS CLK_MUX_HIWORD_MASK 170#define MFLAGS CLK_MUX_HIWORD_MASK
@@ -170,10 +197,10 @@ static struct rockchip_clk_branch rv1108_i2s2_fracmux __initdata =
170 RV1108_CLKSEL_CON(7), 12, 2, MFLAGS); 197 RV1108_CLKSEL_CON(7), 12, 2, MFLAGS);
171 198
172static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = { 199static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
173 MUX(0, "hdmi_phy", mux_hdmiphy_phy_p, CLK_SET_RATE_PARENT, 200 MUX(0, "hdmiphy", mux_hdmiphy_phy_p, CLK_SET_RATE_PARENT,
174 RV1108_MISC_CON, 13, 2, MFLAGS), 201 RV1108_MISC_CON, 13, 1, MFLAGS),
175 MUX(0, "usb480m", mux_usb480m_pre_p, CLK_SET_RATE_PARENT, 202 MUX(0, "usb480m", mux_usb480m_pre_p, CLK_SET_RATE_PARENT,
176 RV1108_MISC_CON, 15, 2, MFLAGS), 203 RV1108_MISC_CON, 15, 1, MFLAGS),
177 /* 204 /*
178 * Clock-Architecture Diagram 2 205 * Clock-Architecture Diagram 2
179 */ 206 */
@@ -197,50 +224,212 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
197 RV1108_CLKGATE_CON(11), 1, GFLAGS), 224 RV1108_CLKGATE_CON(11), 1, GFLAGS),
198 225
199 /* PD_RKVENC */ 226 /* PD_RKVENC */
227 COMPOSITE(0, "aclk_rkvenc_pre", mux_pll_src_4plls_p, 0,
228 RV1108_CLKSEL_CON(37), 6, 2, MFLAGS, 0, 5, DFLAGS,
229 RV1108_CLKGATE_CON(8), 8, GFLAGS),
230 FACTOR_GATE(0, "hclk_rkvenc_pre", "aclk_rkvenc_pre", 0, 1, 4,
231 RV1108_CLKGATE_CON(8), 10, GFLAGS),
232 COMPOSITE(SCLK_VENC_CORE, "clk_venc_core", mux_pll_src_4plls_p, 0,
233 RV1108_CLKSEL_CON(37), 14, 2, MFLAGS, 8, 5, DFLAGS,
234 RV1108_CLKGATE_CON(8), 9, GFLAGS),
235 GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_pre", 0,
236 RV1108_CLKGATE_CON(19), 8, GFLAGS),
237 GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_pre", 0,
238 RV1108_CLKGATE_CON(19), 9, GFLAGS),
239 GATE(0, "aclk_rkvenc_niu", "aclk_rkvenc_pre", CLK_IGNORE_UNUSED,
240 RV1108_CLKGATE_CON(19), 11, GFLAGS),
241 GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc_pre", CLK_IGNORE_UNUSED,
242 RV1108_CLKGATE_CON(19), 10, GFLAGS),
200 243
201 /* PD_RKVDEC */ 244 /* PD_RKVDEC */
245 COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_4plls_p, 0,
246 RV1108_CLKSEL_CON(36), 6, 2, MFLAGS, 0, 5, DFLAGS,
247 RV1108_CLKGATE_CON(8), 2, GFLAGS),
248 FACTOR_GATE(0, "hclk_rkvdec_pre", "sclk_hevc_core", 0, 1, 4,
249 RV1108_CLKGATE_CON(8), 10, GFLAGS),
250 COMPOSITE(SCLK_HEVC_CABAC, "clk_hevc_cabac", mux_pll_src_4plls_p, 0,
251 RV1108_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 5, DFLAGS,
252 RV1108_CLKGATE_CON(8), 1, GFLAGS),
253
254 COMPOSITE(0, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0,
255 RV1108_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
256 RV1108_CLKGATE_CON(8), 0, GFLAGS),
257 COMPOSITE(0, "aclk_vpu_pre", mux_pll_src_4plls_p, 0,
258 RV1108_CLKSEL_CON(36), 14, 2, MFLAGS, 8, 5, DFLAGS,
259 RV1108_CLKGATE_CON(8), 3, GFLAGS),
260 GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0,
261 RV1108_CLKGATE_CON(19), 0, GFLAGS),
262 GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0,
263 RV1108_CLKGATE_CON(19), 1, GFLAGS),
264 GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0,
265 RV1108_CLKGATE_CON(19), 2, GFLAGS),
266 GATE(HCLK_VPU, "hclk_vpu", "hclk_rkvdec_pre", 0,
267 RV1108_CLKGATE_CON(19), 3, GFLAGS),
268 GATE(0, "aclk_rkvdec_niu", "aclk_rkvdec_pre", CLK_IGNORE_UNUSED,
269 RV1108_CLKGATE_CON(19), 4, GFLAGS),
270 GATE(0, "hclk_rkvdec_niu", "hclk_rkvdec_pre", CLK_IGNORE_UNUSED,
271 RV1108_CLKGATE_CON(19), 5, GFLAGS),
272 GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", CLK_IGNORE_UNUSED,
273 RV1108_CLKGATE_CON(19), 6, GFLAGS),
202 274
203 /* PD_PMU_wrapper */ 275 /* PD_PMU_wrapper */
204 COMPOSITE_NOMUX(0, "pmu_24m_ena", "gpll", CLK_IGNORE_UNUSED, 276 COMPOSITE_NOMUX(0, "pmu_24m_ena", "gpll", CLK_IGNORE_UNUSED,
205 RV1108_CLKSEL_CON(38), 0, 5, DFLAGS, 277 RV1108_CLKSEL_CON(38), 0, 5, DFLAGS,
206 RV1108_CLKGATE_CON(8), 12, GFLAGS), 278 RV1108_CLKGATE_CON(8), 12, GFLAGS),
207 GATE(0, "pmu", "pmu_24m_ena", CLK_IGNORE_UNUSED, 279 GATE(0, "pclk_pmu", "pmu_24m_ena", CLK_IGNORE_UNUSED,
208 RV1108_CLKGATE_CON(10), 0, GFLAGS), 280 RV1108_CLKGATE_CON(10), 0, GFLAGS),
209 GATE(0, "intmem1", "pmu_24m_ena", CLK_IGNORE_UNUSED, 281 GATE(0, "pclk_intmem1", "pmu_24m_ena", CLK_IGNORE_UNUSED,
210 RV1108_CLKGATE_CON(10), 1, GFLAGS), 282 RV1108_CLKGATE_CON(10), 1, GFLAGS),
211 GATE(0, "gpio0_pmu", "pmu_24m_ena", CLK_IGNORE_UNUSED, 283 GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pmu_24m_ena", 0,
212 RV1108_CLKGATE_CON(10), 2, GFLAGS), 284 RV1108_CLKGATE_CON(10), 2, GFLAGS),
213 GATE(0, "pmugrf", "pmu_24m_ena", CLK_IGNORE_UNUSED, 285 GATE(0, "pclk_pmugrf", "pmu_24m_ena", CLK_IGNORE_UNUSED,
214 RV1108_CLKGATE_CON(10), 3, GFLAGS), 286 RV1108_CLKGATE_CON(10), 3, GFLAGS),
215 GATE(0, "pmu_noc", "pmu_24m_ena", CLK_IGNORE_UNUSED, 287 GATE(0, "pclk_pmu_niu", "pmu_24m_ena", CLK_IGNORE_UNUSED,
216 RV1108_CLKGATE_CON(10), 4, GFLAGS), 288 RV1108_CLKGATE_CON(10), 4, GFLAGS),
217 GATE(0, "i2c0_pmu_pclk", "pmu_24m_ena", CLK_IGNORE_UNUSED, 289 GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pmu_24m_ena", 0,
218 RV1108_CLKGATE_CON(10), 5, GFLAGS), 290 RV1108_CLKGATE_CON(10), 5, GFLAGS),
219 GATE(0, "pwm0_pmu_pclk", "pmu_24m_ena", CLK_IGNORE_UNUSED, 291 GATE(PCLK_PWM0_PMU, "pclk_pwm0_pmu", "pmu_24m_ena", 0,
220 RV1108_CLKGATE_CON(10), 6, GFLAGS), 292 RV1108_CLKGATE_CON(10), 6, GFLAGS),
221 COMPOSITE(0, "pwm0_pmu_clk", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED, 293 COMPOSITE(SCLK_PWM0_PMU, "sclk_pwm0_pmu", mux_pll_src_2plls_p, 0,
222 RV1108_CLKSEL_CON(12), 7, 1, MFLAGS, 0, 7, DFLAGS, 294 RV1108_CLKSEL_CON(12), 7, 1, MFLAGS, 0, 7, DFLAGS,
223 RV1108_CLKGATE_CON(8), 15, GFLAGS), 295 RV1108_CLKGATE_CON(8), 15, GFLAGS),
224 COMPOSITE(0, "i2c0_pmu_clk", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED, 296 COMPOSITE(SCLK_I2C0_PMU, "sclk_i2c0_pmu", mux_pll_src_2plls_p, 0,
225 RV1108_CLKSEL_CON(19), 7, 1, MFLAGS, 0, 7, DFLAGS, 297 RV1108_CLKSEL_CON(19), 7, 1, MFLAGS, 0, 7, DFLAGS,
226 RV1108_CLKGATE_CON(8), 14, GFLAGS), 298 RV1108_CLKGATE_CON(8), 14, GFLAGS),
227 GATE(0, "pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED, 299 GATE(0, "pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED,
228 RV1108_CLKGATE_CON(8), 13, GFLAGS), 300 RV1108_CLKGATE_CON(8), 13, GFLAGS),
229 301
230 /* 302 /*
303 * Clock-Architecture Diagram 3
304 */
305 COMPOSITE(SCLK_WIFI, "sclk_wifi", mux_wifi_src_p, 0,
306 RV1108_CLKSEL_CON(28), 15, 1, MFLAGS, 8, 6, DFLAGS,
307 RV1108_CLKGATE_CON(9), 8, GFLAGS),
308 COMPOSITE_NODIV(0, "sclk_cifout_src", mux_cifout_src_p, 0,
309 RV1108_CLKSEL_CON(40), 8, 1, MFLAGS,
310 RV1108_CLKGATE_CON(9), 11, GFLAGS),
311 COMPOSITE_NOGATE(SCLK_CIFOUT, "sclk_cifout", mux_cifout_p, 0,
312 RV1108_CLKSEL_CON(40), 12, 1, MFLAGS, 0, 5, DFLAGS),
313 COMPOSITE_NOMUX(SCLK_MIPI_CSI_OUT, "sclk_mipi_csi_out", "xin24m", 0,
314 RV1108_CLKSEL_CON(41), 0, 5, DFLAGS,
315 RV1108_CLKGATE_CON(9), 12, GFLAGS),
316
317 GATE(0, "pclk_acodecphy", "pclk_top_pre", CLK_IGNORE_UNUSED,
318 RV1108_CLKGATE_CON(14), 6, GFLAGS),
319 GATE(0, "pclk_usbgrf", "pclk_top_pre", CLK_IGNORE_UNUSED,
320 RV1108_CLKGATE_CON(14), 14, GFLAGS),
321
322 GATE(ACLK_CIF0, "aclk_cif0", "aclk_vio1_pre", 0,
323 RV1108_CLKGATE_CON(18), 10, GFLAGS),
324 GATE(HCLK_CIF0, "hclk_cif0", "hclk_vio_pre", 0,
325 RV1108_CLKGATE_CON(18), 10, GFLAGS),
326 COMPOSITE_NODIV(SCLK_CIF0, "sclk_cif0", mux_sclk_cif0_src_p, 0,
327 RV1108_CLKSEL_CON(31), 0, 2, MFLAGS,
328 RV1108_CLKGATE_CON(7), 9, GFLAGS),
329 GATE(ACLK_CIF1, "aclk_cif1", "aclk_vio1_pre", 0,
330 RV1108_CLKGATE_CON(17), 6, GFLAGS),
331 GATE(HCLK_CIF1, "hclk_cif1", "hclk_vio_pre", 0,
332 RV1108_CLKGATE_CON(17), 7, GFLAGS),
333 COMPOSITE_NODIV(SCLK_CIF1, "sclk_cif1", mux_sclk_cif1_src_p, 0,
334 RV1108_CLKSEL_CON(31), 2, 2, MFLAGS,
335 RV1108_CLKGATE_CON(7), 10, GFLAGS),
336 GATE(ACLK_CIF2, "aclk_cif2", "aclk_vio1_pre", 0,
337 RV1108_CLKGATE_CON(17), 8, GFLAGS),
338 GATE(HCLK_CIF2, "hclk_cif2", "hclk_vio_pre", 0,
339 RV1108_CLKGATE_CON(17), 9, GFLAGS),
340 COMPOSITE_NODIV(SCLK_CIF2, "sclk_cif2", mux_sclk_cif2_src_p, 0,
341 RV1108_CLKSEL_CON(31), 4, 2, MFLAGS,
342 RV1108_CLKGATE_CON(7), 11, GFLAGS),
343 GATE(ACLK_CIF3, "aclk_cif3", "aclk_vio1_pre", 0,
344 RV1108_CLKGATE_CON(17), 10, GFLAGS),
345 GATE(HCLK_CIF3, "hclk_cif3", "hclk_vio_pre", 0,
346 RV1108_CLKGATE_CON(17), 11, GFLAGS),
347 COMPOSITE_NODIV(SCLK_CIF3, "sclk_cif3", mux_sclk_cif3_src_p, 0,
348 RV1108_CLKSEL_CON(31), 6, 2, MFLAGS,
349 RV1108_CLKGATE_CON(7), 12, GFLAGS),
350 GATE(0, "pclk_cif1to4", "pclk_vip", CLK_IGNORE_UNUSED,
351 RV1108_CLKGATE_CON(7), 8, GFLAGS),
352
353 /* PD_DSP_wrapper */
354 COMPOSITE(SCLK_DSP, "sclk_dsp", mux_dsp_src_p, 0,
355 RV1108_CLKSEL_CON(42), 8, 2, MFLAGS, 0, 5, DFLAGS,
356 RV1108_CLKGATE_CON(9), 0, GFLAGS),
357 GATE(0, "clk_dsp_sys_wd", "sclk_dsp", CLK_IGNORE_UNUSED,
358 RV1108_CLKGATE_CON(16), 0, GFLAGS),
359 GATE(0, "clk_dsp_epp_wd", "sclk_dsp", CLK_IGNORE_UNUSED,
360 RV1108_CLKGATE_CON(16), 1, GFLAGS),
361 GATE(0, "clk_dsp_edp_wd", "sclk_dsp", CLK_IGNORE_UNUSED,
362 RV1108_CLKGATE_CON(16), 2, GFLAGS),
363 GATE(0, "clk_dsp_iop_wd", "sclk_dsp", CLK_IGNORE_UNUSED,
364 RV1108_CLKGATE_CON(16), 3, GFLAGS),
365 GATE(0, "clk_dsp_free", "sclk_dsp", CLK_IGNORE_UNUSED,
366 RV1108_CLKGATE_CON(16), 13, GFLAGS),
367 COMPOSITE_NOMUX(SCLK_DSP_IOP, "sclk_dsp_iop", "sclk_dsp", 0,
368 RV1108_CLKSEL_CON(44), 0, 5, DFLAGS,
369 RV1108_CLKGATE_CON(9), 1, GFLAGS),
370 COMPOSITE_NOMUX(SCLK_DSP_EPP, "sclk_dsp_epp", "sclk_dsp", 0,
371 RV1108_CLKSEL_CON(44), 8, 5, DFLAGS,
372 RV1108_CLKGATE_CON(9), 2, GFLAGS),
373 COMPOSITE_NOMUX(SCLK_DSP_EDP, "sclk_dsp_edp", "sclk_dsp", 0,
374 RV1108_CLKSEL_CON(45), 0, 5, DFLAGS,
375 RV1108_CLKGATE_CON(9), 3, GFLAGS),
376 COMPOSITE_NOMUX(SCLK_DSP_EDAP, "sclk_dsp_edap", "sclk_dsp", 0,
377 RV1108_CLKSEL_CON(45), 8, 5, DFLAGS,
378 RV1108_CLKGATE_CON(9), 4, GFLAGS),
379 GATE(0, "pclk_dsp_iop_niu", "sclk_dsp_iop", CLK_IGNORE_UNUSED,
380 RV1108_CLKGATE_CON(16), 4, GFLAGS),
381 GATE(0, "aclk_dsp_epp_niu", "sclk_dsp_epp", CLK_IGNORE_UNUSED,
382 RV1108_CLKGATE_CON(16), 5, GFLAGS),
383 GATE(0, "aclk_dsp_edp_niu", "sclk_dsp_edp", CLK_IGNORE_UNUSED,
384 RV1108_CLKGATE_CON(16), 6, GFLAGS),
385 GATE(0, "pclk_dsp_dbg_niu", "sclk_dsp", CLK_IGNORE_UNUSED,
386 RV1108_CLKGATE_CON(16), 7, GFLAGS),
387 GATE(0, "aclk_dsp_edap_niu", "sclk_dsp_edap", CLK_IGNORE_UNUSED,
388 RV1108_CLKGATE_CON(16), 14, GFLAGS),
389 COMPOSITE_NOMUX(SCLK_DSP_PFM, "sclk_dsp_pfm", "sclk_dsp", 0,
390 RV1108_CLKSEL_CON(43), 0, 5, DFLAGS,
391 RV1108_CLKGATE_CON(9), 5, GFLAGS),
392 COMPOSITE_NOMUX(PCLK_DSP_CFG, "pclk_dsp_cfg", "sclk_dsp", 0,
393 RV1108_CLKSEL_CON(43), 8, 5, DFLAGS,
394 RV1108_CLKGATE_CON(9), 6, GFLAGS),
395 GATE(0, "pclk_dsp_cfg_niu", "pclk_dsp_cfg", CLK_IGNORE_UNUSED,
396 RV1108_CLKGATE_CON(16), 8, GFLAGS),
397 GATE(0, "pclk_dsp_pfm_mon", "pclk_dsp_cfg", CLK_IGNORE_UNUSED,
398 RV1108_CLKGATE_CON(16), 9, GFLAGS),
399 GATE(0, "pclk_intc", "pclk_dsp_cfg", CLK_IGNORE_UNUSED,
400 RV1108_CLKGATE_CON(16), 10, GFLAGS),
401 GATE(0, "pclk_dsp_grf", "pclk_dsp_cfg", CLK_IGNORE_UNUSED,
402 RV1108_CLKGATE_CON(16), 11, GFLAGS),
403 GATE(0, "pclk_mailbox", "pclk_dsp_cfg", CLK_IGNORE_UNUSED,
404 RV1108_CLKGATE_CON(16), 12, GFLAGS),
405 GATE(0, "aclk_dsp_epp_perf", "sclk_dsp_epp", CLK_IGNORE_UNUSED,
406 RV1108_CLKGATE_CON(16), 15, GFLAGS),
407 GATE(0, "aclk_dsp_edp_perf", "sclk_dsp_edp", CLK_IGNORE_UNUSED,
408 RV1108_CLKGATE_CON(11), 8, GFLAGS),
409
410 /*
231 * Clock-Architecture Diagram 4 411 * Clock-Architecture Diagram 4
232 */ 412 */
233 COMPOSITE(0, "aclk_vio0_2wrap_occ", mux_pll_src_4plls_p, CLK_IGNORE_UNUSED, 413 COMPOSITE(0, "aclk_vio0_pre", mux_pll_src_4plls_p, CLK_IGNORE_UNUSED,
234 RV1108_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS, 414 RV1108_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS,
235 RV1108_CLKGATE_CON(6), 0, GFLAGS), 415 RV1108_CLKGATE_CON(6), 0, GFLAGS),
236 GATE(0, "aclk_vio0_pre", "aclk_vio0_2wrap_occ", CLK_IGNORE_UNUSED, 416 GATE(ACLK_VIO0, "aclk_vio0", "aclk_vio0_pre", 0,
237 RV1108_CLKGATE_CON(17), 0, GFLAGS), 417 RV1108_CLKGATE_CON(17), 0, GFLAGS),
238 COMPOSITE_NOMUX(0, "hclk_vio_pre", "aclk_vio0_pre", 0, 418 COMPOSITE_NOMUX(0, "hclk_vio_pre", "aclk_vio0_pre", 0,
239 RV1108_CLKSEL_CON(29), 0, 5, DFLAGS, 419 RV1108_CLKSEL_CON(29), 0, 5, DFLAGS,
240 RV1108_CLKGATE_CON(7), 2, GFLAGS), 420 RV1108_CLKGATE_CON(7), 2, GFLAGS),
421 GATE(HCLK_VIO, "hclk_vio", "hclk_vio_pre", 0,
422 RV1108_CLKGATE_CON(17), 2, GFLAGS),
241 COMPOSITE_NOMUX(0, "pclk_vio_pre", "aclk_vio0_pre", 0, 423 COMPOSITE_NOMUX(0, "pclk_vio_pre", "aclk_vio0_pre", 0,
242 RV1108_CLKSEL_CON(29), 8, 5, DFLAGS, 424 RV1108_CLKSEL_CON(29), 8, 5, DFLAGS,
243 RV1108_CLKGATE_CON(7), 3, GFLAGS), 425 RV1108_CLKGATE_CON(7), 3, GFLAGS),
426 GATE(PCLK_VIO, "pclk_vio", "pclk_vio_pre", 0,
427 RV1108_CLKGATE_CON(17), 3, GFLAGS),
428 COMPOSITE(0, "aclk_vio1_pre", mux_pll_src_4plls_p, CLK_IGNORE_UNUSED,
429 RV1108_CLKSEL_CON(28), 14, 2, MFLAGS, 8, 5, DFLAGS,
430 RV1108_CLKGATE_CON(6), 1, GFLAGS),
431 GATE(ACLK_VIO1, "aclk_vio1", "aclk_vio1_pre", 0,
432 RV1108_CLKGATE_CON(17), 1, GFLAGS),
244 433
245 INVERTER(0, "pclk_vip", "ext_vip", 434 INVERTER(0, "pclk_vip", "ext_vip",
246 RV1108_CLKSEL_CON(31), 8, IFLAGS), 435 RV1108_CLKSEL_CON(31), 8, IFLAGS),
@@ -252,8 +441,63 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
252 RV1108_CLKGATE_CON(6), 5, GFLAGS), 441 RV1108_CLKGATE_CON(6), 5, GFLAGS),
253 GATE(0, "dclk_hdmiphy_src_dpll", "dpll", CLK_IGNORE_UNUSED, 442 GATE(0, "dclk_hdmiphy_src_dpll", "dpll", CLK_IGNORE_UNUSED,
254 RV1108_CLKGATE_CON(6), 4, GFLAGS), 443 RV1108_CLKGATE_CON(6), 4, GFLAGS),
255 COMPOSITE_NOGATE(0, "dclk_hdmiphy", mux_dclk_hdmiphy_pre_p, 0, 444 COMPOSITE_NOGATE(0, "dclk_hdmiphy_pre", mux_dclk_hdmiphy_pre_p, 0,
256 RV1108_CLKSEL_CON(32), 6, 2, MFLAGS, 8, 6, DFLAGS), 445 RV1108_CLKSEL_CON(32), 6, 1, MFLAGS, 8, 6, DFLAGS),
446 COMPOSITE_NOGATE(DCLK_VOP_SRC, "dclk_vop_src", mux_dclk_hdmiphy_pre_p, 0,
447 RV1108_CLKSEL_CON(32), 6, 1, MFLAGS, 0, 6, DFLAGS),
448 MUX(DCLK_HDMIPHY, "dclk_hdmiphy", mux_dclk_hdmiphy_p, CLK_SET_RATE_PARENT,
449 RV1108_CLKSEL_CON(32), 15, 1, MFLAGS),
450 MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, CLK_SET_RATE_PARENT,
451 RV1108_CLKSEL_CON(32), 7, 1, MFLAGS),
452 GATE(ACLK_VOP, "aclk_vop", "aclk_vio0_pre", 0,
453 RV1108_CLKGATE_CON(18), 0, GFLAGS),
454 GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0,
455 RV1108_CLKGATE_CON(18), 1, GFLAGS),
456 GATE(ACLK_IEP, "aclk_iep", "aclk_vio0_pre", 0,
457 RV1108_CLKGATE_CON(18), 2, GFLAGS),
458 GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 0,
459 RV1108_CLKGATE_CON(18), 3, GFLAGS),
460
461 GATE(ACLK_RGA, "aclk_rga", "aclk_vio1_pre", 0,
462 RV1108_CLKGATE_CON(18), 4, GFLAGS),
463 GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0,
464 RV1108_CLKGATE_CON(18), 5, GFLAGS),
465 COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_4plls_p, 0,
466 RV1108_CLKSEL_CON(33), 6, 2, MFLAGS, 0, 5, DFLAGS,
467 RV1108_CLKGATE_CON(6), 6, GFLAGS),
468
469 COMPOSITE(SCLK_CVBS_HOST, "sclk_cvbs_host", mux_cvbs_src_p, 0,
470 RV1108_CLKSEL_CON(33), 13, 2, MFLAGS, 8, 5, DFLAGS,
471 RV1108_CLKGATE_CON(6), 7, GFLAGS),
472 FACTOR(0, "sclk_cvbs_27m", "sclk_cvbs_host", 0, 1, 2),
473
474 GATE(SCLK_HDMI_SFR, "sclk_hdmi_sfr", "xin24m", 0,
475 RV1108_CLKGATE_CON(6), 8, GFLAGS),
476
477 COMPOSITE(SCLK_HDMI_CEC, "sclk_hdmi_cec", mux_hdmi_cec_src_p, 0,
478 RV1108_CLKSEL_CON(34), 14, 2, MFLAGS, 0, 14, DFLAGS,
479 RV1108_CLKGATE_CON(6), 9, GFLAGS),
480 GATE(PCLK_MIPI_DSI, "pclk_mipi_dsi", "pclk_vio_pre", 0,
481 RV1108_CLKGATE_CON(18), 8, GFLAGS),
482 GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_vio_pre", 0,
483 RV1108_CLKGATE_CON(18), 9, GFLAGS),
484
485 GATE(ACLK_ISP, "aclk_isp", "aclk_vio1_pre", 0,
486 RV1108_CLKGATE_CON(18), 12, GFLAGS),
487 GATE(HCLK_ISP, "hclk_isp", "hclk_vio_pre", 0,
488 RV1108_CLKGATE_CON(18), 11, GFLAGS),
489 COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_4plls_p, 0,
490 RV1108_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
491 RV1108_CLKGATE_CON(6), 3, GFLAGS),
492
493 GATE(0, "clk_dsiphy24m", "xin24m", CLK_IGNORE_UNUSED,
494 RV1108_CLKGATE_CON(9), 10, GFLAGS),
495 GATE(0, "pclk_vdacphy", "pclk_top_pre", CLK_IGNORE_UNUSED,
496 RV1108_CLKGATE_CON(14), 9, GFLAGS),
497 GATE(0, "pclk_mipi_dsiphy", "pclk_top_pre", CLK_IGNORE_UNUSED,
498 RV1108_CLKGATE_CON(14), 11, GFLAGS),
499 GATE(0, "pclk_mipi_csiphy", "pclk_top_pre", CLK_IGNORE_UNUSED,
500 RV1108_CLKGATE_CON(14), 12, GFLAGS),
257 501
258 /* 502 /*
259 * Clock-Architecture Diagram 5 503 * Clock-Architecture Diagram 5
@@ -261,10 +505,11 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
261 505
262 FACTOR(0, "xin12m", "xin24m", 0, 1, 2), 506 FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
263 507
264 COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0, 508
509 COMPOSITE(SCLK_I2S0_SRC, "i2s0_src", mux_pll_src_2plls_p, 0,
265 RV1108_CLKSEL_CON(5), 8, 1, MFLAGS, 0, 7, DFLAGS, 510 RV1108_CLKSEL_CON(5), 8, 1, MFLAGS, 0, 7, DFLAGS,
266 RV1108_CLKGATE_CON(2), 0, GFLAGS), 511 RV1108_CLKGATE_CON(2), 0, GFLAGS),
267 COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT, 512 COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT,
268 RV1108_CLKSEL_CON(8), 0, 513 RV1108_CLKSEL_CON(8), 0,
269 RV1108_CLKGATE_CON(2), 1, GFLAGS, 514 RV1108_CLKGATE_CON(2), 1, GFLAGS,
270 &rv1108_i2s0_fracmux), 515 &rv1108_i2s0_fracmux),
@@ -274,7 +519,7 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
274 RV1108_CLKSEL_CON(5), 15, 1, MFLAGS, 519 RV1108_CLKSEL_CON(5), 15, 1, MFLAGS,
275 RV1108_CLKGATE_CON(2), 3, GFLAGS), 520 RV1108_CLKGATE_CON(2), 3, GFLAGS),
276 521
277 COMPOSITE(0, "i2s1_src", mux_pll_src_2plls_p, 0, 522 COMPOSITE(SCLK_I2S1_SRC, "i2s1_src", mux_pll_src_2plls_p, 0,
278 RV1108_CLKSEL_CON(6), 8, 1, MFLAGS, 0, 7, DFLAGS, 523 RV1108_CLKSEL_CON(6), 8, 1, MFLAGS, 0, 7, DFLAGS,
279 RV1108_CLKGATE_CON(2), 4, GFLAGS), 524 RV1108_CLKGATE_CON(2), 4, GFLAGS),
280 COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT, 525 COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
@@ -284,7 +529,7 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
284 GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT, 529 GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
285 RV1108_CLKGATE_CON(2), 6, GFLAGS), 530 RV1108_CLKGATE_CON(2), 6, GFLAGS),
286 531
287 COMPOSITE(0, "i2s2_src", mux_pll_src_2plls_p, 0, 532 COMPOSITE(SCLK_I2S2_SRC, "i2s2_src", mux_pll_src_2plls_p, 0,
288 RV1108_CLKSEL_CON(7), 8, 1, MFLAGS, 0, 7, DFLAGS, 533 RV1108_CLKSEL_CON(7), 8, 1, MFLAGS, 0, 7, DFLAGS,
289 RV1108_CLKGATE_CON(3), 8, GFLAGS), 534 RV1108_CLKGATE_CON(3), 8, GFLAGS),
290 COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT, 535 COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT,
@@ -303,32 +548,53 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
303 RV1108_CLKGATE_CON(1), 2, GFLAGS), 548 RV1108_CLKGATE_CON(1), 2, GFLAGS),
304 COMPOSITE_NOGATE(ACLK_PRE, "aclk_bus_pre", mux_aclk_bus_src_p, 0, 549 COMPOSITE_NOGATE(ACLK_PRE, "aclk_bus_pre", mux_aclk_bus_src_p, 0,
305 RV1108_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 5, DFLAGS), 550 RV1108_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 5, DFLAGS),
306 COMPOSITE_NOMUX(0, "hclk_bus_pre", "aclk_bus_2wrap_occ", 0, 551 COMPOSITE_NOMUX(HCLK_BUS, "hclk_bus_pre", "aclk_bus_pre", 0,
307 RV1108_CLKSEL_CON(3), 0, 5, DFLAGS, 552 RV1108_CLKSEL_CON(3), 0, 5, DFLAGS,
308 RV1108_CLKGATE_CON(1), 4, GFLAGS), 553 RV1108_CLKGATE_CON(1), 4, GFLAGS),
309 COMPOSITE_NOMUX(0, "pclken_bus", "aclk_bus_2wrap_occ", 0, 554 COMPOSITE_NOMUX(0, "pclk_bus_pre", "aclk_bus_pre", 0,
310 RV1108_CLKSEL_CON(3), 8, 5, DFLAGS, 555 RV1108_CLKSEL_CON(3), 8, 5, DFLAGS,
311 RV1108_CLKGATE_CON(1), 5, GFLAGS), 556 RV1108_CLKGATE_CON(1), 5, GFLAGS),
312 GATE(0, "pclk_bus_pre", "pclken_bus", CLK_IGNORE_UNUSED, 557 GATE(PCLK_BUS, "pclk_bus", "pclk_bus_pre", 0,
313 RV1108_CLKGATE_CON(1), 6, GFLAGS), 558 RV1108_CLKGATE_CON(1), 6, GFLAGS),
314 GATE(0, "pclk_top_pre", "pclken_bus", CLK_IGNORE_UNUSED, 559 GATE(0, "pclk_top_pre", "pclk_bus_pre", CLK_IGNORE_UNUSED,
315 RV1108_CLKGATE_CON(1), 7, GFLAGS), 560 RV1108_CLKGATE_CON(1), 7, GFLAGS),
316 GATE(0, "pclk_ddr_pre", "pclken_bus", CLK_IGNORE_UNUSED, 561 GATE(0, "pclk_ddr_pre", "pclk_bus_pre", CLK_IGNORE_UNUSED,
317 RV1108_CLKGATE_CON(1), 8, GFLAGS), 562 RV1108_CLKGATE_CON(1), 8, GFLAGS),
318 GATE(0, "clk_timer0", "mux_pll_p", CLK_IGNORE_UNUSED, 563 GATE(SCLK_TIMER0, "clk_timer0", "xin24m", 0,
319 RV1108_CLKGATE_CON(1), 9, GFLAGS), 564 RV1108_CLKGATE_CON(1), 9, GFLAGS),
320 GATE(0, "clk_timer1", "mux_pll_p", CLK_IGNORE_UNUSED, 565 GATE(SCLK_TIMER1, "clk_timer1", "xin24m", CLK_IGNORE_UNUSED,
321 RV1108_CLKGATE_CON(1), 10, GFLAGS), 566 RV1108_CLKGATE_CON(1), 10, GFLAGS),
322 GATE(0, "pclk_timer", "pclk_bus_pre", CLK_IGNORE_UNUSED, 567 GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_pre", CLK_IGNORE_UNUSED,
323 RV1108_CLKGATE_CON(13), 4, GFLAGS), 568 RV1108_CLKGATE_CON(13), 4, GFLAGS),
324 569
325 COMPOSITE(0, "uart0_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED, 570 GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_bus_pre", 0,
571 RV1108_CLKGATE_CON(12), 7, GFLAGS),
572 GATE(HCLK_I2S1_2CH, "hclk_i2s1_2ch", "hclk_bus_pre", 0,
573 RV1108_CLKGATE_CON(12), 8, GFLAGS),
574 GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_bus_pre", 0,
575 RV1108_CLKGATE_CON(12), 9, GFLAGS),
576
577 GATE(HCLK_CRYPTO_MST, "hclk_crypto_mst", "hclk_bus_pre", 0,
578 RV1108_CLKGATE_CON(12), 10, GFLAGS),
579 GATE(HCLK_CRYPTO_SLV, "hclk_crypto_slv", "hclk_bus_pre", 0,
580 RV1108_CLKGATE_CON(12), 11, GFLAGS),
581 COMPOSITE(SCLK_CRYPTO, "sclk_crypto", mux_pll_src_2plls_p, 0,
582 RV1108_CLKSEL_CON(11), 7, 1, MFLAGS, 0, 5, DFLAGS,
583 RV1108_CLKGATE_CON(2), 12, GFLAGS),
584
585 COMPOSITE(SCLK_SPI, "sclk_spi", mux_pll_src_2plls_p, 0,
586 RV1108_CLKSEL_CON(11), 15, 1, MFLAGS, 8, 5, DFLAGS,
587 RV1108_CLKGATE_CON(3), 0, GFLAGS),
588 GATE(PCLK_SPI, "pclk_spi", "pclk_bus_pre", 0,
589 RV1108_CLKGATE_CON(13), 5, GFLAGS),
590
591 COMPOSITE(SCLK_UART0_SRC, "uart0_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
326 RV1108_CLKSEL_CON(13), 12, 2, MFLAGS, 0, 7, DFLAGS, 592 RV1108_CLKSEL_CON(13), 12, 2, MFLAGS, 0, 7, DFLAGS,
327 RV1108_CLKGATE_CON(3), 1, GFLAGS), 593 RV1108_CLKGATE_CON(3), 1, GFLAGS),
328 COMPOSITE(0, "uart1_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED, 594 COMPOSITE(SCLK_UART1_SRC, "uart1_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
329 RV1108_CLKSEL_CON(14), 12, 2, MFLAGS, 0, 7, DFLAGS, 595 RV1108_CLKSEL_CON(14), 12, 2, MFLAGS, 0, 7, DFLAGS,
330 RV1108_CLKGATE_CON(3), 3, GFLAGS), 596 RV1108_CLKGATE_CON(3), 3, GFLAGS),
331 COMPOSITE(0, "uart21_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED, 597 COMPOSITE(SCLK_UART2_SRC, "uart2_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
332 RV1108_CLKSEL_CON(15), 12, 2, MFLAGS, 0, 7, DFLAGS, 598 RV1108_CLKSEL_CON(15), 12, 2, MFLAGS, 0, 7, DFLAGS,
333 RV1108_CLKGATE_CON(3), 5, GFLAGS), 599 RV1108_CLKGATE_CON(3), 5, GFLAGS),
334 600
@@ -344,44 +610,58 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
344 RV1108_CLKSEL_CON(18), 0, 610 RV1108_CLKSEL_CON(18), 0,
345 RV1108_CLKGATE_CON(3), 6, GFLAGS, 611 RV1108_CLKGATE_CON(3), 6, GFLAGS,
346 &rv1108_uart2_fracmux), 612 &rv1108_uart2_fracmux),
347 GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_pre", CLK_IGNORE_UNUSED, 613 GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_pre", 0,
348 RV1108_CLKGATE_CON(13), 10, GFLAGS), 614 RV1108_CLKGATE_CON(13), 10, GFLAGS),
349 GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", CLK_IGNORE_UNUSED, 615 GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", 0,
350 RV1108_CLKGATE_CON(13), 11, GFLAGS), 616 RV1108_CLKGATE_CON(13), 11, GFLAGS),
351 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_pre", CLK_IGNORE_UNUSED, 617 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_pre", 0,
352 RV1108_CLKGATE_CON(13), 12, GFLAGS), 618 RV1108_CLKGATE_CON(13), 12, GFLAGS),
353 619
354 COMPOSITE(0, "clk_i2c1", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED, 620 COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_pll_src_2plls_p, 0,
355 RV1108_CLKSEL_CON(19), 15, 2, MFLAGS, 8, 7, DFLAGS, 621 RV1108_CLKSEL_CON(19), 15, 1, MFLAGS, 8, 7, DFLAGS,
356 RV1108_CLKGATE_CON(3), 7, GFLAGS), 622 RV1108_CLKGATE_CON(3), 7, GFLAGS),
357 COMPOSITE(0, "clk_i2c2", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED, 623 COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_pll_src_2plls_p, 0,
358 RV1108_CLKSEL_CON(20), 7, 2, MFLAGS, 0, 7, DFLAGS, 624 RV1108_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 7, DFLAGS,
359 RV1108_CLKGATE_CON(3), 8, GFLAGS), 625 RV1108_CLKGATE_CON(3), 8, GFLAGS),
360 COMPOSITE(0, "clk_i2c3", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED, 626 COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_pll_src_2plls_p, 0,
361 RV1108_CLKSEL_CON(20), 15, 2, MFLAGS, 8, 7, DFLAGS, 627 RV1108_CLKSEL_CON(20), 15, 1, MFLAGS, 8, 7, DFLAGS,
362 RV1108_CLKGATE_CON(3), 9, GFLAGS), 628 RV1108_CLKGATE_CON(3), 9, GFLAGS),
363 GATE(0, "pclk_i2c1", "pclk_bus_pre", CLK_IGNORE_UNUSED, 629 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus_pre", 0,
364 RV1108_CLKGATE_CON(13), 0, GFLAGS), 630 RV1108_CLKGATE_CON(13), 0, GFLAGS),
365 GATE(0, "pclk_i2c2", "pclk_bus_pre", CLK_IGNORE_UNUSED, 631 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus_pre", 0,
366 RV1108_CLKGATE_CON(13), 1, GFLAGS), 632 RV1108_CLKGATE_CON(13), 1, GFLAGS),
367 GATE(0, "pclk_i2c3", "pclk_bus_pre", CLK_IGNORE_UNUSED, 633 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus_pre", 0,
368 RV1108_CLKGATE_CON(13), 2, GFLAGS), 634 RV1108_CLKGATE_CON(13), 2, GFLAGS),
369 COMPOSITE(0, "clk_pwm1", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED, 635 COMPOSITE(SCLK_PWM, "clk_pwm", mux_pll_src_2plls_p, 0,
370 RV1108_CLKSEL_CON(12), 15, 2, MFLAGS, 8, 7, DFLAGS, 636 RV1108_CLKSEL_CON(12), 15, 2, MFLAGS, 8, 7, DFLAGS,
371 RV1108_CLKGATE_CON(3), 10, GFLAGS), 637 RV1108_CLKGATE_CON(3), 10, GFLAGS),
372 GATE(0, "pclk_pwm1", "pclk_bus_pre", CLK_IGNORE_UNUSED, 638 GATE(PCLK_PWM, "pclk_pwm", "pclk_bus_pre", 0,
373 RV1108_CLKGATE_CON(13), 6, GFLAGS), 639 RV1108_CLKGATE_CON(13), 6, GFLAGS),
374 GATE(0, "pclk_wdt", "pclk_bus_pre", CLK_IGNORE_UNUSED, 640 GATE(PCLK_WDT, "pclk_wdt", "pclk_bus_pre", 0,
375 RV1108_CLKGATE_CON(13), 3, GFLAGS), 641 RV1108_CLKGATE_CON(13), 3, GFLAGS),
376 GATE(0, "pclk_gpio1", "pclk_bus_pre", CLK_IGNORE_UNUSED, 642 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus_pre", 0,
377 RV1108_CLKGATE_CON(13), 7, GFLAGS), 643 RV1108_CLKGATE_CON(13), 7, GFLAGS),
378 GATE(0, "pclk_gpio2", "pclk_bus_pre", CLK_IGNORE_UNUSED, 644 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus_pre", 0,
379 RV1108_CLKGATE_CON(13), 8, GFLAGS), 645 RV1108_CLKGATE_CON(13), 8, GFLAGS),
380 GATE(0, "pclk_gpio3", "pclk_bus_pre", CLK_IGNORE_UNUSED, 646 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus_pre", 0,
381 RV1108_CLKGATE_CON(13), 9, GFLAGS), 647 RV1108_CLKGATE_CON(13), 9, GFLAGS),
382 648
383 GATE(0, "pclk_grf", "pclk_bus_pre", CLK_IGNORE_UNUSED, 649 GATE(0, "pclk_grf", "pclk_bus_pre", CLK_IGNORE_UNUSED,
384 RV1108_CLKGATE_CON(14), 0, GFLAGS), 650 RV1108_CLKGATE_CON(14), 0, GFLAGS),
651 GATE(PCLK_EFUSE0, "pclk_efuse0", "pclk_bus_pre", 0,
652 RV1108_CLKGATE_CON(12), 12, GFLAGS),
653 GATE(PCLK_EFUSE1, "pclk_efuse1", "pclk_bus_pre", 0,
654 RV1108_CLKGATE_CON(12), 13, GFLAGS),
655 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus_pre", 0,
656 RV1108_CLKGATE_CON(13), 13, GFLAGS),
657 COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin24m", 0,
658 RV1108_CLKSEL_CON(21), 0, 10, DFLAGS,
659 RV1108_CLKGATE_CON(3), 11, GFLAGS),
660 GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus_pre", 0,
661 RV1108_CLKGATE_CON(13), 14, GFLAGS),
662 COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
663 RV1108_CLKSEL_CON(22), 0, 10, DFLAGS,
664 RV1108_CLKGATE_CON(3), 12, GFLAGS),
385 665
386 GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_pre", 0, 666 GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_pre", 0,
387 RV1108_CLKGATE_CON(12), 2, GFLAGS), 667 RV1108_CLKGATE_CON(12), 2, GFLAGS),
@@ -397,18 +677,24 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
397 RV1108_CLKGATE_CON(0), 9, GFLAGS), 677 RV1108_CLKGATE_CON(0), 9, GFLAGS),
398 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED, 678 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
399 RV1108_CLKGATE_CON(0), 10, GFLAGS), 679 RV1108_CLKGATE_CON(0), 10, GFLAGS),
400 COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED, 680 COMPOSITE_NOGATE(0, "clk_ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED,
401 RV1108_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 3, 681 RV1108_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 3,
402 DFLAGS | CLK_DIVIDER_POWER_OF_TWO, 682 DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
683 FACTOR(0, "clk_ddr", "clk_ddrphy_src", 0, 1, 2),
684 GATE(0, "clk_ddrphy4x", "clk_ddr", CLK_IGNORE_UNUSED,
403 RV1108_CLKGATE_CON(10), 9, GFLAGS), 685 RV1108_CLKGATE_CON(10), 9, GFLAGS),
404 GATE(0, "ddrupctl", "ddrphy_pre", CLK_IGNORE_UNUSED, 686 GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", CLK_IGNORE_UNUSED,
405 RV1108_CLKGATE_CON(12), 4, GFLAGS), 687 RV1108_CLKGATE_CON(12), 4, GFLAGS),
406 GATE(0, "ddrc", "ddrphy", CLK_IGNORE_UNUSED, 688 GATE(0, "nclk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED,
407 RV1108_CLKGATE_CON(12), 5, GFLAGS), 689 RV1108_CLKGATE_CON(12), 5, GFLAGS),
408 GATE(0, "ddrmon", "ddrphy_pre", CLK_IGNORE_UNUSED, 690 GATE(0, "pclk_ddrmon", "pclk_ddr_pre", CLK_IGNORE_UNUSED,
409 RV1108_CLKGATE_CON(12), 6, GFLAGS), 691 RV1108_CLKGATE_CON(12), 6, GFLAGS),
410 GATE(0, "timer_clk", "xin24m", CLK_IGNORE_UNUSED, 692 GATE(0, "timer_clk", "xin24m", CLK_IGNORE_UNUSED,
411 RV1108_CLKGATE_CON(0), 11, GFLAGS), 693 RV1108_CLKGATE_CON(0), 11, GFLAGS),
694 GATE(0, "pclk_mschniu", "pclk_ddr_pre", CLK_IGNORE_UNUSED,
695 RV1108_CLKGATE_CON(14), 2, GFLAGS),
696 GATE(0, "pclk_ddrphy", "pclk_ddr_pre", CLK_IGNORE_UNUSED,
697 RV1108_CLKGATE_CON(14), 4, GFLAGS),
412 698
413 /* 699 /*
414 * Clock-Architecture Diagram 6 700 * Clock-Architecture Diagram 6
@@ -418,23 +704,23 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
418 COMPOSITE_NOMUX(0, "pclk_periph_pre", "gpll", 0, 704 COMPOSITE_NOMUX(0, "pclk_periph_pre", "gpll", 0,
419 RV1108_CLKSEL_CON(23), 10, 5, DFLAGS, 705 RV1108_CLKSEL_CON(23), 10, 5, DFLAGS,
420 RV1108_CLKGATE_CON(4), 5, GFLAGS), 706 RV1108_CLKGATE_CON(4), 5, GFLAGS),
421 GATE(0, "pclk_periph", "pclk_periph_pre", CLK_IGNORE_UNUSED, 707 GATE(PCLK_PERI, "pclk_periph", "pclk_periph_pre", CLK_IGNORE_UNUSED,
422 RV1108_CLKGATE_CON(15), 13, GFLAGS), 708 RV1108_CLKGATE_CON(15), 13, GFLAGS),
423 COMPOSITE_NOMUX(0, "hclk_periph_pre", "gpll", 0, 709 COMPOSITE_NOMUX(0, "hclk_periph_pre", "gpll", 0,
424 RV1108_CLKSEL_CON(23), 5, 5, DFLAGS, 710 RV1108_CLKSEL_CON(23), 5, 5, DFLAGS,
425 RV1108_CLKGATE_CON(4), 4, GFLAGS), 711 RV1108_CLKGATE_CON(4), 4, GFLAGS),
426 GATE(0, "hclk_periph", "hclk_periph_pre", CLK_IGNORE_UNUSED, 712 GATE(HCLK_PERI, "hclk_periph", "hclk_periph_pre", CLK_IGNORE_UNUSED,
427 RV1108_CLKGATE_CON(15), 12, GFLAGS), 713 RV1108_CLKGATE_CON(15), 12, GFLAGS),
428 714
429 GATE(0, "aclk_peri_src_dpll", "dpll", CLK_IGNORE_UNUSED, 715 GATE(0, "aclk_peri_src_dpll", "dpll", CLK_IGNORE_UNUSED,
430 RV1108_CLKGATE_CON(4), 1, GFLAGS), 716 RV1108_CLKGATE_CON(4), 1, GFLAGS),
431 GATE(0, "aclk_peri_src_gpll", "gpll", CLK_IGNORE_UNUSED, 717 GATE(0, "aclk_peri_src_gpll", "gpll", CLK_IGNORE_UNUSED,
432 RV1108_CLKGATE_CON(4), 2, GFLAGS), 718 RV1108_CLKGATE_CON(4), 2, GFLAGS),
433 COMPOSITE(0, "aclk_periph", mux_aclk_peri_src_p, CLK_IGNORE_UNUSED, 719 COMPOSITE(ACLK_PERI, "aclk_periph", mux_aclk_peri_src_p, 0,
434 RV1108_CLKSEL_CON(23), 15, 2, MFLAGS, 0, 5, DFLAGS, 720 RV1108_CLKSEL_CON(23), 15, 1, MFLAGS, 0, 5, DFLAGS,
435 RV1108_CLKGATE_CON(15), 11, GFLAGS), 721 RV1108_CLKGATE_CON(15), 11, GFLAGS),
436 722
437 COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0, 723 COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
438 RV1108_CLKSEL_CON(25), 8, 2, MFLAGS, 0, 8, DFLAGS, 724 RV1108_CLKSEL_CON(25), 8, 2, MFLAGS, 0, 8, DFLAGS,
439 RV1108_CLKGATE_CON(5), 0, GFLAGS), 725 RV1108_CLKGATE_CON(5), 0, GFLAGS),
440 726
@@ -454,23 +740,31 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
454 GATE(HCLK_EMMC, "hclk_emmc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 2, GFLAGS), 740 GATE(HCLK_EMMC, "hclk_emmc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 2, GFLAGS),
455 741
456 COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0, 742 COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0,
457 RV1108_CLKSEL_CON(27), 14, 2, MFLAGS, 8, 5, DFLAGS, 743 RV1108_CLKSEL_CON(27), 14, 1, MFLAGS, 8, 5, DFLAGS,
458 RV1108_CLKGATE_CON(5), 3, GFLAGS), 744 RV1108_CLKGATE_CON(5), 3, GFLAGS),
459 GATE(HCLK_NANDC, "hclk_nandc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 3, GFLAGS), 745 GATE(HCLK_NANDC, "hclk_nandc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 3, GFLAGS),
460 746
747 GATE(HCLK_HOST0, "hclk_host0", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 6, GFLAGS),
748 GATE(0, "hclk_host0_arb", "hclk_periph", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(15), 7, GFLAGS),
749 GATE(HCLK_OTG, "hclk_otg", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 8, GFLAGS),
750 GATE(0, "hclk_otg_pmu", "hclk_periph", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(15), 9, GFLAGS),
751 GATE(SCLK_USBPHY, "clk_usbphy", "xin24m", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(5), 5, GFLAGS),
752
461 COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_2plls_p, 0, 753 COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_2plls_p, 0,
462 RV1108_CLKSEL_CON(27), 7, 2, MFLAGS, 0, 7, DFLAGS, 754 RV1108_CLKSEL_CON(27), 7, 1, MFLAGS, 0, 7, DFLAGS,
463 RV1108_CLKGATE_CON(5), 4, GFLAGS), 755 RV1108_CLKGATE_CON(5), 4, GFLAGS),
464 GATE(HCLK_SFC, "hclk_sfc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 10, GFLAGS), 756 GATE(HCLK_SFC, "hclk_sfc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 10, GFLAGS),
465 757
466 COMPOSITE(0, "sclk_macphy_pre", mux_pll_src_apll_gpll_p, 0, 758 COMPOSITE(SCLK_MAC_PRE, "sclk_mac_pre", mux_pll_src_apll_gpll_p, 0,
467 RV1108_CLKSEL_CON(24), 12, 2, MFLAGS, 0, 5, DFLAGS, 759 RV1108_CLKSEL_CON(24), 12, 1, MFLAGS, 0, 5, DFLAGS,
468 RV1108_CLKGATE_CON(4), 10, GFLAGS), 760 RV1108_CLKGATE_CON(4), 10, GFLAGS),
469 MUX(0, "sclk_macphy", mux_sclk_macphy_p, CLK_SET_RATE_PARENT, 761 MUX(SCLK_MAC, "sclk_mac", mux_sclk_mac_p, CLK_SET_RATE_PARENT,
470 RV1108_CLKSEL_CON(24), 8, 2, MFLAGS), 762 RV1108_CLKSEL_CON(24), 8, 1, MFLAGS),
471 GATE(0, "sclk_macphy_rx", "sclk_macphy", 0, RV1108_CLKGATE_CON(4), 8, GFLAGS), 763 GATE(SCLK_MAC_RX, "sclk_mac_rx", "sclk_mac", 0, RV1108_CLKGATE_CON(4), 8, GFLAGS),
472 GATE(0, "sclk_mac_ref", "sclk_macphy", 0, RV1108_CLKGATE_CON(4), 6, GFLAGS), 764 GATE(SCLK_MAC_REF, "sclk_mac_ref", "sclk_mac", 0, RV1108_CLKGATE_CON(4), 6, GFLAGS),
473 GATE(0, "sclk_mac_refout", "sclk_macphy", 0, RV1108_CLKGATE_CON(4), 7, GFLAGS), 765 GATE(SCLK_MAC_REFOUT, "sclk_mac_refout", "sclk_mac", 0, RV1108_CLKGATE_CON(4), 7, GFLAGS),
766 GATE(ACLK_GMAC, "aclk_gmac", "aclk_periph", 0, RV1108_CLKGATE_CON(15), 4, GFLAGS),
767 GATE(PCLK_GMAC, "pclk_gmac", "pclk_periph", 0, RV1108_CLKGATE_CON(15), 5, GFLAGS),
474 768
475 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RV1108_SDMMC_CON0, 1), 769 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RV1108_SDMMC_CON0, 1),
476 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RV1108_SDMMC_CON1, 1), 770 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RV1108_SDMMC_CON1, 1),
@@ -484,10 +778,16 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
484 778
485static const char *const rv1108_critical_clocks[] __initconst = { 779static const char *const rv1108_critical_clocks[] __initconst = {
486 "aclk_core", 780 "aclk_core",
487 "aclk_bus_src_gpll", 781 "aclk_bus",
782 "hclk_bus",
783 "pclk_bus",
488 "aclk_periph", 784 "aclk_periph",
489 "hclk_periph", 785 "hclk_periph",
490 "pclk_periph", 786 "pclk_periph",
787 "nclk_ddrupctl",
788 "pclk_ddrmon",
789 "pclk_acodecphy",
790 "pclk_pmu",
491}; 791};
492 792
493static void __init rv1108_clk_init(struct device_node *np) 793static void __init rv1108_clk_init(struct device_node *np)
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index fe1d393cf678..b6db79a00602 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -29,6 +29,7 @@
29#include <linux/mfd/syscon.h> 29#include <linux/mfd/syscon.h>
30#include <linux/regmap.h> 30#include <linux/regmap.h>
31#include <linux/reboot.h> 31#include <linux/reboot.h>
32#include <linux/rational.h>
32#include "clk.h" 33#include "clk.h"
33 34
34/** 35/**
@@ -164,6 +165,40 @@ static int rockchip_clk_frac_notifier_cb(struct notifier_block *nb,
164 return notifier_from_errno(ret); 165 return notifier_from_errno(ret);
165} 166}
166 167
168/**
169 * fractional divider must set that denominator is 20 times larger than
170 * numerator to generate precise clock frequency.
171 */
172void rockchip_fractional_approximation(struct clk_hw *hw,
173 unsigned long rate, unsigned long *parent_rate,
174 unsigned long *m, unsigned long *n)
175{
176 struct clk_fractional_divider *fd = to_clk_fd(hw);
177 unsigned long p_rate, p_parent_rate;
178 struct clk_hw *p_parent;
179 unsigned long scale;
180
181 p_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
182 if ((rate * 20 > p_rate) && (p_rate % rate != 0)) {
183 p_parent = clk_hw_get_parent(clk_hw_get_parent(hw));
184 p_parent_rate = clk_hw_get_rate(p_parent);
185 *parent_rate = p_parent_rate;
186 }
187
188 /*
189 * Get rate closer to *parent_rate to guarantee there is no overflow
190 * for m and n. In the result it will be the nearest rate left shifted
191 * by (scale - fd->nwidth) bits.
192 */
193 scale = fls_long(*parent_rate / rate - 1);
194 if (scale > fd->nwidth)
195 rate <<= scale - fd->nwidth;
196
197 rational_best_approximation(rate, *parent_rate,
198 GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
199 m, n);
200}
201
167static struct clk *rockchip_clk_register_frac_branch( 202static struct clk *rockchip_clk_register_frac_branch(
168 struct rockchip_clk_provider *ctx, const char *name, 203 struct rockchip_clk_provider *ctx, const char *name,
169 const char *const *parent_names, u8 num_parents, 204 const char *const *parent_names, u8 num_parents,
@@ -210,6 +245,7 @@ static struct clk *rockchip_clk_register_frac_branch(
210 div->nwidth = 16; 245 div->nwidth = 16;
211 div->nmask = GENMASK(div->nwidth - 1, 0) << div->nshift; 246 div->nmask = GENMASK(div->nwidth - 1, 0) << div->nshift;
212 div->lock = lock; 247 div->lock = lock;
248 div->approximation = rockchip_fractional_approximation;
213 div_ops = &clk_fractional_divider_ops; 249 div_ops = &clk_fractional_divider_ops;
214 250
215 clk = clk_register_composite(NULL, name, parent_names, num_parents, 251 clk = clk_register_composite(NULL, name, parent_names, num_parents,
diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h
index 56f841c22801..55655ab0a4c4 100644
--- a/include/dt-bindings/clock/rk3228-cru.h
+++ b/include/dt-bindings/clock/rk3228-cru.h
@@ -49,6 +49,7 @@
49#define SCLK_EMMC_DRV 117 49#define SCLK_EMMC_DRV 117
50#define SCLK_SDMMC_SAMPLE 118 50#define SCLK_SDMMC_SAMPLE 118
51#define SCLK_SDIO_SAMPLE 119 51#define SCLK_SDIO_SAMPLE 119
52#define SCLK_SDIO_SRC 120
52#define SCLK_EMMC_SAMPLE 121 53#define SCLK_EMMC_SAMPLE 121
53#define SCLK_VOP 122 54#define SCLK_VOP 122
54#define SCLK_HDMI_HDCP 123 55#define SCLK_HDMI_HDCP 123
diff --git a/include/dt-bindings/clock/rv1108-cru.h b/include/dt-bindings/clock/rv1108-cru.h
index ae26f8105914..d8d0e0456dc2 100644
--- a/include/dt-bindings/clock/rv1108-cru.h
+++ b/include/dt-bindings/clock/rv1108-cru.h
@@ -43,12 +43,74 @@
43#define SCLK_SDMMC_SAMPLE 84 43#define SCLK_SDMMC_SAMPLE 84
44#define SCLK_SDIO_SAMPLE 85 44#define SCLK_SDIO_SAMPLE 85
45#define SCLK_EMMC_SAMPLE 86 45#define SCLK_EMMC_SAMPLE 86
46#define SCLK_VENC_CORE 87
47#define SCLK_HEVC_CORE 88
48#define SCLK_HEVC_CABAC 89
49#define SCLK_PWM0_PMU 90
50#define SCLK_I2C0_PMU 91
51#define SCLK_WIFI 92
52#define SCLK_CIFOUT 93
53#define SCLK_MIPI_CSI_OUT 94
54#define SCLK_CIF0 95
55#define SCLK_CIF1 96
56#define SCLK_CIF2 97
57#define SCLK_CIF3 98
58#define SCLK_DSP 99
59#define SCLK_DSP_IOP 100
60#define SCLK_DSP_EPP 101
61#define SCLK_DSP_EDP 102
62#define SCLK_DSP_EDAP 103
63#define SCLK_CVBS_HOST 104
64#define SCLK_HDMI_SFR 105
65#define SCLK_HDMI_CEC 106
66#define SCLK_CRYPTO 107
67#define SCLK_SPI 108
68#define SCLK_SARADC 109
69#define SCLK_TSADC 110
70#define SCLK_MAC_PRE 111
71#define SCLK_MAC 112
72#define SCLK_MAC_RX 113
73#define SCLK_MAC_REF 114
74#define SCLK_MAC_REFOUT 115
75#define SCLK_DSP_PFM 116
76#define SCLK_RGA 117
77#define SCLK_I2C1 118
78#define SCLK_I2C2 119
79#define SCLK_I2C3 120
80#define SCLK_PWM 121
81#define SCLK_ISP 122
82#define SCLK_USBPHY 123
83#define SCLK_I2S0_SRC 124
84#define SCLK_I2S1_SRC 125
85#define SCLK_I2S2_SRC 126
86#define SCLK_UART0_SRC 127
87#define SCLK_UART1_SRC 128
88#define SCLK_UART2_SRC 129
89
90#define DCLK_VOP_SRC 185
91#define DCLK_HDMIPHY 186
92#define DCLK_VOP 187
46 93
47/* aclk gates */ 94/* aclk gates */
48#define ACLK_DMAC 192 95#define ACLK_DMAC 192
49#define ACLK_PRE 193 96#define ACLK_PRE 193
50#define ACLK_CORE 194 97#define ACLK_CORE 194
51#define ACLK_ENMCORE 195 98#define ACLK_ENMCORE 195
99#define ACLK_RKVENC 196
100#define ACLK_RKVDEC 197
101#define ACLK_VPU 198
102#define ACLK_CIF0 199
103#define ACLK_VIO0 200
104#define ACLK_VIO1 201
105#define ACLK_VOP 202
106#define ACLK_IEP 203
107#define ACLK_RGA 204
108#define ACLK_ISP 205
109#define ACLK_CIF1 206
110#define ACLK_CIF2 207
111#define ACLK_CIF3 208
112#define ACLK_PERI 209
113#define ACLK_GMAC 210
52 114
53/* pclk gates */ 115/* pclk gates */
54#define PCLK_GPIO1 256 116#define PCLK_GPIO1 256
@@ -67,10 +129,24 @@
67#define PCLK_PWM 269 129#define PCLK_PWM 269
68#define PCLK_TIMER 270 130#define PCLK_TIMER 270
69#define PCLK_PERI 271 131#define PCLK_PERI 271
132#define PCLK_GPIO0_PMU 272
133#define PCLK_I2C0_PMU 273
134#define PCLK_PWM0_PMU 274
135#define PCLK_ISP 275
136#define PCLK_VIO 276
137#define PCLK_MIPI_DSI 277
138#define PCLK_HDMI_CTRL 278
139#define PCLK_SARADC 279
140#define PCLK_DSP_CFG 280
141#define PCLK_BUS 281
142#define PCLK_EFUSE0 282
143#define PCLK_EFUSE1 283
144#define PCLK_WDT 284
145#define PCLK_GMAC 285
70 146
71/* hclk gates */ 147/* hclk gates */
72#define HCLK_I2S0_8CH 320 148#define HCLK_I2S0_8CH 320
73#define HCLK_I2S1_8CH 321 149#define HCLK_I2S1_2CH 321
74#define HCLK_I2S2_2CH 322 150#define HCLK_I2S2_2CH 322
75#define HCLK_NANDC 323 151#define HCLK_NANDC 323
76#define HCLK_SDMMC 324 152#define HCLK_SDMMC 324
@@ -78,20 +154,37 @@
78#define HCLK_EMMC 326 154#define HCLK_EMMC 326
79#define HCLK_PERI 327 155#define HCLK_PERI 327
80#define HCLK_SFC 328 156#define HCLK_SFC 328
157#define HCLK_RKVENC 329
158#define HCLK_RKVDEC 330
159#define HCLK_CIF0 331
160#define HCLK_VIO 332
161#define HCLK_VOP 333
162#define HCLK_IEP 334
163#define HCLK_RGA 335
164#define HCLK_ISP 336
165#define HCLK_CRYPTO_MST 337
166#define HCLK_CRYPTO_SLV 338
167#define HCLK_HOST0 339
168#define HCLK_OTG 340
169#define HCLK_CIF1 341
170#define HCLK_CIF2 342
171#define HCLK_CIF3 343
172#define HCLK_BUS 344
173#define HCLK_VPU 345
81 174
82#define CLK_NR_CLKS (HCLK_SFC + 1) 175#define CLK_NR_CLKS (HCLK_VPU + 1)
83 176
84/* reset id */ 177/* reset id */
85#define SRST_CORE_PO_AD 0 178#define SRST_CORE_PO_AD 0
86#define SRST_CORE_AD 1 179#define SRST_CORE_AD 1
87#define SRST_L2_AD 2 180#define SRST_L2_AD 2
88#define SRST_CPU_NIU_AD 3 181#define SRST_CPU_NIU_AD 3
89#define SRST_CORE_PO 4 182#define SRST_CORE_PO 4
90#define SRST_CORE 5 183#define SRST_CORE 5
91#define SRST_L2 6 184#define SRST_L2 6
92#define SRST_CORE_DBG 8 185#define SRST_CORE_DBG 8
93#define PRST_DBG 9 186#define PRST_DBG 9
94#define RST_DAP 10 187#define RST_DAP 10
95#define PRST_DBG_NIU 11 188#define PRST_DBG_NIU 11
96#define ARST_STRC_SYS_AD 15 189#define ARST_STRC_SYS_AD 15
97 190
@@ -158,9 +251,9 @@
158#define HRST_SYSBUS 75 251#define HRST_SYSBUS 75
159#define PRST_USBGRF 76 252#define PRST_USBGRF 76
160 253
161#define ARST_PERIPH_NIU 80 254#define ARST_PERIPH_NIU 80
162#define HRST_PERIPH_NIU 81 255#define HRST_PERIPH_NIU 81
163#define PRST_PERIPH_NIU 82 256#define PRST_PERIPH_NIU 82
164#define HRST_PERIPH 83 257#define HRST_PERIPH 83
165#define HRST_SDMMC 84 258#define HRST_SDMMC 84
166#define HRST_SDIO 85 259#define HRST_SDIO 85
@@ -178,7 +271,7 @@
178#define HRST_HOST0_AUX 96 271#define HRST_HOST0_AUX 96
179#define HRST_HOST0_ARB 97 272#define HRST_HOST0_ARB 97
180#define SRST_HOST0_EHCIPHY 98 273#define SRST_HOST0_EHCIPHY 98
181#define SRST_HOST0_UTMI 99 274#define SRST_HOST0_UTMI 99
182#define SRST_USBPOR 100 275#define SRST_USBPOR 100
183#define SRST_UTMI0 101 276#define SRST_UTMI0 101
184#define SRST_UTMI1 102 277#define SRST_UTMI1 102
@@ -225,21 +318,21 @@
225#define HRST_VPU_NIU 141 318#define HRST_VPU_NIU 141
226#define ARST_VPU 142 319#define ARST_VPU 142
227#define HRST_VPU 143 320#define HRST_VPU 143
228#define ARST_RKVDEC_NIU 144 321#define ARST_RKVDEC_NIU 144
229#define HRST_RKVDEC_NIU 145 322#define HRST_RKVDEC_NIU 145
230#define ARST_RKVDEC 146 323#define ARST_RKVDEC 146
231#define HRST_RKVDEC 147 324#define HRST_RKVDEC 147
232#define SRST_RKVDEC_CABAC 148 325#define SRST_RKVDEC_CABAC 148
233#define SRST_RKVDEC_CORE 149 326#define SRST_RKVDEC_CORE 149
234#define ARST_RKVENC_NIU 150 327#define ARST_RKVENC_NIU 150
235#define HRST_RKVENC_NIU 151 328#define HRST_RKVENC_NIU 151
236#define ARST_RKVENC 152 329#define ARST_RKVENC 152
237#define HRST_RKVENC 153 330#define HRST_RKVENC 153
238#define SRST_RKVENC_CORE 154 331#define SRST_RKVENC_CORE 154
239 332
240#define SRST_DSP_CORE 156 333#define SRST_DSP_CORE 156
241#define SRST_DSP_SYS 157 334#define SRST_DSP_SYS 157
242#define SRST_DSP_GLOBAL 158 335#define SRST_DSP_GLOBAL 158
243#define SRST_DSP_OECM 159 336#define SRST_DSP_OECM 159
244#define PRST_DSP_IOP_NIU 160 337#define PRST_DSP_IOP_NIU 160
245#define ARST_DSP_EPP_NIU 161 338#define ARST_DSP_EPP_NIU 161
@@ -257,7 +350,7 @@
257#define SRST_PMU_I2C0 173 350#define SRST_PMU_I2C0 173
258#define PRST_PMU_I2C0 174 351#define PRST_PMU_I2C0 174
259#define PRST_PMU_GPIO0 175 352#define PRST_PMU_GPIO0 175
260#define PRST_PMU_INTMEM 176 353#define PRST_PMU_INTMEM 176
261#define PRST_PMU_PWM0 177 354#define PRST_PMU_PWM0 177
262#define SRST_PMU_PWM0 178 355#define SRST_PMU_PWM0 178
263#define PRST_PMU_GRF 179 356#define PRST_PMU_GRF 179
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index c59c62571e4f..1fc113fbf955 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -565,6 +565,9 @@ struct clk_fractional_divider {
565 u8 nwidth; 565 u8 nwidth;
566 u32 nmask; 566 u32 nmask;
567 u8 flags; 567 u8 flags;
568 void (*approximation)(struct clk_hw *hw,
569 unsigned long rate, unsigned long *parent_rate,
570 unsigned long *m, unsigned long *n);
568 spinlock_t *lock; 571 spinlock_t *lock;
569}; 572};
570 573
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-24 13:50:20 -0400