diff options
author | Stephen Warren <swarren@nvidia.com> | 2016-07-25 17:02:21 -0400 |
---|---|---|
committer | Bjorn Helgaas <bhelgaas@google.com> | 2016-07-26 15:57:04 -0400 |
commit | cf5d31801278be39bd2cc28a8cf582398e58402a (patch) | |
tree | 7457f514e90545e8aba266f44561202769ef555c | |
parent | 08203f1fac4d2c3cfab43fd157c76127f48bc5b3 (diff) |
PCI: tegra: Program PADS_REFCLK_CFG* always, not just on legacy SoCs
tegra_pcie_phy_power_on() calls tegra_pcie_phy_enable() only for legacy
SoCs. However, part of tegra_pcie_phy_enable() needs to happen in all
cases. Move that code up one level into tegra_pcie_phy_power_on().
[bhelgaas: changelog]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
-rw-r--r-- | drivers/pci/host/pci-tegra.c | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index bbf77a49517d..8cac1a07077b 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c | |||
@@ -838,12 +838,6 @@ static int tegra_pcie_phy_enable(struct tegra_pcie *pcie) | |||
838 | value |= PADS_PLL_CTL_RST_B4SM; | 838 | value |= PADS_PLL_CTL_RST_B4SM; |
839 | pads_writel(pcie, value, soc->pads_pll_ctl); | 839 | pads_writel(pcie, value, soc->pads_pll_ctl); |
840 | 840 | ||
841 | /* Configure the reference clock driver */ | ||
842 | value = PADS_REFCLK_CFG_VALUE | (PADS_REFCLK_CFG_VALUE << 16); | ||
843 | pads_writel(pcie, value, PADS_REFCLK_CFG0); | ||
844 | if (soc->num_ports > 2) | ||
845 | pads_writel(pcie, PADS_REFCLK_CFG_VALUE, PADS_REFCLK_CFG1); | ||
846 | |||
847 | /* wait for the PLL to lock */ | 841 | /* wait for the PLL to lock */ |
848 | err = tegra_pcie_pll_wait(pcie, 500); | 842 | err = tegra_pcie_pll_wait(pcie, 500); |
849 | if (err < 0) { | 843 | if (err < 0) { |
@@ -927,7 +921,9 @@ static int tegra_pcie_port_phy_power_off(struct tegra_pcie_port *port) | |||
927 | 921 | ||
928 | static int tegra_pcie_phy_power_on(struct tegra_pcie *pcie) | 922 | static int tegra_pcie_phy_power_on(struct tegra_pcie *pcie) |
929 | { | 923 | { |
924 | const struct tegra_pcie_soc_data *soc = pcie->soc_data; | ||
930 | struct tegra_pcie_port *port; | 925 | struct tegra_pcie_port *port; |
926 | u32 value; | ||
931 | int err; | 927 | int err; |
932 | 928 | ||
933 | if (pcie->legacy_phy) { | 929 | if (pcie->legacy_phy) { |
@@ -952,6 +948,13 @@ static int tegra_pcie_phy_power_on(struct tegra_pcie *pcie) | |||
952 | } | 948 | } |
953 | } | 949 | } |
954 | 950 | ||
951 | /* Configure the reference clock driver */ | ||
952 | value = PADS_REFCLK_CFG_VALUE | (PADS_REFCLK_CFG_VALUE << 16); | ||
953 | pads_writel(pcie, value, PADS_REFCLK_CFG0); | ||
954 | |||
955 | if (soc->num_ports > 2) | ||
956 | pads_writel(pcie, PADS_REFCLK_CFG_VALUE, PADS_REFCLK_CFG1); | ||
957 | |||
955 | return 0; | 958 | return 0; |
956 | } | 959 | } |
957 | 960 | ||