mtd: spi-nor: fix nor->addr_width when its value configured from SFDP does not match the actual width

IS25LP256 gets BFPT_DWORD1_ADDRESS_BYTES_3_ONLY from BFPT table for
address width. But in actual fact the flash can support 4-byte address.
Use a post bfpt fixup hook to overwrite the address width advertised by
the BFPT.

Signed-off-by: Liu Xiang <liu.xiang6@zte.com.cn>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>

1 files changed, 24 insertions, 1 deletions

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 9d03fe50533e..e3a28c0f22cb 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1687,6 +1687,28 @@ static int sr2_bit7_quad_enable(struct spi_nor *nor)
                 .flags = SPI_NOR_NO_FR | SPI_S3AN,
 
 static int
+is25lp256_post_bfpt_fixups(struct spi_nor *nor,
+                           const struct sfdp_parameter_header *bfpt_header,
+                           const struct sfdp_bfpt *bfpt,
+                           struct spi_nor_flash_parameter *params)
+{
+        /*
+         * IS25LP256 supports 4B opcodes, but the BFPT advertises a
+         * BFPT_DWORD1_ADDRESS_BYTES_3_ONLY address width.
+         * Overwrite the address width advertised by the BFPT.
+         */
+        if ((bfpt->dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) ==
+                BFPT_DWORD1_ADDRESS_BYTES_3_ONLY)
+                nor->addr_width = 4;
+
+        return 0;
+}
+
+static struct spi_nor_fixups is25lp256_fixups = {
+        .post_bfpt = is25lp256_post_bfpt_fixups,
+};
+
+static int
 mx25l25635_post_bfpt_fixups(struct spi_nor *nor,
                             const struct sfdp_parameter_header *bfpt_header,
                             const struct sfdp_bfpt *bfpt,
@@ -1827,7 +1849,8 @@ static const struct flash_info spi_nor_ids[] = {
                         SECT_4K | SPI_NOR_DUAL_READ) },
         { "is25lp256",  INFO(0x9d6019, 0, 64 * 1024, 512,
                         SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
-                        SPI_NOR_4B_OPCODES) },
+                        SPI_NOR_4B_OPCODES)
+                        .fixups = &is25lp256_fixups },
         { "is25wp032",  INFO(0x9d7016, 0, 64 * 1024,  64,
                         SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
         { "is25wp064",  INFO(0x9d7017, 0, 64 * 1024, 128,