diff options
author | Hou Zhiqiang <Zhiqiang.Hou@nxp.com> | 2019-07-05 05:56:49 -0400 |
---|---|---|
committer | Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2019-07-08 07:39:09 -0400 |
commit | cf22c591f93dbc92f9a1ec69343a17c74aac9743 (patch) | |
tree | 99008c7f1fe26267fa4226c2b06f48c438cbc6c8 | |
parent | 4b7e2e59f0e50f13d6498190da41e758e01e6489 (diff) |
PCI: mobiveil: Clear the control fields before updating it
While programming the inbound and outbound windows in
program_{ib/ob}_windows()
we shoud clear the control fields in the registers before programming
it with a new value to prevent stale bits from older configuration.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
-rw-r--r-- | drivers/pci/controller/pcie-mobiveil.c | 17 |
1 files changed, 12 insertions, 5 deletions
diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c index 0560344dc588..7d18e5976fc1 100644 --- a/drivers/pci/controller/pcie-mobiveil.c +++ b/drivers/pci/controller/pcie-mobiveil.c | |||
@@ -65,6 +65,8 @@ | |||
65 | #define PAB_AXI_AMAP_CTRL(win) PAB_REG_ADDR(0x0ba0, win) | 65 | #define PAB_AXI_AMAP_CTRL(win) PAB_REG_ADDR(0x0ba0, win) |
66 | #define WIN_ENABLE_SHIFT 0 | 66 | #define WIN_ENABLE_SHIFT 0 |
67 | #define WIN_TYPE_SHIFT 1 | 67 | #define WIN_TYPE_SHIFT 1 |
68 | #define WIN_TYPE_MASK 0x3 | ||
69 | #define WIN_SIZE_MASK 0xfffffc00 | ||
68 | 70 | ||
69 | #define PAB_EXT_AXI_AMAP_SIZE(win) PAB_EXT_REG_ADDR(0xbaf0, win) | 71 | #define PAB_EXT_AXI_AMAP_SIZE(win) PAB_EXT_REG_ADDR(0xbaf0, win) |
70 | 72 | ||
@@ -82,6 +84,7 @@ | |||
82 | #define PAB_PEX_AMAP_CTRL(win) PAB_REG_ADDR(0x4ba0, win) | 84 | #define PAB_PEX_AMAP_CTRL(win) PAB_REG_ADDR(0x4ba0, win) |
83 | #define AMAP_CTRL_EN_SHIFT 0 | 85 | #define AMAP_CTRL_EN_SHIFT 0 |
84 | #define AMAP_CTRL_TYPE_SHIFT 1 | 86 | #define AMAP_CTRL_TYPE_SHIFT 1 |
87 | #define AMAP_CTRL_TYPE_MASK 3 | ||
85 | 88 | ||
86 | #define PAB_EXT_PEX_AMAP_SIZEN(win) PAB_EXT_REG_ADDR(0xbef0, win) | 89 | #define PAB_EXT_PEX_AMAP_SIZEN(win) PAB_EXT_REG_ADDR(0xbef0, win) |
87 | #define PAB_PEX_AMAP_AXI_WIN(win) PAB_REG_ADDR(0x4ba4, win) | 90 | #define PAB_PEX_AMAP_AXI_WIN(win) PAB_REG_ADDR(0x4ba4, win) |
@@ -469,9 +472,9 @@ static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num, | |||
469 | csr_writel(pcie, value, PAB_PEX_PIO_CTRL); | 472 | csr_writel(pcie, value, PAB_PEX_PIO_CTRL); |
470 | 473 | ||
471 | value = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num)); | 474 | value = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num)); |
472 | value |= (type << AMAP_CTRL_TYPE_SHIFT) | | 475 | value &= ~(AMAP_CTRL_TYPE_MASK << AMAP_CTRL_TYPE_SHIFT | WIN_SIZE_MASK); |
473 | (1 << AMAP_CTRL_EN_SHIFT) | | 476 | value |= type << AMAP_CTRL_TYPE_SHIFT | 1 << AMAP_CTRL_EN_SHIFT | |
474 | lower_32_bits(size64); | 477 | lower_32_bits(size64); |
475 | csr_writel(pcie, value, PAB_PEX_AMAP_CTRL(win_num)); | 478 | csr_writel(pcie, value, PAB_PEX_AMAP_CTRL(win_num)); |
476 | 479 | ||
477 | csr_writel(pcie, upper_32_bits(size64), | 480 | csr_writel(pcie, upper_32_bits(size64), |
@@ -490,6 +493,7 @@ static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num, | |||
490 | static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, | 493 | static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, |
491 | u64 cpu_addr, u64 pci_addr, u32 type, u64 size) | 494 | u64 cpu_addr, u64 pci_addr, u32 type, u64 size) |
492 | { | 495 | { |
496 | u32 value; | ||
493 | u64 size64 = ~(size - 1); | 497 | u64 size64 = ~(size - 1); |
494 | 498 | ||
495 | if (win_num >= pcie->apio_wins) { | 499 | if (win_num >= pcie->apio_wins) { |
@@ -502,8 +506,11 @@ static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, | |||
502 | * program Enable Bit to 1, Type Bit to (00) base 2, AXI Window Size Bit | 506 | * program Enable Bit to 1, Type Bit to (00) base 2, AXI Window Size Bit |
503 | * to 4 KB in PAB_AXI_AMAP_CTRL register | 507 | * to 4 KB in PAB_AXI_AMAP_CTRL register |
504 | */ | 508 | */ |
505 | csr_writel(pcie, 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT | | 509 | value = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num)); |
506 | lower_32_bits(size64), PAB_AXI_AMAP_CTRL(win_num)); | 510 | value &= ~(WIN_TYPE_MASK << WIN_TYPE_SHIFT | WIN_SIZE_MASK); |
511 | value |= 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT | | ||
512 | lower_32_bits(size64); | ||
513 | csr_writel(pcie, value, PAB_AXI_AMAP_CTRL(win_num)); | ||
507 | 514 | ||
508 | csr_writel(pcie, upper_32_bits(size64), PAB_EXT_AXI_AMAP_SIZE(win_num)); | 515 | csr_writel(pcie, upper_32_bits(size64), PAB_EXT_AXI_AMAP_SIZE(win_num)); |
509 | 516 | ||