aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorRob Rice <rob.rice@broadcom.com>2016-11-14 13:26:05 -0500
committerJassi Brar <jaswinder.singh@linaro.org>2016-12-19 09:40:23 -0500
commitcf17581340d730175f1f3f4ce6e90ae434154e37 (patch)
tree5c2a0794b11416581ef4595d11aa3c6fb46ac3f0
parent30d1ef623fd1e99bc1bab5211ba1da0d97d40e64 (diff)
mailbox: bcm-pdc: Remove unnecessary void* casts
Remove unnecessary void* casts in register writes. Fix two other minor formatting issues. Signed-off-by: Rob Rice <rob.rice@broadcom.com> Reviewed-by: Andy Gospodarek <gospo@broadcom.com> Reviewed-by: Jon Mason <jon.mason@broadcom.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
-rw-r--r--drivers/mailbox/bcm-pdc-mailbox.c41
1 files changed, 20 insertions, 21 deletions
diff --git a/drivers/mailbox/bcm-pdc-mailbox.c b/drivers/mailbox/bcm-pdc-mailbox.c
index c1ec17cfa03a..2aeb034d5fb9 100644
--- a/drivers/mailbox/bcm-pdc-mailbox.c
+++ b/drivers/mailbox/bcm-pdc-mailbox.c
@@ -468,7 +468,7 @@ static ssize_t pdc_debugfs_read(struct file *filp, char __user *ubuf,
468 out_offset += snprintf(buf + out_offset, out_count - out_offset, 468 out_offset += snprintf(buf + out_offset, out_count - out_offset,
469 "Num frags in rx ring............%u\n", 469 "Num frags in rx ring............%u\n",
470 NRXDACTIVE(pdcs->rxin, pdcs->last_rx_curr, 470 NRXDACTIVE(pdcs->rxin, pdcs->last_rx_curr,
471 pdcs->nrxpost)); 471 pdcs->nrxpost));
472 472
473 if (out_offset > out_count) 473 if (out_offset > out_count)
474 out_offset = out_count; 474 out_offset = out_count;
@@ -683,7 +683,7 @@ pdc_receive(struct pdc_state *pdcs)
683 683
684 /* read last_rx_curr from register once */ 684 /* read last_rx_curr from register once */
685 pdcs->last_rx_curr = 685 pdcs->last_rx_curr =
686 (ioread32((void *)&pdcs->rxregs_64->status0) & 686 (ioread32(&pdcs->rxregs_64->status0) &
687 CRYPTO_D64_RS0_CD_MASK) / RING_ENTRY_SIZE; 687 CRYPTO_D64_RS0_CD_MASK) / RING_ENTRY_SIZE;
688 688
689 do { 689 do {
@@ -793,8 +793,8 @@ static int pdc_tx_list_final(struct pdc_state *pdcs)
793 * before chip starts to process new request 793 * before chip starts to process new request
794 */ 794 */
795 wmb(); 795 wmb();
796 iowrite32(pdcs->rxout << 4, (void *)&pdcs->rxregs_64->ptr); 796 iowrite32(pdcs->rxout << 4, &pdcs->rxregs_64->ptr);
797 iowrite32(pdcs->txout << 4, (void *)&pdcs->txregs_64->ptr); 797 iowrite32(pdcs->txout << 4, &pdcs->txregs_64->ptr);
798 pdcs->pdc_requests++; 798 pdcs->pdc_requests++;
799 799
800 return PDC_SUCCESS; 800 return PDC_SUCCESS;
@@ -1034,47 +1034,46 @@ static int pdc_ring_init(struct pdc_state *pdcs, int ringset)
1034 /* But first disable DMA and set curptr to 0 for both TX & RX */ 1034 /* But first disable DMA and set curptr to 0 for both TX & RX */
1035 iowrite32(PDC_TX_CTL, &dma_reg->dmaxmt.control); 1035 iowrite32(PDC_TX_CTL, &dma_reg->dmaxmt.control);
1036 iowrite32((PDC_RX_CTL + (pdcs->rx_status_len << 1)), 1036 iowrite32((PDC_RX_CTL + (pdcs->rx_status_len << 1)),
1037 (void *)&dma_reg->dmarcv.control); 1037 &dma_reg->dmarcv.control);
1038 iowrite32(0, (void *)&dma_reg->dmaxmt.ptr); 1038 iowrite32(0, &dma_reg->dmaxmt.ptr);
1039 iowrite32(0, (void *)&dma_reg->dmarcv.ptr); 1039 iowrite32(0, &dma_reg->dmarcv.ptr);
1040 1040
1041 /* Set base DMA addresses */ 1041 /* Set base DMA addresses */
1042 iowrite32(lower_32_bits(pdcs->tx_ring_alloc.dmabase), 1042 iowrite32(lower_32_bits(pdcs->tx_ring_alloc.dmabase),
1043 (void *)&dma_reg->dmaxmt.addrlow); 1043 &dma_reg->dmaxmt.addrlow);
1044 iowrite32(upper_32_bits(pdcs->tx_ring_alloc.dmabase), 1044 iowrite32(upper_32_bits(pdcs->tx_ring_alloc.dmabase),
1045 (void *)&dma_reg->dmaxmt.addrhigh); 1045 &dma_reg->dmaxmt.addrhigh);
1046 1046
1047 iowrite32(lower_32_bits(pdcs->rx_ring_alloc.dmabase), 1047 iowrite32(lower_32_bits(pdcs->rx_ring_alloc.dmabase),
1048 (void *)&dma_reg->dmarcv.addrlow); 1048 &dma_reg->dmarcv.addrlow);
1049 iowrite32(upper_32_bits(pdcs->rx_ring_alloc.dmabase), 1049 iowrite32(upper_32_bits(pdcs->rx_ring_alloc.dmabase),
1050 (void *)&dma_reg->dmarcv.addrhigh); 1050 &dma_reg->dmarcv.addrhigh);
1051 1051
1052 /* Re-enable DMA */ 1052 /* Re-enable DMA */
1053 iowrite32(PDC_TX_CTL | PDC_TX_ENABLE, &dma_reg->dmaxmt.control); 1053 iowrite32(PDC_TX_CTL | PDC_TX_ENABLE, &dma_reg->dmaxmt.control);
1054 iowrite32((PDC_RX_CTL | PDC_RX_ENABLE | (pdcs->rx_status_len << 1)), 1054 iowrite32((PDC_RX_CTL | PDC_RX_ENABLE | (pdcs->rx_status_len << 1)),
1055 (void *)&dma_reg->dmarcv.control); 1055 &dma_reg->dmarcv.control);
1056 1056
1057 /* Initialize descriptors */ 1057 /* Initialize descriptors */
1058 for (i = 0; i < PDC_RING_ENTRIES; i++) { 1058 for (i = 0; i < PDC_RING_ENTRIES; i++) {
1059 /* Every tx descriptor can be used for start of frame. */ 1059 /* Every tx descriptor can be used for start of frame. */
1060 if (i != pdcs->ntxpost) { 1060 if (i != pdcs->ntxpost) {
1061 iowrite32(D64_CTRL1_SOF | D64_CTRL1_EOF, 1061 iowrite32(D64_CTRL1_SOF | D64_CTRL1_EOF,
1062 (void *)&pdcs->txd_64[i].ctrl1); 1062 &pdcs->txd_64[i].ctrl1);
1063 } else { 1063 } else {
1064 /* Last descriptor in ringset. Set End of Table. */ 1064 /* Last descriptor in ringset. Set End of Table. */
1065 iowrite32(D64_CTRL1_SOF | D64_CTRL1_EOF | 1065 iowrite32(D64_CTRL1_SOF | D64_CTRL1_EOF |
1066 D64_CTRL1_EOT, 1066 D64_CTRL1_EOT, &pdcs->txd_64[i].ctrl1);
1067 (void *)&pdcs->txd_64[i].ctrl1);
1068 } 1067 }
1069 1068
1070 /* Every rx descriptor can be used for start of frame */ 1069 /* Every rx descriptor can be used for start of frame */
1071 if (i != pdcs->nrxpost) { 1070 if (i != pdcs->nrxpost) {
1072 iowrite32(D64_CTRL1_SOF, 1071 iowrite32(D64_CTRL1_SOF,
1073 (void *)&pdcs->rxd_64[i].ctrl1); 1072 &pdcs->rxd_64[i].ctrl1);
1074 } else { 1073 } else {
1075 /* Last descriptor in ringset. Set End of Table. */ 1074 /* Last descriptor in ringset. Set End of Table. */
1076 iowrite32(D64_CTRL1_SOF | D64_CTRL1_EOT, 1075 iowrite32(D64_CTRL1_SOF | D64_CTRL1_EOT,
1077 (void *)&pdcs->rxd_64[i].ctrl1); 1076 &pdcs->rxd_64[i].ctrl1);
1078 } 1077 }
1079 } 1078 }
1080 return PDC_SUCCESS; 1079 return PDC_SUCCESS;
@@ -1300,10 +1299,10 @@ void pdc_hw_init(struct pdc_state *pdcs)
1300 /* initialize data structures */ 1299 /* initialize data structures */
1301 pdcs->regs = (struct pdc_regs *)pdcs->pdc_reg_vbase; 1300 pdcs->regs = (struct pdc_regs *)pdcs->pdc_reg_vbase;
1302 pdcs->txregs_64 = (struct dma64_regs *) 1301 pdcs->txregs_64 = (struct dma64_regs *)
1303 (void *)(((u8 *)pdcs->pdc_reg_vbase) + 1302 (((u8 *)pdcs->pdc_reg_vbase) +
1304 PDC_TXREGS_OFFSET + (sizeof(struct dma64) * ringset)); 1303 PDC_TXREGS_OFFSET + (sizeof(struct dma64) * ringset));
1305 pdcs->rxregs_64 = (struct dma64_regs *) 1304 pdcs->rxregs_64 = (struct dma64_regs *)
1306 (void *)(((u8 *)pdcs->pdc_reg_vbase) + 1305 (((u8 *)pdcs->pdc_reg_vbase) +
1307 PDC_RXREGS_OFFSET + (sizeof(struct dma64) * ringset)); 1306 PDC_RXREGS_OFFSET + (sizeof(struct dma64) * ringset));
1308 1307
1309 pdcs->ntxd = PDC_RING_ENTRIES; 1308 pdcs->ntxd = PDC_RING_ENTRIES;
@@ -1318,7 +1317,7 @@ void pdc_hw_init(struct pdc_state *pdcs)
1318 iowrite32(PDC_TX_CTL, &dma_reg->dmaxmt.control); 1317 iowrite32(PDC_TX_CTL, &dma_reg->dmaxmt.control);
1319 1318
1320 iowrite32(PDC_RX_CTL + (pdcs->rx_status_len << 1), 1319 iowrite32(PDC_RX_CTL + (pdcs->rx_status_len << 1),
1321 (void *)&dma_reg->dmarcv.control); 1320 &dma_reg->dmarcv.control);
1322 1321
1323 /* Reset current index pointers after making sure DMA is disabled */ 1322 /* Reset current index pointers after making sure DMA is disabled */
1324 iowrite32(0, &dma_reg->dmaxmt.ptr); 1323 iowrite32(0, &dma_reg->dmaxmt.ptr);
@@ -1567,7 +1566,7 @@ static int pdc_probe(struct platform_device *pdev)
1567 pdc_hw_init(pdcs); 1566 pdc_hw_init(pdcs);
1568 1567
1569 /* Init tasklet for deferred DMA rx processing */ 1568 /* Init tasklet for deferred DMA rx processing */
1570 tasklet_init(&pdcs->rx_tasklet, pdc_tasklet_cb, (unsigned long) pdcs); 1569 tasklet_init(&pdcs->rx_tasklet, pdc_tasklet_cb, (unsigned long)pdcs);
1571 1570
1572 err = pdc_interrupts_init(pdcs); 1571 err = pdc_interrupts_init(pdcs);
1573 if (err) 1572 if (err)