aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorDave Airlie <airlied@redhat.com>2016-05-12 21:48:01 -0400
committerDave Airlie <airlied@redhat.com>2016-05-12 21:48:01 -0400
commitcf15fabd6f66e966ae5744f088538f7936df9a4d (patch)
treea1b4af4e2b29bb3dae7a3c9102d63af94b611de8
parent7d020672615d09cf6ec42c500f34d70adf6758a9 (diff)
parent227e4f4079e198695b9b5df344aa0e29676a5a29 (diff)
Merge tag 'drm/panel/for-4.7-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next
drm/panel: Changes for v4.7-rc1 This contains support for a bunch of new panels in the simple panel driver along with some cleanup and support for a new Analogix HDMI to DP bridge. * tag 'drm/panel/for-4.7-rc1' of git://anongit.freedesktop.org/tegra/linux: drm/panel: simple: Add support for TPK U.S.A. LLC Fusion 7" and 10.1" panels drm/bridge: Add Analogix anx78xx support devicetree: Add ANX7814 SlimPort transmitter binding of: Add vendor prefix for Analogix Semiconductor drm/dp: Add define to set 0.5% down-spread in MAX_DOWNSPREAD register drm/panel: simple: Add support for Innolux AT070TN92 drm/panel: simple: Remove useless drm_mode_set_name() drm/panel: simple: Set appropriate mode type drm/panel: simple: Add timings for the Olimex LCD-OLinuXino-4.3TS drm/panel: simple: Add the 7" DPI panel from Adafruit of: Add vendor prefix for On Tat Industrial Company.
Diffstat
-rw-r--r--Documentation/devicetree/bindings/display/panel/innolux,at070tn92.txt7
-rw-r--r--Documentation/devicetree/bindings/display/panel/olimex,lcd-olinuxino-43-ts.txt7
-rw-r--r--Documentation/devicetree/bindings/display/panel/ontat,yx700wv03.txt7
-rw-r--r--Documentation/devicetree/bindings/display/panel/tpk,f07a-0102.txt8
-rw-r--r--Documentation/devicetree/bindings/display/panel/tpk,f10a-0102.txt8
-rw-r--r--Documentation/devicetree/bindings/vendor-prefixes.txt3
-rw-r--r--Documentation/devicetree/bindings/video/bridge/anx7814.txt40
-rw-r--r--drivers/gpu/drm/bridge/Kconfig10
-rw-r--r--drivers/gpu/drm/bridge/Makefile1
-rw-r--r--drivers/gpu/drm/bridge/analogix-anx78xx.c1514
-rw-r--r--drivers/gpu/drm/bridge/analogix-anx78xx.h719
-rw-r--r--drivers/gpu/drm/panel/panel-simple.c151
-rw-r--r--include/drm/drm_dp_helper.h1
13 files changed, 2475 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/display/panel/innolux,at070tn92.txt b/Documentation/devicetree/bindings/display/panel/innolux,at070tn92.txt
new file mode 100644
index 000000000000..3e10cd782491
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/innolux,at070tn92.txt
@@ -0,0 +1,7 @@
1Innolux AT070TN92 7.0" WQVGA TFT LCD panel
2
3Required properties:
4- compatible: should be "innolux,at070tn92"
5
6This binding is compatible with the simple-panel binding, which is specified
7in simple-panel.txt in this directory.
diff --git a/Documentation/devicetree/bindings/display/panel/olimex,lcd-olinuxino-43-ts.txt b/Documentation/devicetree/bindings/display/panel/olimex,lcd-olinuxino-43-ts.txt
new file mode 100644
index 000000000000..74540a090669
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/olimex,lcd-olinuxino-43-ts.txt
@@ -0,0 +1,7 @@
1Olimex 4.3" TFT LCD panel
2
3Required properties:
4- compatible: should be "olimex,lcd-olinuxino-43-ts"
5
6This binding is compatible with the simple-panel binding, which is specified
7in simple-panel.txt in this directory.
diff --git a/Documentation/devicetree/bindings/display/panel/ontat,yx700wv03.txt b/Documentation/devicetree/bindings/display/panel/ontat,yx700wv03.txt
new file mode 100644
index 000000000000..3d8a5e029242
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/ontat,yx700wv03.txt
@@ -0,0 +1,7 @@
1On Tat Industrial Company 7" DPI TFT panel.
2
3Required properties:
4- compatible: should be "ontat,yx700wv03"
5
6This binding is compatible with the simple-panel binding, which is specified
7in simple-panel.txt in this directory.
diff --git a/Documentation/devicetree/bindings/display/panel/tpk,f07a-0102.txt b/Documentation/devicetree/bindings/display/panel/tpk,f07a-0102.txt
new file mode 100644
index 000000000000..a2613b9675df
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/tpk,f07a-0102.txt
@@ -0,0 +1,8 @@
1TPK U.S.A. LLC Fusion 7" integrated projected capacitive touch display with,
2800 x 480 (WVGA) LCD panel.
3
4Required properties:
5- compatible: should be "tpk,f07a-0102"
6
7This binding is compatible with the simple-panel binding, which is specified
8in simple-panel.txt in this directory.
diff --git a/Documentation/devicetree/bindings/display/panel/tpk,f10a-0102.txt b/Documentation/devicetree/bindings/display/panel/tpk,f10a-0102.txt
new file mode 100644
index 000000000000..b9d051196ba9
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/tpk,f10a-0102.txt
@@ -0,0 +1,8 @@
1TPK U.S.A. LLC Fusion 10.1" integrated projected capacitive touch display with,
21024 x 600 (WSVGA) LCD panel.
3
4Required properties:
5- compatible: should be "tpk,f10a-0102"
6
7This binding is compatible with the simple-panel binding, which is specified
8in simple-panel.txt in this directory.
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 86740d4a270d..42b6688c4a98 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -22,6 +22,7 @@ amlogic Amlogic, Inc.
22ampire Ampire Co., Ltd. 22ampire Ampire Co., Ltd.
23ams AMS AG 23ams AMS AG
24amstaos AMS-Taos Inc. 24amstaos AMS-Taos Inc.
25analogix Analogix Semiconductor, Inc.
25apm Applied Micro Circuits Corporation (APM) 26apm Applied Micro Circuits Corporation (APM)
26aptina Aptina Imaging 27aptina Aptina Imaging
27arasan Arasan Chip Systems 28arasan Arasan Chip Systems
@@ -172,6 +173,7 @@ nxp NXP Semiconductors
172okaya Okaya Electric America, Inc. 173okaya Okaya Electric America, Inc.
173olimex OLIMEX Ltd. 174olimex OLIMEX Ltd.
174onnn ON Semiconductor Corp. 175onnn ON Semiconductor Corp.
176ontat On Tat Industrial Company
175opencores OpenCores.org 177opencores OpenCores.org
176option Option NV 178option Option NV
177ortustech Ortus Technology Co., Ltd. 179ortustech Ortus Technology Co., Ltd.
@@ -247,6 +249,7 @@ toradex Toradex AG
247toshiba Toshiba Corporation 249toshiba Toshiba Corporation
248toumaz Toumaz 250toumaz Toumaz
249tplink TP-LINK Technologies Co., Ltd. 251tplink TP-LINK Technologies Co., Ltd.
252tpk TPK U.S.A. LLC
250tronfy Tronfy 253tronfy Tronfy
251tronsmart Tronsmart 254tronsmart Tronsmart
252truly Truly Semiconductors Limited 255truly Truly Semiconductors Limited
diff --git a/Documentation/devicetree/bindings/video/bridge/anx7814.txt b/Documentation/devicetree/bindings/video/bridge/anx7814.txt
new file mode 100644
index 000000000000..b2a22c28c9b3
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/bridge/anx7814.txt
@@ -0,0 +1,40 @@
1Analogix ANX7814 SlimPort (Full-HD Transmitter)
2-----------------------------------------------
3
4The ANX7814 is an ultra-low power Full-HD (1080p60) SlimPort transmitter
5designed for portable devices.
6
7Required properties:
8
9 - compatible : "analogix,anx7814"
10 - reg : I2C address of the device
11 - interrupt-parent : Should be the phandle of the interrupt controller
12 that services interrupts for this device
13 - interrupts : Should contain the INTP interrupt
14 - hpd-gpios : Which GPIO to use for hpd
15 - pd-gpios : Which GPIO to use for power down
16 - reset-gpios : Which GPIO to use for reset
17
18Optional properties:
19
20 - dvdd10-supply : Regulator for 1.0V digital core power.
21 - Video port for HDMI input, using the DT bindings defined in [1].
22
23[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
24
25Example:
26
27 anx7814: anx7814@38 {
28 compatible = "analogix,anx7814";
29 reg = <0x38>;
30 interrupt-parent = <&gpio0>;
31 interrupts = <99 IRQ_TYPE_LEVEL_LOW>; /* INTP */
32 hpd-gpios = <&pio 36 GPIO_ACTIVE_HIGH>;
33 pd-gpios = <&pio 33 GPIO_ACTIVE_HIGH>;
34 reset-gpios = <&pio 98 GPIO_ACTIVE_HIGH>;
35 port {
36 anx7814_in: endpoint {
37 remote-endpoint = <&hdmi0_out>;
38 };
39 };
40 };
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index efd94e00c3e5..8f7423f18da5 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -7,6 +7,16 @@ config DRM_BRIDGE
7menu "Display Interface Bridges" 7menu "Display Interface Bridges"
8 depends on DRM && DRM_BRIDGE 8 depends on DRM && DRM_BRIDGE
9 9
10config DRM_ANALOGIX_ANX78XX
11 tristate "Analogix ANX78XX bridge"
12 select DRM_KMS_HELPER
13 select REGMAP_I2C
14 ---help---
15 ANX78XX is an ultra-low Full-HD SlimPort transmitter
16 designed for portable devices. The ANX78XX transforms
17 the HDMI output of an application processor to MyDP
18 or DisplayPort.
19
10config DRM_DW_HDMI 20config DRM_DW_HDMI
11 tristate 21 tristate
12 select DRM_KMS_HELPER 22 select DRM_KMS_HELPER
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index ff821f4b5833..96b13b30e6ab 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -1,5 +1,6 @@
1ccflags-y := -Iinclude/drm 1ccflags-y := -Iinclude/drm
2 2
3obj-$(CONFIG_DRM_ANALOGIX_ANX78XX) += analogix-anx78xx.o
3obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o 4obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
4obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o 5obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
5obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o 6obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
diff --git a/drivers/gpu/drm/bridge/analogix-anx78xx.c b/drivers/gpu/drm/bridge/analogix-anx78xx.c
new file mode 100644
index 000000000000..d087b054c360
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix-anx78xx.c
@@ -0,0 +1,1514 @@
1/*
2 * Copyright(c) 2016, Analogix Semiconductor.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * Based on anx7808 driver obtained from chromeos with copyright:
14 * Copyright(c) 2013, Google Inc.
15 *
16 */
17#include <linux/delay.h>
18#include <linux/err.h>
19#include <linux/interrupt.h>
20#include <linux/i2c.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/of_gpio.h>
24#include <linux/of_irq.h>
25#include <linux/of_platform.h>
26#include <linux/regmap.h>
27#include <linux/types.h>
28#include <linux/gpio/consumer.h>
29#include <linux/regulator/consumer.h>
30
31#include <drm/drmP.h>
32#include <drm/drm_atomic_helper.h>
33#include <drm/drm_crtc.h>
34#include <drm/drm_crtc_helper.h>
35#include <drm/drm_dp_helper.h>
36#include <drm/drm_edid.h>
37
38#include "analogix-anx78xx.h"
39
40#define I2C_NUM_ADDRESSES 5
41#define I2C_IDX_TX_P0 0
42#define I2C_IDX_TX_P1 1
43#define I2C_IDX_TX_P2 2
44#define I2C_IDX_RX_P0 3
45#define I2C_IDX_RX_P1 4
46
47#define XTAL_CLK 270 /* 27M */
48#define AUX_CH_BUFFER_SIZE 16
49#define AUX_WAIT_TIMEOUT_MS 15
50
51static const u8 anx78xx_i2c_addresses[] = {
52 [I2C_IDX_TX_P0] = TX_P0,
53 [I2C_IDX_TX_P1] = TX_P1,
54 [I2C_IDX_TX_P2] = TX_P2,
55 [I2C_IDX_RX_P0] = RX_P0,
56 [I2C_IDX_RX_P1] = RX_P1,
57};
58
59struct anx78xx_platform_data {
60 struct regulator *dvdd10;
61 struct gpio_desc *gpiod_hpd;
62 struct gpio_desc *gpiod_pd;
63 struct gpio_desc *gpiod_reset;
64
65 int hpd_irq;
66 int intp_irq;
67};
68
69struct anx78xx {
70 struct drm_dp_aux aux;
71 struct drm_bridge bridge;
72 struct i2c_client *client;
73 struct edid *edid;
74 struct drm_connector connector;
75 struct drm_dp_link link;
76 struct anx78xx_platform_data pdata;
77 struct mutex lock;
78
79 /*
80 * I2C Slave addresses of ANX7814 are mapped as TX_P0, TX_P1, TX_P2,
81 * RX_P0 and RX_P1.
82 */
83 struct i2c_client *i2c_dummy[I2C_NUM_ADDRESSES];
84 struct regmap *map[I2C_NUM_ADDRESSES];
85
86 u16 chipid;
87 u8 dpcd[DP_RECEIVER_CAP_SIZE];
88
89 bool powered;
90};
91
92static inline struct anx78xx *connector_to_anx78xx(struct drm_connector *c)
93{
94 return container_of(c, struct anx78xx, connector);
95}
96
97static inline struct anx78xx *bridge_to_anx78xx(struct drm_bridge *bridge)
98{
99 return container_of(bridge, struct anx78xx, bridge);
100}
101
102static int anx78xx_set_bits(struct regmap *map, u8 reg, u8 mask)
103{
104 return regmap_update_bits(map, reg, mask, mask);
105}
106
107static int anx78xx_clear_bits(struct regmap *map, u8 reg, u8 mask)
108{
109 return regmap_update_bits(map, reg, mask, 0);
110}
111
112static bool anx78xx_aux_op_finished(struct anx78xx *anx78xx)
113{
114 unsigned int value;
115 int err;
116
117 err = regmap_read(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL2_REG,
118 &value);
119 if (err < 0)
120 return false;
121
122 return (value & SP_AUX_EN) == 0;
123}
124
125static int anx78xx_aux_wait(struct anx78xx *anx78xx)
126{
127 unsigned long timeout;
128 unsigned int status;
129 int err;
130
131 timeout = jiffies + msecs_to_jiffies(AUX_WAIT_TIMEOUT_MS) + 1;
132
133 while (!anx78xx_aux_op_finished(anx78xx)) {
134 if (time_after(jiffies, timeout)) {
135 if (!anx78xx_aux_op_finished(anx78xx)) {
136 DRM_ERROR("Timed out waiting AUX to finish\n");
137 return -ETIMEDOUT;
138 }
139
140 break;
141 }
142
143 usleep_range(1000, 2000);
144 }
145
146 /* Read the AUX channel access status */
147 err = regmap_read(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_CH_STATUS_REG,
148 &status);
149 if (err < 0) {
150 DRM_ERROR("Failed to read from AUX channel: %d\n", err);
151 return err;
152 }
153
154 if (status & SP_AUX_STATUS) {
155 DRM_ERROR("Failed to wait for AUX channel (status: %02x)\n",
156 status);
157 return -ETIMEDOUT;
158 }
159
160 return 0;
161}
162
163static int anx78xx_aux_address(struct anx78xx *anx78xx, unsigned int addr)
164{
165 int err;
166
167 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_ADDR_7_0_REG,
168 addr & 0xff);
169 if (err)
170 return err;
171
172 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_ADDR_15_8_REG,
173 (addr & 0xff00) >> 8);
174 if (err)
175 return err;
176
177 /*
178 * DP AUX CH Address Register #2, only update bits[3:0]
179 * [7:4] RESERVED
180 * [3:0] AUX_ADDR[19:16], Register control AUX CH address.
181 */
182 err = regmap_update_bits(anx78xx->map[I2C_IDX_TX_P0],
183 SP_AUX_ADDR_19_16_REG,
184 SP_AUX_ADDR_19_16_MASK,
185 (addr & 0xf0000) >> 16);
186
187 if (err)
188 return err;
189
190 return 0;
191}
192
193static ssize_t anx78xx_aux_transfer(struct drm_dp_aux *aux,
194 struct drm_dp_aux_msg *msg)
195{
196 struct anx78xx *anx78xx = container_of(aux, struct anx78xx, aux);
197 u8 ctrl1 = msg->request;
198 u8 ctrl2 = SP_AUX_EN;
199 u8 *buffer = msg->buffer;
200 int err;
201
202 /* The DP AUX transmit and receive buffer has 16 bytes. */
203 if (WARN_ON(msg->size > AUX_CH_BUFFER_SIZE))
204 return -E2BIG;
205
206 /* Zero-sized messages specify address-only transactions. */
207 if (msg->size < 1)
208 ctrl2 |= SP_ADDR_ONLY;
209 else /* For non-zero-sized set the length field. */
210 ctrl1 |= (msg->size - 1) << SP_AUX_LENGTH_SHIFT;
211
212 if ((msg->request & DP_AUX_I2C_READ) == 0) {
213 /* When WRITE | MOT write values to data buffer */
214 err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P0],
215 SP_DP_BUF_DATA0_REG, buffer,
216 msg->size);
217 if (err)
218 return err;
219 }
220
221 /* Write address and request */
222 err = anx78xx_aux_address(anx78xx, msg->address);
223 if (err)
224 return err;
225
226 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL1_REG,
227 ctrl1);
228 if (err)
229 return err;
230
231 /* Start transaction */
232 err = regmap_update_bits(anx78xx->map[I2C_IDX_TX_P0],
233 SP_DP_AUX_CH_CTRL2_REG, SP_ADDR_ONLY |
234 SP_AUX_EN, ctrl2);
235 if (err)
236 return err;
237
238 err = anx78xx_aux_wait(anx78xx);
239 if (err)
240 return err;
241
242 msg->reply = DP_AUX_I2C_REPLY_ACK;
243
244 if ((msg->size > 0) && (msg->request & DP_AUX_I2C_READ)) {
245 /* Read values from data buffer */
246 err = regmap_bulk_read(anx78xx->map[I2C_IDX_TX_P0],
247 SP_DP_BUF_DATA0_REG, buffer,
248 msg->size);
249 if (err)
250 return err;
251 }
252
253 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
254 SP_DP_AUX_CH_CTRL2_REG, SP_ADDR_ONLY);
255 if (err)
256 return err;
257
258 return msg->size;
259}
260
261static int anx78xx_set_hpd(struct anx78xx *anx78xx)
262{
263 int err;
264
265 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0],
266 SP_TMDS_CTRL_BASE + 7, SP_PD_RT);
267 if (err)
268 return err;
269
270 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL3_REG,
271 SP_HPD_OUT);
272 if (err)
273 return err;
274
275 return 0;
276}
277
278static int anx78xx_clear_hpd(struct anx78xx *anx78xx)
279{
280 int err;
281
282 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL3_REG,
283 SP_HPD_OUT);
284 if (err)
285 return err;
286
287 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
288 SP_TMDS_CTRL_BASE + 7, SP_PD_RT);
289 if (err)
290 return err;
291
292 return 0;
293}
294
295static const struct reg_sequence tmds_phy_initialization[] = {
296 { SP_TMDS_CTRL_BASE + 1, 0x90 },
297 { SP_TMDS_CTRL_BASE + 2, 0xa9 },
298 { SP_TMDS_CTRL_BASE + 6, 0x92 },
299 { SP_TMDS_CTRL_BASE + 7, 0x80 },
300 { SP_TMDS_CTRL_BASE + 20, 0xf2 },
301 { SP_TMDS_CTRL_BASE + 22, 0xc4 },
302 { SP_TMDS_CTRL_BASE + 23, 0x18 },
303};
304
305static int anx78xx_rx_initialization(struct anx78xx *anx78xx)
306{
307 int err;
308
309 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_HDMI_MUTE_CTRL_REG,
310 SP_AUD_MUTE | SP_VID_MUTE);
311 if (err)
312 return err;
313
314 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], SP_CHIP_CTRL_REG,
315 SP_MAN_HDMI5V_DET | SP_PLLLOCK_CKDT_EN |
316 SP_DIGITAL_CKDT_EN);
317 if (err)
318 return err;
319
320 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
321 SP_SOFTWARE_RESET1_REG, SP_HDCP_MAN_RST |
322 SP_SW_MAN_RST | SP_TMDS_RST | SP_VIDEO_RST);
323 if (err)
324 return err;
325
326 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0],
327 SP_SOFTWARE_RESET1_REG, SP_HDCP_MAN_RST |
328 SP_SW_MAN_RST | SP_TMDS_RST | SP_VIDEO_RST);
329 if (err)
330 return err;
331
332 /* Sync detect change, GP set mute */
333 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
334 SP_AUD_EXCEPTION_ENABLE_BASE + 1, BIT(5) |
335 BIT(6));
336 if (err)
337 return err;
338
339 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
340 SP_AUD_EXCEPTION_ENABLE_BASE + 3,
341 SP_AEC_EN21);
342 if (err)
343 return err;
344
345 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], SP_AUDVID_CTRL_REG,
346 SP_AVC_EN | SP_AAC_OE | SP_AAC_EN);
347 if (err)
348 return err;
349
350 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0],
351 SP_SYSTEM_POWER_DOWN1_REG, SP_PWDN_CTRL);
352 if (err)
353 return err;
354
355 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
356 SP_VID_DATA_RANGE_CTRL_REG, SP_R2Y_INPUT_LIMIT);
357 if (err)
358 return err;
359
360 /* Enable DDC stretch */
361 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
362 SP_DP_EXTRA_I2C_DEV_ADDR_REG, SP_I2C_EXTRA_ADDR);
363 if (err)
364 return err;
365
366 /* TMDS phy initialization */
367 err = regmap_multi_reg_write(anx78xx->map[I2C_IDX_RX_P0],
368 tmds_phy_initialization,
369 ARRAY_SIZE(tmds_phy_initialization));
370 if (err)
371 return err;
372
373 err = anx78xx_clear_hpd(anx78xx);
374 if (err)
375 return err;
376
377 return 0;
378}
379
380static const u8 dp_tx_output_precise_tune_bits[20] = {
381 0x01, 0x03, 0x07, 0x7f, 0x71, 0x6b, 0x7f,
382 0x73, 0x7f, 0x7f, 0x00, 0x00, 0x00, 0x00,
383 0x0c, 0x42, 0x1e, 0x3e, 0x72, 0x7e,
384};
385
386static int anx78xx_link_phy_initialization(struct anx78xx *anx78xx)
387{
388 int err;
389
390 /*
391 * REVISIT : It is writing to a RESERVED bits in Analog Control 0
392 * register.
393 */
394 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_ANALOG_CTRL0_REG,
395 0x02);
396 if (err)
397 return err;
398
399 /*
400 * Write DP TX output emphasis precise tune bits.
401 */
402 err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P1],
403 SP_DP_TX_LT_CTRL0_REG,
404 dp_tx_output_precise_tune_bits,
405 ARRAY_SIZE(dp_tx_output_precise_tune_bits));
406
407 if (err)
408 return err;
409
410 return 0;
411}
412
413static int anx78xx_xtal_clk_sel(struct anx78xx *anx78xx)
414{
415 unsigned int value;
416 int err;
417
418 err = regmap_update_bits(anx78xx->map[I2C_IDX_TX_P2],
419 SP_ANALOG_DEBUG2_REG,
420 SP_XTAL_FRQ | SP_FORCE_SW_OFF_BYPASS,
421 SP_XTAL_FRQ_27M);
422 if (err)
423 return err;
424
425 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL3_REG,
426 XTAL_CLK & SP_WAIT_COUNTER_7_0_MASK);
427 if (err)
428 return err;
429
430 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL4_REG,
431 ((XTAL_CLK & 0xff00) >> 2) | (XTAL_CLK / 10));
432 if (err)
433 return err;
434
435 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
436 SP_I2C_GEN_10US_TIMER0_REG, XTAL_CLK & 0xff);
437 if (err)
438 return err;
439
440 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
441 SP_I2C_GEN_10US_TIMER1_REG,
442 (XTAL_CLK & 0xff00) >> 8);
443 if (err)
444 return err;
445
446 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_MISC_CTRL_REG,
447 XTAL_CLK / 10 - 1);
448 if (err)
449 return err;
450
451 err = regmap_read(anx78xx->map[I2C_IDX_RX_P0],
452 SP_HDMI_US_TIMER_CTRL_REG,
453 &value);
454 if (err)
455 return err;
456
457 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0],
458 SP_HDMI_US_TIMER_CTRL_REG,
459 (value & SP_MS_TIMER_MARGIN_10_8_MASK) |
460 ((((XTAL_CLK / 10) >> 1) - 2) << 3));
461 if (err)
462 return err;
463
464 return 0;
465}
466
467static const struct reg_sequence otp_key_protect[] = {
468 { SP_OTP_KEY_PROTECT1_REG, SP_OTP_PSW1 },
469 { SP_OTP_KEY_PROTECT2_REG, SP_OTP_PSW2 },
470 { SP_OTP_KEY_PROTECT3_REG, SP_OTP_PSW3 },
471};
472
473static int anx78xx_tx_initialization(struct anx78xx *anx78xx)
474{
475 int err;
476
477 /* Set terminal resistor to 50 ohm */
478 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL2_REG,
479 0x30);
480 if (err)
481 return err;
482
483 /* Enable aux double diff output */
484 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
485 SP_DP_AUX_CH_CTRL2_REG, 0x08);
486 if (err)
487 return err;
488
489 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
490 SP_DP_HDCP_CTRL_REG, SP_AUTO_EN |
491 SP_AUTO_START);
492 if (err)
493 return err;
494
495 err = regmap_multi_reg_write(anx78xx->map[I2C_IDX_TX_P0],
496 otp_key_protect,
497 ARRAY_SIZE(otp_key_protect));
498 if (err)
499 return err;
500
501 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
502 SP_HDCP_KEY_COMMAND_REG, SP_DISABLE_SYNC_HDCP);
503 if (err)
504 return err;
505
506 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL8_REG,
507 SP_VID_VRES_TH);
508 if (err)
509 return err;
510
511 /*
512 * DP HDCP auto authentication wait timer (when downstream starts to
513 * auth, DP side will wait for this period then do auth automatically)
514 */
515 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_HDCP_AUTO_TIMER_REG,
516 0x00);
517 if (err)
518 return err;
519
520 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
521 SP_DP_HDCP_CTRL_REG, SP_LINK_POLLING);
522 if (err)
523 return err;
524
525 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
526 SP_DP_LINK_DEBUG_CTRL_REG, SP_M_VID_DEBUG);
527 if (err)
528 return err;
529
530 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2],
531 SP_ANALOG_DEBUG2_REG, SP_POWERON_TIME_1P5MS);
532 if (err)
533 return err;
534
535 err = anx78xx_xtal_clk_sel(anx78xx);
536 if (err)
537 return err;
538
539 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_DEFER_CTRL_REG,
540 SP_DEFER_CTRL_EN | 0x0c);
541 if (err)
542 return err;
543
544 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
545 SP_DP_POLLING_CTRL_REG,
546 SP_AUTO_POLLING_DISABLE);
547 if (err)
548 return err;
549
550 /*
551 * Short the link integrity check timer to speed up bstatus
552 * polling for HDCP CTS item 1A-07
553 */
554 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
555 SP_HDCP_LINK_CHECK_TIMER_REG, 0x1d);
556 if (err)
557 return err;
558
559 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
560 SP_DP_MISC_CTRL_REG, SP_EQ_TRAINING_LOOP);
561 if (err)
562 return err;
563
564 /* Power down the main link by default */
565 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
566 SP_DP_ANALOG_POWER_DOWN_REG, SP_CH0_PD);
567 if (err)
568 return err;
569
570 err = anx78xx_link_phy_initialization(anx78xx);
571 if (err)
572 return err;
573
574 /* Gen m_clk with downspreading */
575 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
576 SP_DP_M_CALCULATION_CTRL_REG, SP_M_GEN_CLK_SEL);
577 if (err)
578 return err;
579
580 return 0;
581}
582
583static int anx78xx_enable_interrupts(struct anx78xx *anx78xx)
584{
585 int err;
586
587 /*
588 * BIT0: INT pin assertion polarity: 1 = assert high
589 * BIT1: INT pin output type: 0 = push/pull
590 */
591 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_INT_CTRL_REG, 0x01);
592 if (err)
593 return err;
594
595 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2],
596 SP_COMMON_INT_MASK4_REG, SP_HPD_LOST | SP_HPD_PLUG);
597 if (err)
598 return err;
599
600 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_MASK1_REG,
601 SP_TRAINING_FINISH);
602 if (err)
603 return err;
604
605 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_INT_MASK1_REG,
606 SP_CKDT_CHG | SP_SCDT_CHG);
607 if (err)
608 return err;
609
610 return 0;
611}
612
613static void anx78xx_poweron(struct anx78xx *anx78xx)
614{
615 struct anx78xx_platform_data *pdata = &anx78xx->pdata;
616 int err;
617
618 if (WARN_ON(anx78xx->powered))
619 return;
620
621 if (pdata->dvdd10) {
622 err = regulator_enable(pdata->dvdd10);
623 if (err) {
624 DRM_ERROR("Failed to enable DVDD10 regulator: %d\n",
625 err);
626 return;
627 }
628
629 usleep_range(1000, 2000);
630 }
631
632 gpiod_set_value_cansleep(pdata->gpiod_reset, 1);
633 usleep_range(1000, 2000);
634
635 gpiod_set_value_cansleep(pdata->gpiod_pd, 0);
636 usleep_range(1000, 2000);
637
638 gpiod_set_value_cansleep(pdata->gpiod_reset, 0);
639
640 /* Power on registers module */
641 anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG,
642 SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD | SP_LINK_PD);
643 anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG,
644 SP_REGISTER_PD | SP_TOTAL_PD);
645
646 anx78xx->powered = true;
647}
648
649static void anx78xx_poweroff(struct anx78xx *anx78xx)
650{
651 struct anx78xx_platform_data *pdata = &anx78xx->pdata;
652 int err;
653
654 if (WARN_ON(!anx78xx->powered))
655 return;
656
657 gpiod_set_value_cansleep(pdata->gpiod_reset, 1);
658 usleep_range(1000, 2000);
659
660 gpiod_set_value_cansleep(pdata->gpiod_pd, 1);
661 usleep_range(1000, 2000);
662
663 if (pdata->dvdd10) {
664 err = regulator_disable(pdata->dvdd10);
665 if (err) {
666 DRM_ERROR("Failed to disable DVDD10 regulator: %d\n",
667 err);
668 return;
669 }
670
671 usleep_range(1000, 2000);
672 }
673
674 anx78xx->powered = false;
675}
676
677static int anx78xx_start(struct anx78xx *anx78xx)
678{
679 int err;
680
681 /* Power on all modules */
682 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2],
683 SP_POWERDOWN_CTRL_REG,
684 SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD |
685 SP_LINK_PD);
686
687 err = anx78xx_enable_interrupts(anx78xx);
688 if (err) {
689 DRM_ERROR("Failed to enable interrupts: %d\n", err);
690 goto err_poweroff;
691 }
692
693 err = anx78xx_rx_initialization(anx78xx);
694 if (err) {
695 DRM_ERROR("Failed receiver initialization: %d\n", err);
696 goto err_poweroff;
697 }
698
699 err = anx78xx_tx_initialization(anx78xx);
700 if (err) {
701 DRM_ERROR("Failed transmitter initialization: %d\n", err);
702 goto err_poweroff;
703 }
704
705 /*
706 * This delay seems to help keep the hardware in a good state. Without
707 * it, there are times where it fails silently.
708 */
709 usleep_range(10000, 15000);
710
711 return 0;
712
713err_poweroff:
714 DRM_ERROR("Failed SlimPort transmitter initialization: %d\n", err);
715 anx78xx_poweroff(anx78xx);
716
717 return err;
718}
719
720static int anx78xx_init_pdata(struct anx78xx *anx78xx)
721{
722 struct anx78xx_platform_data *pdata = &anx78xx->pdata;
723 struct device *dev = &anx78xx->client->dev;
724
725 /* 1.0V digital core power regulator */
726 pdata->dvdd10 = devm_regulator_get(dev, "dvdd10");
727 if (IS_ERR(pdata->dvdd10)) {
728 DRM_ERROR("DVDD10 regulator not found\n");
729 return PTR_ERR(pdata->dvdd10);
730 }
731
732 /* GPIO for HPD */
733 pdata->gpiod_hpd = devm_gpiod_get(dev, "hpd", GPIOD_IN);
734 if (IS_ERR(pdata->gpiod_hpd))
735 return PTR_ERR(pdata->gpiod_hpd);
736
737 /* GPIO for chip power down */
738 pdata->gpiod_pd = devm_gpiod_get(dev, "pd", GPIOD_OUT_HIGH);
739 if (IS_ERR(pdata->gpiod_pd))
740 return PTR_ERR(pdata->gpiod_pd);
741
742 /* GPIO for chip reset */
743 pdata->gpiod_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
744
745 return PTR_ERR_OR_ZERO(pdata->gpiod_reset);
746}
747
748static int anx78xx_dp_link_training(struct anx78xx *anx78xx)
749{
750 u8 dp_bw, value;
751 int err;
752
753 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_HDMI_MUTE_CTRL_REG,
754 0x0);
755 if (err)
756 return err;
757
758 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2],
759 SP_POWERDOWN_CTRL_REG,
760 SP_TOTAL_PD);
761 if (err)
762 return err;
763
764 err = drm_dp_dpcd_readb(&anx78xx->aux, DP_MAX_LINK_RATE, &dp_bw);
765 if (err < 0)
766 return err;
767
768 switch (dp_bw) {
769 case DP_LINK_BW_1_62:
770 case DP_LINK_BW_2_7:
771 case DP_LINK_BW_5_4:
772 break;
773
774 default:
775 DRM_DEBUG_KMS("DP bandwidth (%#02x) not supported\n", dp_bw);
776 return -EINVAL;
777 }
778
779 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG,
780 SP_VIDEO_MUTE);
781 if (err)
782 return err;
783
784 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2],
785 SP_VID_CTRL1_REG, SP_VIDEO_EN);
786 if (err)
787 return err;
788
789 /* Get DPCD info */
790 err = drm_dp_dpcd_read(&anx78xx->aux, DP_DPCD_REV,
791 &anx78xx->dpcd, DP_RECEIVER_CAP_SIZE);
792 if (err < 0) {
793 DRM_ERROR("Failed to read DPCD: %d\n", err);
794 return err;
795 }
796
797 /* Clear channel x SERDES power down */
798 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
799 SP_DP_ANALOG_POWER_DOWN_REG, SP_CH0_PD);
800 if (err)
801 return err;
802
803 /* Check link capabilities */
804 err = drm_dp_link_probe(&anx78xx->aux, &anx78xx->link);
805 if (err < 0) {
806 DRM_ERROR("Failed to probe link capabilities: %d\n", err);
807 return err;
808 }
809
810 /* Power up the sink */
811 err = drm_dp_link_power_up(&anx78xx->aux, &anx78xx->link);
812 if (err < 0) {
813 DRM_ERROR("Failed to power up DisplayPort link: %d\n", err);
814 return err;
815 }
816
817 /* Possibly enable downspread on the sink */
818 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
819 SP_DP_DOWNSPREAD_CTRL1_REG, 0);
820 if (err)
821 return err;
822
823 if (anx78xx->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5) {
824 DRM_DEBUG("Enable downspread on the sink\n");
825 /* 4000PPM */
826 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
827 SP_DP_DOWNSPREAD_CTRL1_REG, 8);
828 if (err)
829 return err;
830
831 err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_DOWNSPREAD_CTRL,
832 DP_SPREAD_AMP_0_5);
833 if (err < 0)
834 return err;
835 } else {
836 err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_DOWNSPREAD_CTRL, 0);
837 if (err < 0)
838 return err;
839 }
840
841 /* Set the lane count and the link rate on the sink */
842 if (drm_dp_enhanced_frame_cap(anx78xx->dpcd))
843 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
844 SP_DP_SYSTEM_CTRL_BASE + 4,
845 SP_ENHANCED_MODE);
846 else
847 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
848 SP_DP_SYSTEM_CTRL_BASE + 4,
849 SP_ENHANCED_MODE);
850 if (err)
851 return err;
852
853 value = drm_dp_link_rate_to_bw_code(anx78xx->link.rate);
854 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
855 SP_DP_MAIN_LINK_BW_SET_REG, value);
856 if (err)
857 return err;
858
859 err = drm_dp_link_configure(&anx78xx->aux, &anx78xx->link);
860 if (err < 0) {
861 DRM_ERROR("Failed to configure DisplayPort link: %d\n", err);
862 return err;
863 }
864
865 /* Start training on the source */
866 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_LT_CTRL_REG,
867 SP_LT_EN);
868 if (err)
869 return err;
870
871 return 0;
872}
873
874static int anx78xx_config_dp_output(struct anx78xx *anx78xx)
875{
876 int err;
877
878 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG,
879 SP_VIDEO_MUTE);
880 if (err)
881 return err;
882
883 /* Enable DP output */
884 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG,
885 SP_VIDEO_EN);
886 if (err)
887 return err;
888
889 return 0;
890}
891
892static int anx78xx_send_video_infoframe(struct anx78xx *anx78xx,
893 struct hdmi_avi_infoframe *frame)
894{
895 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
896 int err;
897
898 err = hdmi_avi_infoframe_pack(frame, buffer, sizeof(buffer));
899 if (err < 0) {
900 DRM_ERROR("Failed to pack AVI infoframe: %d\n", err);
901 return err;
902 }
903
904 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
905 SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_EN);
906 if (err)
907 return err;
908
909 err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P2],
910 SP_INFOFRAME_AVI_DB1_REG, buffer,
911 frame->length);
912 if (err)
913 return err;
914
915 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
916 SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_UD);
917 if (err)
918 return err;
919
920 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
921 SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_EN);
922 if (err)
923 return err;
924
925 return 0;
926}
927
928static int anx78xx_get_downstream_info(struct anx78xx *anx78xx)
929{
930 u8 value;
931 int err;
932
933 err = drm_dp_dpcd_readb(&anx78xx->aux, DP_SINK_COUNT, &value);
934 if (err < 0) {
935 DRM_ERROR("Get sink count failed %d\n", err);
936 return err;
937 }
938
939 if (!DP_GET_SINK_COUNT(value)) {
940 DRM_ERROR("Downstream disconnected\n");
941 return -EIO;
942 }
943
944 return 0;
945}
946
947static int anx78xx_get_modes(struct drm_connector *connector)
948{
949 struct anx78xx *anx78xx = connector_to_anx78xx(connector);
950 int err, num_modes = 0;
951
952 if (WARN_ON(!anx78xx->powered))
953 return 0;
954
955 if (anx78xx->edid)
956 return drm_add_edid_modes(connector, anx78xx->edid);
957
958 mutex_lock(&anx78xx->lock);
959
960 err = anx78xx_get_downstream_info(anx78xx);
961 if (err) {
962 DRM_ERROR("Failed to get downstream info: %d\n", err);
963 goto unlock;
964 }
965
966 anx78xx->edid = drm_get_edid(connector, &anx78xx->aux.ddc);
967 if (!anx78xx->edid) {
968 DRM_ERROR("Failed to read EDID\n");
969 goto unlock;
970 }
971
972 err = drm_mode_connector_update_edid_property(connector,
973 anx78xx->edid);
974 if (err) {
975 DRM_ERROR("Failed to update EDID property: %d\n", err);
976 goto unlock;
977 }
978
979 num_modes = drm_add_edid_modes(connector, anx78xx->edid);
980 /* Store the ELD */
981 drm_edid_to_eld(connector, anx78xx->edid);
982
983unlock:
984 mutex_unlock(&anx78xx->lock);
985
986 return num_modes;
987}
988
989static struct drm_encoder *anx78xx_best_encoder(struct drm_connector *connector)
990{
991 struct anx78xx *anx78xx = connector_to_anx78xx(connector);
992
993 return anx78xx->bridge.encoder;
994}
995
996static const struct drm_connector_helper_funcs anx78xx_connector_helper_funcs = {
997 .get_modes = anx78xx_get_modes,
998 .best_encoder = anx78xx_best_encoder,
999};
1000
1001static enum drm_connector_status anx78xx_detect(struct drm_connector *connector,
1002 bool force)
1003{
1004 struct anx78xx *anx78xx = connector_to_anx78xx(connector);
1005
1006 if (!gpiod_get_value(anx78xx->pdata.gpiod_hpd))
1007 return connector_status_disconnected;
1008
1009 return connector_status_connected;
1010}
1011
1012static void anx78xx_connector_destroy(struct drm_connector *connector)
1013{
1014 drm_connector_cleanup(connector);
1015}
1016
1017static const struct drm_connector_funcs anx78xx_connector_funcs = {
1018 .dpms = drm_atomic_helper_connector_dpms,
1019 .fill_modes = drm_helper_probe_single_connector_modes,
1020 .detect = anx78xx_detect,
1021 .destroy = anx78xx_connector_destroy,
1022 .reset = drm_atomic_helper_connector_reset,
1023 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1024 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1025};
1026
1027static int anx78xx_bridge_attach(struct drm_bridge *bridge)
1028{
1029 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
1030 int err;
1031
1032 if (!bridge->encoder) {
1033 DRM_ERROR("Parent encoder object not found");
1034 return -ENODEV;
1035 }
1036
1037 /* Register aux channel */
1038 anx78xx->aux.name = "DP-AUX";
1039 anx78xx->aux.dev = &anx78xx->client->dev;
1040 anx78xx->aux.transfer = anx78xx_aux_transfer;
1041
1042 err = drm_dp_aux_register(&anx78xx->aux);
1043 if (err < 0) {
1044 DRM_ERROR("Failed to register aux channel: %d\n", err);
1045 return err;
1046 }
1047
1048 err = drm_connector_init(bridge->dev, &anx78xx->connector,
1049 &anx78xx_connector_funcs,
1050 DRM_MODE_CONNECTOR_DisplayPort);
1051 if (err) {
1052 DRM_ERROR("Failed to initialize connector: %d\n", err);
1053 return err;
1054 }
1055
1056 drm_connector_helper_add(&anx78xx->connector,
1057 &anx78xx_connector_helper_funcs);
1058
1059 err = drm_connector_register(&anx78xx->connector);
1060 if (err) {
1061 DRM_ERROR("Failed to register connector: %d\n", err);
1062 return err;
1063 }
1064
1065 anx78xx->connector.polled = DRM_CONNECTOR_POLL_HPD;
1066
1067 err = drm_mode_connector_attach_encoder(&anx78xx->connector,
1068 bridge->encoder);
1069 if (err) {
1070 DRM_ERROR("Failed to link up connector to encoder: %d\n", err);
1071 return err;
1072 }
1073
1074 return 0;
1075}
1076
1077static bool anx78xx_bridge_mode_fixup(struct drm_bridge *bridge,
1078 const struct drm_display_mode *mode,
1079 struct drm_display_mode *adjusted_mode)
1080{
1081 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1082 return false;
1083
1084 /* Max 1200p at 5.4 Ghz, one lane */
1085 if (mode->clock > 154000)
1086 return false;
1087
1088 return true;
1089}
1090
1091static void anx78xx_bridge_disable(struct drm_bridge *bridge)
1092{
1093 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
1094
1095 /* Power off all modules except configuration registers access */
1096 anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG,
1097 SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD | SP_LINK_PD);
1098}
1099
1100static void anx78xx_bridge_mode_set(struct drm_bridge *bridge,
1101 struct drm_display_mode *mode,
1102 struct drm_display_mode *adjusted_mode)
1103{
1104 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
1105 struct hdmi_avi_infoframe frame;
1106 int err;
1107
1108 if (WARN_ON(!anx78xx->powered))
1109 return;
1110
1111 mutex_lock(&anx78xx->lock);
1112
1113 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, adjusted_mode);
1114 if (err) {
1115 DRM_ERROR("Failed to setup AVI infoframe: %d\n", err);
1116 goto unlock;
1117 }
1118
1119 err = anx78xx_send_video_infoframe(anx78xx, &frame);
1120 if (err)
1121 DRM_ERROR("Failed to send AVI infoframe: %d\n", err);
1122
1123unlock:
1124 mutex_unlock(&anx78xx->lock);
1125}
1126
1127static void anx78xx_bridge_enable(struct drm_bridge *bridge)
1128{
1129 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
1130 int err;
1131
1132 err = anx78xx_start(anx78xx);
1133 if (err) {
1134 DRM_ERROR("Failed to initialize: %d\n", err);
1135 return;
1136 }
1137
1138 err = anx78xx_set_hpd(anx78xx);
1139 if (err)
1140 DRM_ERROR("Failed to set HPD: %d\n", err);
1141}
1142
1143static const struct drm_bridge_funcs anx78xx_bridge_funcs = {
1144 .attach = anx78xx_bridge_attach,
1145 .mode_fixup = anx78xx_bridge_mode_fixup,
1146 .disable = anx78xx_bridge_disable,
1147 .mode_set = anx78xx_bridge_mode_set,
1148 .enable = anx78xx_bridge_enable,
1149};
1150
1151static irqreturn_t anx78xx_hpd_threaded_handler(int irq, void *data)
1152{
1153 struct anx78xx *anx78xx = data;
1154 int err;
1155
1156 if (anx78xx->powered)
1157 return IRQ_HANDLED;
1158
1159 mutex_lock(&anx78xx->lock);
1160
1161 /* Cable is pulled, power on the chip */
1162 anx78xx_poweron(anx78xx);
1163
1164 err = anx78xx_enable_interrupts(anx78xx);
1165 if (err)
1166 DRM_ERROR("Failed to enable interrupts: %d\n", err);
1167
1168 mutex_unlock(&anx78xx->lock);
1169
1170 return IRQ_HANDLED;
1171}
1172
1173static int anx78xx_handle_dp_int_1(struct anx78xx *anx78xx, u8 irq)
1174{
1175 int err;
1176
1177 DRM_DEBUG_KMS("Handle DP interrupt 1: %02x\n", irq);
1178
1179 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_STATUS1_REG,
1180 irq);
1181 if (err)
1182 return err;
1183
1184 if (irq & SP_TRAINING_FINISH) {
1185 DRM_DEBUG_KMS("IRQ: hardware link training finished\n");
1186 err = anx78xx_config_dp_output(anx78xx);
1187 }
1188
1189 return err;
1190}
1191
1192static bool anx78xx_handle_common_int_4(struct anx78xx *anx78xx, u8 irq)
1193{
1194 bool event = false;
1195 int err;
1196
1197 DRM_DEBUG_KMS("Handle common interrupt 4: %02x\n", irq);
1198
1199 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2],
1200 SP_COMMON_INT_STATUS4_REG, irq);
1201 if (err) {
1202 DRM_ERROR("Failed to write SP_COMMON_INT_STATUS4 %d\n", err);
1203 return event;
1204 }
1205
1206 if (irq & SP_HPD_LOST) {
1207 DRM_DEBUG_KMS("IRQ: Hot plug detect - cable is pulled out\n");
1208 event = true;
1209 anx78xx_poweroff(anx78xx);
1210 /* Free cached EDID */
1211 kfree(anx78xx->edid);
1212 anx78xx->edid = NULL;
1213 } else if (irq & SP_HPD_PLUG) {
1214 DRM_DEBUG_KMS("IRQ: Hot plug detect - cable plug\n");
1215 event = true;
1216 }
1217
1218 return event;
1219}
1220
1221static void anx78xx_handle_hdmi_int_1(struct anx78xx *anx78xx, u8 irq)
1222{
1223 unsigned int value;
1224 int err;
1225
1226 DRM_DEBUG_KMS("Handle HDMI interrupt 1: %02x\n", irq);
1227
1228 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_INT_STATUS1_REG,
1229 irq);
1230 if (err) {
1231 DRM_ERROR("Write HDMI int 1 failed: %d\n", err);
1232 return;
1233 }
1234
1235 if ((irq & SP_CKDT_CHG) || (irq & SP_SCDT_CHG)) {
1236 DRM_DEBUG_KMS("IRQ: HDMI input detected\n");
1237
1238 err = regmap_read(anx78xx->map[I2C_IDX_RX_P0],
1239 SP_SYSTEM_STATUS_REG, &value);
1240 if (err) {
1241 DRM_ERROR("Read system status reg failed: %d\n", err);
1242 return;
1243 }
1244
1245 if (!(value & SP_TMDS_CLOCK_DET)) {
1246 DRM_DEBUG_KMS("IRQ: *** Waiting for HDMI clock ***\n");
1247 return;
1248 }
1249
1250 if (!(value & SP_TMDS_DE_DET)) {
1251 DRM_DEBUG_KMS("IRQ: *** Waiting for HDMI signal ***\n");
1252 return;
1253 }
1254
1255 err = anx78xx_dp_link_training(anx78xx);
1256 if (err)
1257 DRM_ERROR("Failed to start link training: %d\n", err);
1258 }
1259}
1260
1261static irqreturn_t anx78xx_intp_threaded_handler(int unused, void *data)
1262{
1263 struct anx78xx *anx78xx = data;
1264 bool event = false;
1265 unsigned int irq;
1266 int err;
1267
1268 mutex_lock(&anx78xx->lock);
1269
1270 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_STATUS1_REG,
1271 &irq);
1272 if (err) {
1273 DRM_ERROR("Failed to read DP interrupt 1 status: %d\n", err);
1274 goto unlock;
1275 }
1276
1277 if (irq)
1278 anx78xx_handle_dp_int_1(anx78xx, irq);
1279
1280 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2],
1281 SP_COMMON_INT_STATUS4_REG, &irq);
1282 if (err) {
1283 DRM_ERROR("Failed to read common interrupt 4 status: %d\n",
1284 err);
1285 goto unlock;
1286 }
1287
1288 if (irq)
1289 event = anx78xx_handle_common_int_4(anx78xx, irq);
1290
1291 /* Make sure we are still powered after handle HPD events */
1292 if (!anx78xx->powered)
1293 goto unlock;
1294
1295 err = regmap_read(anx78xx->map[I2C_IDX_RX_P0], SP_INT_STATUS1_REG,
1296 &irq);
1297 if (err) {
1298 DRM_ERROR("Failed to read HDMI int 1 status: %d\n", err);
1299 goto unlock;
1300 }
1301
1302 if (irq)
1303 anx78xx_handle_hdmi_int_1(anx78xx, irq);
1304
1305unlock:
1306 mutex_unlock(&anx78xx->lock);
1307
1308 if (event)
1309 drm_helper_hpd_irq_event(anx78xx->connector.dev);
1310
1311 return IRQ_HANDLED;
1312}
1313
1314static void unregister_i2c_dummy_clients(struct anx78xx *anx78xx)
1315{
1316 unsigned int i;
1317
1318 for (i = 0; i < ARRAY_SIZE(anx78xx->i2c_dummy); i++)
1319 if (anx78xx->i2c_dummy[i])
1320 i2c_unregister_device(anx78xx->i2c_dummy[i]);
1321}
1322
1323static const struct regmap_config anx78xx_regmap_config = {
1324 .reg_bits = 8,
1325 .val_bits = 8,
1326};
1327
1328static const u16 anx78xx_chipid_list[] = {
1329 0x7812,
1330 0x7814,
1331 0x7818,
1332};
1333
1334static int anx78xx_i2c_probe(struct i2c_client *client,
1335 const struct i2c_device_id *id)
1336{
1337 struct anx78xx *anx78xx;
1338 struct anx78xx_platform_data *pdata;
1339 unsigned int i, idl, idh, version;
1340 bool found = false;
1341 int err;
1342
1343 anx78xx = devm_kzalloc(&client->dev, sizeof(*anx78xx), GFP_KERNEL);
1344 if (!anx78xx)
1345 return -ENOMEM;
1346
1347 pdata = &anx78xx->pdata;
1348
1349 mutex_init(&anx78xx->lock);
1350
1351#if IS_ENABLED(CONFIG_OF)
1352 anx78xx->bridge.of_node = client->dev.of_node;
1353#endif
1354
1355 anx78xx->client = client;
1356 i2c_set_clientdata(client, anx78xx);
1357
1358 err = anx78xx_init_pdata(anx78xx);
1359 if (err) {
1360 DRM_ERROR("Failed to initialize pdata: %d\n", err);
1361 return err;
1362 }
1363
1364 pdata->hpd_irq = gpiod_to_irq(pdata->gpiod_hpd);
1365 if (pdata->hpd_irq < 0) {
1366 DRM_ERROR("Failed to get HPD IRQ: %d\n", pdata->hpd_irq);
1367 return -ENODEV;
1368 }
1369
1370 pdata->intp_irq = client->irq;
1371 if (!pdata->intp_irq) {
1372 DRM_ERROR("Failed to get CABLE_DET and INTP IRQ\n");
1373 return -ENODEV;
1374 }
1375
1376 /* Map slave addresses of ANX7814 */
1377 for (i = 0; i < I2C_NUM_ADDRESSES; i++) {
1378 anx78xx->i2c_dummy[i] = i2c_new_dummy(client->adapter,
1379 anx78xx_i2c_addresses[i] >> 1);
1380 if (!anx78xx->i2c_dummy[i]) {
1381 err = -ENOMEM;
1382 DRM_ERROR("Failed to reserve I2C bus %02x\n",
1383 anx78xx_i2c_addresses[i]);
1384 goto err_unregister_i2c;
1385 }
1386
1387 anx78xx->map[i] = devm_regmap_init_i2c(anx78xx->i2c_dummy[i],
1388 &anx78xx_regmap_config);
1389 if (IS_ERR(anx78xx->map[i])) {
1390 err = PTR_ERR(anx78xx->map[i]);
1391 DRM_ERROR("Failed regmap initialization %02x\n",
1392 anx78xx_i2c_addresses[i]);
1393 goto err_unregister_i2c;
1394 }
1395 }
1396
1397 /* Look for supported chip ID */
1398 anx78xx_poweron(anx78xx);
1399
1400 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_IDL_REG,
1401 &idl);
1402 if (err)
1403 goto err_poweroff;
1404
1405 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_IDH_REG,
1406 &idh);
1407 if (err)
1408 goto err_poweroff;
1409
1410 anx78xx->chipid = (u8)idl | ((u8)idh << 8);
1411
1412 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_VERSION_REG,
1413 &version);
1414 if (err)
1415 goto err_poweroff;
1416
1417 for (i = 0; i < ARRAY_SIZE(anx78xx_chipid_list); i++) {
1418 if (anx78xx->chipid == anx78xx_chipid_list[i]) {
1419 DRM_INFO("Found ANX%x (ver. %d) SlimPort Transmitter\n",
1420 anx78xx->chipid, version);
1421 found = true;
1422 break;
1423 }
1424 }
1425
1426 if (!found) {
1427 DRM_ERROR("ANX%x (ver. %d) not supported by this driver\n",
1428 anx78xx->chipid, version);
1429 err = -ENODEV;
1430 goto err_poweroff;
1431 }
1432
1433 err = devm_request_threaded_irq(&client->dev, pdata->hpd_irq, NULL,
1434 anx78xx_hpd_threaded_handler,
1435 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1436 "anx78xx-hpd", anx78xx);
1437 if (err) {
1438 DRM_ERROR("Failed to request CABLE_DET threaded IRQ: %d\n",
1439 err);
1440 goto err_poweroff;
1441 }
1442
1443 err = devm_request_threaded_irq(&client->dev, pdata->intp_irq, NULL,
1444 anx78xx_intp_threaded_handler,
1445 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1446 "anx78xx-intp", anx78xx);
1447 if (err) {
1448 DRM_ERROR("Failed to request INTP threaded IRQ: %d\n", err);
1449 goto err_poweroff;
1450 }
1451
1452 anx78xx->bridge.funcs = &anx78xx_bridge_funcs;
1453
1454 err = drm_bridge_add(&anx78xx->bridge);
1455 if (err < 0) {
1456 DRM_ERROR("Failed to add drm bridge: %d\n", err);
1457 goto err_poweroff;
1458 }
1459
1460 /* If cable is pulled out, just poweroff and wait for HPD event */
1461 if (!gpiod_get_value(anx78xx->pdata.gpiod_hpd))
1462 anx78xx_poweroff(anx78xx);
1463
1464 return 0;
1465
1466err_poweroff:
1467 anx78xx_poweroff(anx78xx);
1468
1469err_unregister_i2c:
1470 unregister_i2c_dummy_clients(anx78xx);
1471 return err;
1472}
1473
1474static int anx78xx_i2c_remove(struct i2c_client *client)
1475{
1476 struct anx78xx *anx78xx = i2c_get_clientdata(client);
1477
1478 drm_bridge_remove(&anx78xx->bridge);
1479
1480 unregister_i2c_dummy_clients(anx78xx);
1481
1482 kfree(anx78xx->edid);
1483
1484 return 0;
1485}
1486
1487static const struct i2c_device_id anx78xx_id[] = {
1488 { "anx7814", 0 },
1489 { /* sentinel */ }
1490};
1491MODULE_DEVICE_TABLE(i2c, anx78xx_id);
1492
1493#if IS_ENABLED(CONFIG_OF)
1494static const struct of_device_id anx78xx_match_table[] = {
1495 { .compatible = "analogix,anx7814", },
1496 { /* sentinel */ },
1497};
1498MODULE_DEVICE_TABLE(of, anx78xx_match_table);
1499#endif
1500
1501static struct i2c_driver anx78xx_driver = {
1502 .driver = {
1503 .name = "anx7814",
1504 .of_match_table = of_match_ptr(anx78xx_match_table),
1505 },
1506 .probe = anx78xx_i2c_probe,
1507 .remove = anx78xx_i2c_remove,
1508 .id_table = anx78xx_id,
1509};
1510module_i2c_driver(anx78xx_driver);
1511
1512MODULE_DESCRIPTION("ANX78xx SlimPort Transmitter driver");
1513MODULE_AUTHOR("Enric Balletbo i Serra <enric.balletbo@collabora.com>");
1514MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/bridge/analogix-anx78xx.h b/drivers/gpu/drm/bridge/analogix-anx78xx.h
new file mode 100644
index 000000000000..38753c870137
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix-anx78xx.h
@@ -0,0 +1,719 @@
1/*
2 * Copyright(c) 2016, Analogix Semiconductor. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 */
14
15#ifndef __ANX78xx_H
16#define __ANX78xx_H
17
18#define TX_P0 0x70
19#define TX_P1 0x7a
20#define TX_P2 0x72
21
22#define RX_P0 0x7e
23#define RX_P1 0x80
24
25/***************************************************************/
26/* Register definition of device address 0x7e */
27/***************************************************************/
28
29/*
30 * System Control and Status
31 */
32
33/* Software Reset Register 1 */
34#define SP_SOFTWARE_RESET1_REG 0x11
35#define SP_VIDEO_RST BIT(4)
36#define SP_HDCP_MAN_RST BIT(2)
37#define SP_TMDS_RST BIT(1)
38#define SP_SW_MAN_RST BIT(0)
39
40/* System Status Register */
41#define SP_SYSTEM_STATUS_REG 0x14
42#define SP_TMDS_CLOCK_DET BIT(1)
43#define SP_TMDS_DE_DET BIT(0)
44
45/* HDMI Status Register */
46#define SP_HDMI_STATUS_REG 0x15
47#define SP_HDMI_AUD_LAYOUT BIT(3)
48#define SP_HDMI_DET BIT(0)
49# define SP_DVI_MODE 0
50# define SP_HDMI_MODE 1
51
52/* HDMI Mute Control Register */
53#define SP_HDMI_MUTE_CTRL_REG 0x16
54#define SP_AUD_MUTE BIT(1)
55#define SP_VID_MUTE BIT(0)
56
57/* System Power Down Register 1 */
58#define SP_SYSTEM_POWER_DOWN1_REG 0x18
59#define SP_PWDN_CTRL BIT(0)
60
61/*
62 * Audio and Video Auto Control
63 */
64
65/* Auto Audio and Video Control register */
66#define SP_AUDVID_CTRL_REG 0x20
67#define SP_AVC_OE BIT(7)
68#define SP_AAC_OE BIT(6)
69#define SP_AVC_EN BIT(1)
70#define SP_AAC_EN BIT(0)
71
72/* Audio Exception Enable Registers */
73#define SP_AUD_EXCEPTION_ENABLE_BASE (0x24 - 1)
74/* Bits for Audio Exception Enable Register 3 */
75#define SP_AEC_EN21 BIT(5)
76
77/*
78 * Interrupt
79 */
80
81/* Interrupt Status Register 1 */
82#define SP_INT_STATUS1_REG 0x31
83/* Bits for Interrupt Status Register 1 */
84#define SP_HDMI_DVI BIT(7)
85#define SP_CKDT_CHG BIT(6)
86#define SP_SCDT_CHG BIT(5)
87#define SP_PCLK_CHG BIT(4)
88#define SP_PLL_UNLOCK BIT(3)
89#define SP_CABLE_PLUG_CHG BIT(2)
90#define SP_SET_MUTE BIT(1)
91#define SP_SW_INTR BIT(0)
92/* Bits for Interrupt Status Register 2 */
93#define SP_HDCP_ERR BIT(5)
94#define SP_AUDIO_SAMPLE_CHG BIT(0) /* undocumented */
95/* Bits for Interrupt Status Register 3 */
96#define SP_AUD_MODE_CHG BIT(0)
97/* Bits for Interrupt Status Register 5 */
98#define SP_AUDIO_RCV BIT(0)
99/* Bits for Interrupt Status Register 6 */
100#define SP_INT_STATUS6_REG 0x36
101#define SP_CTS_RCV BIT(7)
102#define SP_NEW_AUD_PKT BIT(4)
103#define SP_NEW_AVI_PKT BIT(1)
104#define SP_NEW_CP_PKT BIT(0)
105/* Bits for Interrupt Status Register 7 */
106#define SP_NO_VSI BIT(7)
107#define SP_NEW_VS BIT(4)
108
109/* Interrupt Mask 1 Status Registers */
110#define SP_INT_MASK1_REG 0x41
111
112/* HDMI US TIMER Control Register */
113#define SP_HDMI_US_TIMER_CTRL_REG 0x49
114#define SP_MS_TIMER_MARGIN_10_8_MASK 0x07
115
116/*
117 * TMDS Control
118 */
119
120/* TMDS Control Registers */
121#define SP_TMDS_CTRL_BASE (0x50 - 1)
122/* Bits for TMDS Control Register 7 */
123#define SP_PD_RT BIT(0)
124
125/*
126 * Video Control
127 */
128
129/* Video Status Register */
130#define SP_VIDEO_STATUS_REG 0x70
131#define SP_COLOR_DEPTH_MASK 0xf0
132#define SP_COLOR_DEPTH_SHIFT 4
133# define SP_COLOR_DEPTH_MODE_LEGACY 0x00
134# define SP_COLOR_DEPTH_MODE_24BIT 0x04
135# define SP_COLOR_DEPTH_MODE_30BIT 0x05
136# define SP_COLOR_DEPTH_MODE_36BIT 0x06
137# define SP_COLOR_DEPTH_MODE_48BIT 0x07
138
139/* Video Data Range Control Register */
140#define SP_VID_DATA_RANGE_CTRL_REG 0x83
141#define SP_R2Y_INPUT_LIMIT BIT(1)
142
143/* Pixel Clock High Resolution Counter Registers */
144#define SP_PCLK_HIGHRES_CNT_BASE (0x8c - 1)
145
146/*
147 * Audio Control
148 */
149
150/* Number of Audio Channels Status Registers */
151#define SP_AUD_CH_STATUS_REG_NUM 6
152
153/* Audio IN S/PDIF Channel Status Registers */
154#define SP_AUD_SPDIF_CH_STATUS_BASE 0xc7
155
156/* Audio IN S/PDIF Channel Status Register 4 */
157#define SP_FS_FREQ_MASK 0x0f
158# define SP_FS_FREQ_44100HZ 0x00
159# define SP_FS_FREQ_48000HZ 0x02
160# define SP_FS_FREQ_32000HZ 0x03
161# define SP_FS_FREQ_88200HZ 0x08
162# define SP_FS_FREQ_96000HZ 0x0a
163# define SP_FS_FREQ_176400HZ 0x0c
164# define SP_FS_FREQ_192000HZ 0x0e
165
166/*
167 * Micellaneous Control Block
168 */
169
170/* CHIP Control Register */
171#define SP_CHIP_CTRL_REG 0xe3
172#define SP_MAN_HDMI5V_DET BIT(3)
173#define SP_PLLLOCK_CKDT_EN BIT(2)
174#define SP_ANALOG_CKDT_EN BIT(1)
175#define SP_DIGITAL_CKDT_EN BIT(0)
176
177/* Packet Receiving Status Register */
178#define SP_PACKET_RECEIVING_STATUS_REG 0xf3
179#define SP_AVI_RCVD BIT(5)
180#define SP_VSI_RCVD BIT(1)
181
182/***************************************************************/
183/* Register definition of device address 0x80 */
184/***************************************************************/
185
186/* HDCP BCAPS Shadow Register */
187#define SP_HDCP_BCAPS_SHADOW_REG 0x2a
188#define SP_BCAPS_REPEATER BIT(5)
189
190/* HDCP Status Register */
191#define SP_RX_HDCP_STATUS_REG 0x3f
192#define SP_AUTH_EN BIT(4)
193
194/*
195 * InfoFrame and Control Packet Registers
196 */
197
198/* AVI InfoFrame packet checksum */
199#define SP_AVI_INFOFRAME_CHECKSUM 0xa3
200
201/* AVI InfoFrame Registers */
202#define SP_AVI_INFOFRAME_DATA_BASE 0xa4
203
204#define SP_AVI_COLOR_F_MASK 0x60
205#define SP_AVI_COLOR_F_SHIFT 5
206
207/* Audio InfoFrame Registers */
208#define SP_AUD_INFOFRAME_DATA_BASE 0xc4
209#define SP_AUD_INFOFRAME_LAYOUT_MASK 0x0f
210
211/* MPEG/HDMI Vendor Specific InfoFrame Packet type code */
212#define SP_MPEG_VS_INFOFRAME_TYPE_REG 0xe0
213
214/* MPEG/HDMI Vendor Specific InfoFrame Packet length */
215#define SP_MPEG_VS_INFOFRAME_LEN_REG 0xe2
216
217/* MPEG/HDMI Vendor Specific InfoFrame Packet version number */
218#define SP_MPEG_VS_INFOFRAME_VER_REG 0xe1
219
220/* MPEG/HDMI Vendor Specific InfoFrame Packet content */
221#define SP_MPEG_VS_INFOFRAME_DATA_BASE 0xe4
222
223/* General Control Packet Register */
224#define SP_GENERAL_CTRL_PACKET_REG 0x9f
225#define SP_CLEAR_AVMUTE BIT(4)
226#define SP_SET_AVMUTE BIT(0)
227
228/***************************************************************/
229/* Register definition of device address 0x70 */
230/***************************************************************/
231
232/* HDCP Status Register */
233#define SP_TX_HDCP_STATUS_REG 0x00
234#define SP_AUTH_FAIL BIT(5)
235#define SP_AUTHEN_PASS BIT(1)
236
237/* HDCP Control Register 0 */
238#define SP_HDCP_CTRL0_REG 0x01
239#define SP_RX_REPEATER BIT(6)
240#define SP_RE_AUTH BIT(5)
241#define SP_SW_AUTH_OK BIT(4)
242#define SP_HARD_AUTH_EN BIT(3)
243#define SP_HDCP_ENC_EN BIT(2)
244#define SP_BKSV_SRM_PASS BIT(1)
245#define SP_KSVLIST_VLD BIT(0)
246/* HDCP Function Enabled */
247#define SP_HDCP_FUNCTION_ENABLED (BIT(0) | BIT(1) | BIT(2) | BIT(3))
248
249/* HDCP Receiver BSTATUS Register 0 */
250#define SP_HDCP_RX_BSTATUS0_REG 0x1b
251/* HDCP Receiver BSTATUS Register 1 */
252#define SP_HDCP_RX_BSTATUS1_REG 0x1c
253
254/* HDCP Embedded "Blue Screen" Content Registers */
255#define SP_HDCP_VID0_BLUE_SCREEN_REG 0x2c
256#define SP_HDCP_VID1_BLUE_SCREEN_REG 0x2d
257#define SP_HDCP_VID2_BLUE_SCREEN_REG 0x2e
258
259/* HDCP Wait R0 Timing Register */
260#define SP_HDCP_WAIT_R0_TIME_REG 0x40
261
262/* HDCP Link Integrity Check Timer Register */
263#define SP_HDCP_LINK_CHECK_TIMER_REG 0x41
264
265/* HDCP Repeater Ready Wait Timer Register */
266#define SP_HDCP_RPTR_RDY_WAIT_TIME_REG 0x42
267
268/* HDCP Auto Timer Register */
269#define SP_HDCP_AUTO_TIMER_REG 0x51
270
271/* HDCP Key Status Register */
272#define SP_HDCP_KEY_STATUS_REG 0x5e
273
274/* HDCP Key Command Register */
275#define SP_HDCP_KEY_COMMAND_REG 0x5f
276#define SP_DISABLE_SYNC_HDCP BIT(2)
277
278/* OTP Memory Key Protection Registers */
279#define SP_OTP_KEY_PROTECT1_REG 0x60
280#define SP_OTP_KEY_PROTECT2_REG 0x61
281#define SP_OTP_KEY_PROTECT3_REG 0x62
282#define SP_OTP_PSW1 0xa2
283#define SP_OTP_PSW2 0x7e
284#define SP_OTP_PSW3 0xc6
285
286/* DP System Control Registers */
287#define SP_DP_SYSTEM_CTRL_BASE (0x80 - 1)
288/* Bits for DP System Control Register 2 */
289#define SP_CHA_STA BIT(2)
290/* Bits for DP System Control Register 3 */
291#define SP_HPD_STATUS BIT(6)
292#define SP_STRM_VALID BIT(2)
293/* Bits for DP System Control Register 4 */
294#define SP_ENHANCED_MODE BIT(3)
295
296/* DP Video Control Register */
297#define SP_DP_VIDEO_CTRL_REG 0x84
298#define SP_COLOR_F_MASK 0x06
299#define SP_COLOR_F_SHIFT 1
300#define SP_BPC_MASK 0xe0
301#define SP_BPC_SHIFT 5
302# define SP_BPC_6BITS 0x00
303# define SP_BPC_8BITS 0x01
304# define SP_BPC_10BITS 0x02
305# define SP_BPC_12BITS 0x03
306
307/* DP Audio Control Register */
308#define SP_DP_AUDIO_CTRL_REG 0x87
309#define SP_AUD_EN BIT(0)
310
311/* 10us Pulse Generate Timer Registers */
312#define SP_I2C_GEN_10US_TIMER0_REG 0x88
313#define SP_I2C_GEN_10US_TIMER1_REG 0x89
314
315/* Packet Send Control Register */
316#define SP_PACKET_SEND_CTRL_REG 0x90
317#define SP_AUD_IF_UP BIT(7)
318#define SP_AVI_IF_UD BIT(6)
319#define SP_MPEG_IF_UD BIT(5)
320#define SP_SPD_IF_UD BIT(4)
321#define SP_AUD_IF_EN BIT(3)
322#define SP_AVI_IF_EN BIT(2)
323#define SP_MPEG_IF_EN BIT(1)
324#define SP_SPD_IF_EN BIT(0)
325
326/* DP HDCP Control Register */
327#define SP_DP_HDCP_CTRL_REG 0x92
328#define SP_AUTO_EN BIT(7)
329#define SP_AUTO_START BIT(5)
330#define SP_LINK_POLLING BIT(1)
331
332/* DP Main Link Bandwidth Setting Register */
333#define SP_DP_MAIN_LINK_BW_SET_REG 0xa0
334#define SP_LINK_BW_SET_MASK 0x1f
335#define SP_INITIAL_SLIM_M_AUD_SEL BIT(5)
336
337/* DP Training Pattern Set Register */
338#define SP_DP_TRAINING_PATTERN_SET_REG 0xa2
339
340/* DP Lane 0 Link Training Control Register */
341#define SP_DP_LANE0_LT_CTRL_REG 0xa3
342#define SP_TX_SW_SET_MASK 0x1b
343#define SP_MAX_PRE_REACH BIT(5)
344#define SP_MAX_DRIVE_REACH BIT(4)
345#define SP_PRE_EMP_LEVEL1 BIT(3)
346#define SP_DRVIE_CURRENT_LEVEL1 BIT(0)
347
348/* DP Link Training Control Register */
349#define SP_DP_LT_CTRL_REG 0xa8
350#define SP_LT_ERROR_TYPE_MASK 0x70
351# define SP_LT_NO_ERROR 0x00
352# define SP_LT_AUX_WRITE_ERROR 0x01
353# define SP_LT_MAX_DRIVE_REACHED 0x02
354# define SP_LT_WRONG_LANE_COUNT_SET 0x03
355# define SP_LT_LOOP_SAME_5_TIME 0x04
356# define SP_LT_CR_FAIL_IN_EQ 0x05
357# define SP_LT_EQ_LOOP_5_TIME 0x06
358#define SP_LT_EN BIT(0)
359
360/* DP CEP Training Control Registers */
361#define SP_DP_CEP_TRAINING_CTRL0_REG 0xa9
362#define SP_DP_CEP_TRAINING_CTRL1_REG 0xaa
363
364/* DP Debug Register 1 */
365#define SP_DP_DEBUG1_REG 0xb0
366#define SP_DEBUG_PLL_LOCK BIT(4)
367#define SP_POLLING_EN BIT(1)
368
369/* DP Polling Control Register */
370#define SP_DP_POLLING_CTRL_REG 0xb4
371#define SP_AUTO_POLLING_DISABLE BIT(0)
372
373/* DP Link Debug Control Register */
374#define SP_DP_LINK_DEBUG_CTRL_REG 0xb8
375#define SP_M_VID_DEBUG BIT(5)
376#define SP_NEW_PRBS7 BIT(4)
377#define SP_INSERT_ER BIT(1)
378#define SP_PRBS31_EN BIT(0)
379
380/* AUX Misc control Register */
381#define SP_AUX_MISC_CTRL_REG 0xbf
382
383/* DP PLL control Register */
384#define SP_DP_PLL_CTRL_REG 0xc7
385#define SP_PLL_RST BIT(6)
386
387/* DP Analog Power Down Register */
388#define SP_DP_ANALOG_POWER_DOWN_REG 0xc8
389#define SP_CH0_PD BIT(0)
390
391/* DP Misc Control Register */
392#define SP_DP_MISC_CTRL_REG 0xcd
393#define SP_EQ_TRAINING_LOOP BIT(6)
394
395/* DP Extra I2C Device Address Register */
396#define SP_DP_EXTRA_I2C_DEV_ADDR_REG 0xce
397#define SP_I2C_STRETCH_DISABLE BIT(7)
398
399#define SP_I2C_EXTRA_ADDR 0x50
400
401/* DP Downspread Control Register 1 */
402#define SP_DP_DOWNSPREAD_CTRL1_REG 0xd0
403
404/* DP M Value Calculation Control Register */
405#define SP_DP_M_CALCULATION_CTRL_REG 0xd9
406#define SP_M_GEN_CLK_SEL BIT(0)
407
408/* AUX Channel Access Status Register */
409#define SP_AUX_CH_STATUS_REG 0xe0
410#define SP_AUX_STATUS 0x0f
411
412/* AUX Channel DEFER Control Register */
413#define SP_AUX_DEFER_CTRL_REG 0xe2
414#define SP_DEFER_CTRL_EN BIT(7)
415
416/* DP Buffer Data Count Register */
417#define SP_BUF_DATA_COUNT_REG 0xe4
418#define SP_BUF_DATA_COUNT_MASK 0x1f
419#define SP_BUF_CLR BIT(7)
420
421/* DP AUX Channel Control Register 1 */
422#define SP_DP_AUX_CH_CTRL1_REG 0xe5
423#define SP_AUX_TX_COMM_MASK 0x0f
424#define SP_AUX_LENGTH_MASK 0xf0
425#define SP_AUX_LENGTH_SHIFT 4
426
427/* DP AUX CH Address Register 0 */
428#define SP_AUX_ADDR_7_0_REG 0xe6
429
430/* DP AUX CH Address Register 1 */
431#define SP_AUX_ADDR_15_8_REG 0xe7
432
433/* DP AUX CH Address Register 2 */
434#define SP_AUX_ADDR_19_16_REG 0xe8
435#define SP_AUX_ADDR_19_16_MASK 0x0f
436
437/* DP AUX Channel Control Register 2 */
438#define SP_DP_AUX_CH_CTRL2_REG 0xe9
439#define SP_AUX_SEL_RXCM BIT(6)
440#define SP_AUX_CHSEL BIT(3)
441#define SP_AUX_PN_INV BIT(2)
442#define SP_ADDR_ONLY BIT(1)
443#define SP_AUX_EN BIT(0)
444
445/* DP Video Stream Control InfoFrame Register */
446#define SP_DP_3D_VSC_CTRL_REG 0xea
447#define SP_INFO_FRAME_VSC_EN BIT(0)
448
449/* DP Video Stream Data Byte 1 Register */
450#define SP_DP_VSC_DB1_REG 0xeb
451
452/* DP AUX Channel Control Register 3 */
453#define SP_DP_AUX_CH_CTRL3_REG 0xec
454#define SP_WAIT_COUNTER_7_0_MASK 0xff
455
456/* DP AUX Channel Control Register 4 */
457#define SP_DP_AUX_CH_CTRL4_REG 0xed
458
459/* DP AUX Buffer Data Registers */
460#define SP_DP_BUF_DATA0_REG 0xf0
461
462/***************************************************************/
463/* Register definition of device address 0x72 */
464/***************************************************************/
465
466/*
467 * Core Register Definitions
468 */
469
470/* Device ID Low Byte Register */
471#define SP_DEVICE_IDL_REG 0x02
472
473/* Device ID High Byte Register */
474#define SP_DEVICE_IDH_REG 0x03
475
476/* Device version register */
477#define SP_DEVICE_VERSION_REG 0x04
478
479/* Power Down Control Register */
480#define SP_POWERDOWN_CTRL_REG 0x05
481#define SP_REGISTER_PD BIT(7)
482#define SP_HDCP_PD BIT(5)
483#define SP_AUDIO_PD BIT(4)
484#define SP_VIDEO_PD BIT(3)
485#define SP_LINK_PD BIT(2)
486#define SP_TOTAL_PD BIT(1)
487
488/* Reset Control Register 1 */
489#define SP_RESET_CTRL1_REG 0x06
490#define SP_MISC_RST BIT(7)
491#define SP_VIDCAP_RST BIT(6)
492#define SP_VIDFIF_RST BIT(5)
493#define SP_AUDFIF_RST BIT(4)
494#define SP_AUDCAP_RST BIT(3)
495#define SP_HDCP_RST BIT(2)
496#define SP_SW_RST BIT(1)
497#define SP_HW_RST BIT(0)
498
499/* Reset Control Register 2 */
500#define SP_RESET_CTRL2_REG 0x07
501#define SP_AUX_RST BIT(2)
502#define SP_SERDES_FIFO_RST BIT(1)
503#define SP_I2C_REG_RST BIT(0)
504
505/* Video Control Register 1 */
506#define SP_VID_CTRL1_REG 0x08
507#define SP_VIDEO_EN BIT(7)
508#define SP_VIDEO_MUTE BIT(2)
509#define SP_DE_GEN BIT(1)
510#define SP_DEMUX BIT(0)
511
512/* Video Control Register 2 */
513#define SP_VID_CTRL2_REG 0x09
514#define SP_IN_COLOR_F_MASK 0x03
515#define SP_IN_YC_BIT_SEL BIT(2)
516#define SP_IN_BPC_MASK 0x70
517#define SP_IN_BPC_SHIFT 4
518# define SP_IN_BPC_12BIT 0x03
519# define SP_IN_BPC_10BIT 0x02
520# define SP_IN_BPC_8BIT 0x01
521# define SP_IN_BPC_6BIT 0x00
522#define SP_IN_D_RANGE BIT(7)
523
524/* Video Control Register 3 */
525#define SP_VID_CTRL3_REG 0x0a
526#define SP_HPD_OUT BIT(6)
527
528/* Video Control Register 5 */
529#define SP_VID_CTRL5_REG 0x0c
530#define SP_CSC_STD_SEL BIT(7)
531#define SP_XVYCC_RNG_LMT BIT(6)
532#define SP_RANGE_Y2R BIT(5)
533#define SP_CSPACE_Y2R BIT(4)
534#define SP_RGB_RNG_LMT BIT(3)
535#define SP_Y_RNG_LMT BIT(2)
536#define SP_RANGE_R2Y BIT(1)
537#define SP_CSPACE_R2Y BIT(0)
538
539/* Video Control Register 6 */
540#define SP_VID_CTRL6_REG 0x0d
541#define SP_TEST_PATTERN_EN BIT(7)
542#define SP_VIDEO_PROCESS_EN BIT(6)
543#define SP_VID_US_MODE BIT(3)
544#define SP_VID_DS_MODE BIT(2)
545#define SP_UP_SAMPLE BIT(1)
546#define SP_DOWN_SAMPLE BIT(0)
547
548/* Video Control Register 8 */
549#define SP_VID_CTRL8_REG 0x0f
550#define SP_VID_VRES_TH BIT(0)
551
552/* Total Line Status Low Byte Register */
553#define SP_TOTAL_LINE_STAL_REG 0x24
554
555/* Total Line Status High Byte Register */
556#define SP_TOTAL_LINE_STAH_REG 0x25
557
558/* Active Line Status Low Byte Register */
559#define SP_ACT_LINE_STAL_REG 0x26
560
561/* Active Line Status High Byte Register */
562#define SP_ACT_LINE_STAH_REG 0x27
563
564/* Vertical Front Porch Status Register */
565#define SP_V_F_PORCH_STA_REG 0x28
566
567/* Vertical SYNC Width Status Register */
568#define SP_V_SYNC_STA_REG 0x29
569
570/* Vertical Back Porch Status Register */
571#define SP_V_B_PORCH_STA_REG 0x2a
572
573/* Total Pixel Status Low Byte Register */
574#define SP_TOTAL_PIXEL_STAL_REG 0x2b
575
576/* Total Pixel Status High Byte Register */
577#define SP_TOTAL_PIXEL_STAH_REG 0x2c
578
579/* Active Pixel Status Low Byte Register */
580#define SP_ACT_PIXEL_STAL_REG 0x2d
581
582/* Active Pixel Status High Byte Register */
583#define SP_ACT_PIXEL_STAH_REG 0x2e
584
585/* Horizontal Front Porch Status Low Byte Register */
586#define SP_H_F_PORCH_STAL_REG 0x2f
587
588/* Horizontal Front Porch Statys High Byte Register */
589#define SP_H_F_PORCH_STAH_REG 0x30
590
591/* Horizontal SYNC Width Status Low Byte Register */
592#define SP_H_SYNC_STAL_REG 0x31
593
594/* Horizontal SYNC Width Status High Byte Register */
595#define SP_H_SYNC_STAH_REG 0x32
596
597/* Horizontal Back Porch Status Low Byte Register */
598#define SP_H_B_PORCH_STAL_REG 0x33
599
600/* Horizontal Back Porch Status High Byte Register */
601#define SP_H_B_PORCH_STAH_REG 0x34
602
603/* InfoFrame AVI Packet DB1 Register */
604#define SP_INFOFRAME_AVI_DB1_REG 0x70
605
606/* Bit Control Specific Register */
607#define SP_BIT_CTRL_SPECIFIC_REG 0x80
608#define SP_BIT_CTRL_SELECT_SHIFT 1
609#define SP_ENABLE_BIT_CTRL BIT(0)
610
611/* InfoFrame Audio Packet DB1 Register */
612#define SP_INFOFRAME_AUD_DB1_REG 0x83
613
614/* InfoFrame MPEG Packet DB1 Register */
615#define SP_INFOFRAME_MPEG_DB1_REG 0xb0
616
617/* Audio Channel Status Registers */
618#define SP_AUD_CH_STATUS_BASE 0xd0
619
620/* Audio Channel Num Register 5 */
621#define SP_I2S_CHANNEL_NUM_MASK 0xe0
622# define SP_I2S_CH_NUM_1 (0x00 << 5)
623# define SP_I2S_CH_NUM_2 (0x01 << 5)
624# define SP_I2S_CH_NUM_3 (0x02 << 5)
625# define SP_I2S_CH_NUM_4 (0x03 << 5)
626# define SP_I2S_CH_NUM_5 (0x04 << 5)
627# define SP_I2S_CH_NUM_6 (0x05 << 5)
628# define SP_I2S_CH_NUM_7 (0x06 << 5)
629# define SP_I2S_CH_NUM_8 (0x07 << 5)
630#define SP_EXT_VUCP BIT(2)
631#define SP_VBIT BIT(1)
632#define SP_AUDIO_LAYOUT BIT(0)
633
634/* Analog Debug Register 2 */
635#define SP_ANALOG_DEBUG2_REG 0xdd
636#define SP_FORCE_SW_OFF_BYPASS 0x20
637#define SP_XTAL_FRQ 0x1c
638# define SP_XTAL_FRQ_19M2 (0x00 << 2)
639# define SP_XTAL_FRQ_24M (0x01 << 2)
640# define SP_XTAL_FRQ_25M (0x02 << 2)
641# define SP_XTAL_FRQ_26M (0x03 << 2)
642# define SP_XTAL_FRQ_27M (0x04 << 2)
643# define SP_XTAL_FRQ_38M4 (0x05 << 2)
644# define SP_XTAL_FRQ_52M (0x06 << 2)
645#define SP_POWERON_TIME_1P5MS 0x03
646
647/* Analog Control 0 Register */
648#define SP_ANALOG_CTRL0_REG 0xe1
649
650/* Common Interrupt Status Register 1 */
651#define SP_COMMON_INT_STATUS_BASE (0xf1 - 1)
652#define SP_PLL_LOCK_CHG 0x40
653
654/* Common Interrupt Status Register 2 */
655#define SP_COMMON_INT_STATUS2 0xf2
656#define SP_HDCP_AUTH_CHG BIT(1)
657#define SP_HDCP_AUTH_DONE BIT(0)
658
659#define SP_HDCP_LINK_CHECK_FAIL BIT(0)
660
661/* Common Interrupt Status Register 4 */
662#define SP_COMMON_INT_STATUS4_REG 0xf4
663#define SP_HPD_IRQ BIT(6)
664#define SP_HPD_ESYNC_ERR BIT(4)
665#define SP_HPD_CHG BIT(2)
666#define SP_HPD_LOST BIT(1)
667#define SP_HPD_PLUG BIT(0)
668
669/* DP Interrupt Status Register */
670#define SP_DP_INT_STATUS1_REG 0xf7
671#define SP_TRAINING_FINISH BIT(5)
672#define SP_POLLING_ERR BIT(4)
673
674/* Common Interrupt Mask Register */
675#define SP_COMMON_INT_MASK_BASE (0xf8 - 1)
676
677#define SP_COMMON_INT_MASK4_REG 0xfb
678
679/* DP Interrupts Mask Register */
680#define SP_DP_INT_MASK1_REG 0xfe
681
682/* Interrupt Control Register */
683#define SP_INT_CTRL_REG 0xff
684
685/***************************************************************/
686/* Register definition of device address 0x7a */
687/***************************************************************/
688
689/* DP TX Link Training Control Register */
690#define SP_DP_TX_LT_CTRL0_REG 0x30
691
692/* PD 1.2 Lint Training 80bit Pattern Register */
693#define SP_DP_LT_80BIT_PATTERN0_REG 0x80
694#define SP_DP_LT_80BIT_PATTERN_REG_NUM 10
695
696/* Audio Interface Control Register 0 */
697#define SP_AUD_INTERFACE_CTRL0_REG 0x5f
698#define SP_AUD_INTERFACE_DISABLE 0x80
699
700/* Audio Interface Control Register 2 */
701#define SP_AUD_INTERFACE_CTRL2_REG 0x60
702#define SP_M_AUD_ADJUST_ST 0x04
703
704/* Audio Interface Control Register 3 */
705#define SP_AUD_INTERFACE_CTRL3_REG 0x62
706
707/* Audio Interface Control Register 4 */
708#define SP_AUD_INTERFACE_CTRL4_REG 0x67
709
710/* Audio Interface Control Register 5 */
711#define SP_AUD_INTERFACE_CTRL5_REG 0x68
712
713/* Audio Interface Control Register 6 */
714#define SP_AUD_INTERFACE_CTRL6_REG 0x69
715
716/* Firmware Version Register */
717#define SP_FW_VER_REG 0xb7
718
719#endif
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
index b19c88f188b0..3a7bdf1c842b 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -117,7 +117,11 @@ static int panel_simple_get_fixed_modes(struct panel_simple *panel)
117 } 117 }
118 118
119 drm_display_mode_from_videomode(&vm, mode); 119 drm_display_mode_from_videomode(&vm, mode);
120 drm_mode_set_name(mode); 120
121 mode->type |= DRM_MODE_TYPE_DRIVER;
122
123 if (panel->desc->num_modes == 1)
124 mode->type |= DRM_MODE_TYPE_PREFERRED;
121 125
122 drm_mode_probed_add(connector, mode); 126 drm_mode_probed_add(connector, mode);
123 num++; 127 num++;
@@ -133,6 +137,11 @@ static int panel_simple_get_fixed_modes(struct panel_simple *panel)
133 continue; 137 continue;
134 } 138 }
135 139
140 mode->type |= DRM_MODE_TYPE_DRIVER;
141
142 if (panel->desc->num_modes == 1)
143 mode->type |= DRM_MODE_TYPE_PREFERRED;
144
136 drm_mode_set_name(mode); 145 drm_mode_set_name(mode);
137 146
138 drm_mode_probed_add(connector, mode); 147 drm_mode_probed_add(connector, mode);
@@ -815,6 +824,29 @@ static const struct panel_desc innolux_at043tn24 = {
815 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 824 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
816}; 825};
817 826
827static const struct drm_display_mode innolux_at070tn92_mode = {
828 .clock = 33333,
829 .hdisplay = 800,
830 .hsync_start = 800 + 210,
831 .hsync_end = 800 + 210 + 20,
832 .htotal = 800 + 210 + 20 + 46,
833 .vdisplay = 480,
834 .vsync_start = 480 + 22,
835 .vsync_end = 480 + 22 + 10,
836 .vtotal = 480 + 22 + 23 + 10,
837 .vrefresh = 60,
838};
839
840static const struct panel_desc innolux_at070tn92 = {
841 .modes = &innolux_at070tn92_mode,
842 .num_modes = 1,
843 .size = {
844 .width = 154,
845 .height = 86,
846 },
847 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
848};
849
818static const struct drm_display_mode innolux_g121i1_l01_mode = { 850static const struct drm_display_mode innolux_g121i1_l01_mode = {
819 .clock = 71000, 851 .clock = 71000,
820 .hdisplay = 1280, 852 .hdisplay = 1280,
@@ -1087,6 +1119,63 @@ static const struct panel_desc okaya_rs800480t_7x0gp = {
1087 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1119 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1088}; 1120};
1089 1121
1122static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
1123 .clock = 9000,
1124 .hdisplay = 480,
1125 .hsync_start = 480 + 5,
1126 .hsync_end = 480 + 5 + 30,
1127 .htotal = 480 + 5 + 30 + 10,
1128 .vdisplay = 272,
1129 .vsync_start = 272 + 8,
1130 .vsync_end = 272 + 8 + 5,
1131 .vtotal = 272 + 8 + 5 + 3,
1132 .vrefresh = 60,
1133};
1134
1135static const struct panel_desc olimex_lcd_olinuxino_43ts = {
1136 .modes = &olimex_lcd_olinuxino_43ts_mode,
1137 .num_modes = 1,
1138 .size = {
1139 .width = 105,
1140 .height = 67,
1141 },
1142 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1143};
1144
1145/*
1146 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
1147 * pixel clocks, but this is the timing that was being used in the Adafruit
1148 * installation instructions.
1149 */
1150static const struct drm_display_mode ontat_yx700wv03_mode = {
1151 .clock = 29500,
1152 .hdisplay = 800,
1153 .hsync_start = 824,
1154 .hsync_end = 896,
1155 .htotal = 992,
1156 .vdisplay = 480,
1157 .vsync_start = 483,
1158 .vsync_end = 493,
1159 .vtotal = 500,
1160 .vrefresh = 60,
1161 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1162};
1163
1164/*
1165 * Specification at:
1166 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
1167 */
1168static const struct panel_desc ontat_yx700wv03 = {
1169 .modes = &ontat_yx700wv03_mode,
1170 .num_modes = 1,
1171 .bpc = 8,
1172 .size = {
1173 .width = 154,
1174 .height = 83,
1175 },
1176 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1177};
1178
1090static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 1179static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
1091 .clock = 25000, 1180 .clock = 25000,
1092 .hdisplay = 480, 1181 .hdisplay = 480,
@@ -1204,6 +1293,51 @@ static const struct panel_desc shelly_sca07010_bfn_lnn = {
1204 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1293 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1205}; 1294};
1206 1295
1296static const struct drm_display_mode tpk_f07a_0102_mode = {
1297 .clock = 33260,
1298 .hdisplay = 800,
1299 .hsync_start = 800 + 40,
1300 .hsync_end = 800 + 40 + 128,
1301 .htotal = 800 + 40 + 128 + 88,
1302 .vdisplay = 480,
1303 .vsync_start = 480 + 10,
1304 .vsync_end = 480 + 10 + 2,
1305 .vtotal = 480 + 10 + 2 + 33,
1306 .vrefresh = 60,
1307};
1308
1309static const struct panel_desc tpk_f07a_0102 = {
1310 .modes = &tpk_f07a_0102_mode,
1311 .num_modes = 1,
1312 .size = {
1313 .width = 152,
1314 .height = 91,
1315 },
1316 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
1317};
1318
1319static const struct drm_display_mode tpk_f10a_0102_mode = {
1320 .clock = 45000,
1321 .hdisplay = 1024,
1322 .hsync_start = 1024 + 176,
1323 .hsync_end = 1024 + 176 + 5,
1324 .htotal = 1024 + 176 + 5 + 88,
1325 .vdisplay = 600,
1326 .vsync_start = 600 + 20,
1327 .vsync_end = 600 + 20 + 5,
1328 .vtotal = 600 + 20 + 5 + 25,
1329 .vrefresh = 60,
1330};
1331
1332static const struct panel_desc tpk_f10a_0102 = {
1333 .modes = &tpk_f10a_0102_mode,
1334 .num_modes = 1,
1335 .size = {
1336 .width = 223,
1337 .height = 125,
1338 },
1339};
1340
1207static const struct display_timing urt_umsh_8596md_timing = { 1341static const struct display_timing urt_umsh_8596md_timing = {
1208 .pixelclock = { 33260000, 33260000, 33260000 }, 1342 .pixelclock = { 33260000, 33260000, 33260000 },
1209 .hactive = { 800, 800, 800 }, 1343 .hactive = { 800, 800, 800 },
@@ -1299,6 +1433,9 @@ static const struct of_device_id platform_of_match[] = {
1299 .compatible = "innolux,at043tn24", 1433 .compatible = "innolux,at043tn24",
1300 .data = &innolux_at043tn24, 1434 .data = &innolux_at043tn24,
1301 }, { 1435 }, {
1436 .compatible = "innolux,at070tn92",
1437 .data = &innolux_at070tn92,
1438 }, {
1302 .compatible ="innolux,g121i1-l01", 1439 .compatible ="innolux,g121i1-l01",
1303 .data = &innolux_g121i1_l01 1440 .data = &innolux_g121i1_l01
1304 }, { 1441 }, {
@@ -1332,6 +1469,12 @@ static const struct of_device_id platform_of_match[] = {
1332 .compatible = "okaya,rs800480t-7x0gp", 1469 .compatible = "okaya,rs800480t-7x0gp",
1333 .data = &okaya_rs800480t_7x0gp, 1470 .data = &okaya_rs800480t_7x0gp,
1334 }, { 1471 }, {
1472 .compatible = "olimex,lcd-olinuxino-43-ts",
1473 .data = &olimex_lcd_olinuxino_43ts,
1474 }, {
1475 .compatible = "ontat,yx700wv03",
1476 .data = &ontat_yx700wv03,
1477 }, {
1335 .compatible = "ortustech,com43h4m85ulc", 1478 .compatible = "ortustech,com43h4m85ulc",
1336 .data = &ortustech_com43h4m85ulc, 1479 .data = &ortustech_com43h4m85ulc,
1337 }, { 1480 }, {
@@ -1347,6 +1490,12 @@ static const struct of_device_id platform_of_match[] = {
1347 .compatible = "shelly,sca07010-bfn-lnn", 1490 .compatible = "shelly,sca07010-bfn-lnn",
1348 .data = &shelly_sca07010_bfn_lnn, 1491 .data = &shelly_sca07010_bfn_lnn,
1349 }, { 1492 }, {
1493 .compatible = "tpk,f07a-0102",
1494 .data = &tpk_f07a_0102,
1495 }, {
1496 .compatible = "tpk,f10a-0102",
1497 .data = &tpk_f10a_0102,
1498 }, {
1350 .compatible = "urt,umsh-8596md-t", 1499 .compatible = "urt,umsh-8596md-t",
1351 .data = &urt_umsh_8596md_parallel, 1500 .data = &urt_umsh_8596md_parallel,
1352 }, { 1501 }, {
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 1252108da0ef..9d03f167007b 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -73,6 +73,7 @@
73# define DP_ENHANCED_FRAME_CAP (1 << 7) 73# define DP_ENHANCED_FRAME_CAP (1 << 7)
74 74
75#define DP_MAX_DOWNSPREAD 0x003 75#define DP_MAX_DOWNSPREAD 0x003
76# define DP_MAX_DOWNSPREAD_0_5 (1 << 0)
76# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) 77# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
77 78
78#define DP_NORP 0x004 79#define DP_NORP 0x004
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-05 21:48:46 -0400