aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorKalle Valo <kvalo@codeaurora.org>2015-11-17 08:56:52 -0500
committerKalle Valo <kvalo@codeaurora.org>2015-11-17 08:56:52 -0500
commitcecd4cfb540ed627fba81a0c4d92e205ed8314e6 (patch)
tree8fab518fea6db966404c7784d0666817252c10b0
parent948cca9fc3052be86d937bcb74170215b38117e8 (diff)
parent6419fdbb6f90e147690f8833cba59d289d613da5 (diff)
Merge ath-current from ath.git
ath10k * fix invalid NSS for 4x4 devices * add QCA9377 hw1.0 support * fix QCA6174 regression with CE5 usage wil6210 * new maintainer - Maya Erez
-rw-r--r--MAINTAINERS2
-rw-r--r--drivers/net/wireless/ath/ath10k/core.c49
-rw-r--r--drivers/net/wireless/ath/ath10k/core.h1
-rw-r--r--drivers/net/wireless/ath/ath10k/hw.h17
-rw-r--r--drivers/net/wireless/ath/ath10k/mac.c2
-rw-r--r--drivers/net/wireless/ath/ath10k/pci.c53
6 files changed, 108 insertions, 16 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index 45320675a460..c5bee001fbdc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1847,7 +1847,7 @@ S: Supported
1847F: drivers/net/wireless/ath/ath6kl/ 1847F: drivers/net/wireless/ath/ath6kl/
1848 1848
1849WILOCITY WIL6210 WIRELESS DRIVER 1849WILOCITY WIL6210 WIRELESS DRIVER
1850M: Vladimir Kondratiev <qca_vkondrat@qca.qualcomm.com> 1850M: Maya Erez <qca_merez@qca.qualcomm.com>
1851L: linux-wireless@vger.kernel.org 1851L: linux-wireless@vger.kernel.org
1852L: wil6210@qca.qualcomm.com 1852L: wil6210@qca.qualcomm.com
1853S: Supported 1853S: Supported
diff --git a/drivers/net/wireless/ath/ath10k/core.c b/drivers/net/wireless/ath/ath10k/core.c
index aa9bd92ac4ed..0947cc271e69 100644
--- a/drivers/net/wireless/ath/ath10k/core.c
+++ b/drivers/net/wireless/ath/ath10k/core.c
@@ -51,6 +51,7 @@ MODULE_PARM_DESC(rawmode, "Use raw 802.11 frame datapath");
51static const struct ath10k_hw_params ath10k_hw_params_list[] = { 51static const struct ath10k_hw_params ath10k_hw_params_list[] = {
52 { 52 {
53 .id = QCA988X_HW_2_0_VERSION, 53 .id = QCA988X_HW_2_0_VERSION,
54 .dev_id = QCA988X_2_0_DEVICE_ID,
54 .name = "qca988x hw2.0", 55 .name = "qca988x hw2.0",
55 .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR, 56 .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR,
56 .uart_pin = 7, 57 .uart_pin = 7,
@@ -69,6 +70,25 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
69 }, 70 },
70 { 71 {
71 .id = QCA6174_HW_2_1_VERSION, 72 .id = QCA6174_HW_2_1_VERSION,
73 .dev_id = QCA6164_2_1_DEVICE_ID,
74 .name = "qca6164 hw2.1",
75 .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR,
76 .uart_pin = 6,
77 .otp_exe_param = 0,
78 .channel_counters_freq_hz = 88000,
79 .max_probe_resp_desc_thres = 0,
80 .fw = {
81 .dir = QCA6174_HW_2_1_FW_DIR,
82 .fw = QCA6174_HW_2_1_FW_FILE,
83 .otp = QCA6174_HW_2_1_OTP_FILE,
84 .board = QCA6174_HW_2_1_BOARD_DATA_FILE,
85 .board_size = QCA6174_BOARD_DATA_SZ,
86 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
87 },
88 },
89 {
90 .id = QCA6174_HW_2_1_VERSION,
91 .dev_id = QCA6174_2_1_DEVICE_ID,
72 .name = "qca6174 hw2.1", 92 .name = "qca6174 hw2.1",
73 .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR, 93 .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR,
74 .uart_pin = 6, 94 .uart_pin = 6,
@@ -86,6 +106,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
86 }, 106 },
87 { 107 {
88 .id = QCA6174_HW_3_0_VERSION, 108 .id = QCA6174_HW_3_0_VERSION,
109 .dev_id = QCA6174_2_1_DEVICE_ID,
89 .name = "qca6174 hw3.0", 110 .name = "qca6174 hw3.0",
90 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR, 111 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
91 .uart_pin = 6, 112 .uart_pin = 6,
@@ -103,6 +124,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
103 }, 124 },
104 { 125 {
105 .id = QCA6174_HW_3_2_VERSION, 126 .id = QCA6174_HW_3_2_VERSION,
127 .dev_id = QCA6174_2_1_DEVICE_ID,
106 .name = "qca6174 hw3.2", 128 .name = "qca6174 hw3.2",
107 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR, 129 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
108 .uart_pin = 6, 130 .uart_pin = 6,
@@ -121,6 +143,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
121 }, 143 },
122 { 144 {
123 .id = QCA99X0_HW_2_0_DEV_VERSION, 145 .id = QCA99X0_HW_2_0_DEV_VERSION,
146 .dev_id = QCA99X0_2_0_DEVICE_ID,
124 .name = "qca99x0 hw2.0", 147 .name = "qca99x0 hw2.0",
125 .patch_load_addr = QCA99X0_HW_2_0_PATCH_LOAD_ADDR, 148 .patch_load_addr = QCA99X0_HW_2_0_PATCH_LOAD_ADDR,
126 .uart_pin = 7, 149 .uart_pin = 7,
@@ -139,10 +162,31 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
139 }, 162 },
140 { 163 {
141 .id = QCA9377_HW_1_0_DEV_VERSION, 164 .id = QCA9377_HW_1_0_DEV_VERSION,
165 .dev_id = QCA9377_1_0_DEVICE_ID,
142 .name = "qca9377 hw1.0", 166 .name = "qca9377 hw1.0",
143 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR, 167 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
144 .uart_pin = 7, 168 .uart_pin = 6,
145 .otp_exe_param = 0, 169 .otp_exe_param = 0,
170 .channel_counters_freq_hz = 88000,
171 .max_probe_resp_desc_thres = 0,
172 .fw = {
173 .dir = QCA9377_HW_1_0_FW_DIR,
174 .fw = QCA9377_HW_1_0_FW_FILE,
175 .otp = QCA9377_HW_1_0_OTP_FILE,
176 .board = QCA9377_HW_1_0_BOARD_DATA_FILE,
177 .board_size = QCA9377_BOARD_DATA_SZ,
178 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
179 },
180 },
181 {
182 .id = QCA9377_HW_1_1_DEV_VERSION,
183 .dev_id = QCA9377_1_0_DEVICE_ID,
184 .name = "qca9377 hw1.1",
185 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
186 .uart_pin = 6,
187 .otp_exe_param = 0,
188 .channel_counters_freq_hz = 88000,
189 .max_probe_resp_desc_thres = 0,
146 .fw = { 190 .fw = {
147 .dir = QCA9377_HW_1_0_FW_DIR, 191 .dir = QCA9377_HW_1_0_FW_DIR,
148 .fw = QCA9377_HW_1_0_FW_FILE, 192 .fw = QCA9377_HW_1_0_FW_FILE,
@@ -1263,7 +1307,8 @@ static int ath10k_init_hw_params(struct ath10k *ar)
1263 for (i = 0; i < ARRAY_SIZE(ath10k_hw_params_list); i++) { 1307 for (i = 0; i < ARRAY_SIZE(ath10k_hw_params_list); i++) {
1264 hw_params = &ath10k_hw_params_list[i]; 1308 hw_params = &ath10k_hw_params_list[i];
1265 1309
1266 if (hw_params->id == ar->target_version) 1310 if (hw_params->id == ar->target_version &&
1311 hw_params->dev_id == ar->dev_id)
1267 break; 1312 break;
1268 } 1313 }
1269 1314
diff --git a/drivers/net/wireless/ath/ath10k/core.h b/drivers/net/wireless/ath/ath10k/core.h
index 018c64f4fd25..858d75f49a9f 100644
--- a/drivers/net/wireless/ath/ath10k/core.h
+++ b/drivers/net/wireless/ath/ath10k/core.h
@@ -636,6 +636,7 @@ struct ath10k {
636 636
637 struct ath10k_hw_params { 637 struct ath10k_hw_params {
638 u32 id; 638 u32 id;
639 u16 dev_id;
639 const char *name; 640 const char *name;
640 u32 patch_load_addr; 641 u32 patch_load_addr;
641 int uart_pin; 642 int uart_pin;
diff --git a/drivers/net/wireless/ath/ath10k/hw.h b/drivers/net/wireless/ath/ath10k/hw.h
index 39966a05c1cc..713c2bcea178 100644
--- a/drivers/net/wireless/ath/ath10k/hw.h
+++ b/drivers/net/wireless/ath/ath10k/hw.h
@@ -22,6 +22,12 @@
22 22
23#define ATH10K_FW_DIR "ath10k" 23#define ATH10K_FW_DIR "ath10k"
24 24
25#define QCA988X_2_0_DEVICE_ID (0x003c)
26#define QCA6164_2_1_DEVICE_ID (0x0041)
27#define QCA6174_2_1_DEVICE_ID (0x003e)
28#define QCA99X0_2_0_DEVICE_ID (0x0040)
29#define QCA9377_1_0_DEVICE_ID (0x0042)
30
25/* QCA988X 1.0 definitions (unsupported) */ 31/* QCA988X 1.0 definitions (unsupported) */
26#define QCA988X_HW_1_0_CHIP_ID_REV 0x0 32#define QCA988X_HW_1_0_CHIP_ID_REV 0x0
27 33
@@ -42,6 +48,10 @@
42#define QCA6174_HW_3_0_VERSION 0x05020000 48#define QCA6174_HW_3_0_VERSION 0x05020000
43#define QCA6174_HW_3_2_VERSION 0x05030000 49#define QCA6174_HW_3_2_VERSION 0x05030000
44 50
51/* QCA9377 target BMI version signatures */
52#define QCA9377_HW_1_0_DEV_VERSION 0x05020000
53#define QCA9377_HW_1_1_DEV_VERSION 0x05020001
54
45enum qca6174_pci_rev { 55enum qca6174_pci_rev {
46 QCA6174_PCI_REV_1_1 = 0x11, 56 QCA6174_PCI_REV_1_1 = 0x11,
47 QCA6174_PCI_REV_1_3 = 0x13, 57 QCA6174_PCI_REV_1_3 = 0x13,
@@ -60,6 +70,11 @@ enum qca6174_chip_id_rev {
60 QCA6174_HW_3_2_CHIP_ID_REV = 10, 70 QCA6174_HW_3_2_CHIP_ID_REV = 10,
61}; 71};
62 72
73enum qca9377_chip_id_rev {
74 QCA9377_HW_1_0_CHIP_ID_REV = 0x0,
75 QCA9377_HW_1_1_CHIP_ID_REV = 0x1,
76};
77
63#define QCA6174_HW_2_1_FW_DIR "ath10k/QCA6174/hw2.1" 78#define QCA6174_HW_2_1_FW_DIR "ath10k/QCA6174/hw2.1"
64#define QCA6174_HW_2_1_FW_FILE "firmware.bin" 79#define QCA6174_HW_2_1_FW_FILE "firmware.bin"
65#define QCA6174_HW_2_1_OTP_FILE "otp.bin" 80#define QCA6174_HW_2_1_OTP_FILE "otp.bin"
@@ -85,8 +100,6 @@ enum qca6174_chip_id_rev {
85#define QCA99X0_HW_2_0_PATCH_LOAD_ADDR 0x1234 100#define QCA99X0_HW_2_0_PATCH_LOAD_ADDR 0x1234
86 101
87/* QCA9377 1.0 definitions */ 102/* QCA9377 1.0 definitions */
88#define QCA9377_HW_1_0_DEV_VERSION 0x05020001
89#define QCA9377_HW_1_0_CHIP_ID_REV 0x1
90#define QCA9377_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9377/hw1.0" 103#define QCA9377_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9377/hw1.0"
91#define QCA9377_HW_1_0_FW_FILE "firmware.bin" 104#define QCA9377_HW_1_0_FW_FILE "firmware.bin"
92#define QCA9377_HW_1_0_OTP_FILE "otp.bin" 105#define QCA9377_HW_1_0_OTP_FILE "otp.bin"
diff --git a/drivers/net/wireless/ath/ath10k/mac.c b/drivers/net/wireless/ath/ath10k/mac.c
index a7411fe90cc4..95a55405ebf0 100644
--- a/drivers/net/wireless/ath/ath10k/mac.c
+++ b/drivers/net/wireless/ath/ath10k/mac.c
@@ -4225,7 +4225,7 @@ static int ath10k_config(struct ieee80211_hw *hw, u32 changed)
4225 4225
4226static u32 get_nss_from_chainmask(u16 chain_mask) 4226static u32 get_nss_from_chainmask(u16 chain_mask)
4227{ 4227{
4228 if ((chain_mask & 0x15) == 0x15) 4228 if ((chain_mask & 0xf) == 0xf)
4229 return 4; 4229 return 4;
4230 else if ((chain_mask & 0x7) == 0x7) 4230 else if ((chain_mask & 0x7) == 0x7)
4231 return 3; 4231 return 3;
diff --git a/drivers/net/wireless/ath/ath10k/pci.c b/drivers/net/wireless/ath/ath10k/pci.c
index 3fca200b986c..930785a724e1 100644
--- a/drivers/net/wireless/ath/ath10k/pci.c
+++ b/drivers/net/wireless/ath/ath10k/pci.c
@@ -57,12 +57,6 @@ MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)");
57#define ATH10K_PCI_TARGET_WAIT 3000 57#define ATH10K_PCI_TARGET_WAIT 3000
58#define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3 58#define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3
59 59
60#define QCA988X_2_0_DEVICE_ID (0x003c)
61#define QCA6164_2_1_DEVICE_ID (0x0041)
62#define QCA6174_2_1_DEVICE_ID (0x003e)
63#define QCA99X0_2_0_DEVICE_ID (0x0040)
64#define QCA9377_1_0_DEVICE_ID (0x0042)
65
66static const struct pci_device_id ath10k_pci_id_table[] = { 60static const struct pci_device_id ath10k_pci_id_table[] = {
67 { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */ 61 { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */
68 { PCI_VDEVICE(ATHEROS, QCA6164_2_1_DEVICE_ID) }, /* PCI-E QCA6164 V2.1 */ 62 { PCI_VDEVICE(ATHEROS, QCA6164_2_1_DEVICE_ID) }, /* PCI-E QCA6164 V2.1 */
@@ -92,7 +86,9 @@ static const struct ath10k_pci_supp_chip ath10k_pci_supp_chips[] = {
92 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV }, 86 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV },
93 87
94 { QCA99X0_2_0_DEVICE_ID, QCA99X0_HW_2_0_CHIP_ID_REV }, 88 { QCA99X0_2_0_DEVICE_ID, QCA99X0_HW_2_0_CHIP_ID_REV },
89
95 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_0_CHIP_ID_REV }, 90 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_0_CHIP_ID_REV },
91 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_1_CHIP_ID_REV },
96}; 92};
97 93
98static void ath10k_pci_buffer_cleanup(struct ath10k *ar); 94static void ath10k_pci_buffer_cleanup(struct ath10k *ar);
@@ -111,8 +107,9 @@ static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state);
111static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state); 107static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state);
112static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state); 108static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state);
113static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state); 109static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state);
110static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state);
114 111
115static const struct ce_attr host_ce_config_wlan[] = { 112static struct ce_attr host_ce_config_wlan[] = {
116 /* CE0: host->target HTC control and raw streams */ 113 /* CE0: host->target HTC control and raw streams */
117 { 114 {
118 .flags = CE_ATTR_FLAGS, 115 .flags = CE_ATTR_FLAGS,
@@ -128,7 +125,7 @@ static const struct ce_attr host_ce_config_wlan[] = {
128 .src_nentries = 0, 125 .src_nentries = 0,
129 .src_sz_max = 2048, 126 .src_sz_max = 2048,
130 .dest_nentries = 512, 127 .dest_nentries = 512,
131 .recv_cb = ath10k_pci_htc_rx_cb, 128 .recv_cb = ath10k_pci_htt_htc_rx_cb,
132 }, 129 },
133 130
134 /* CE2: target->host WMI */ 131 /* CE2: target->host WMI */
@@ -217,7 +214,7 @@ static const struct ce_attr host_ce_config_wlan[] = {
217}; 214};
218 215
219/* Target firmware's Copy Engine configuration. */ 216/* Target firmware's Copy Engine configuration. */
220static const struct ce_pipe_config target_ce_config_wlan[] = { 217static struct ce_pipe_config target_ce_config_wlan[] = {
221 /* CE0: host->target HTC control and raw streams */ 218 /* CE0: host->target HTC control and raw streams */
222 { 219 {
223 .pipenum = __cpu_to_le32(0), 220 .pipenum = __cpu_to_le32(0),
@@ -330,7 +327,7 @@ static const struct ce_pipe_config target_ce_config_wlan[] = {
330 * This table is derived from the CE_PCI TABLE, above. 327 * This table is derived from the CE_PCI TABLE, above.
331 * It is passed to the Target at startup for use by firmware. 328 * It is passed to the Target at startup for use by firmware.
332 */ 329 */
333static const struct service_to_pipe target_service_to_ce_map_wlan[] = { 330static struct service_to_pipe target_service_to_ce_map_wlan[] = {
334 { 331 {
335 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO), 332 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
336 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 333 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
@@ -1208,6 +1205,16 @@ static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state)
1208 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler); 1205 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
1209} 1206}
1210 1207
1208static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state)
1209{
1210 /* CE4 polling needs to be done whenever CE pipe which transports
1211 * HTT Rx (target->host) is processed.
1212 */
1213 ath10k_ce_per_engine_service(ce_state->ar, 4);
1214
1215 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
1216}
1217
1211/* Called by lower (CE) layer when a send to HTT Target completes. */ 1218/* Called by lower (CE) layer when a send to HTT Target completes. */
1212static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state) 1219static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state)
1213{ 1220{
@@ -2027,6 +2034,29 @@ static int ath10k_pci_init_config(struct ath10k *ar)
2027 return 0; 2034 return 0;
2028} 2035}
2029 2036
2037static void ath10k_pci_override_ce_config(struct ath10k *ar)
2038{
2039 struct ce_attr *attr;
2040 struct ce_pipe_config *config;
2041
2042 /* For QCA6174 we're overriding the Copy Engine 5 configuration,
2043 * since it is currently used for other feature.
2044 */
2045
2046 /* Override Host's Copy Engine 5 configuration */
2047 attr = &host_ce_config_wlan[5];
2048 attr->src_sz_max = 0;
2049 attr->dest_nentries = 0;
2050
2051 /* Override Target firmware's Copy Engine configuration */
2052 config = &target_ce_config_wlan[5];
2053 config->pipedir = __cpu_to_le32(PIPEDIR_OUT);
2054 config->nbytes_max = __cpu_to_le32(2048);
2055
2056 /* Map from service/endpoint to Copy Engine */
2057 target_service_to_ce_map_wlan[15].pipenum = __cpu_to_le32(1);
2058}
2059
2030static int ath10k_pci_alloc_pipes(struct ath10k *ar) 2060static int ath10k_pci_alloc_pipes(struct ath10k *ar)
2031{ 2061{
2032 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2062 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
@@ -3020,6 +3050,9 @@ static int ath10k_pci_probe(struct pci_dev *pdev,
3020 goto err_core_destroy; 3050 goto err_core_destroy;
3021 } 3051 }
3022 3052
3053 if (QCA_REV_6174(ar))
3054 ath10k_pci_override_ce_config(ar);
3055
3023 ret = ath10k_pci_alloc_pipes(ar); 3056 ret = ath10k_pci_alloc_pipes(ar);
3024 if (ret) { 3057 if (ret) {
3025 ath10k_err(ar, "failed to allocate copy engine pipes: %d\n", 3058 ath10k_err(ar, "failed to allocate copy engine pipes: %d\n",