Merge tag 'tegra-for-3.9-soc-usb' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc

From Stephen Warren:
ARM: tegra: USB driver cleanup

The Tegra USB driver has a number of issues:

1) The PHY driver isn't a true platform device, and doesn't implement
   the standard USB PHY API.

2) struct device instance numbers were used to make decisions in the
   driver, rather than being parameterized by DT or platform data.

This pull request solves issue (2), and lays the groundwork for solving
issue (1). The work on issue (1) involved introducing new DT nodes for
the USB PHYs, which in turn interacted with the Tegra common clock
framework changes, due to the move of clock lookups into device tree.
Hence, these USB driver changes are taken through the Tegra tree with
acks from USB maintainers.

This pull request is based on the previous pull request, with tag
tegra-for-3.9-soc-ccf.

* tag 'tegra-for-3.9-soc-usb' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
  usb: host: tegra: make use of PHY pointer of HCD
  ARM: tegra: Add reset GPIO information to PHY DT node
  usb: host: tegra: don't touch EMC clock
  usb: add APIs to access host registers from Tegra PHY
  USB: PHY: tegra: Get rid of instance number to differentiate PHY type
  USB: PHY: tegra: get rid of instance number to differentiate legacy controller
  ARM: tegra: add clocks properties to USB PHY nodes
  ARM: tegra: add DT nodes for Tegra USB PHY
  usb: phy: remove unused APIs from Tegra PHY.
  usb: host: tegra: Resetting PORT0 based on information received via DT.
  ARM: tegra: Add new DT property to USB node.
  usb: phy: use kzalloc to allocate struct tegra_usb_phy
  ARM: tegra: remove USB address related macros from iomap.h

13 files changed, 191 insertions, 138 deletions

diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
index e9b005dc7625..34c952883276 100644
--- a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
+++ b/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
@@ -11,6 +11,7 @@ Required properties :
  - phy_type : Should be one of "ulpi" or "utmi".
  - nvidia,vbus-gpio : If present, specifies a gpio that needs to be
    activated for the bus to be powered.
+ - nvidia,phy : phandle of the PHY instance, the controller is connected to.
 
 Required properties for phy_type == ulpi:
   - nvidia,phy-reset-gpio : The GPIO used to reset the PHY.
@@ -27,3 +28,5 @@ Optional properties:
     registers are accessed through the APB_MISC base address instead of
     the USB controller. Since this is a legacy issue it probably does not
     warrant a compatible string of its own.
+  - nvidia,needs-double-reset : boolean is to be set for some of the Tegra2
+    USB ports, which need reset twice due to hardware issues.
diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt
new file mode 100644
index 000000000000..6bdaba2f0aa1
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt
@@ -0,0 +1,17 @@
+Tegra SOC USB PHY
+
+The device node for Tegra SOC USB PHY:
+
+Required properties :
+ - compatible : Should be "nvidia,tegra20-usb-phy".
+ - reg : Address and length of the register set for the USB PHY interface.
+ - phy_type : Should be one of "ulpi" or "utmi".
+
+Required properties for phy_type == ulpi:
+  - nvidia,phy-reset-gpio : The GPIO used to reset the PHY.
+
+Optional properties:
+  - nvidia,has-legacy-mode : boolean indicates whether this controller can
+    operate in legacy mode (as APX 2500 / 2600). In legacy mode some
+    registers are accessed through the APB_MISC base address instead of
+    the USB controller.
\ No newline at end of file
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index 43eb72af8948..2b4169702c8d 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -432,6 +432,10 @@
                 status = "okay";
         };
 
+        usb-phy@c5004400 {
+                nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+        };
+
         sdhci@c8000200 {
                 status = "okay";
                 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index a965fe9c7aa1..11b30db63ff2 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -420,6 +420,10 @@
                 status = "okay";
         };
 
+        usb-phy@c5004400 {
+                nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+        };
+
         sdhci@c8000000 {
                 status = "okay";
                 cd-gpios = <&gpio 173 0>; /* gpio PV5 */
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 420459825b46..607bf0c6bf9c 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -561,6 +561,10 @@
                 status = "okay";
         };
 
+        usb-phy@c5004400 {
+                nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+        };
+
         sdhci@c8000000 {
                 status = "okay";
                 power-gpios = <&gpio 86 0>; /* gpio PK6 */
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index b70b4cb754c8..e47cf6a58b6f 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -310,6 +310,10 @@
                 status = "okay";
         };
 
+        usb-phy@c5004400 {
+                nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+        };
+
         sdhci@c8000000 {
                 status = "okay";
                 bus-width = <4>;
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index adc47547eaae..f6c61d10fd27 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -497,6 +497,10 @@
                 status = "okay";
         };
 
+        usb-phy@c5004400 {
+                nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+        };
+
         sdhci@c8000000 {
                 status = "okay";
                 power-gpios = <&gpio 86 0>; /* gpio PK6 */
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index d665a67d4358..649391579871 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -400,6 +400,31 @@
                 #size-cells = <0>;
         };
 
+        phy1: usb-phy@c5000400 {
+                compatible = "nvidia,tegra20-usb-phy";
+                reg = <0xc5000400 0x3c00>;
+                phy_type = "utmi";
+                nvidia,has-legacy-mode;
+                clocks = <&tegra_car 22>, <&tegra_car 127>;
+                clock-names = "phy", "pll_u";
+        };
+
+        phy2: usb-phy@c5004400 {
+                compatible = "nvidia,tegra20-usb-phy";
+                reg = <0xc5004400 0x3c00>;
+                phy_type = "ulpi";
+                clocks = <&tegra_car 94>, <&tegra_car 127>;
+                clock-names = "phy", "pll_u";
+        };
+
+        phy3: usb-phy@c5008400 {
+                compatible = "nvidia,tegra20-usb-phy";
+                reg = <0xc5008400 0x3C00>;
+                phy_type = "utmi";
+                clocks = <&tegra_car 22>, <&tegra_car 127>;
+                clock-names = "phy", "pll_u";
+        };
+
         usb@c5000000 {
                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
                 reg = <0xc5000000 0x4000>;
@@ -407,6 +432,8 @@
                 phy_type = "utmi";
                 nvidia,has-legacy-mode;
                 clocks = <&tegra_car 22>;
+                nvidia,needs-double-reset;
+                nvidia,phy = <&phy1>;
                 status = "disabled";
         };
 
@@ -416,6 +443,7 @@
                 interrupts = <0 21 0x04>;
                 phy_type = "ulpi";
                 clocks = <&tegra_car 58>;
+                nvidia,phy = <&phy2>;