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authorVladimir Zapolskiy <vz@mleia.com>2019-04-19 16:54:46 -0400
committerVladimir Zapolskiy <vz@mleia.com>2019-04-19 16:57:04 -0400
commitcea862386791e281c4e9ab07dd118321f6655435 (patch)
tree63a94e5d0b2cf170990c97b95621c440ae1c3d03
parent4c546175dbe1b9bde68f547666a2c1f75d65b817 (diff)
ARM: dts: lpc32xx: add address and size cell values to SPI controller nodes
All 4 SPI controllers on NXP LPC32xx SoC support SPI slaves discerning them by one cell address value, set it as default to avoid duplication in board device tree files. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
-rw-r--r--arch/arm/boot/dts/lpc3250-phy3250.dts2
-rw-r--r--arch/arm/boot/dts/lpc32xx.dtsi8
2 files changed, 8 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/lpc3250-phy3250.dts b/arch/arm/boot/dts/lpc3250-phy3250.dts
index b99726d278f6..1b15f798794b 100644
--- a/arch/arm/boot/dts/lpc3250-phy3250.dts
+++ b/arch/arm/boot/dts/lpc3250-phy3250.dts
@@ -202,8 +202,6 @@
202}; 202};
203 203
204&ssp0 { 204&ssp0 {
205 #address-cells = <1>;
206 #size-cells = <0>;
207 num-cs = <1>; 205 num-cs = <1>;
208 cs-gpios = <&gpio 3 5 0>; 206 cs-gpios = <&gpio 3 5 0>;
209 status = "okay"; 207 status = "okay";
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index a0fedab579b4..bc32450de423 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -187,6 +187,8 @@
187 interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; 187 interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
188 clocks = <&clk LPC32XX_CLK_SSP0>; 188 clocks = <&clk LPC32XX_CLK_SSP0>;
189 clock-names = "apb_pclk"; 189 clock-names = "apb_pclk";
190 #address-cells = <1>;
191 #size-cells = <0>;
190 status = "disabled"; 192 status = "disabled";
191 }; 193 };
192 194
@@ -194,6 +196,8 @@
194 compatible = "nxp,lpc3220-spi"; 196 compatible = "nxp,lpc3220-spi";
195 reg = <0x20088000 0x1000>; 197 reg = <0x20088000 0x1000>;
196 clocks = <&clk LPC32XX_CLK_SPI1>; 198 clocks = <&clk LPC32XX_CLK_SPI1>;
199 #address-cells = <1>;
200 #size-cells = <0>;
197 status = "disabled"; 201 status = "disabled";
198 }; 202 };
199 203
@@ -207,6 +211,8 @@
207 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; 211 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
208 clocks = <&clk LPC32XX_CLK_SSP1>; 212 clocks = <&clk LPC32XX_CLK_SSP1>;
209 clock-names = "apb_pclk"; 213 clock-names = "apb_pclk";
214 #address-cells = <1>;
215 #size-cells = <0>;
210 status = "disabled"; 216 status = "disabled";
211 }; 217 };
212 218
@@ -214,6 +220,8 @@
214 compatible = "nxp,lpc3220-spi"; 220 compatible = "nxp,lpc3220-spi";
215 reg = <0x20090000 0x1000>; 221 reg = <0x20090000 0x1000>;
216 clocks = <&clk LPC32XX_CLK_SPI2>; 222 clocks = <&clk LPC32XX_CLK_SPI2>;
223 #address-cells = <1>;
224 #size-cells = <0>;
217 status = "disabled"; 225 status = "disabled";
218 }; 226 };
219 227