diff options
author | Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | 2018-01-28 22:09:02 -0500 |
---|---|---|
committer | Mark Brown <broonie@kernel.org> | 2018-02-12 04:42:40 -0500 |
commit | ce8d1015a2b8d1301c98f7e6b774fb1c28220cea (patch) | |
tree | 6110090136feb2d4957dd8cc91fec41a5db0d8e4 | |
parent | 7928b2cbe55b2a410a0f5c1f154610059c57b1b2 (diff) |
ASoC: wm8961: replace codec to component
Now we can replace Codec to Component. Let's do it.
Note:
xxx_codec_xxx() -> xxx_component_xxx()
.idle_bias_off = 0 -> .idle_bias_on = 1
.ignore_pmdown_time = 0 -> .use_pmdown_time = 1
- -> .endianness = 1
- -> .non_legacy_dai_naming = 1
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r-- | sound/soc/codecs/wm8961.c | 241 |
1 files changed, 117 insertions, 124 deletions
diff --git a/sound/soc/codecs/wm8961.c b/sound/soc/codecs/wm8961.c index e23ceac76015..f70f563d59f3 100644 --- a/sound/soc/codecs/wm8961.c +++ b/sound/soc/codecs/wm8961.c | |||
@@ -194,89 +194,89 @@ static bool wm8961_readable(struct device *dev, unsigned int reg) | |||
194 | static int wm8961_hp_event(struct snd_soc_dapm_widget *w, | 194 | static int wm8961_hp_event(struct snd_soc_dapm_widget *w, |
195 | struct snd_kcontrol *kcontrol, int event) | 195 | struct snd_kcontrol *kcontrol, int event) |
196 | { | 196 | { |
197 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); | 197 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); |
198 | u16 hp_reg = snd_soc_read(codec, WM8961_ANALOGUE_HP_0); | 198 | u16 hp_reg = snd_soc_component_read32(component, WM8961_ANALOGUE_HP_0); |
199 | u16 cp_reg = snd_soc_read(codec, WM8961_CHARGE_PUMP_1); | 199 | u16 cp_reg = snd_soc_component_read32(component, WM8961_CHARGE_PUMP_1); |
200 | u16 pwr_reg = snd_soc_read(codec, WM8961_PWR_MGMT_2); | 200 | u16 pwr_reg = snd_soc_component_read32(component, WM8961_PWR_MGMT_2); |
201 | u16 dcs_reg = snd_soc_read(codec, WM8961_DC_SERVO_1); | 201 | u16 dcs_reg = snd_soc_component_read32(component, WM8961_DC_SERVO_1); |
202 | int timeout = 500; | 202 | int timeout = 500; |
203 | 203 | ||
204 | if (event & SND_SOC_DAPM_POST_PMU) { | 204 | if (event & SND_SOC_DAPM_POST_PMU) { |
205 | /* Make sure the output is shorted */ | 205 | /* Make sure the output is shorted */ |
206 | hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT); | 206 | hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT); |
207 | snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); | 207 | snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg); |
208 | 208 | ||
209 | /* Enable the charge pump */ | 209 | /* Enable the charge pump */ |
210 | cp_reg |= WM8961_CP_ENA; | 210 | cp_reg |= WM8961_CP_ENA; |
211 | snd_soc_write(codec, WM8961_CHARGE_PUMP_1, cp_reg); | 211 | snd_soc_component_write(component, WM8961_CHARGE_PUMP_1, cp_reg); |
212 | mdelay(5); | 212 | mdelay(5); |
213 | 213 | ||
214 | /* Enable the PGA */ | 214 | /* Enable the PGA */ |
215 | pwr_reg |= WM8961_LOUT1_PGA | WM8961_ROUT1_PGA; | 215 | pwr_reg |= WM8961_LOUT1_PGA | WM8961_ROUT1_PGA; |
216 | snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg); | 216 | snd_soc_component_write(component, WM8961_PWR_MGMT_2, pwr_reg); |
217 | 217 | ||
218 | /* Enable the amplifier */ | 218 | /* Enable the amplifier */ |
219 | hp_reg |= WM8961_HPR_ENA | WM8961_HPL_ENA; | 219 | hp_reg |= WM8961_HPR_ENA | WM8961_HPL_ENA; |
220 | snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); | 220 | snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg); |
221 | 221 | ||
222 | /* Second stage enable */ | 222 | /* Second stage enable */ |
223 | hp_reg |= WM8961_HPR_ENA_DLY | WM8961_HPL_ENA_DLY; | 223 | hp_reg |= WM8961_HPR_ENA_DLY | WM8961_HPL_ENA_DLY; |
224 | snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); | 224 | snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg); |
225 | 225 | ||
226 | /* Enable the DC servo & trigger startup */ | 226 | /* Enable the DC servo & trigger startup */ |
227 | dcs_reg |= | 227 | dcs_reg |= |
228 | WM8961_DCS_ENA_CHAN_HPR | WM8961_DCS_TRIG_STARTUP_HPR | | 228 | WM8961_DCS_ENA_CHAN_HPR | WM8961_DCS_TRIG_STARTUP_HPR | |
229 | WM8961_DCS_ENA_CHAN_HPL | WM8961_DCS_TRIG_STARTUP_HPL; | 229 | WM8961_DCS_ENA_CHAN_HPL | WM8961_DCS_TRIG_STARTUP_HPL; |
230 | dev_dbg(codec->dev, "Enabling DC servo\n"); | 230 | dev_dbg(component->dev, "Enabling DC servo\n"); |
231 | 231 | ||
232 | snd_soc_write(codec, WM8961_DC_SERVO_1, dcs_reg); | 232 | snd_soc_component_write(component, WM8961_DC_SERVO_1, dcs_reg); |
233 | do { | 233 | do { |
234 | msleep(1); | 234 | msleep(1); |
235 | dcs_reg = snd_soc_read(codec, WM8961_DC_SERVO_1); | 235 | dcs_reg = snd_soc_component_read32(component, WM8961_DC_SERVO_1); |
236 | } while (--timeout && | 236 | } while (--timeout && |
237 | dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR | | 237 | dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR | |
238 | WM8961_DCS_TRIG_STARTUP_HPL)); | 238 | WM8961_DCS_TRIG_STARTUP_HPL)); |
239 | if (dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR | | 239 | if (dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR | |
240 | WM8961_DCS_TRIG_STARTUP_HPL)) | 240 | WM8961_DCS_TRIG_STARTUP_HPL)) |
241 | dev_err(codec->dev, "DC servo timed out\n"); | 241 | dev_err(component->dev, "DC servo timed out\n"); |
242 | else | 242 | else |
243 | dev_dbg(codec->dev, "DC servo startup complete\n"); | 243 | dev_dbg(component->dev, "DC servo startup complete\n"); |
244 | 244 | ||
245 | /* Enable the output stage */ | 245 | /* Enable the output stage */ |
246 | hp_reg |= WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP; | 246 | hp_reg |= WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP; |
247 | snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); | 247 | snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg); |
248 | 248 | ||
249 | /* Remove the short on the output stage */ | 249 | /* Remove the short on the output stage */ |
250 | hp_reg |= WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT; | 250 | hp_reg |= WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT; |
251 | snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); | 251 | snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg); |
252 | } | 252 | } |
253 | 253 | ||
254 | if (event & SND_SOC_DAPM_PRE_PMD) { | 254 | if (event & SND_SOC_DAPM_PRE_PMD) { |
255 | /* Short the output */ | 255 | /* Short the output */ |
256 | hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT); | 256 | hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT); |
257 | snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); | 257 | snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg); |
258 | 258 | ||
259 | /* Disable the output stage */ | 259 | /* Disable the output stage */ |
260 | hp_reg &= ~(WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP); | 260 | hp_reg &= ~(WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP); |
261 | snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); | 261 | snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg); |
262 | 262 | ||
263 | /* Disable DC offset cancellation */ | 263 | /* Disable DC offset cancellation */ |
264 | dcs_reg &= ~(WM8961_DCS_ENA_CHAN_HPR | | 264 | dcs_reg &= ~(WM8961_DCS_ENA_CHAN_HPR | |
265 | WM8961_DCS_ENA_CHAN_HPL); | 265 | WM8961_DCS_ENA_CHAN_HPL); |
266 | snd_soc_write(codec, WM8961_DC_SERVO_1, dcs_reg); | 266 | snd_soc_component_write(component, WM8961_DC_SERVO_1, dcs_reg); |
267 | 267 | ||
268 | /* Finish up */ | 268 | /* Finish up */ |
269 | hp_reg &= ~(WM8961_HPR_ENA_DLY | WM8961_HPR_ENA | | 269 | hp_reg &= ~(WM8961_HPR_ENA_DLY | WM8961_HPR_ENA | |
270 | WM8961_HPL_ENA_DLY | WM8961_HPL_ENA); | 270 | WM8961_HPL_ENA_DLY | WM8961_HPL_ENA); |
271 | snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); | 271 | snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg); |
272 | 272 | ||
273 | /* Disable the PGA */ | 273 | /* Disable the PGA */ |
274 | pwr_reg &= ~(WM8961_LOUT1_PGA | WM8961_ROUT1_PGA); | 274 | pwr_reg &= ~(WM8961_LOUT1_PGA | WM8961_ROUT1_PGA); |
275 | snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg); | 275 | snd_soc_component_write(component, WM8961_PWR_MGMT_2, pwr_reg); |
276 | 276 | ||
277 | /* Disable the charge pump */ | 277 | /* Disable the charge pump */ |
278 | dev_dbg(codec->dev, "Disabling charge pump\n"); | 278 | dev_dbg(component->dev, "Disabling charge pump\n"); |
279 | snd_soc_write(codec, WM8961_CHARGE_PUMP_1, | 279 | snd_soc_component_write(component, WM8961_CHARGE_PUMP_1, |
280 | cp_reg & ~WM8961_CP_ENA); | 280 | cp_reg & ~WM8961_CP_ENA); |
281 | } | 281 | } |
282 | 282 | ||
@@ -286,28 +286,28 @@ static int wm8961_hp_event(struct snd_soc_dapm_widget *w, | |||
286 | static int wm8961_spk_event(struct snd_soc_dapm_widget *w, | 286 | static int wm8961_spk_event(struct snd_soc_dapm_widget *w, |
287 | struct snd_kcontrol *kcontrol, int event) | 287 | struct snd_kcontrol *kcontrol, int event) |
288 | { | 288 | { |
289 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); | 289 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); |
290 | u16 pwr_reg = snd_soc_read(codec, WM8961_PWR_MGMT_2); | 290 | u16 pwr_reg = snd_soc_component_read32(component, WM8961_PWR_MGMT_2); |
291 | u16 spk_reg = snd_soc_read(codec, WM8961_CLASS_D_CONTROL_1); | 291 | u16 spk_reg = snd_soc_component_read32(component, WM8961_CLASS_D_CONTROL_1); |
292 | 292 | ||
293 | if (event & SND_SOC_DAPM_POST_PMU) { | 293 | if (event & SND_SOC_DAPM_POST_PMU) { |
294 | /* Enable the PGA */ | 294 | /* Enable the PGA */ |
295 | pwr_reg |= WM8961_SPKL_PGA | WM8961_SPKR_PGA; | 295 | pwr_reg |= WM8961_SPKL_PGA | WM8961_SPKR_PGA; |
296 | snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg); | 296 | snd_soc_component_write(component, WM8961_PWR_MGMT_2, pwr_reg); |
297 | 297 | ||
298 | /* Enable the amplifier */ | 298 | /* Enable the amplifier */ |
299 | spk_reg |= WM8961_SPKL_ENA | WM8961_SPKR_ENA; | 299 | spk_reg |= WM8961_SPKL_ENA | WM8961_SPKR_ENA; |
300 | snd_soc_write(codec, WM8961_CLASS_D_CONTROL_1, spk_reg); | 300 | snd_soc_component_write(component, WM8961_CLASS_D_CONTROL_1, spk_reg); |
301 | } | 301 | } |
302 | 302 | ||
303 | if (event & SND_SOC_DAPM_PRE_PMD) { | 303 | if (event & SND_SOC_DAPM_PRE_PMD) { |
304 | /* Disable the amplifier */ | 304 | /* Disable the amplifier */ |
305 | spk_reg &= ~(WM8961_SPKL_ENA | WM8961_SPKR_ENA); | 305 | spk_reg &= ~(WM8961_SPKL_ENA | WM8961_SPKR_ENA); |
306 | snd_soc_write(codec, WM8961_CLASS_D_CONTROL_1, spk_reg); | 306 | snd_soc_component_write(component, WM8961_CLASS_D_CONTROL_1, spk_reg); |
307 | 307 | ||
308 | /* Disable the PGA */ | 308 | /* Disable the PGA */ |
309 | pwr_reg &= ~(WM8961_SPKL_PGA | WM8961_SPKR_PGA); | 309 | pwr_reg &= ~(WM8961_SPKL_PGA | WM8961_SPKR_PGA); |
310 | snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg); | 310 | snd_soc_component_write(component, WM8961_PWR_MGMT_2, pwr_reg); |
311 | } | 311 | } |
312 | 312 | ||
313 | return 0; | 313 | return 0; |
@@ -505,15 +505,15 @@ static int wm8961_hw_params(struct snd_pcm_substream *substream, | |||
505 | struct snd_pcm_hw_params *params, | 505 | struct snd_pcm_hw_params *params, |
506 | struct snd_soc_dai *dai) | 506 | struct snd_soc_dai *dai) |
507 | { | 507 | { |
508 | struct snd_soc_codec *codec = dai->codec; | 508 | struct snd_soc_component *component = dai->component; |
509 | struct wm8961_priv *wm8961 = snd_soc_codec_get_drvdata(codec); | 509 | struct wm8961_priv *wm8961 = snd_soc_component_get_drvdata(component); |
510 | int i, best, target, fs; | 510 | int i, best, target, fs; |
511 | u16 reg; | 511 | u16 reg; |
512 | 512 | ||
513 | fs = params_rate(params); | 513 | fs = params_rate(params); |
514 | 514 | ||
515 | if (!wm8961->sysclk) { | 515 | if (!wm8961->sysclk) { |
516 | dev_err(codec->dev, "MCLK has not been specified\n"); | 516 | dev_err(component->dev, "MCLK has not been specified\n"); |
517 | return -EINVAL; | 517 | return -EINVAL; |
518 | } | 518 | } |
519 | 519 | ||
@@ -524,23 +524,23 @@ static int wm8961_hw_params(struct snd_pcm_substream *substream, | |||
524 | abs(wm8961_srate[best].rate - fs)) | 524 | abs(wm8961_srate[best].rate - fs)) |
525 | best = i; | 525 | best = i; |
526 | } | 526 | } |
527 | reg = snd_soc_read(codec, WM8961_ADDITIONAL_CONTROL_3); | 527 | reg = snd_soc_component_read32(component, WM8961_ADDITIONAL_CONTROL_3); |
528 | reg &= ~WM8961_SAMPLE_RATE_MASK; | 528 | reg &= ~WM8961_SAMPLE_RATE_MASK; |
529 | reg |= wm8961_srate[best].val; | 529 | reg |= wm8961_srate[best].val; |
530 | snd_soc_write(codec, WM8961_ADDITIONAL_CONTROL_3, reg); | 530 | snd_soc_component_write(component, WM8961_ADDITIONAL_CONTROL_3, reg); |
531 | dev_dbg(codec->dev, "Selected SRATE %dHz for %dHz\n", | 531 | dev_dbg(component->dev, "Selected SRATE %dHz for %dHz\n", |
532 | wm8961_srate[best].rate, fs); | 532 | wm8961_srate[best].rate, fs); |
533 | 533 | ||
534 | /* Select a CLK_SYS/fs ratio equal to or higher than required */ | 534 | /* Select a CLK_SYS/fs ratio equal to or higher than required */ |
535 | target = wm8961->sysclk / fs; | 535 | target = wm8961->sysclk / fs; |
536 | 536 | ||
537 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && target < 64) { | 537 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && target < 64) { |
538 | dev_err(codec->dev, | 538 | dev_err(component->dev, |
539 | "SYSCLK must be at least 64*fs for DAC\n"); | 539 | "SYSCLK must be at least 64*fs for DAC\n"); |
540 | return -EINVAL; | 540 | return -EINVAL; |
541 | } | 541 | } |
542 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE && target < 256) { | 542 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE && target < 256) { |
543 | dev_err(codec->dev, | 543 | dev_err(component->dev, |
544 | "SYSCLK must be at least 256*fs for ADC\n"); | 544 | "SYSCLK must be at least 256*fs for ADC\n"); |
545 | return -EINVAL; | 545 | return -EINVAL; |
546 | } | 546 | } |
@@ -550,19 +550,19 @@ static int wm8961_hw_params(struct snd_pcm_substream *substream, | |||
550 | break; | 550 | break; |
551 | } | 551 | } |
552 | if (i == ARRAY_SIZE(wm8961_clk_sys_ratio)) { | 552 | if (i == ARRAY_SIZE(wm8961_clk_sys_ratio)) { |
553 | dev_err(codec->dev, "Unable to generate CLK_SYS_RATE\n"); | 553 | dev_err(component->dev, "Unable to generate CLK_SYS_RATE\n"); |
554 | return -EINVAL; | 554 | return -EINVAL; |
555 | } | 555 | } |
556 | dev_dbg(codec->dev, "Selected CLK_SYS_RATE of %d for %d/%d=%d\n", | 556 | dev_dbg(component->dev, "Selected CLK_SYS_RATE of %d for %d/%d=%d\n", |
557 | wm8961_clk_sys_ratio[i].ratio, wm8961->sysclk, fs, | 557 | wm8961_clk_sys_ratio[i].ratio, wm8961->sysclk, fs, |
558 | wm8961->sysclk / fs); | 558 | wm8961->sysclk / fs); |
559 | 559 | ||
560 | reg = snd_soc_read(codec, WM8961_CLOCKING_4); | 560 | reg = snd_soc_component_read32(component, WM8961_CLOCKING_4); |
561 | reg &= ~WM8961_CLK_SYS_RATE_MASK; | 561 | reg &= ~WM8961_CLK_SYS_RATE_MASK; |
562 | reg |= wm8961_clk_sys_ratio[i].val << WM8961_CLK_SYS_RATE_SHIFT; | 562 | reg |= wm8961_clk_sys_ratio[i].val << WM8961_CLK_SYS_RATE_SHIFT; |
563 | snd_soc_write(codec, WM8961_CLOCKING_4, reg); | 563 | snd_soc_component_write(component, WM8961_CLOCKING_4, reg); |
564 | 564 | ||
565 | reg = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_0); | 565 | reg = snd_soc_component_read32(component, WM8961_AUDIO_INTERFACE_0); |
566 | reg &= ~WM8961_WL_MASK; | 566 | reg &= ~WM8961_WL_MASK; |
567 | switch (params_width(params)) { | 567 | switch (params_width(params)) { |
568 | case 16: | 568 | case 16: |
@@ -579,15 +579,15 @@ static int wm8961_hw_params(struct snd_pcm_substream *substream, | |||
579 | default: | 579 | default: |
580 | return -EINVAL; | 580 | return -EINVAL; |
581 | } | 581 | } |
582 | snd_soc_write(codec, WM8961_AUDIO_INTERFACE_0, reg); | 582 | snd_soc_component_write(component, WM8961_AUDIO_INTERFACE_0, reg); |
583 | 583 | ||
584 | /* Sloping stop-band filter is recommended for <= 24kHz */ | 584 | /* Sloping stop-band filter is recommended for <= 24kHz */ |
585 | reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_2); | 585 | reg = snd_soc_component_read32(component, WM8961_ADC_DAC_CONTROL_2); |
586 | if (fs <= 24000) | 586 | if (fs <= 24000) |
587 | reg |= WM8961_DACSLOPE; | 587 | reg |= WM8961_DACSLOPE; |
588 | else | 588 | else |
589 | reg &= ~WM8961_DACSLOPE; | 589 | reg &= ~WM8961_DACSLOPE; |
590 | snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_2, reg); | 590 | snd_soc_component_write(component, WM8961_ADC_DAC_CONTROL_2, reg); |
591 | 591 | ||
592 | return 0; | 592 | return 0; |
593 | } | 593 | } |
@@ -596,25 +596,25 @@ static int wm8961_set_sysclk(struct snd_soc_dai *dai, int clk_id, | |||
596 | unsigned int freq, | 596 | unsigned int freq, |
597 | int dir) | 597 | int dir) |
598 | { | 598 | { |
599 | struct snd_soc_codec *codec = dai->codec; | 599 | struct snd_soc_component *component = dai->component; |
600 | struct wm8961_priv *wm8961 = snd_soc_codec_get_drvdata(codec); | 600 | struct wm8961_priv *wm8961 = snd_soc_component_get_drvdata(component); |
601 | u16 reg = snd_soc_read(codec, WM8961_CLOCKING1); | 601 | u16 reg = snd_soc_component_read32(component, WM8961_CLOCKING1); |
602 | 602 | ||
603 | if (freq > 33000000) { | 603 | if (freq > 33000000) { |
604 | dev_err(codec->dev, "MCLK must be <33MHz\n"); | 604 | dev_err(component->dev, "MCLK must be <33MHz\n"); |
605 | return -EINVAL; | 605 | return -EINVAL; |
606 | } | 606 | } |
607 | 607 | ||
608 | if (freq > 16500000) { | 608 | if (freq > 16500000) { |
609 | dev_dbg(codec->dev, "Using MCLK/2 for %dHz MCLK\n", freq); | 609 | dev_dbg(component->dev, "Using MCLK/2 for %dHz MCLK\n", freq); |
610 | reg |= WM8961_MCLKDIV; | 610 | reg |= WM8961_MCLKDIV; |
611 | freq /= 2; | 611 | freq /= 2; |
612 | } else { | 612 | } else { |
613 | dev_dbg(codec->dev, "Using MCLK/1 for %dHz MCLK\n", freq); | 613 | dev_dbg(component->dev, "Using MCLK/1 for %dHz MCLK\n", freq); |
614 | reg &= ~WM8961_MCLKDIV; | 614 | reg &= ~WM8961_MCLKDIV; |
615 | } | 615 | } |
616 | 616 | ||
617 | snd_soc_write(codec, WM8961_CLOCKING1, reg); | 617 | snd_soc_component_write(component, WM8961_CLOCKING1, reg); |
618 | 618 | ||
619 | wm8961->sysclk = freq; | 619 | wm8961->sysclk = freq; |
620 | 620 | ||
@@ -623,8 +623,8 @@ static int wm8961_set_sysclk(struct snd_soc_dai *dai, int clk_id, | |||
623 | 623 | ||
624 | static int wm8961_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) | 624 | static int wm8961_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) |
625 | { | 625 | { |
626 | struct snd_soc_codec *codec = dai->codec; | 626 | struct snd_soc_component *component = dai->component; |
627 | u16 aif = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_0); | 627 | u16 aif = snd_soc_component_read32(component, WM8961_AUDIO_INTERFACE_0); |
628 | 628 | ||
629 | aif &= ~(WM8961_BCLKINV | WM8961_LRP | | 629 | aif &= ~(WM8961_BCLKINV | WM8961_LRP | |
630 | WM8961_MS | WM8961_FORMAT_MASK); | 630 | WM8961_MS | WM8961_FORMAT_MASK); |
@@ -684,26 +684,26 @@ static int wm8961_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) | |||
684 | return -EINVAL; | 684 | return -EINVAL; |
685 | } | 685 | } |
686 | 686 | ||
687 | return snd_soc_write(codec, WM8961_AUDIO_INTERFACE_0, aif); | 687 | return snd_soc_component_write(component, WM8961_AUDIO_INTERFACE_0, aif); |
688 | } | 688 | } |
689 | 689 | ||
690 | static int wm8961_set_tristate(struct snd_soc_dai *dai, int tristate) | 690 | static int wm8961_set_tristate(struct snd_soc_dai *dai, int tristate) |
691 | { | 691 | { |
692 | struct snd_soc_codec *codec = dai->codec; | 692 | struct snd_soc_component *component = dai->component; |
693 | u16 reg = snd_soc_read(codec, WM8961_ADDITIONAL_CONTROL_2); | 693 | u16 reg = snd_soc_component_read32(component, WM8961_ADDITIONAL_CONTROL_2); |
694 | 694 | ||
695 | if (tristate) | 695 | if (tristate) |
696 | reg |= WM8961_TRIS; | 696 | reg |= WM8961_TRIS; |
697 | else | 697 | else |
698 | reg &= ~WM8961_TRIS; | 698 | reg &= ~WM8961_TRIS; |
699 | 699 | ||
700 | return snd_soc_write(codec, WM8961_ADDITIONAL_CONTROL_2, reg); | 700 | return snd_soc_component_write(component, WM8961_ADDITIONAL_CONTROL_2, reg); |
701 | } | 701 | } |
702 | 702 | ||
703 | static int wm8961_digital_mute(struct snd_soc_dai *dai, int mute) | 703 | static int wm8961_digital_mute(struct snd_soc_dai *dai, int mute) |
704 | { | 704 | { |
705 | struct snd_soc_codec *codec = dai->codec; | 705 | struct snd_soc_component *component = dai->component; |
706 | u16 reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_1); | 706 | u16 reg = snd_soc_component_read32(component, WM8961_ADC_DAC_CONTROL_1); |
707 | 707 | ||
708 | if (mute) | 708 | if (mute) |
709 | reg |= WM8961_DACMU; | 709 | reg |= WM8961_DACMU; |
@@ -712,27 +712,27 @@ static int wm8961_digital_mute(struct snd_soc_dai *dai, int mute) | |||
712 | 712 | ||
713 | msleep(17); | 713 | msleep(17); |
714 | 714 | ||
715 | return snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_1, reg); | 715 | return snd_soc_component_write(component, WM8961_ADC_DAC_CONTROL_1, reg); |
716 | } | 716 | } |
717 | 717 | ||
718 | static int wm8961_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div) | 718 | static int wm8961_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div) |
719 | { | 719 | { |
720 | struct snd_soc_codec *codec = dai->codec; | 720 | struct snd_soc_component *component = dai->component; |
721 | u16 reg; | 721 | u16 reg; |
722 | 722 | ||
723 | switch (div_id) { | 723 | switch (div_id) { |
724 | case WM8961_BCLK: | 724 | case WM8961_BCLK: |
725 | reg = snd_soc_read(codec, WM8961_CLOCKING2); | 725 | reg = snd_soc_component_read32(component, WM8961_CLOCKING2); |
726 | reg &= ~WM8961_BCLKDIV_MASK; | 726 | reg &= ~WM8961_BCLKDIV_MASK; |
727 | reg |= div; | 727 | reg |= div; |
728 | snd_soc_write(codec, WM8961_CLOCKING2, reg); | 728 | snd_soc_component_write(component, WM8961_CLOCKING2, reg); |
729 | break; | 729 | break; |
730 | 730 | ||
731 | case WM8961_LRCLK: | 731 | case WM8961_LRCLK: |
732 | reg = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_2); | 732 | reg = snd_soc_component_read32(component, WM8961_AUDIO_INTERFACE_2); |
733 | reg &= ~WM8961_LRCLK_RATE_MASK; | 733 | reg &= ~WM8961_LRCLK_RATE_MASK; |
734 | reg |= div; | 734 | reg |= div; |
735 | snd_soc_write(codec, WM8961_AUDIO_INTERFACE_2, reg); | 735 | snd_soc_component_write(component, WM8961_AUDIO_INTERFACE_2, reg); |
736 | break; | 736 | break; |
737 | 737 | ||
738 | default: | 738 | default: |
@@ -742,7 +742,7 @@ static int wm8961_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div) | |||
742 | return 0; | 742 | return 0; |
743 | } | 743 | } |
744 | 744 | ||
745 | static int wm8961_set_bias_level(struct snd_soc_codec *codec, | 745 | static int wm8961_set_bias_level(struct snd_soc_component *component, |
746 | enum snd_soc_bias_level level) | 746 | enum snd_soc_bias_level level) |
747 | { | 747 | { |
748 | u16 reg; | 748 | u16 reg; |
@@ -757,36 +757,36 @@ static int wm8961_set_bias_level(struct snd_soc_codec *codec, | |||
757 | break; | 757 | break; |
758 | 758 | ||
759 | case SND_SOC_BIAS_PREPARE: | 759 | case SND_SOC_BIAS_PREPARE: |
760 | if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_STANDBY) { | 760 | if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY) { |
761 | /* Enable bias generation */ | 761 | /* Enable bias generation */ |
762 | reg = snd_soc_read(codec, WM8961_ANTI_POP); | 762 | reg = snd_soc_component_read32(component, WM8961_ANTI_POP); |
763 | reg |= WM8961_BUFIOEN | WM8961_BUFDCOPEN; | 763 | reg |= WM8961_BUFIOEN | WM8961_BUFDCOPEN; |
764 | snd_soc_write(codec, WM8961_ANTI_POP, reg); | 764 | snd_soc_component_write(component, WM8961_ANTI_POP, reg); |
765 | 765 | ||
766 | /* VMID=2*50k, VREF */ | 766 | /* VMID=2*50k, VREF */ |
767 | reg = snd_soc_read(codec, WM8961_PWR_MGMT_1); | 767 | reg = snd_soc_component_read32(component, WM8961_PWR_MGMT_1); |
768 | reg &= ~WM8961_VMIDSEL_MASK; | 768 | reg &= ~WM8961_VMIDSEL_MASK; |
769 | reg |= (1 << WM8961_VMIDSEL_SHIFT) | WM8961_VREF; | 769 | reg |= (1 << WM8961_VMIDSEL_SHIFT) | WM8961_VREF; |
770 | snd_soc_write(codec, WM8961_PWR_MGMT_1, reg); | 770 | snd_soc_component_write(component, WM8961_PWR_MGMT_1, reg); |
771 | } | 771 | } |
772 | break; | 772 | break; |
773 | 773 | ||
774 | case SND_SOC_BIAS_STANDBY: | 774 | case SND_SOC_BIAS_STANDBY: |
775 | if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_PREPARE) { | 775 | if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE) { |
776 | /* VREF off */ | 776 | /* VREF off */ |
777 | reg = snd_soc_read(codec, WM8961_PWR_MGMT_1); | 777 | reg = snd_soc_component_read32(component, WM8961_PWR_MGMT_1); |
778 | reg &= ~WM8961_VREF; | 778 | reg &= ~WM8961_VREF; |
779 | snd_soc_write(codec, WM8961_PWR_MGMT_1, reg); | 779 | snd_soc_component_write(component, WM8961_PWR_MGMT_1, reg); |
780 | 780 | ||
781 | /* Bias generation off */ | 781 | /* Bias generation off */ |
782 | reg = snd_soc_read(codec, WM8961_ANTI_POP); | 782 | reg = snd_soc_component_read32(component, WM8961_ANTI_POP); |
783 | reg &= ~(WM8961_BUFIOEN | WM8961_BUFDCOPEN); | 783 | reg &= ~(WM8961_BUFIOEN | WM8961_BUFDCOPEN); |
784 | snd_soc_write(codec, WM8961_ANTI_POP, reg); | 784 | snd_soc_component_write(component, WM8961_ANTI_POP, reg); |
785 | 785 | ||
786 | /* VMID off */ | 786 | /* VMID off */ |
787 | reg = snd_soc_read(codec, WM8961_PWR_MGMT_1); | 787 | reg = snd_soc_component_read32(component, WM8961_PWR_MGMT_1); |
788 | reg &= ~WM8961_VMIDSEL_MASK; | 788 | reg &= ~WM8961_VMIDSEL_MASK; |
789 | snd_soc_write(codec, WM8961_PWR_MGMT_1, reg); | 789 | snd_soc_component_write(component, WM8961_PWR_MGMT_1, reg); |
790 | } | 790 | } |
791 | break; | 791 | break; |
792 | 792 | ||
@@ -830,51 +830,51 @@ static struct snd_soc_dai_driver wm8961_dai = { | |||
830 | .ops = &wm8961_dai_ops, | 830 | .ops = &wm8961_dai_ops, |
831 | }; | 831 | }; |
832 | 832 | ||
833 | static int wm8961_probe(struct snd_soc_codec *codec) | 833 | static int wm8961_probe(struct snd_soc_component *component) |
834 | { | 834 | { |
835 | u16 reg; | 835 | u16 reg; |
836 | 836 | ||
837 | /* Enable class W */ | 837 | /* Enable class W */ |
838 | reg = snd_soc_read(codec, WM8961_CHARGE_PUMP_B); | 838 | reg = snd_soc_component_read32(component, WM8961_CHARGE_PUMP_B); |
839 | reg |= WM8961_CP_DYN_PWR_MASK; | 839 | reg |= WM8961_CP_DYN_PWR_MASK; |
840 | snd_soc_write(codec, WM8961_CHARGE_PUMP_B, reg); | 840 | snd_soc_component_write(component, WM8961_CHARGE_PUMP_B, reg); |
841 | 841 | ||
842 | /* Latch volume update bits (right channel only, we always | 842 | /* Latch volume update bits (right channel only, we always |
843 | * write both out) and default ZC on. */ | 843 | * write both out) and default ZC on. */ |
844 | reg = snd_soc_read(codec, WM8961_ROUT1_VOLUME); | 844 | reg = snd_soc_component_read32(component, WM8961_ROUT1_VOLUME); |
845 | snd_soc_write(codec, WM8961_ROUT1_VOLUME, | 845 | snd_soc_component_write(component, WM8961_ROUT1_VOLUME, |
846 | reg | WM8961_LO1ZC | WM8961_OUT1VU); | 846 | reg | WM8961_LO1ZC | WM8961_OUT1VU); |
847 | snd_soc_write(codec, WM8961_LOUT1_VOLUME, reg | WM8961_LO1ZC); | 847 | snd_soc_component_write(component, WM8961_LOUT1_VOLUME, reg | WM8961_LO1ZC); |
848 | reg = snd_soc_read(codec, WM8961_ROUT2_VOLUME); | 848 | reg = snd_soc_component_read32(component, WM8961_ROUT2_VOLUME); |
849 | snd_soc_write(codec, WM8961_ROUT2_VOLUME, | 849 | snd_soc_component_write(component, WM8961_ROUT2_VOLUME, |
850 | reg | WM8961_SPKRZC | WM8961_SPKVU); | 850 | reg | WM8961_SPKRZC | WM8961_SPKVU); |
851 | snd_soc_write(codec, WM8961_LOUT2_VOLUME, reg | WM8961_SPKLZC); | 851 | snd_soc_component_write(component, WM8961_LOUT2_VOLUME, reg | WM8961_SPKLZC); |
852 | 852 | ||
853 | reg = snd_soc_read(codec, WM8961_RIGHT_ADC_VOLUME); | 853 | reg = snd_soc_component_read32(component, WM8961_RIGHT_ADC_VOLUME); |
854 | snd_soc_write(codec, WM8961_RIGHT_ADC_VOLUME, reg | WM8961_ADCVU); | 854 | snd_soc_component_write(component, WM8961_RIGHT_ADC_VOLUME, reg | WM8961_ADCVU); |
855 | reg = snd_soc_read(codec, WM8961_RIGHT_INPUT_VOLUME); | 855 | reg = snd_soc_component_read32(component, WM8961_RIGHT_INPUT_VOLUME); |
856 | snd_soc_write(codec, WM8961_RIGHT_INPUT_VOLUME, reg | WM8961_IPVU); | 856 | snd_soc_component_write(component, WM8961_RIGHT_INPUT_VOLUME, reg | WM8961_IPVU); |
857 | 857 | ||
858 | /* Use soft mute by default */ | 858 | /* Use soft mute by default */ |
859 | reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_2); | 859 | reg = snd_soc_component_read32(component, WM8961_ADC_DAC_CONTROL_2); |
860 | reg |= WM8961_DACSMM; | 860 | reg |= WM8961_DACSMM; |
861 | snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_2, reg); | 861 | snd_soc_component_write(component, WM8961_ADC_DAC_CONTROL_2, reg); |
862 | 862 | ||
863 | /* Use automatic clocking mode by default; for now this is all | 863 | /* Use automatic clocking mode by default; for now this is all |
864 | * we support. | 864 | * we support. |
865 | */ | 865 | */ |
866 | reg = snd_soc_read(codec, WM8961_CLOCKING_3); | 866 | reg = snd_soc_component_read32(component, WM8961_CLOCKING_3); |
867 | reg &= ~WM8961_MANUAL_MODE; | 867 | reg &= ~WM8961_MANUAL_MODE; |
868 | snd_soc_write(codec, WM8961_CLOCKING_3, reg); | 868 | snd_soc_component_write(component, WM8961_CLOCKING_3, reg); |
869 | 869 | ||
870 | return 0; | 870 | return 0; |
871 | } | 871 | } |
872 | 872 | ||
873 | #ifdef CONFIG_PM | 873 | #ifdef CONFIG_PM |
874 | 874 | ||
875 | static int wm8961_resume(struct snd_soc_codec *codec) | 875 | static int wm8961_resume(struct snd_soc_component *component) |
876 | { | 876 | { |
877 | snd_soc_cache_sync(codec); | 877 | snd_soc_component_cache_sync(component); |
878 | 878 | ||
879 | return 0; | 879 | return 0; |
880 | } | 880 | } |
@@ -882,20 +882,21 @@ static int wm8961_resume(struct snd_soc_codec *codec) | |||
882 | #define wm8961_resume NULL | 882 | #define wm8961_resume NULL |
883 | #endif | 883 | #endif |
884 | 884 | ||
885 | static const struct snd_soc_codec_driver soc_codec_dev_wm8961 = { | 885 | static const struct snd_soc_component_driver soc_component_dev_wm8961 = { |
886 | .probe = wm8961_probe, | 886 | .probe = wm8961_probe, |
887 | .resume = wm8961_resume, | 887 | .resume = wm8961_resume, |
888 | .set_bias_level = wm8961_set_bias_level, | 888 | .set_bias_level = wm8961_set_bias_level, |
889 | .suspend_bias_off = true, | 889 | .controls = wm8961_snd_controls, |
890 | 890 | .num_controls = ARRAY_SIZE(wm8961_snd_controls), | |
891 | .component_driver = { | 891 | .dapm_widgets = wm8961_dapm_widgets, |
892 | .controls = wm8961_snd_controls, | 892 | .num_dapm_widgets = ARRAY_SIZE(wm8961_dapm_widgets), |
893 | .num_controls = ARRAY_SIZE(wm8961_snd_controls), | 893 | .dapm_routes = audio_paths, |
894 | .dapm_widgets = wm8961_dapm_widgets, | 894 | .num_dapm_routes = ARRAY_SIZE(audio_paths), |
895 | .num_dapm_widgets = ARRAY_SIZE(wm8961_dapm_widgets), | 895 | .suspend_bias_off = 1, |
896 | .dapm_routes = audio_paths, | 896 | .idle_bias_on = 1, |
897 | .num_dapm_routes = ARRAY_SIZE(audio_paths), | 897 | .use_pmdown_time = 1, |
898 | }, | 898 | .endianness = 1, |
899 | .non_legacy_dai_naming = 1, | ||
899 | }; | 900 | }; |
900 | 901 | ||
901 | static const struct regmap_config wm8961_regmap = { | 902 | static const struct regmap_config wm8961_regmap = { |
@@ -961,19 +962,12 @@ static int wm8961_i2c_probe(struct i2c_client *i2c, | |||
961 | 962 | ||
962 | i2c_set_clientdata(i2c, wm8961); | 963 | i2c_set_clientdata(i2c, wm8961); |
963 | 964 | ||
964 | ret = snd_soc_register_codec(&i2c->dev, | 965 | ret = devm_snd_soc_register_component(&i2c->dev, |
965 | &soc_codec_dev_wm8961, &wm8961_dai, 1); | 966 | &soc_component_dev_wm8961, &wm8961_dai, 1); |
966 | 967 | ||
967 | return ret; | 968 | return ret; |
968 | } | 969 | } |
969 | 970 | ||
970 | static int wm8961_i2c_remove(struct i2c_client *client) | ||
971 | { | ||
972 | snd_soc_unregister_codec(&client->dev); | ||
973 | |||
974 | return 0; | ||
975 | } | ||
976 | |||
977 | static const struct i2c_device_id wm8961_i2c_id[] = { | 971 | static const struct i2c_device_id wm8961_i2c_id[] = { |
978 | { "wm8961", 0 }, | 972 | { "wm8961", 0 }, |
979 | { } | 973 | { } |
@@ -985,7 +979,6 @@ static struct i2c_driver wm8961_i2c_driver = { | |||
985 | .name = "wm8961", | 979 | .name = "wm8961", |
986 | }, | 980 | }, |
987 | .probe = wm8961_i2c_probe, | 981 | .probe = wm8961_i2c_probe, |
988 | .remove = wm8961_i2c_remove, | ||
989 | .id_table = wm8961_i2c_id, | 982 | .id_table = wm8961_i2c_id, |
990 | }; | 983 | }; |
991 | 984 | ||